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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
fab04b22 | 4 | * Copyright (c) 2013, Intel Corporation. |
26717172 LB |
5 | * Len Brown <len.brown@intel.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
49 | * There is currently no kernel-based automatic probing/loading mechanism | |
50 | * if the driver is built as a module. | |
51 | */ | |
52 | ||
53 | /* un-comment DEBUG to enable pr_debug() statements */ | |
54 | #define DEBUG | |
55 | ||
56 | #include <linux/kernel.h> | |
57 | #include <linux/cpuidle.h> | |
76962caa | 58 | #include <linux/tick.h> |
26717172 LB |
59 | #include <trace/events/power.h> |
60 | #include <linux/sched.h> | |
2a2d31c8 SL |
61 | #include <linux/notifier.h> |
62 | #include <linux/cpu.h> | |
7c52d551 | 63 | #include <linux/module.h> |
b66b8b9a | 64 | #include <asm/cpu_device_id.h> |
bc83cccc | 65 | #include <asm/mwait.h> |
14796fca | 66 | #include <asm/msr.h> |
26717172 | 67 | |
d70e28f5 | 68 | #define INTEL_IDLE_VERSION "0.4.1" |
26717172 LB |
69 | #define PREFIX "intel_idle: " |
70 | ||
26717172 LB |
71 | static struct cpuidle_driver intel_idle_driver = { |
72 | .name = "intel_idle", | |
73 | .owner = THIS_MODULE, | |
74 | }; | |
75 | /* intel_idle.max_cstate=0 disables driver */ | |
137ecc77 | 76 | static int max_cstate = CPUIDLE_STATE_MAX - 1; |
26717172 | 77 | |
c4236282 | 78 | static unsigned int mwait_substates; |
26717172 | 79 | |
2a2d31c8 | 80 | #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF |
26717172 | 81 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
d13780d4 | 82 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
26717172 | 83 | |
b66b8b9a AK |
84 | struct idle_cpu { |
85 | struct cpuidle_state *state_table; | |
86 | ||
87 | /* | |
88 | * Hardware C-state auto-demotion may not always be optimal. | |
89 | * Indicate which enable bits to clear here. | |
90 | */ | |
91 | unsigned long auto_demotion_disable_flags; | |
8c058d53 | 92 | bool byt_auto_demotion_disable_flag; |
32e95180 | 93 | bool disable_promotion_to_c1e; |
b66b8b9a AK |
94 | }; |
95 | ||
96 | static const struct idle_cpu *icpu; | |
3265eba0 | 97 | static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; |
46bcfad7 DD |
98 | static int intel_idle(struct cpuidle_device *dev, |
99 | struct cpuidle_driver *drv, int index); | |
5fe2e527 RW |
100 | static void intel_idle_freeze(struct cpuidle_device *dev, |
101 | struct cpuidle_driver *drv, int index); | |
25ac7761 | 102 | static int intel_idle_cpu_init(int cpu); |
26717172 LB |
103 | |
104 | static struct cpuidle_state *cpuidle_state_table; | |
105 | ||
956d033f LB |
106 | /* |
107 | * Set this flag for states where the HW flushes the TLB for us | |
108 | * and so we don't need cross-calls to keep it consistent. | |
109 | * If this flag is set, SW flushes the TLB, so even if the | |
110 | * HW doesn't do the flushing, this flag is safe to use. | |
111 | */ | |
112 | #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 | |
113 | ||
b1beab48 LB |
114 | /* |
115 | * MWAIT takes an 8-bit "hint" in EAX "suggesting" | |
116 | * the C-state (top nibble) and sub-state (bottom nibble) | |
117 | * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. | |
118 | * | |
119 | * We store the hint at the top of our "flags" for each state. | |
120 | */ | |
121 | #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) | |
122 | #define MWAIT2flg(eax) ((eax & 0xFF) << 24) | |
123 | ||
26717172 LB |
124 | /* |
125 | * States are indexed by the cstate number, | |
126 | * which is also the index into the MWAIT hint array. | |
127 | * Thus C0 is a dummy. | |
128 | */ | |
ba0dc81e | 129 | static struct cpuidle_state nehalem_cstates[] = { |
e022e7eb | 130 | { |
15e123e5 | 131 | .name = "C1-NHM", |
26717172 | 132 | .desc = "MWAIT 0x00", |
b82b6cca | 133 | .flags = MWAIT2flg(0x00), |
26717172 | 134 | .exit_latency = 3, |
26717172 | 135 | .target_residency = 6, |
5fe2e527 RW |
136 | .enter = &intel_idle, |
137 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
138 | { |
139 | .name = "C1E-NHM", | |
140 | .desc = "MWAIT 0x01", | |
b82b6cca | 141 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
142 | .exit_latency = 10, |
143 | .target_residency = 20, | |
5fe2e527 RW |
144 | .enter = &intel_idle, |
145 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 146 | { |
15e123e5 | 147 | .name = "C3-NHM", |
26717172 | 148 | .desc = "MWAIT 0x10", |
b82b6cca | 149 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 150 | .exit_latency = 20, |
26717172 | 151 | .target_residency = 80, |
5fe2e527 RW |
152 | .enter = &intel_idle, |
153 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 154 | { |
15e123e5 | 155 | .name = "C6-NHM", |
26717172 | 156 | .desc = "MWAIT 0x20", |
b82b6cca | 157 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 158 | .exit_latency = 200, |
26717172 | 159 | .target_residency = 800, |
5fe2e527 RW |
160 | .enter = &intel_idle, |
161 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
162 | { |
163 | .enter = NULL } | |
26717172 LB |
164 | }; |
165 | ||
ba0dc81e | 166 | static struct cpuidle_state snb_cstates[] = { |
e022e7eb | 167 | { |
15e123e5 | 168 | .name = "C1-SNB", |
d13780d4 | 169 | .desc = "MWAIT 0x00", |
b82b6cca | 170 | .flags = MWAIT2flg(0x00), |
32e95180 LB |
171 | .exit_latency = 2, |
172 | .target_residency = 2, | |
5fe2e527 RW |
173 | .enter = &intel_idle, |
174 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
175 | { |
176 | .name = "C1E-SNB", | |
177 | .desc = "MWAIT 0x01", | |
b82b6cca | 178 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
179 | .exit_latency = 10, |
180 | .target_residency = 20, | |
5fe2e527 RW |
181 | .enter = &intel_idle, |
182 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 183 | { |
15e123e5 | 184 | .name = "C3-SNB", |
d13780d4 | 185 | .desc = "MWAIT 0x10", |
b82b6cca | 186 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 187 | .exit_latency = 80, |
ddbd550d | 188 | .target_residency = 211, |
5fe2e527 RW |
189 | .enter = &intel_idle, |
190 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 191 | { |
15e123e5 | 192 | .name = "C6-SNB", |
d13780d4 | 193 | .desc = "MWAIT 0x20", |
b82b6cca | 194 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 195 | .exit_latency = 104, |
ddbd550d | 196 | .target_residency = 345, |
5fe2e527 RW |
197 | .enter = &intel_idle, |
198 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 199 | { |
15e123e5 | 200 | .name = "C7-SNB", |
d13780d4 | 201 | .desc = "MWAIT 0x30", |
b82b6cca | 202 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 203 | .exit_latency = 109, |
ddbd550d | 204 | .target_residency = 345, |
5fe2e527 RW |
205 | .enter = &intel_idle, |
206 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
207 | { |
208 | .enter = NULL } | |
d13780d4 LB |
209 | }; |
210 | ||
718987d6 LB |
211 | static struct cpuidle_state byt_cstates[] = { |
212 | { | |
213 | .name = "C1-BYT", | |
214 | .desc = "MWAIT 0x00", | |
b82b6cca | 215 | .flags = MWAIT2flg(0x00), |
718987d6 LB |
216 | .exit_latency = 1, |
217 | .target_residency = 1, | |
5fe2e527 RW |
218 | .enter = &intel_idle, |
219 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
220 | { |
221 | .name = "C6N-BYT", | |
222 | .desc = "MWAIT 0x58", | |
b82b6cca | 223 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, |
d7ef7671 | 224 | .exit_latency = 300, |
718987d6 | 225 | .target_residency = 275, |
5fe2e527 RW |
226 | .enter = &intel_idle, |
227 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
228 | { |
229 | .name = "C6S-BYT", | |
230 | .desc = "MWAIT 0x52", | |
b82b6cca | 231 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
d7ef7671 | 232 | .exit_latency = 500, |
718987d6 | 233 | .target_residency = 560, |
5fe2e527 RW |
234 | .enter = &intel_idle, |
235 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
236 | { |
237 | .name = "C7-BYT", | |
238 | .desc = "MWAIT 0x60", | |
b82b6cca | 239 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 | 240 | .exit_latency = 1200, |
d7ef7671 | 241 | .target_residency = 4000, |
5fe2e527 RW |
242 | .enter = &intel_idle, |
243 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
244 | { |
245 | .name = "C7S-BYT", | |
246 | .desc = "MWAIT 0x64", | |
b82b6cca | 247 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 LB |
248 | .exit_latency = 10000, |
249 | .target_residency = 20000, | |
5fe2e527 RW |
250 | .enter = &intel_idle, |
251 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
252 | { |
253 | .enter = NULL } | |
254 | }; | |
255 | ||
cab07a56 LB |
256 | static struct cpuidle_state cht_cstates[] = { |
257 | { | |
258 | .name = "C1-CHT", | |
259 | .desc = "MWAIT 0x00", | |
260 | .flags = MWAIT2flg(0x00), | |
261 | .exit_latency = 1, | |
262 | .target_residency = 1, | |
263 | .enter = &intel_idle, | |
264 | .enter_freeze = intel_idle_freeze, }, | |
265 | { | |
266 | .name = "C6N-CHT", | |
267 | .desc = "MWAIT 0x58", | |
268 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, | |
269 | .exit_latency = 80, | |
270 | .target_residency = 275, | |
271 | .enter = &intel_idle, | |
272 | .enter_freeze = intel_idle_freeze, }, | |
273 | { | |
274 | .name = "C6S-CHT", | |
275 | .desc = "MWAIT 0x52", | |
276 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, | |
277 | .exit_latency = 200, | |
278 | .target_residency = 560, | |
279 | .enter = &intel_idle, | |
280 | .enter_freeze = intel_idle_freeze, }, | |
281 | { | |
282 | .name = "C7-CHT", | |
283 | .desc = "MWAIT 0x60", | |
284 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
285 | .exit_latency = 1200, | |
286 | .target_residency = 4000, | |
287 | .enter = &intel_idle, | |
288 | .enter_freeze = intel_idle_freeze, }, | |
289 | { | |
290 | .name = "C7S-CHT", | |
291 | .desc = "MWAIT 0x64", | |
292 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, | |
293 | .exit_latency = 10000, | |
294 | .target_residency = 20000, | |
295 | .enter = &intel_idle, | |
296 | .enter_freeze = intel_idle_freeze, }, | |
297 | { | |
298 | .enter = NULL } | |
299 | }; | |
300 | ||
ba0dc81e | 301 | static struct cpuidle_state ivb_cstates[] = { |
e022e7eb | 302 | { |
6edab08c LB |
303 | .name = "C1-IVB", |
304 | .desc = "MWAIT 0x00", | |
b82b6cca | 305 | .flags = MWAIT2flg(0x00), |
6edab08c LB |
306 | .exit_latency = 1, |
307 | .target_residency = 1, | |
5fe2e527 RW |
308 | .enter = &intel_idle, |
309 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
310 | { |
311 | .name = "C1E-IVB", | |
312 | .desc = "MWAIT 0x01", | |
b82b6cca | 313 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
314 | .exit_latency = 10, |
315 | .target_residency = 20, | |
5fe2e527 RW |
316 | .enter = &intel_idle, |
317 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 318 | { |
6edab08c LB |
319 | .name = "C3-IVB", |
320 | .desc = "MWAIT 0x10", | |
b82b6cca | 321 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
322 | .exit_latency = 59, |
323 | .target_residency = 156, | |
5fe2e527 RW |
324 | .enter = &intel_idle, |
325 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 326 | { |
6edab08c LB |
327 | .name = "C6-IVB", |
328 | .desc = "MWAIT 0x20", | |
b82b6cca | 329 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
330 | .exit_latency = 80, |
331 | .target_residency = 300, | |
5fe2e527 RW |
332 | .enter = &intel_idle, |
333 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 334 | { |
6edab08c LB |
335 | .name = "C7-IVB", |
336 | .desc = "MWAIT 0x30", | |
b82b6cca | 337 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
338 | .exit_latency = 87, |
339 | .target_residency = 300, | |
5fe2e527 RW |
340 | .enter = &intel_idle, |
341 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
342 | { |
343 | .enter = NULL } | |
6edab08c LB |
344 | }; |
345 | ||
0138d8f0 LB |
346 | static struct cpuidle_state ivt_cstates[] = { |
347 | { | |
348 | .name = "C1-IVT", | |
349 | .desc = "MWAIT 0x00", | |
b82b6cca | 350 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
351 | .exit_latency = 1, |
352 | .target_residency = 1, | |
5fe2e527 RW |
353 | .enter = &intel_idle, |
354 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
355 | { |
356 | .name = "C1E-IVT", | |
357 | .desc = "MWAIT 0x01", | |
b82b6cca | 358 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
359 | .exit_latency = 10, |
360 | .target_residency = 80, | |
5fe2e527 RW |
361 | .enter = &intel_idle, |
362 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
363 | { |
364 | .name = "C3-IVT", | |
365 | .desc = "MWAIT 0x10", | |
b82b6cca | 366 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
367 | .exit_latency = 59, |
368 | .target_residency = 156, | |
5fe2e527 RW |
369 | .enter = &intel_idle, |
370 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
371 | { |
372 | .name = "C6-IVT", | |
373 | .desc = "MWAIT 0x20", | |
b82b6cca | 374 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
375 | .exit_latency = 82, |
376 | .target_residency = 300, | |
5fe2e527 RW |
377 | .enter = &intel_idle, |
378 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
379 | { |
380 | .enter = NULL } | |
381 | }; | |
382 | ||
383 | static struct cpuidle_state ivt_cstates_4s[] = { | |
384 | { | |
385 | .name = "C1-IVT-4S", | |
386 | .desc = "MWAIT 0x00", | |
b82b6cca | 387 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
388 | .exit_latency = 1, |
389 | .target_residency = 1, | |
5fe2e527 RW |
390 | .enter = &intel_idle, |
391 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
392 | { |
393 | .name = "C1E-IVT-4S", | |
394 | .desc = "MWAIT 0x01", | |
b82b6cca | 395 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
396 | .exit_latency = 10, |
397 | .target_residency = 250, | |
5fe2e527 RW |
398 | .enter = &intel_idle, |
399 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
400 | { |
401 | .name = "C3-IVT-4S", | |
402 | .desc = "MWAIT 0x10", | |
b82b6cca | 403 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
404 | .exit_latency = 59, |
405 | .target_residency = 300, | |
5fe2e527 RW |
406 | .enter = &intel_idle, |
407 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
408 | { |
409 | .name = "C6-IVT-4S", | |
410 | .desc = "MWAIT 0x20", | |
b82b6cca | 411 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
412 | .exit_latency = 84, |
413 | .target_residency = 400, | |
5fe2e527 RW |
414 | .enter = &intel_idle, |
415 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
416 | { |
417 | .enter = NULL } | |
418 | }; | |
419 | ||
420 | static struct cpuidle_state ivt_cstates_8s[] = { | |
421 | { | |
422 | .name = "C1-IVT-8S", | |
423 | .desc = "MWAIT 0x00", | |
b82b6cca | 424 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
425 | .exit_latency = 1, |
426 | .target_residency = 1, | |
5fe2e527 RW |
427 | .enter = &intel_idle, |
428 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
429 | { |
430 | .name = "C1E-IVT-8S", | |
431 | .desc = "MWAIT 0x01", | |
b82b6cca | 432 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
433 | .exit_latency = 10, |
434 | .target_residency = 500, | |
5fe2e527 RW |
435 | .enter = &intel_idle, |
436 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
437 | { |
438 | .name = "C3-IVT-8S", | |
439 | .desc = "MWAIT 0x10", | |
b82b6cca | 440 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
441 | .exit_latency = 59, |
442 | .target_residency = 600, | |
5fe2e527 RW |
443 | .enter = &intel_idle, |
444 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
445 | { |
446 | .name = "C6-IVT-8S", | |
447 | .desc = "MWAIT 0x20", | |
b82b6cca | 448 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
449 | .exit_latency = 88, |
450 | .target_residency = 700, | |
5fe2e527 RW |
451 | .enter = &intel_idle, |
452 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
453 | { |
454 | .enter = NULL } | |
455 | }; | |
456 | ||
ba0dc81e | 457 | static struct cpuidle_state hsw_cstates[] = { |
e022e7eb | 458 | { |
85a4d2d4 LB |
459 | .name = "C1-HSW", |
460 | .desc = "MWAIT 0x00", | |
b82b6cca | 461 | .flags = MWAIT2flg(0x00), |
85a4d2d4 LB |
462 | .exit_latency = 2, |
463 | .target_residency = 2, | |
5fe2e527 RW |
464 | .enter = &intel_idle, |
465 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
466 | { |
467 | .name = "C1E-HSW", | |
468 | .desc = "MWAIT 0x01", | |
b82b6cca | 469 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
470 | .exit_latency = 10, |
471 | .target_residency = 20, | |
5fe2e527 RW |
472 | .enter = &intel_idle, |
473 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 474 | { |
85a4d2d4 LB |
475 | .name = "C3-HSW", |
476 | .desc = "MWAIT 0x10", | |
b82b6cca | 477 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
478 | .exit_latency = 33, |
479 | .target_residency = 100, | |
5fe2e527 RW |
480 | .enter = &intel_idle, |
481 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 482 | { |
85a4d2d4 LB |
483 | .name = "C6-HSW", |
484 | .desc = "MWAIT 0x20", | |
b82b6cca | 485 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
486 | .exit_latency = 133, |
487 | .target_residency = 400, | |
5fe2e527 RW |
488 | .enter = &intel_idle, |
489 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 490 | { |
85a4d2d4 LB |
491 | .name = "C7s-HSW", |
492 | .desc = "MWAIT 0x32", | |
b82b6cca | 493 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
494 | .exit_latency = 166, |
495 | .target_residency = 500, | |
5fe2e527 RW |
496 | .enter = &intel_idle, |
497 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb LB |
498 | { |
499 | .name = "C8-HSW", | |
500 | .desc = "MWAIT 0x40", | |
b82b6cca | 501 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
502 | .exit_latency = 300, |
503 | .target_residency = 900, | |
5fe2e527 RW |
504 | .enter = &intel_idle, |
505 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb LB |
506 | { |
507 | .name = "C9-HSW", | |
508 | .desc = "MWAIT 0x50", | |
b82b6cca | 509 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
510 | .exit_latency = 600, |
511 | .target_residency = 1800, | |
5fe2e527 RW |
512 | .enter = &intel_idle, |
513 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb LB |
514 | { |
515 | .name = "C10-HSW", | |
516 | .desc = "MWAIT 0x60", | |
b82b6cca | 517 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
518 | .exit_latency = 2600, |
519 | .target_residency = 7700, | |
5fe2e527 RW |
520 | .enter = &intel_idle, |
521 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
522 | { |
523 | .enter = NULL } | |
85a4d2d4 | 524 | }; |
a138b568 LB |
525 | static struct cpuidle_state bdw_cstates[] = { |
526 | { | |
527 | .name = "C1-BDW", | |
528 | .desc = "MWAIT 0x00", | |
b82b6cca | 529 | .flags = MWAIT2flg(0x00), |
a138b568 LB |
530 | .exit_latency = 2, |
531 | .target_residency = 2, | |
5fe2e527 RW |
532 | .enter = &intel_idle, |
533 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
534 | { |
535 | .name = "C1E-BDW", | |
536 | .desc = "MWAIT 0x01", | |
b82b6cca | 537 | .flags = MWAIT2flg(0x01), |
a138b568 LB |
538 | .exit_latency = 10, |
539 | .target_residency = 20, | |
5fe2e527 RW |
540 | .enter = &intel_idle, |
541 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
542 | { |
543 | .name = "C3-BDW", | |
544 | .desc = "MWAIT 0x10", | |
b82b6cca | 545 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
546 | .exit_latency = 40, |
547 | .target_residency = 100, | |
5fe2e527 RW |
548 | .enter = &intel_idle, |
549 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
550 | { |
551 | .name = "C6-BDW", | |
552 | .desc = "MWAIT 0x20", | |
b82b6cca | 553 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
554 | .exit_latency = 133, |
555 | .target_residency = 400, | |
5fe2e527 RW |
556 | .enter = &intel_idle, |
557 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
558 | { |
559 | .name = "C7s-BDW", | |
560 | .desc = "MWAIT 0x32", | |
b82b6cca | 561 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
562 | .exit_latency = 166, |
563 | .target_residency = 500, | |
5fe2e527 RW |
564 | .enter = &intel_idle, |
565 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
566 | { |
567 | .name = "C8-BDW", | |
568 | .desc = "MWAIT 0x40", | |
b82b6cca | 569 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
570 | .exit_latency = 300, |
571 | .target_residency = 900, | |
5fe2e527 RW |
572 | .enter = &intel_idle, |
573 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
574 | { |
575 | .name = "C9-BDW", | |
576 | .desc = "MWAIT 0x50", | |
b82b6cca | 577 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
578 | .exit_latency = 600, |
579 | .target_residency = 1800, | |
5fe2e527 RW |
580 | .enter = &intel_idle, |
581 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
582 | { |
583 | .name = "C10-BDW", | |
584 | .desc = "MWAIT 0x60", | |
b82b6cca | 585 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
586 | .exit_latency = 2600, |
587 | .target_residency = 7700, | |
5fe2e527 RW |
588 | .enter = &intel_idle, |
589 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
590 | { |
591 | .enter = NULL } | |
592 | }; | |
85a4d2d4 | 593 | |
493f133f LB |
594 | static struct cpuidle_state skl_cstates[] = { |
595 | { | |
596 | .name = "C1-SKL", | |
597 | .desc = "MWAIT 0x00", | |
598 | .flags = MWAIT2flg(0x00), | |
599 | .exit_latency = 2, | |
600 | .target_residency = 2, | |
601 | .enter = &intel_idle, | |
602 | .enter_freeze = intel_idle_freeze, }, | |
603 | { | |
604 | .name = "C1E-SKL", | |
605 | .desc = "MWAIT 0x01", | |
606 | .flags = MWAIT2flg(0x01), | |
607 | .exit_latency = 10, | |
608 | .target_residency = 20, | |
609 | .enter = &intel_idle, | |
610 | .enter_freeze = intel_idle_freeze, }, | |
611 | { | |
612 | .name = "C3-SKL", | |
613 | .desc = "MWAIT 0x10", | |
614 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | |
615 | .exit_latency = 70, | |
616 | .target_residency = 100, | |
617 | .enter = &intel_idle, | |
618 | .enter_freeze = intel_idle_freeze, }, | |
619 | { | |
620 | .name = "C6-SKL", | |
621 | .desc = "MWAIT 0x20", | |
622 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
135919a3 | 623 | .exit_latency = 85, |
493f133f LB |
624 | .target_residency = 200, |
625 | .enter = &intel_idle, | |
626 | .enter_freeze = intel_idle_freeze, }, | |
627 | { | |
628 | .name = "C7s-SKL", | |
629 | .desc = "MWAIT 0x33", | |
630 | .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED, | |
631 | .exit_latency = 124, | |
632 | .target_residency = 800, | |
633 | .enter = &intel_idle, | |
634 | .enter_freeze = intel_idle_freeze, }, | |
635 | { | |
636 | .name = "C8-SKL", | |
637 | .desc = "MWAIT 0x40", | |
638 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | |
135919a3 | 639 | .exit_latency = 200, |
493f133f LB |
640 | .target_residency = 800, |
641 | .enter = &intel_idle, | |
642 | .enter_freeze = intel_idle_freeze, }, | |
135919a3 LB |
643 | { |
644 | .name = "C9-SKL", | |
645 | .desc = "MWAIT 0x50", | |
646 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | |
647 | .exit_latency = 480, | |
648 | .target_residency = 5000, | |
649 | .enter = &intel_idle, | |
650 | .enter_freeze = intel_idle_freeze, }, | |
493f133f LB |
651 | { |
652 | .name = "C10-SKL", | |
653 | .desc = "MWAIT 0x60", | |
654 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
655 | .exit_latency = 890, | |
656 | .target_residency = 5000, | |
657 | .enter = &intel_idle, | |
658 | .enter_freeze = intel_idle_freeze, }, | |
659 | { | |
660 | .enter = NULL } | |
661 | }; | |
662 | ||
f9e71657 LB |
663 | static struct cpuidle_state skx_cstates[] = { |
664 | { | |
665 | .name = "C1-SKX", | |
666 | .desc = "MWAIT 0x00", | |
667 | .flags = MWAIT2flg(0x00), | |
668 | .exit_latency = 2, | |
669 | .target_residency = 2, | |
670 | .enter = &intel_idle, | |
671 | .enter_freeze = intel_idle_freeze, }, | |
672 | { | |
673 | .name = "C1E-SKX", | |
674 | .desc = "MWAIT 0x01", | |
675 | .flags = MWAIT2flg(0x01), | |
676 | .exit_latency = 10, | |
677 | .target_residency = 20, | |
678 | .enter = &intel_idle, | |
679 | .enter_freeze = intel_idle_freeze, }, | |
680 | { | |
681 | .name = "C6-SKX", | |
682 | .desc = "MWAIT 0x20", | |
683 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
684 | .exit_latency = 133, | |
685 | .target_residency = 600, | |
686 | .enter = &intel_idle, | |
687 | .enter_freeze = intel_idle_freeze, }, | |
688 | { | |
689 | .enter = NULL } | |
690 | }; | |
691 | ||
ba0dc81e | 692 | static struct cpuidle_state atom_cstates[] = { |
e022e7eb | 693 | { |
32e95180 | 694 | .name = "C1E-ATM", |
26717172 | 695 | .desc = "MWAIT 0x00", |
b82b6cca | 696 | .flags = MWAIT2flg(0x00), |
32e95180 LB |
697 | .exit_latency = 10, |
698 | .target_residency = 20, | |
5fe2e527 RW |
699 | .enter = &intel_idle, |
700 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 701 | { |
15e123e5 | 702 | .name = "C2-ATM", |
26717172 | 703 | .desc = "MWAIT 0x10", |
b82b6cca | 704 | .flags = MWAIT2flg(0x10), |
26717172 | 705 | .exit_latency = 20, |
26717172 | 706 | .target_residency = 80, |
5fe2e527 RW |
707 | .enter = &intel_idle, |
708 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 709 | { |
15e123e5 | 710 | .name = "C4-ATM", |
26717172 | 711 | .desc = "MWAIT 0x30", |
b82b6cca | 712 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 713 | .exit_latency = 100, |
26717172 | 714 | .target_residency = 400, |
5fe2e527 RW |
715 | .enter = &intel_idle, |
716 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 717 | { |
15e123e5 | 718 | .name = "C6-ATM", |
7fcca7d9 | 719 | .desc = "MWAIT 0x52", |
b82b6cca | 720 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
7fcca7d9 | 721 | .exit_latency = 140, |
7fcca7d9 | 722 | .target_residency = 560, |
5fe2e527 RW |
723 | .enter = &intel_idle, |
724 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
725 | { |
726 | .enter = NULL } | |
26717172 | 727 | }; |
88390996 | 728 | static struct cpuidle_state avn_cstates[] = { |
fab04b22 LB |
729 | { |
730 | .name = "C1-AVN", | |
731 | .desc = "MWAIT 0x00", | |
b82b6cca | 732 | .flags = MWAIT2flg(0x00), |
fab04b22 LB |
733 | .exit_latency = 2, |
734 | .target_residency = 2, | |
5fe2e527 RW |
735 | .enter = &intel_idle, |
736 | .enter_freeze = intel_idle_freeze, }, | |
fab04b22 LB |
737 | { |
738 | .name = "C6-AVN", | |
739 | .desc = "MWAIT 0x51", | |
b82b6cca | 740 | .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, |
fab04b22 LB |
741 | .exit_latency = 15, |
742 | .target_residency = 45, | |
5fe2e527 RW |
743 | .enter = &intel_idle, |
744 | .enter_freeze = intel_idle_freeze, }, | |
88390996 JL |
745 | { |
746 | .enter = NULL } | |
fab04b22 | 747 | }; |
281baf7a DC |
748 | static struct cpuidle_state knl_cstates[] = { |
749 | { | |
750 | .name = "C1-KNL", | |
751 | .desc = "MWAIT 0x00", | |
752 | .flags = MWAIT2flg(0x00), | |
753 | .exit_latency = 1, | |
754 | .target_residency = 2, | |
755 | .enter = &intel_idle, | |
756 | .enter_freeze = intel_idle_freeze }, | |
757 | { | |
758 | .name = "C6-KNL", | |
759 | .desc = "MWAIT 0x10", | |
760 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | |
761 | .exit_latency = 120, | |
762 | .target_residency = 500, | |
763 | .enter = &intel_idle, | |
764 | .enter_freeze = intel_idle_freeze }, | |
765 | { | |
766 | .enter = NULL } | |
767 | }; | |
26717172 | 768 | |
5dcef694 LB |
769 | static struct cpuidle_state bxt_cstates[] = { |
770 | { | |
771 | .name = "C1-BXT", | |
772 | .desc = "MWAIT 0x00", | |
773 | .flags = MWAIT2flg(0x00), | |
774 | .exit_latency = 2, | |
775 | .target_residency = 2, | |
776 | .enter = &intel_idle, | |
777 | .enter_freeze = intel_idle_freeze, }, | |
778 | { | |
779 | .name = "C1E-BXT", | |
780 | .desc = "MWAIT 0x01", | |
781 | .flags = MWAIT2flg(0x01), | |
782 | .exit_latency = 10, | |
783 | .target_residency = 20, | |
784 | .enter = &intel_idle, | |
785 | .enter_freeze = intel_idle_freeze, }, | |
786 | { | |
787 | .name = "C6-BXT", | |
788 | .desc = "MWAIT 0x20", | |
789 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
790 | .exit_latency = 133, | |
791 | .target_residency = 133, | |
792 | .enter = &intel_idle, | |
793 | .enter_freeze = intel_idle_freeze, }, | |
794 | { | |
795 | .name = "C7s-BXT", | |
796 | .desc = "MWAIT 0x31", | |
797 | .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, | |
798 | .exit_latency = 155, | |
799 | .target_residency = 155, | |
800 | .enter = &intel_idle, | |
801 | .enter_freeze = intel_idle_freeze, }, | |
802 | { | |
803 | .name = "C8-BXT", | |
804 | .desc = "MWAIT 0x40", | |
805 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | |
806 | .exit_latency = 1000, | |
807 | .target_residency = 1000, | |
808 | .enter = &intel_idle, | |
809 | .enter_freeze = intel_idle_freeze, }, | |
810 | { | |
811 | .name = "C9-BXT", | |
812 | .desc = "MWAIT 0x50", | |
813 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | |
814 | .exit_latency = 2000, | |
815 | .target_residency = 2000, | |
816 | .enter = &intel_idle, | |
817 | .enter_freeze = intel_idle_freeze, }, | |
818 | { | |
819 | .name = "C10-BXT", | |
820 | .desc = "MWAIT 0x60", | |
821 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
822 | .exit_latency = 10000, | |
823 | .target_residency = 10000, | |
824 | .enter = &intel_idle, | |
825 | .enter_freeze = intel_idle_freeze, }, | |
826 | { | |
827 | .enter = NULL } | |
828 | }; | |
829 | ||
26717172 LB |
830 | /** |
831 | * intel_idle | |
832 | * @dev: cpuidle_device | |
46bcfad7 | 833 | * @drv: cpuidle driver |
e978aa7d | 834 | * @index: index of cpuidle state |
26717172 | 835 | * |
63ff07be | 836 | * Must be called under local_irq_disable(). |
26717172 | 837 | */ |
46bcfad7 DD |
838 | static int intel_idle(struct cpuidle_device *dev, |
839 | struct cpuidle_driver *drv, int index) | |
26717172 LB |
840 | { |
841 | unsigned long ecx = 1; /* break on interrupt flag */ | |
46bcfad7 | 842 | struct cpuidle_state *state = &drv->states[index]; |
b1beab48 | 843 | unsigned long eax = flg2MWAIT(state->flags); |
26717172 | 844 | unsigned int cstate; |
26717172 LB |
845 | int cpu = smp_processor_id(); |
846 | ||
847 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
848 | ||
6110a1f4 | 849 | /* |
c8381cc3 LB |
850 | * leave_mm() to avoid costly and often unnecessary wakeups |
851 | * for flushing the user TLB's associated with the active mm. | |
6110a1f4 | 852 | */ |
c8381cc3 | 853 | if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) |
6110a1f4 SS |
854 | leave_mm(cpu); |
855 | ||
26717172 | 856 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
f6cee191 | 857 | tick_broadcast_enter(); |
26717172 | 858 | |
16824255 | 859 | mwait_idle_with_hints(eax, ecx); |
26717172 | 860 | |
26717172 | 861 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
f6cee191 | 862 | tick_broadcast_exit(); |
26717172 | 863 | |
e978aa7d | 864 | return index; |
26717172 LB |
865 | } |
866 | ||
5fe2e527 RW |
867 | /** |
868 | * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle | |
869 | * @dev: cpuidle_device | |
870 | * @drv: cpuidle driver | |
871 | * @index: state index | |
872 | */ | |
873 | static void intel_idle_freeze(struct cpuidle_device *dev, | |
874 | struct cpuidle_driver *drv, int index) | |
875 | { | |
876 | unsigned long ecx = 1; /* break on interrupt flag */ | |
877 | unsigned long eax = flg2MWAIT(drv->states[index].flags); | |
878 | ||
879 | mwait_idle_with_hints(eax, ecx); | |
880 | } | |
881 | ||
2a2d31c8 SL |
882 | static void __setup_broadcast_timer(void *arg) |
883 | { | |
76962caa | 884 | unsigned long on = (unsigned long)arg; |
2a2d31c8 | 885 | |
76962caa TG |
886 | if (on) |
887 | tick_broadcast_enable(); | |
888 | else | |
889 | tick_broadcast_disable(); | |
2a2d31c8 SL |
890 | } |
891 | ||
25ac7761 DL |
892 | static int cpu_hotplug_notify(struct notifier_block *n, |
893 | unsigned long action, void *hcpu) | |
2a2d31c8 SL |
894 | { |
895 | int hotcpu = (unsigned long)hcpu; | |
25ac7761 | 896 | struct cpuidle_device *dev; |
2a2d31c8 | 897 | |
e2401453 | 898 | switch (action & ~CPU_TASKS_FROZEN) { |
2a2d31c8 | 899 | case CPU_ONLINE: |
25ac7761 DL |
900 | |
901 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
902 | smp_call_function_single(hotcpu, __setup_broadcast_timer, | |
903 | (void *)true, 1); | |
904 | ||
905 | /* | |
906 | * Some systems can hotplug a cpu at runtime after | |
907 | * the kernel has booted, we have to initialize the | |
908 | * driver in this case | |
909 | */ | |
910 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); | |
08820546 RC |
911 | if (dev->registered) |
912 | break; | |
913 | ||
914 | if (intel_idle_cpu_init(hotcpu)) | |
915 | return NOTIFY_BAD; | |
25ac7761 | 916 | |
2a2d31c8 | 917 | break; |
2a2d31c8 SL |
918 | } |
919 | return NOTIFY_OK; | |
920 | } | |
921 | ||
25ac7761 DL |
922 | static struct notifier_block cpu_hotplug_notifier = { |
923 | .notifier_call = cpu_hotplug_notify, | |
2a2d31c8 SL |
924 | }; |
925 | ||
14796fca LB |
926 | static void auto_demotion_disable(void *dummy) |
927 | { | |
928 | unsigned long long msr_bits; | |
929 | ||
930 | rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); | |
b66b8b9a | 931 | msr_bits &= ~(icpu->auto_demotion_disable_flags); |
14796fca LB |
932 | wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); |
933 | } | |
32e95180 LB |
934 | static void c1e_promotion_disable(void *dummy) |
935 | { | |
936 | unsigned long long msr_bits; | |
937 | ||
938 | rdmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
939 | msr_bits &= ~0x2; | |
940 | wrmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
941 | } | |
14796fca | 942 | |
b66b8b9a AK |
943 | static const struct idle_cpu idle_cpu_nehalem = { |
944 | .state_table = nehalem_cstates, | |
b66b8b9a | 945 | .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, |
32e95180 | 946 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
947 | }; |
948 | ||
949 | static const struct idle_cpu idle_cpu_atom = { | |
950 | .state_table = atom_cstates, | |
951 | }; | |
952 | ||
953 | static const struct idle_cpu idle_cpu_lincroft = { | |
954 | .state_table = atom_cstates, | |
955 | .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, | |
956 | }; | |
957 | ||
958 | static const struct idle_cpu idle_cpu_snb = { | |
959 | .state_table = snb_cstates, | |
32e95180 | 960 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
961 | }; |
962 | ||
718987d6 LB |
963 | static const struct idle_cpu idle_cpu_byt = { |
964 | .state_table = byt_cstates, | |
965 | .disable_promotion_to_c1e = true, | |
8c058d53 | 966 | .byt_auto_demotion_disable_flag = true, |
718987d6 LB |
967 | }; |
968 | ||
cab07a56 LB |
969 | static const struct idle_cpu idle_cpu_cht = { |
970 | .state_table = cht_cstates, | |
971 | .disable_promotion_to_c1e = true, | |
972 | .byt_auto_demotion_disable_flag = true, | |
973 | }; | |
974 | ||
6edab08c LB |
975 | static const struct idle_cpu idle_cpu_ivb = { |
976 | .state_table = ivb_cstates, | |
32e95180 | 977 | .disable_promotion_to_c1e = true, |
6edab08c LB |
978 | }; |
979 | ||
0138d8f0 LB |
980 | static const struct idle_cpu idle_cpu_ivt = { |
981 | .state_table = ivt_cstates, | |
982 | .disable_promotion_to_c1e = true, | |
983 | }; | |
984 | ||
85a4d2d4 LB |
985 | static const struct idle_cpu idle_cpu_hsw = { |
986 | .state_table = hsw_cstates, | |
32e95180 | 987 | .disable_promotion_to_c1e = true, |
85a4d2d4 LB |
988 | }; |
989 | ||
a138b568 LB |
990 | static const struct idle_cpu idle_cpu_bdw = { |
991 | .state_table = bdw_cstates, | |
992 | .disable_promotion_to_c1e = true, | |
993 | }; | |
994 | ||
493f133f LB |
995 | static const struct idle_cpu idle_cpu_skl = { |
996 | .state_table = skl_cstates, | |
997 | .disable_promotion_to_c1e = true, | |
998 | }; | |
999 | ||
f9e71657 LB |
1000 | static const struct idle_cpu idle_cpu_skx = { |
1001 | .state_table = skx_cstates, | |
1002 | .disable_promotion_to_c1e = true, | |
1003 | }; | |
493f133f | 1004 | |
fab04b22 LB |
1005 | static const struct idle_cpu idle_cpu_avn = { |
1006 | .state_table = avn_cstates, | |
1007 | .disable_promotion_to_c1e = true, | |
1008 | }; | |
1009 | ||
281baf7a DC |
1010 | static const struct idle_cpu idle_cpu_knl = { |
1011 | .state_table = knl_cstates, | |
1012 | }; | |
1013 | ||
5dcef694 LB |
1014 | static const struct idle_cpu idle_cpu_bxt = { |
1015 | .state_table = bxt_cstates, | |
1016 | .disable_promotion_to_c1e = true, | |
1017 | }; | |
1018 | ||
b66b8b9a AK |
1019 | #define ICPU(model, cpu) \ |
1020 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | |
1021 | ||
d5cdc3c4 | 1022 | static const struct x86_cpu_id intel_idle_ids[] __initconst = { |
b66b8b9a AK |
1023 | ICPU(0x1a, idle_cpu_nehalem), |
1024 | ICPU(0x1e, idle_cpu_nehalem), | |
1025 | ICPU(0x1f, idle_cpu_nehalem), | |
8bf11938 BH |
1026 | ICPU(0x25, idle_cpu_nehalem), |
1027 | ICPU(0x2c, idle_cpu_nehalem), | |
1028 | ICPU(0x2e, idle_cpu_nehalem), | |
b66b8b9a AK |
1029 | ICPU(0x1c, idle_cpu_atom), |
1030 | ICPU(0x26, idle_cpu_lincroft), | |
8bf11938 | 1031 | ICPU(0x2f, idle_cpu_nehalem), |
b66b8b9a AK |
1032 | ICPU(0x2a, idle_cpu_snb), |
1033 | ICPU(0x2d, idle_cpu_snb), | |
acead1b0 | 1034 | ICPU(0x36, idle_cpu_atom), |
718987d6 | 1035 | ICPU(0x37, idle_cpu_byt), |
cab07a56 | 1036 | ICPU(0x4c, idle_cpu_cht), |
6edab08c | 1037 | ICPU(0x3a, idle_cpu_ivb), |
0138d8f0 | 1038 | ICPU(0x3e, idle_cpu_ivt), |
85a4d2d4 LB |
1039 | ICPU(0x3c, idle_cpu_hsw), |
1040 | ICPU(0x3f, idle_cpu_hsw), | |
1041 | ICPU(0x45, idle_cpu_hsw), | |
0b15841b | 1042 | ICPU(0x46, idle_cpu_hsw), |
a138b568 LB |
1043 | ICPU(0x4d, idle_cpu_avn), |
1044 | ICPU(0x3d, idle_cpu_bdw), | |
bea57077 | 1045 | ICPU(0x47, idle_cpu_bdw), |
a138b568 LB |
1046 | ICPU(0x4f, idle_cpu_bdw), |
1047 | ICPU(0x56, idle_cpu_bdw), | |
493f133f LB |
1048 | ICPU(0x4e, idle_cpu_skl), |
1049 | ICPU(0x5e, idle_cpu_skl), | |
3ce093d4 LB |
1050 | ICPU(0x8e, idle_cpu_skl), |
1051 | ICPU(0x9e, idle_cpu_skl), | |
f9e71657 | 1052 | ICPU(0x55, idle_cpu_skx), |
281baf7a | 1053 | ICPU(0x57, idle_cpu_knl), |
5dcef694 | 1054 | ICPU(0x5c, idle_cpu_bxt), |
b66b8b9a AK |
1055 | {} |
1056 | }; | |
1057 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); | |
1058 | ||
26717172 LB |
1059 | /* |
1060 | * intel_idle_probe() | |
1061 | */ | |
00f3e755 | 1062 | static int __init intel_idle_probe(void) |
26717172 | 1063 | { |
c4236282 | 1064 | unsigned int eax, ebx, ecx; |
b66b8b9a | 1065 | const struct x86_cpu_id *id; |
26717172 LB |
1066 | |
1067 | if (max_cstate == 0) { | |
1068 | pr_debug(PREFIX "disabled\n"); | |
1069 | return -EPERM; | |
1070 | } | |
1071 | ||
b66b8b9a AK |
1072 | id = x86_match_cpu(intel_idle_ids); |
1073 | if (!id) { | |
1074 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
1075 | boot_cpu_data.x86 == 6) | |
1076 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
1077 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
26717172 | 1078 | return -ENODEV; |
b66b8b9a | 1079 | } |
26717172 LB |
1080 | |
1081 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
1082 | return -ENODEV; | |
1083 | ||
c4236282 | 1084 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
1085 | |
1086 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
5c2a9f06 TR |
1087 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || |
1088 | !mwait_substates) | |
26717172 | 1089 | return -ENODEV; |
26717172 | 1090 | |
c4236282 | 1091 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 | 1092 | |
b66b8b9a AK |
1093 | icpu = (const struct idle_cpu *)id->driver_data; |
1094 | cpuidle_state_table = icpu->state_table; | |
26717172 LB |
1095 | |
1096 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION | |
1097 | " model 0x%X\n", boot_cpu_data.x86_model); | |
1098 | ||
26717172 LB |
1099 | return 0; |
1100 | } | |
1101 | ||
1102 | /* | |
1103 | * intel_idle_cpuidle_devices_uninit() | |
ca42489d | 1104 | * Unregisters the cpuidle devices. |
26717172 LB |
1105 | */ |
1106 | static void intel_idle_cpuidle_devices_uninit(void) | |
1107 | { | |
1108 | int i; | |
1109 | struct cpuidle_device *dev; | |
1110 | ||
1111 | for_each_online_cpu(i) { | |
1112 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
1113 | cpuidle_unregister_device(dev); | |
1114 | } | |
26717172 | 1115 | } |
0138d8f0 LB |
1116 | |
1117 | /* | |
d70e28f5 | 1118 | * ivt_idle_state_table_update(void) |
0138d8f0 | 1119 | * |
d70e28f5 | 1120 | * Tune IVT multi-socket targets |
0138d8f0 LB |
1121 | * Assumption: num_sockets == (max_package_num + 1) |
1122 | */ | |
d70e28f5 | 1123 | static void ivt_idle_state_table_update(void) |
0138d8f0 LB |
1124 | { |
1125 | /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */ | |
d70e28f5 LB |
1126 | int cpu, package_num, num_sockets = 1; |
1127 | ||
1128 | for_each_online_cpu(cpu) { | |
1129 | package_num = topology_physical_package_id(cpu); | |
1130 | if (package_num + 1 > num_sockets) { | |
1131 | num_sockets = package_num + 1; | |
1132 | ||
1133 | if (num_sockets > 4) { | |
1134 | cpuidle_state_table = ivt_cstates_8s; | |
1135 | return; | |
0138d8f0 LB |
1136 | } |
1137 | } | |
d70e28f5 LB |
1138 | } |
1139 | ||
1140 | if (num_sockets > 2) | |
1141 | cpuidle_state_table = ivt_cstates_4s; | |
1142 | ||
1143 | /* else, 1 and 2 socket systems use default ivt_cstates */ | |
1144 | } | |
5dcef694 LB |
1145 | |
1146 | /* | |
1147 | * Translate IRTL (Interrupt Response Time Limit) MSR to usec | |
1148 | */ | |
1149 | ||
1150 | static unsigned int irtl_ns_units[] = { | |
1151 | 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; | |
1152 | ||
1153 | static unsigned long long irtl_2_usec(unsigned long long irtl) | |
1154 | { | |
1155 | unsigned long long ns; | |
1156 | ||
1157 | ns = irtl_ns_units[(irtl >> 10) & 0x3]; | |
1158 | ||
1159 | return div64_u64((irtl & 0x3FF) * ns, 1000); | |
1160 | } | |
1161 | /* | |
1162 | * bxt_idle_state_table_update(void) | |
1163 | * | |
1164 | * On BXT, we trust the IRTL to show the definitive maximum latency | |
1165 | * We use the same value for target_residency. | |
1166 | */ | |
1167 | static void bxt_idle_state_table_update(void) | |
1168 | { | |
1169 | unsigned long long msr; | |
1170 | ||
1171 | rdmsrl(MSR_PKGC6_IRTL, msr); | |
1172 | if (msr) { | |
1173 | unsigned int usec = irtl_2_usec(msr); | |
1174 | ||
1175 | bxt_cstates[2].exit_latency = usec; | |
1176 | bxt_cstates[2].target_residency = usec; | |
1177 | } | |
1178 | ||
1179 | rdmsrl(MSR_PKGC7_IRTL, msr); | |
1180 | if (msr) { | |
1181 | unsigned int usec = irtl_2_usec(msr); | |
1182 | ||
1183 | bxt_cstates[3].exit_latency = usec; | |
1184 | bxt_cstates[3].target_residency = usec; | |
1185 | } | |
1186 | ||
1187 | rdmsrl(MSR_PKGC8_IRTL, msr); | |
1188 | if (msr) { | |
1189 | unsigned int usec = irtl_2_usec(msr); | |
1190 | ||
1191 | bxt_cstates[4].exit_latency = usec; | |
1192 | bxt_cstates[4].target_residency = usec; | |
1193 | } | |
1194 | ||
1195 | rdmsrl(MSR_PKGC9_IRTL, msr); | |
1196 | if (msr) { | |
1197 | unsigned int usec = irtl_2_usec(msr); | |
1198 | ||
1199 | bxt_cstates[5].exit_latency = usec; | |
1200 | bxt_cstates[5].target_residency = usec; | |
1201 | } | |
1202 | ||
1203 | rdmsrl(MSR_PKGC10_IRTL, msr); | |
1204 | if (msr) { | |
1205 | unsigned int usec = irtl_2_usec(msr); | |
1206 | ||
1207 | bxt_cstates[6].exit_latency = usec; | |
1208 | bxt_cstates[6].target_residency = usec; | |
1209 | } | |
1210 | ||
1211 | } | |
d70e28f5 LB |
1212 | /* |
1213 | * sklh_idle_state_table_update(void) | |
1214 | * | |
1215 | * On SKL-H (model 0x5e) disable C8 and C9 if: | |
1216 | * C10 is enabled and SGX disabled | |
1217 | */ | |
1218 | static void sklh_idle_state_table_update(void) | |
1219 | { | |
1220 | unsigned long long msr; | |
1221 | unsigned int eax, ebx, ecx, edx; | |
1222 | ||
1223 | ||
1224 | /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */ | |
1225 | if (max_cstate <= 7) | |
1226 | return; | |
1227 | ||
1228 | /* if PC10 not present in CPUID.MWAIT.EDX */ | |
1229 | if ((mwait_substates & (0xF << 28)) == 0) | |
1230 | return; | |
1231 | ||
1232 | rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr); | |
1233 | ||
1234 | /* PC10 is not enabled in PKG C-state limit */ | |
1235 | if ((msr & 0xF) != 8) | |
1236 | return; | |
1237 | ||
1238 | ecx = 0; | |
1239 | cpuid(7, &eax, &ebx, &ecx, &edx); | |
1240 | ||
1241 | /* if SGX is present */ | |
1242 | if (ebx & (1 << 2)) { | |
0138d8f0 | 1243 | |
d70e28f5 LB |
1244 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); |
1245 | ||
1246 | /* if SGX is enabled */ | |
1247 | if (msr & (1 << 18)) | |
1248 | return; | |
1249 | } | |
1250 | ||
1251 | skl_cstates[5].disabled = 1; /* C8-SKL */ | |
1252 | skl_cstates[6].disabled = 1; /* C9-SKL */ | |
1253 | } | |
1254 | /* | |
1255 | * intel_idle_state_table_update() | |
1256 | * | |
1257 | * Update the default state_table for this CPU-id | |
1258 | */ | |
1259 | ||
1260 | static void intel_idle_state_table_update(void) | |
1261 | { | |
1262 | switch (boot_cpu_data.x86_model) { | |
1263 | ||
1264 | case 0x3e: /* IVT */ | |
1265 | ivt_idle_state_table_update(); | |
1266 | break; | |
5dcef694 LB |
1267 | case 0x5c: /* BXT */ |
1268 | bxt_idle_state_table_update(); | |
1269 | break; | |
d70e28f5 LB |
1270 | case 0x5e: /* SKL-H */ |
1271 | sklh_idle_state_table_update(); | |
1272 | break; | |
0138d8f0 | 1273 | } |
0138d8f0 LB |
1274 | } |
1275 | ||
46bcfad7 DD |
1276 | /* |
1277 | * intel_idle_cpuidle_driver_init() | |
1278 | * allocate, initialize cpuidle_states | |
1279 | */ | |
5469c827 | 1280 | static void __init intel_idle_cpuidle_driver_init(void) |
46bcfad7 DD |
1281 | { |
1282 | int cstate; | |
1283 | struct cpuidle_driver *drv = &intel_idle_driver; | |
1284 | ||
0138d8f0 LB |
1285 | intel_idle_state_table_update(); |
1286 | ||
46bcfad7 DD |
1287 | drv->state_count = 1; |
1288 | ||
e022e7eb | 1289 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
24bfa950 | 1290 | int num_substates, mwait_hint, mwait_cstate; |
46bcfad7 | 1291 | |
7dd0e0af LB |
1292 | if ((cpuidle_state_table[cstate].enter == NULL) && |
1293 | (cpuidle_state_table[cstate].enter_freeze == NULL)) | |
e022e7eb LB |
1294 | break; |
1295 | ||
1296 | if (cstate + 1 > max_cstate) { | |
46bcfad7 DD |
1297 | printk(PREFIX "max_cstate %d reached\n", |
1298 | max_cstate); | |
1299 | break; | |
1300 | } | |
1301 | ||
e022e7eb LB |
1302 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
1303 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
e022e7eb | 1304 | |
24bfa950 | 1305 | /* number of sub-states for this state in CPUID.MWAIT */ |
e022e7eb | 1306 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
46bcfad7 | 1307 | & MWAIT_SUBSTATE_MASK; |
e022e7eb | 1308 | |
24bfa950 LB |
1309 | /* if NO sub-states for this state in CPUID, skip it */ |
1310 | if (num_substates == 0) | |
46bcfad7 | 1311 | continue; |
46bcfad7 | 1312 | |
d70e28f5 LB |
1313 | /* if state marked as disabled, skip it */ |
1314 | if (cpuidle_state_table[cstate].disabled != 0) { | |
1315 | pr_debug(PREFIX "state %s is disabled", | |
1316 | cpuidle_state_table[cstate].name); | |
1317 | continue; | |
1318 | } | |
1319 | ||
1320 | ||
e022e7eb | 1321 | if (((mwait_cstate + 1) > 2) && |
46bcfad7 DD |
1322 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
1323 | mark_tsc_unstable("TSC halts in idle" | |
1324 | " states deeper than C2"); | |
1325 | ||
1326 | drv->states[drv->state_count] = /* structure copy */ | |
1327 | cpuidle_state_table[cstate]; | |
1328 | ||
1329 | drv->state_count += 1; | |
1330 | } | |
1331 | ||
8c058d53 LB |
1332 | if (icpu->byt_auto_demotion_disable_flag) { |
1333 | wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); | |
1334 | wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); | |
1335 | } | |
46bcfad7 DD |
1336 | } |
1337 | ||
1338 | ||
26717172 | 1339 | /* |
65b7f839 | 1340 | * intel_idle_cpu_init() |
26717172 | 1341 | * allocate, initialize, register cpuidle_devices |
65b7f839 | 1342 | * @cpu: cpu/core to initialize |
26717172 | 1343 | */ |
25ac7761 | 1344 | static int intel_idle_cpu_init(int cpu) |
26717172 | 1345 | { |
26717172 LB |
1346 | struct cpuidle_device *dev; |
1347 | ||
65b7f839 | 1348 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); |
26717172 | 1349 | |
65b7f839 | 1350 | dev->cpu = cpu; |
26717172 | 1351 | |
65b7f839 TR |
1352 | if (cpuidle_register_device(dev)) { |
1353 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); | |
65b7f839 | 1354 | return -EIO; |
26717172 LB |
1355 | } |
1356 | ||
b66b8b9a | 1357 | if (icpu->auto_demotion_disable_flags) |
65b7f839 TR |
1358 | smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); |
1359 | ||
dbf87ab8 BZ |
1360 | if (icpu->disable_promotion_to_c1e) |
1361 | smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1); | |
1362 | ||
26717172 LB |
1363 | return 0; |
1364 | } | |
26717172 LB |
1365 | |
1366 | static int __init intel_idle_init(void) | |
1367 | { | |
65b7f839 | 1368 | int retval, i; |
26717172 | 1369 | |
d1896049 TR |
1370 | /* Do not load intel_idle at all for now if idle= is passed */ |
1371 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
1372 | return -ENODEV; | |
1373 | ||
26717172 LB |
1374 | retval = intel_idle_probe(); |
1375 | if (retval) | |
1376 | return retval; | |
1377 | ||
e9df69cc RC |
1378 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); |
1379 | if (intel_idle_cpuidle_devices == NULL) | |
1380 | return -ENOMEM; | |
1381 | ||
46bcfad7 | 1382 | intel_idle_cpuidle_driver_init(); |
26717172 LB |
1383 | retval = cpuidle_register_driver(&intel_idle_driver); |
1384 | if (retval) { | |
3735d524 | 1385 | struct cpuidle_driver *drv = cpuidle_get_driver(); |
26717172 | 1386 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", |
3735d524 | 1387 | drv ? drv->name : "none"); |
e9df69cc | 1388 | free_percpu(intel_idle_cpuidle_devices); |
26717172 LB |
1389 | return retval; |
1390 | } | |
1391 | ||
07494d54 SB |
1392 | cpu_notifier_register_begin(); |
1393 | ||
65b7f839 TR |
1394 | for_each_online_cpu(i) { |
1395 | retval = intel_idle_cpu_init(i); | |
1396 | if (retval) { | |
b69ef2c0 | 1397 | intel_idle_cpuidle_devices_uninit(); |
07494d54 | 1398 | cpu_notifier_register_done(); |
65b7f839 | 1399 | cpuidle_unregister_driver(&intel_idle_driver); |
ca42489d | 1400 | free_percpu(intel_idle_cpuidle_devices); |
65b7f839 TR |
1401 | return retval; |
1402 | } | |
26717172 | 1403 | } |
07494d54 SB |
1404 | __register_cpu_notifier(&cpu_hotplug_notifier); |
1405 | ||
2259a819 RC |
1406 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ |
1407 | lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; | |
1408 | else | |
1409 | on_each_cpu(__setup_broadcast_timer, (void *)true, 1); | |
1410 | ||
07494d54 | 1411 | cpu_notifier_register_done(); |
26717172 | 1412 | |
2259a819 RC |
1413 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", |
1414 | lapic_timer_reliable_states); | |
1415 | ||
26717172 LB |
1416 | return 0; |
1417 | } | |
1418 | ||
1419 | static void __exit intel_idle_exit(void) | |
1420 | { | |
3e66a9ab RC |
1421 | struct cpuidle_device *dev; |
1422 | int i; | |
1423 | ||
07494d54 | 1424 | cpu_notifier_register_begin(); |
25ac7761 DL |
1425 | |
1426 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
39a74fde | 1427 | on_each_cpu(__setup_broadcast_timer, (void *)false, 1); |
07494d54 | 1428 | __unregister_cpu_notifier(&cpu_hotplug_notifier); |
3e66a9ab RC |
1429 | |
1430 | for_each_possible_cpu(i) { | |
1431 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
1432 | cpuidle_unregister_device(dev); | |
1433 | } | |
07494d54 SB |
1434 | |
1435 | cpu_notifier_register_done(); | |
51319918 RC |
1436 | |
1437 | cpuidle_unregister_driver(&intel_idle_driver); | |
ca42489d | 1438 | free_percpu(intel_idle_cpuidle_devices); |
26717172 LB |
1439 | } |
1440 | ||
1441 | module_init(intel_idle_init); | |
1442 | module_exit(intel_idle_exit); | |
1443 | ||
26717172 | 1444 | module_param(max_cstate, int, 0444); |
26717172 LB |
1445 | |
1446 | MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); | |
1447 | MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); | |
1448 | MODULE_LICENSE("GPL"); |