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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
fab04b22 | 4 | * Copyright (c) 2013, Intel Corporation. |
26717172 LB |
5 | * Len Brown <len.brown@intel.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
49 | * There is currently no kernel-based automatic probing/loading mechanism | |
50 | * if the driver is built as a module. | |
51 | */ | |
52 | ||
53 | /* un-comment DEBUG to enable pr_debug() statements */ | |
54 | #define DEBUG | |
55 | ||
56 | #include <linux/kernel.h> | |
57 | #include <linux/cpuidle.h> | |
58 | #include <linux/clockchips.h> | |
26717172 LB |
59 | #include <trace/events/power.h> |
60 | #include <linux/sched.h> | |
2a2d31c8 SL |
61 | #include <linux/notifier.h> |
62 | #include <linux/cpu.h> | |
7c52d551 | 63 | #include <linux/module.h> |
b66b8b9a | 64 | #include <asm/cpu_device_id.h> |
bc83cccc | 65 | #include <asm/mwait.h> |
14796fca | 66 | #include <asm/msr.h> |
26717172 LB |
67 | |
68 | #define INTEL_IDLE_VERSION "0.4" | |
69 | #define PREFIX "intel_idle: " | |
70 | ||
26717172 LB |
71 | static struct cpuidle_driver intel_idle_driver = { |
72 | .name = "intel_idle", | |
73 | .owner = THIS_MODULE, | |
74 | }; | |
75 | /* intel_idle.max_cstate=0 disables driver */ | |
137ecc77 | 76 | static int max_cstate = CPUIDLE_STATE_MAX - 1; |
26717172 | 77 | |
c4236282 | 78 | static unsigned int mwait_substates; |
26717172 | 79 | |
2a2d31c8 | 80 | #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF |
26717172 | 81 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
d13780d4 | 82 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
26717172 | 83 | |
b66b8b9a AK |
84 | struct idle_cpu { |
85 | struct cpuidle_state *state_table; | |
86 | ||
87 | /* | |
88 | * Hardware C-state auto-demotion may not always be optimal. | |
89 | * Indicate which enable bits to clear here. | |
90 | */ | |
91 | unsigned long auto_demotion_disable_flags; | |
32e95180 | 92 | bool disable_promotion_to_c1e; |
b66b8b9a AK |
93 | }; |
94 | ||
95 | static const struct idle_cpu *icpu; | |
3265eba0 | 96 | static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; |
46bcfad7 DD |
97 | static int intel_idle(struct cpuidle_device *dev, |
98 | struct cpuidle_driver *drv, int index); | |
25ac7761 | 99 | static int intel_idle_cpu_init(int cpu); |
26717172 LB |
100 | |
101 | static struct cpuidle_state *cpuidle_state_table; | |
102 | ||
956d033f LB |
103 | /* |
104 | * Set this flag for states where the HW flushes the TLB for us | |
105 | * and so we don't need cross-calls to keep it consistent. | |
106 | * If this flag is set, SW flushes the TLB, so even if the | |
107 | * HW doesn't do the flushing, this flag is safe to use. | |
108 | */ | |
109 | #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 | |
110 | ||
b1beab48 LB |
111 | /* |
112 | * MWAIT takes an 8-bit "hint" in EAX "suggesting" | |
113 | * the C-state (top nibble) and sub-state (bottom nibble) | |
114 | * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. | |
115 | * | |
116 | * We store the hint at the top of our "flags" for each state. | |
117 | */ | |
118 | #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) | |
119 | #define MWAIT2flg(eax) ((eax & 0xFF) << 24) | |
120 | ||
26717172 LB |
121 | /* |
122 | * States are indexed by the cstate number, | |
123 | * which is also the index into the MWAIT hint array. | |
124 | * Thus C0 is a dummy. | |
125 | */ | |
ba0dc81e | 126 | static struct cpuidle_state nehalem_cstates[] = { |
e022e7eb | 127 | { |
15e123e5 | 128 | .name = "C1-NHM", |
26717172 | 129 | .desc = "MWAIT 0x00", |
b1beab48 | 130 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
26717172 | 131 | .exit_latency = 3, |
26717172 LB |
132 | .target_residency = 6, |
133 | .enter = &intel_idle }, | |
32e95180 LB |
134 | { |
135 | .name = "C1E-NHM", | |
136 | .desc = "MWAIT 0x01", | |
137 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
138 | .exit_latency = 10, | |
139 | .target_residency = 20, | |
140 | .enter = &intel_idle }, | |
e022e7eb | 141 | { |
15e123e5 | 142 | .name = "C3-NHM", |
26717172 | 143 | .desc = "MWAIT 0x10", |
b1beab48 | 144 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 145 | .exit_latency = 20, |
26717172 LB |
146 | .target_residency = 80, |
147 | .enter = &intel_idle }, | |
e022e7eb | 148 | { |
15e123e5 | 149 | .name = "C6-NHM", |
26717172 | 150 | .desc = "MWAIT 0x20", |
b1beab48 | 151 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 152 | .exit_latency = 200, |
26717172 LB |
153 | .target_residency = 800, |
154 | .enter = &intel_idle }, | |
e022e7eb LB |
155 | { |
156 | .enter = NULL } | |
26717172 LB |
157 | }; |
158 | ||
ba0dc81e | 159 | static struct cpuidle_state snb_cstates[] = { |
e022e7eb | 160 | { |
15e123e5 | 161 | .name = "C1-SNB", |
d13780d4 | 162 | .desc = "MWAIT 0x00", |
b1beab48 | 163 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
32e95180 LB |
164 | .exit_latency = 2, |
165 | .target_residency = 2, | |
166 | .enter = &intel_idle }, | |
167 | { | |
168 | .name = "C1E-SNB", | |
169 | .desc = "MWAIT 0x01", | |
170 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
171 | .exit_latency = 10, | |
172 | .target_residency = 20, | |
d13780d4 | 173 | .enter = &intel_idle }, |
e022e7eb | 174 | { |
15e123e5 | 175 | .name = "C3-SNB", |
d13780d4 | 176 | .desc = "MWAIT 0x10", |
b1beab48 | 177 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 178 | .exit_latency = 80, |
ddbd550d | 179 | .target_residency = 211, |
d13780d4 | 180 | .enter = &intel_idle }, |
e022e7eb | 181 | { |
15e123e5 | 182 | .name = "C6-SNB", |
d13780d4 | 183 | .desc = "MWAIT 0x20", |
b1beab48 | 184 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 185 | .exit_latency = 104, |
ddbd550d | 186 | .target_residency = 345, |
d13780d4 | 187 | .enter = &intel_idle }, |
e022e7eb | 188 | { |
15e123e5 | 189 | .name = "C7-SNB", |
d13780d4 | 190 | .desc = "MWAIT 0x30", |
b1beab48 | 191 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 192 | .exit_latency = 109, |
ddbd550d | 193 | .target_residency = 345, |
d13780d4 | 194 | .enter = &intel_idle }, |
e022e7eb LB |
195 | { |
196 | .enter = NULL } | |
d13780d4 LB |
197 | }; |
198 | ||
ba0dc81e | 199 | static struct cpuidle_state ivb_cstates[] = { |
e022e7eb | 200 | { |
6edab08c LB |
201 | .name = "C1-IVB", |
202 | .desc = "MWAIT 0x00", | |
b1beab48 | 203 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
6edab08c LB |
204 | .exit_latency = 1, |
205 | .target_residency = 1, | |
206 | .enter = &intel_idle }, | |
32e95180 LB |
207 | { |
208 | .name = "C1E-IVB", | |
209 | .desc = "MWAIT 0x01", | |
210 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
211 | .exit_latency = 10, | |
212 | .target_residency = 20, | |
213 | .enter = &intel_idle }, | |
e022e7eb | 214 | { |
6edab08c LB |
215 | .name = "C3-IVB", |
216 | .desc = "MWAIT 0x10", | |
b1beab48 | 217 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
218 | .exit_latency = 59, |
219 | .target_residency = 156, | |
220 | .enter = &intel_idle }, | |
e022e7eb | 221 | { |
6edab08c LB |
222 | .name = "C6-IVB", |
223 | .desc = "MWAIT 0x20", | |
b1beab48 | 224 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
225 | .exit_latency = 80, |
226 | .target_residency = 300, | |
227 | .enter = &intel_idle }, | |
e022e7eb | 228 | { |
6edab08c LB |
229 | .name = "C7-IVB", |
230 | .desc = "MWAIT 0x30", | |
b1beab48 | 231 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
232 | .exit_latency = 87, |
233 | .target_residency = 300, | |
234 | .enter = &intel_idle }, | |
e022e7eb LB |
235 | { |
236 | .enter = NULL } | |
6edab08c LB |
237 | }; |
238 | ||
ba0dc81e | 239 | static struct cpuidle_state hsw_cstates[] = { |
e022e7eb | 240 | { |
85a4d2d4 LB |
241 | .name = "C1-HSW", |
242 | .desc = "MWAIT 0x00", | |
243 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, | |
244 | .exit_latency = 2, | |
245 | .target_residency = 2, | |
246 | .enter = &intel_idle }, | |
32e95180 LB |
247 | { |
248 | .name = "C1E-HSW", | |
249 | .desc = "MWAIT 0x01", | |
250 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
251 | .exit_latency = 10, | |
252 | .target_residency = 20, | |
253 | .enter = &intel_idle }, | |
e022e7eb | 254 | { |
85a4d2d4 LB |
255 | .name = "C3-HSW", |
256 | .desc = "MWAIT 0x10", | |
257 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
258 | .exit_latency = 33, | |
259 | .target_residency = 100, | |
260 | .enter = &intel_idle }, | |
e022e7eb | 261 | { |
85a4d2d4 LB |
262 | .name = "C6-HSW", |
263 | .desc = "MWAIT 0x20", | |
264 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
265 | .exit_latency = 133, | |
266 | .target_residency = 400, | |
267 | .enter = &intel_idle }, | |
e022e7eb | 268 | { |
85a4d2d4 LB |
269 | .name = "C7s-HSW", |
270 | .desc = "MWAIT 0x32", | |
271 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
272 | .exit_latency = 166, | |
273 | .target_residency = 500, | |
274 | .enter = &intel_idle }, | |
86239ceb LB |
275 | { |
276 | .name = "C8-HSW", | |
277 | .desc = "MWAIT 0x40", | |
278 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
279 | .exit_latency = 300, | |
280 | .target_residency = 900, | |
281 | .enter = &intel_idle }, | |
282 | { | |
283 | .name = "C9-HSW", | |
284 | .desc = "MWAIT 0x50", | |
285 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
286 | .exit_latency = 600, | |
287 | .target_residency = 1800, | |
288 | .enter = &intel_idle }, | |
289 | { | |
290 | .name = "C10-HSW", | |
291 | .desc = "MWAIT 0x60", | |
292 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
293 | .exit_latency = 2600, | |
294 | .target_residency = 7700, | |
295 | .enter = &intel_idle }, | |
e022e7eb LB |
296 | { |
297 | .enter = NULL } | |
85a4d2d4 LB |
298 | }; |
299 | ||
ba0dc81e | 300 | static struct cpuidle_state atom_cstates[] = { |
e022e7eb | 301 | { |
32e95180 | 302 | .name = "C1E-ATM", |
26717172 | 303 | .desc = "MWAIT 0x00", |
b1beab48 | 304 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
32e95180 LB |
305 | .exit_latency = 10, |
306 | .target_residency = 20, | |
26717172 | 307 | .enter = &intel_idle }, |
e022e7eb | 308 | { |
15e123e5 | 309 | .name = "C2-ATM", |
26717172 | 310 | .desc = "MWAIT 0x10", |
b1beab48 | 311 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, |
26717172 | 312 | .exit_latency = 20, |
26717172 LB |
313 | .target_residency = 80, |
314 | .enter = &intel_idle }, | |
e022e7eb | 315 | { |
15e123e5 | 316 | .name = "C4-ATM", |
26717172 | 317 | .desc = "MWAIT 0x30", |
b1beab48 | 318 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 319 | .exit_latency = 100, |
26717172 LB |
320 | .target_residency = 400, |
321 | .enter = &intel_idle }, | |
e022e7eb | 322 | { |
15e123e5 | 323 | .name = "C6-ATM", |
7fcca7d9 | 324 | .desc = "MWAIT 0x52", |
b1beab48 | 325 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
7fcca7d9 | 326 | .exit_latency = 140, |
7fcca7d9 LB |
327 | .target_residency = 560, |
328 | .enter = &intel_idle }, | |
e022e7eb LB |
329 | { |
330 | .enter = NULL } | |
26717172 | 331 | }; |
88390996 | 332 | static struct cpuidle_state avn_cstates[] = { |
fab04b22 LB |
333 | { |
334 | .name = "C1-AVN", | |
335 | .desc = "MWAIT 0x00", | |
336 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, | |
337 | .exit_latency = 2, | |
338 | .target_residency = 2, | |
339 | .enter = &intel_idle }, | |
340 | { | |
341 | .name = "C6-AVN", | |
342 | .desc = "MWAIT 0x51", | |
22e580d0 | 343 | .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
fab04b22 LB |
344 | .exit_latency = 15, |
345 | .target_residency = 45, | |
346 | .enter = &intel_idle }, | |
88390996 JL |
347 | { |
348 | .enter = NULL } | |
fab04b22 | 349 | }; |
26717172 | 350 | |
26717172 LB |
351 | /** |
352 | * intel_idle | |
353 | * @dev: cpuidle_device | |
46bcfad7 | 354 | * @drv: cpuidle driver |
e978aa7d | 355 | * @index: index of cpuidle state |
26717172 | 356 | * |
63ff07be | 357 | * Must be called under local_irq_disable(). |
26717172 | 358 | */ |
46bcfad7 DD |
359 | static int intel_idle(struct cpuidle_device *dev, |
360 | struct cpuidle_driver *drv, int index) | |
26717172 LB |
361 | { |
362 | unsigned long ecx = 1; /* break on interrupt flag */ | |
46bcfad7 | 363 | struct cpuidle_state *state = &drv->states[index]; |
b1beab48 | 364 | unsigned long eax = flg2MWAIT(state->flags); |
26717172 | 365 | unsigned int cstate; |
26717172 LB |
366 | int cpu = smp_processor_id(); |
367 | ||
368 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
369 | ||
6110a1f4 | 370 | /* |
c8381cc3 LB |
371 | * leave_mm() to avoid costly and often unnecessary wakeups |
372 | * for flushing the user TLB's associated with the active mm. | |
6110a1f4 | 373 | */ |
c8381cc3 | 374 | if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) |
6110a1f4 SS |
375 | leave_mm(cpu); |
376 | ||
26717172 LB |
377 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
378 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
379 | ||
ea811747 | 380 | if (!current_set_polling_and_test()) { |
26717172 | 381 | |
40e2d7f9 LB |
382 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
383 | clflush((void *)¤t_thread_info()->flags); | |
384 | ||
26717172 LB |
385 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
386 | smp_mb(); | |
387 | if (!need_resched()) | |
388 | __mwait(eax, ecx); | |
389 | } | |
390 | ||
26717172 LB |
391 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
392 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
393 | ||
e978aa7d | 394 | return index; |
26717172 LB |
395 | } |
396 | ||
2a2d31c8 SL |
397 | static void __setup_broadcast_timer(void *arg) |
398 | { | |
399 | unsigned long reason = (unsigned long)arg; | |
400 | int cpu = smp_processor_id(); | |
401 | ||
402 | reason = reason ? | |
403 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
404 | ||
405 | clockevents_notify(reason, &cpu); | |
406 | } | |
407 | ||
25ac7761 DL |
408 | static int cpu_hotplug_notify(struct notifier_block *n, |
409 | unsigned long action, void *hcpu) | |
2a2d31c8 SL |
410 | { |
411 | int hotcpu = (unsigned long)hcpu; | |
25ac7761 | 412 | struct cpuidle_device *dev; |
2a2d31c8 | 413 | |
e2401453 | 414 | switch (action & ~CPU_TASKS_FROZEN) { |
2a2d31c8 | 415 | case CPU_ONLINE: |
25ac7761 DL |
416 | |
417 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
418 | smp_call_function_single(hotcpu, __setup_broadcast_timer, | |
419 | (void *)true, 1); | |
420 | ||
421 | /* | |
422 | * Some systems can hotplug a cpu at runtime after | |
423 | * the kernel has booted, we have to initialize the | |
424 | * driver in this case | |
425 | */ | |
426 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); | |
427 | if (!dev->registered) | |
428 | intel_idle_cpu_init(hotcpu); | |
429 | ||
2a2d31c8 | 430 | break; |
2a2d31c8 SL |
431 | } |
432 | return NOTIFY_OK; | |
433 | } | |
434 | ||
25ac7761 DL |
435 | static struct notifier_block cpu_hotplug_notifier = { |
436 | .notifier_call = cpu_hotplug_notify, | |
2a2d31c8 SL |
437 | }; |
438 | ||
14796fca LB |
439 | static void auto_demotion_disable(void *dummy) |
440 | { | |
441 | unsigned long long msr_bits; | |
442 | ||
443 | rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); | |
b66b8b9a | 444 | msr_bits &= ~(icpu->auto_demotion_disable_flags); |
14796fca LB |
445 | wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); |
446 | } | |
32e95180 LB |
447 | static void c1e_promotion_disable(void *dummy) |
448 | { | |
449 | unsigned long long msr_bits; | |
450 | ||
451 | rdmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
452 | msr_bits &= ~0x2; | |
453 | wrmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
454 | } | |
14796fca | 455 | |
b66b8b9a AK |
456 | static const struct idle_cpu idle_cpu_nehalem = { |
457 | .state_table = nehalem_cstates, | |
b66b8b9a | 458 | .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, |
32e95180 | 459 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
460 | }; |
461 | ||
462 | static const struct idle_cpu idle_cpu_atom = { | |
463 | .state_table = atom_cstates, | |
464 | }; | |
465 | ||
466 | static const struct idle_cpu idle_cpu_lincroft = { | |
467 | .state_table = atom_cstates, | |
468 | .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, | |
469 | }; | |
470 | ||
471 | static const struct idle_cpu idle_cpu_snb = { | |
472 | .state_table = snb_cstates, | |
32e95180 | 473 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
474 | }; |
475 | ||
6edab08c LB |
476 | static const struct idle_cpu idle_cpu_ivb = { |
477 | .state_table = ivb_cstates, | |
32e95180 | 478 | .disable_promotion_to_c1e = true, |
6edab08c LB |
479 | }; |
480 | ||
85a4d2d4 LB |
481 | static const struct idle_cpu idle_cpu_hsw = { |
482 | .state_table = hsw_cstates, | |
32e95180 | 483 | .disable_promotion_to_c1e = true, |
85a4d2d4 LB |
484 | }; |
485 | ||
fab04b22 LB |
486 | static const struct idle_cpu idle_cpu_avn = { |
487 | .state_table = avn_cstates, | |
488 | .disable_promotion_to_c1e = true, | |
489 | }; | |
490 | ||
b66b8b9a AK |
491 | #define ICPU(model, cpu) \ |
492 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | |
493 | ||
494 | static const struct x86_cpu_id intel_idle_ids[] = { | |
495 | ICPU(0x1a, idle_cpu_nehalem), | |
496 | ICPU(0x1e, idle_cpu_nehalem), | |
497 | ICPU(0x1f, idle_cpu_nehalem), | |
8bf11938 BH |
498 | ICPU(0x25, idle_cpu_nehalem), |
499 | ICPU(0x2c, idle_cpu_nehalem), | |
500 | ICPU(0x2e, idle_cpu_nehalem), | |
b66b8b9a AK |
501 | ICPU(0x1c, idle_cpu_atom), |
502 | ICPU(0x26, idle_cpu_lincroft), | |
8bf11938 | 503 | ICPU(0x2f, idle_cpu_nehalem), |
b66b8b9a AK |
504 | ICPU(0x2a, idle_cpu_snb), |
505 | ICPU(0x2d, idle_cpu_snb), | |
6edab08c | 506 | ICPU(0x3a, idle_cpu_ivb), |
23795e58 | 507 | ICPU(0x3e, idle_cpu_ivb), |
85a4d2d4 LB |
508 | ICPU(0x3c, idle_cpu_hsw), |
509 | ICPU(0x3f, idle_cpu_hsw), | |
510 | ICPU(0x45, idle_cpu_hsw), | |
0b15841b | 511 | ICPU(0x46, idle_cpu_hsw), |
fab04b22 | 512 | ICPU(0x4D, idle_cpu_avn), |
b66b8b9a AK |
513 | {} |
514 | }; | |
515 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); | |
516 | ||
26717172 LB |
517 | /* |
518 | * intel_idle_probe() | |
519 | */ | |
00f3e755 | 520 | static int __init intel_idle_probe(void) |
26717172 | 521 | { |
c4236282 | 522 | unsigned int eax, ebx, ecx; |
b66b8b9a | 523 | const struct x86_cpu_id *id; |
26717172 LB |
524 | |
525 | if (max_cstate == 0) { | |
526 | pr_debug(PREFIX "disabled\n"); | |
527 | return -EPERM; | |
528 | } | |
529 | ||
b66b8b9a AK |
530 | id = x86_match_cpu(intel_idle_ids); |
531 | if (!id) { | |
532 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
533 | boot_cpu_data.x86 == 6) | |
534 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
535 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
26717172 | 536 | return -ENODEV; |
b66b8b9a | 537 | } |
26717172 LB |
538 | |
539 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
540 | return -ENODEV; | |
541 | ||
c4236282 | 542 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
543 | |
544 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
5c2a9f06 TR |
545 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || |
546 | !mwait_substates) | |
26717172 | 547 | return -ENODEV; |
26717172 | 548 | |
c4236282 | 549 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 | 550 | |
b66b8b9a AK |
551 | icpu = (const struct idle_cpu *)id->driver_data; |
552 | cpuidle_state_table = icpu->state_table; | |
26717172 | 553 | |
56b9aea3 | 554 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ |
2a2d31c8 | 555 | lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; |
25ac7761 | 556 | else |
39a74fde | 557 | on_each_cpu(__setup_broadcast_timer, (void *)true, 1); |
25ac7761 | 558 | |
26717172 LB |
559 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION |
560 | " model 0x%X\n", boot_cpu_data.x86_model); | |
561 | ||
562 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", | |
563 | lapic_timer_reliable_states); | |
564 | return 0; | |
565 | } | |
566 | ||
567 | /* | |
568 | * intel_idle_cpuidle_devices_uninit() | |
569 | * unregister, free cpuidle_devices | |
570 | */ | |
571 | static void intel_idle_cpuidle_devices_uninit(void) | |
572 | { | |
573 | int i; | |
574 | struct cpuidle_device *dev; | |
575 | ||
576 | for_each_online_cpu(i) { | |
577 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
578 | cpuidle_unregister_device(dev); | |
579 | } | |
580 | ||
581 | free_percpu(intel_idle_cpuidle_devices); | |
582 | return; | |
583 | } | |
46bcfad7 DD |
584 | /* |
585 | * intel_idle_cpuidle_driver_init() | |
586 | * allocate, initialize cpuidle_states | |
587 | */ | |
00f3e755 | 588 | static int __init intel_idle_cpuidle_driver_init(void) |
46bcfad7 DD |
589 | { |
590 | int cstate; | |
591 | struct cpuidle_driver *drv = &intel_idle_driver; | |
592 | ||
593 | drv->state_count = 1; | |
594 | ||
e022e7eb LB |
595 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
596 | int num_substates, mwait_hint, mwait_cstate, mwait_substate; | |
46bcfad7 | 597 | |
e022e7eb LB |
598 | if (cpuidle_state_table[cstate].enter == NULL) |
599 | break; | |
600 | ||
601 | if (cstate + 1 > max_cstate) { | |
46bcfad7 DD |
602 | printk(PREFIX "max_cstate %d reached\n", |
603 | max_cstate); | |
604 | break; | |
605 | } | |
606 | ||
e022e7eb LB |
607 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
608 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
609 | mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); | |
610 | ||
46bcfad7 | 611 | /* does the state exist in CPUID.MWAIT? */ |
e022e7eb | 612 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
46bcfad7 | 613 | & MWAIT_SUBSTATE_MASK; |
e022e7eb LB |
614 | |
615 | /* if sub-state in table is not enumerated by CPUID */ | |
616 | if ((mwait_substate + 1) > num_substates) | |
46bcfad7 | 617 | continue; |
46bcfad7 | 618 | |
e022e7eb | 619 | if (((mwait_cstate + 1) > 2) && |
46bcfad7 DD |
620 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
621 | mark_tsc_unstable("TSC halts in idle" | |
622 | " states deeper than C2"); | |
623 | ||
624 | drv->states[drv->state_count] = /* structure copy */ | |
625 | cpuidle_state_table[cstate]; | |
626 | ||
627 | drv->state_count += 1; | |
628 | } | |
629 | ||
b66b8b9a | 630 | if (icpu->auto_demotion_disable_flags) |
39a74fde | 631 | on_each_cpu(auto_demotion_disable, NULL, 1); |
46bcfad7 | 632 | |
32e95180 LB |
633 | if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ |
634 | on_each_cpu(c1e_promotion_disable, NULL, 1); | |
635 | ||
46bcfad7 DD |
636 | return 0; |
637 | } | |
638 | ||
639 | ||
26717172 | 640 | /* |
65b7f839 | 641 | * intel_idle_cpu_init() |
26717172 | 642 | * allocate, initialize, register cpuidle_devices |
65b7f839 | 643 | * @cpu: cpu/core to initialize |
26717172 | 644 | */ |
25ac7761 | 645 | static int intel_idle_cpu_init(int cpu) |
26717172 | 646 | { |
65b7f839 | 647 | int cstate; |
26717172 LB |
648 | struct cpuidle_device *dev; |
649 | ||
65b7f839 | 650 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); |
26717172 | 651 | |
65b7f839 | 652 | dev->state_count = 1; |
26717172 | 653 | |
e022e7eb LB |
654 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
655 | int num_substates, mwait_hint, mwait_cstate, mwait_substate; | |
26717172 | 656 | |
e022e7eb | 657 | if (cpuidle_state_table[cstate].enter == NULL) |
eba682a5 | 658 | break; |
e022e7eb LB |
659 | |
660 | if (cstate + 1 > max_cstate) { | |
dc716e96 | 661 | printk(PREFIX "max_cstate %d reached\n", max_cstate); |
65b7f839 TR |
662 | break; |
663 | } | |
26717172 | 664 | |
e022e7eb LB |
665 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
666 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
667 | mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); | |
668 | ||
65b7f839 | 669 | /* does the state exist in CPUID.MWAIT? */ |
e022e7eb LB |
670 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
671 | & MWAIT_SUBSTATE_MASK; | |
672 | ||
673 | /* if sub-state in table is not enumerated by CPUID */ | |
674 | if ((mwait_substate + 1) > num_substates) | |
65b7f839 | 675 | continue; |
26717172 | 676 | |
dc716e96 MPS |
677 | dev->state_count += 1; |
678 | } | |
679 | ||
65b7f839 | 680 | dev->cpu = cpu; |
26717172 | 681 | |
65b7f839 TR |
682 | if (cpuidle_register_device(dev)) { |
683 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); | |
684 | intel_idle_cpuidle_devices_uninit(); | |
685 | return -EIO; | |
26717172 LB |
686 | } |
687 | ||
b66b8b9a | 688 | if (icpu->auto_demotion_disable_flags) |
65b7f839 TR |
689 | smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); |
690 | ||
26717172 LB |
691 | return 0; |
692 | } | |
26717172 LB |
693 | |
694 | static int __init intel_idle_init(void) | |
695 | { | |
65b7f839 | 696 | int retval, i; |
26717172 | 697 | |
d1896049 TR |
698 | /* Do not load intel_idle at all for now if idle= is passed */ |
699 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
700 | return -ENODEV; | |
701 | ||
26717172 LB |
702 | retval = intel_idle_probe(); |
703 | if (retval) | |
704 | return retval; | |
705 | ||
46bcfad7 | 706 | intel_idle_cpuidle_driver_init(); |
26717172 LB |
707 | retval = cpuidle_register_driver(&intel_idle_driver); |
708 | if (retval) { | |
3735d524 | 709 | struct cpuidle_driver *drv = cpuidle_get_driver(); |
26717172 | 710 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", |
3735d524 | 711 | drv ? drv->name : "none"); |
26717172 LB |
712 | return retval; |
713 | } | |
714 | ||
65b7f839 TR |
715 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); |
716 | if (intel_idle_cpuidle_devices == NULL) | |
717 | return -ENOMEM; | |
718 | ||
719 | for_each_online_cpu(i) { | |
720 | retval = intel_idle_cpu_init(i); | |
721 | if (retval) { | |
722 | cpuidle_unregister_driver(&intel_idle_driver); | |
723 | return retval; | |
724 | } | |
26717172 | 725 | } |
6f8c2e79 | 726 | register_cpu_notifier(&cpu_hotplug_notifier); |
26717172 LB |
727 | |
728 | return 0; | |
729 | } | |
730 | ||
731 | static void __exit intel_idle_exit(void) | |
732 | { | |
733 | intel_idle_cpuidle_devices_uninit(); | |
734 | cpuidle_unregister_driver(&intel_idle_driver); | |
735 | ||
25ac7761 DL |
736 | |
737 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
39a74fde | 738 | on_each_cpu(__setup_broadcast_timer, (void *)false, 1); |
25ac7761 | 739 | unregister_cpu_notifier(&cpu_hotplug_notifier); |
2a2d31c8 | 740 | |
26717172 LB |
741 | return; |
742 | } | |
743 | ||
744 | module_init(intel_idle_init); | |
745 | module_exit(intel_idle_exit); | |
746 | ||
26717172 | 747 | module_param(max_cstate, int, 0444); |
26717172 LB |
748 | |
749 | MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); | |
750 | MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); | |
751 | MODULE_LICENSE("GPL"); |