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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
4 | * Copyright (c) 2010, Intel Corporation. | |
5 | * Len Brown <len.brown@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
49 | * There is currently no kernel-based automatic probing/loading mechanism | |
50 | * if the driver is built as a module. | |
51 | */ | |
52 | ||
53 | /* un-comment DEBUG to enable pr_debug() statements */ | |
54 | #define DEBUG | |
55 | ||
56 | #include <linux/kernel.h> | |
57 | #include <linux/cpuidle.h> | |
58 | #include <linux/clockchips.h> | |
26717172 LB |
59 | #include <trace/events/power.h> |
60 | #include <linux/sched.h> | |
2a2d31c8 SL |
61 | #include <linux/notifier.h> |
62 | #include <linux/cpu.h> | |
7c52d551 | 63 | #include <linux/module.h> |
b66b8b9a | 64 | #include <asm/cpu_device_id.h> |
bc83cccc | 65 | #include <asm/mwait.h> |
14796fca | 66 | #include <asm/msr.h> |
26717172 LB |
67 | |
68 | #define INTEL_IDLE_VERSION "0.4" | |
69 | #define PREFIX "intel_idle: " | |
70 | ||
26717172 LB |
71 | static struct cpuidle_driver intel_idle_driver = { |
72 | .name = "intel_idle", | |
73 | .owner = THIS_MODULE, | |
a474a515 | 74 | .en_core_tk_irqen = 1, |
26717172 LB |
75 | }; |
76 | /* intel_idle.max_cstate=0 disables driver */ | |
137ecc77 | 77 | static int max_cstate = CPUIDLE_STATE_MAX - 1; |
26717172 | 78 | |
c4236282 | 79 | static unsigned int mwait_substates; |
26717172 | 80 | |
2a2d31c8 | 81 | #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF |
26717172 | 82 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
d13780d4 | 83 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
26717172 | 84 | |
b66b8b9a AK |
85 | struct idle_cpu { |
86 | struct cpuidle_state *state_table; | |
87 | ||
88 | /* | |
89 | * Hardware C-state auto-demotion may not always be optimal. | |
90 | * Indicate which enable bits to clear here. | |
91 | */ | |
92 | unsigned long auto_demotion_disable_flags; | |
32e95180 | 93 | bool disable_promotion_to_c1e; |
b66b8b9a AK |
94 | }; |
95 | ||
96 | static const struct idle_cpu *icpu; | |
3265eba0 | 97 | static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; |
46bcfad7 DD |
98 | static int intel_idle(struct cpuidle_device *dev, |
99 | struct cpuidle_driver *drv, int index); | |
25ac7761 | 100 | static int intel_idle_cpu_init(int cpu); |
26717172 LB |
101 | |
102 | static struct cpuidle_state *cpuidle_state_table; | |
103 | ||
956d033f LB |
104 | /* |
105 | * Set this flag for states where the HW flushes the TLB for us | |
106 | * and so we don't need cross-calls to keep it consistent. | |
107 | * If this flag is set, SW flushes the TLB, so even if the | |
108 | * HW doesn't do the flushing, this flag is safe to use. | |
109 | */ | |
110 | #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 | |
111 | ||
b1beab48 LB |
112 | /* |
113 | * MWAIT takes an 8-bit "hint" in EAX "suggesting" | |
114 | * the C-state (top nibble) and sub-state (bottom nibble) | |
115 | * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. | |
116 | * | |
117 | * We store the hint at the top of our "flags" for each state. | |
118 | */ | |
119 | #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) | |
120 | #define MWAIT2flg(eax) ((eax & 0xFF) << 24) | |
121 | ||
26717172 LB |
122 | /* |
123 | * States are indexed by the cstate number, | |
124 | * which is also the index into the MWAIT hint array. | |
125 | * Thus C0 is a dummy. | |
126 | */ | |
137ecc77 | 127 | static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 128 | { |
15e123e5 | 129 | .name = "C1-NHM", |
26717172 | 130 | .desc = "MWAIT 0x00", |
b1beab48 | 131 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
26717172 | 132 | .exit_latency = 3, |
26717172 LB |
133 | .target_residency = 6, |
134 | .enter = &intel_idle }, | |
32e95180 LB |
135 | { |
136 | .name = "C1E-NHM", | |
137 | .desc = "MWAIT 0x01", | |
138 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
139 | .exit_latency = 10, | |
140 | .target_residency = 20, | |
141 | .enter = &intel_idle }, | |
e022e7eb | 142 | { |
15e123e5 | 143 | .name = "C3-NHM", |
26717172 | 144 | .desc = "MWAIT 0x10", |
b1beab48 | 145 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 146 | .exit_latency = 20, |
26717172 LB |
147 | .target_residency = 80, |
148 | .enter = &intel_idle }, | |
e022e7eb | 149 | { |
15e123e5 | 150 | .name = "C6-NHM", |
26717172 | 151 | .desc = "MWAIT 0x20", |
b1beab48 | 152 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 153 | .exit_latency = 200, |
26717172 LB |
154 | .target_residency = 800, |
155 | .enter = &intel_idle }, | |
e022e7eb LB |
156 | { |
157 | .enter = NULL } | |
26717172 LB |
158 | }; |
159 | ||
137ecc77 | 160 | static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 161 | { |
15e123e5 | 162 | .name = "C1-SNB", |
d13780d4 | 163 | .desc = "MWAIT 0x00", |
b1beab48 | 164 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
32e95180 LB |
165 | .exit_latency = 2, |
166 | .target_residency = 2, | |
167 | .enter = &intel_idle }, | |
168 | { | |
169 | .name = "C1E-SNB", | |
170 | .desc = "MWAIT 0x01", | |
171 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
172 | .exit_latency = 10, | |
173 | .target_residency = 20, | |
d13780d4 | 174 | .enter = &intel_idle }, |
e022e7eb | 175 | { |
15e123e5 | 176 | .name = "C3-SNB", |
d13780d4 | 177 | .desc = "MWAIT 0x10", |
b1beab48 | 178 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 179 | .exit_latency = 80, |
ddbd550d | 180 | .target_residency = 211, |
d13780d4 | 181 | .enter = &intel_idle }, |
e022e7eb | 182 | { |
15e123e5 | 183 | .name = "C6-SNB", |
d13780d4 | 184 | .desc = "MWAIT 0x20", |
b1beab48 | 185 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 186 | .exit_latency = 104, |
ddbd550d | 187 | .target_residency = 345, |
d13780d4 | 188 | .enter = &intel_idle }, |
e022e7eb | 189 | { |
15e123e5 | 190 | .name = "C7-SNB", |
d13780d4 | 191 | .desc = "MWAIT 0x30", |
b1beab48 | 192 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 193 | .exit_latency = 109, |
ddbd550d | 194 | .target_residency = 345, |
d13780d4 | 195 | .enter = &intel_idle }, |
e022e7eb LB |
196 | { |
197 | .enter = NULL } | |
d13780d4 LB |
198 | }; |
199 | ||
137ecc77 | 200 | static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 201 | { |
6edab08c LB |
202 | .name = "C1-IVB", |
203 | .desc = "MWAIT 0x00", | |
b1beab48 | 204 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
6edab08c LB |
205 | .exit_latency = 1, |
206 | .target_residency = 1, | |
207 | .enter = &intel_idle }, | |
32e95180 LB |
208 | { |
209 | .name = "C1E-IVB", | |
210 | .desc = "MWAIT 0x01", | |
211 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
212 | .exit_latency = 10, | |
213 | .target_residency = 20, | |
214 | .enter = &intel_idle }, | |
e022e7eb | 215 | { |
6edab08c LB |
216 | .name = "C3-IVB", |
217 | .desc = "MWAIT 0x10", | |
b1beab48 | 218 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
219 | .exit_latency = 59, |
220 | .target_residency = 156, | |
221 | .enter = &intel_idle }, | |
e022e7eb | 222 | { |
6edab08c LB |
223 | .name = "C6-IVB", |
224 | .desc = "MWAIT 0x20", | |
b1beab48 | 225 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
226 | .exit_latency = 80, |
227 | .target_residency = 300, | |
228 | .enter = &intel_idle }, | |
e022e7eb | 229 | { |
6edab08c LB |
230 | .name = "C7-IVB", |
231 | .desc = "MWAIT 0x30", | |
b1beab48 | 232 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
233 | .exit_latency = 87, |
234 | .target_residency = 300, | |
235 | .enter = &intel_idle }, | |
e022e7eb LB |
236 | { |
237 | .enter = NULL } | |
6edab08c LB |
238 | }; |
239 | ||
137ecc77 | 240 | static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 241 | { |
85a4d2d4 LB |
242 | .name = "C1-HSW", |
243 | .desc = "MWAIT 0x00", | |
244 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, | |
245 | .exit_latency = 2, | |
246 | .target_residency = 2, | |
247 | .enter = &intel_idle }, | |
32e95180 LB |
248 | { |
249 | .name = "C1E-HSW", | |
250 | .desc = "MWAIT 0x01", | |
251 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
252 | .exit_latency = 10, | |
253 | .target_residency = 20, | |
254 | .enter = &intel_idle }, | |
e022e7eb | 255 | { |
85a4d2d4 LB |
256 | .name = "C3-HSW", |
257 | .desc = "MWAIT 0x10", | |
258 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
259 | .exit_latency = 33, | |
260 | .target_residency = 100, | |
261 | .enter = &intel_idle }, | |
e022e7eb | 262 | { |
85a4d2d4 LB |
263 | .name = "C6-HSW", |
264 | .desc = "MWAIT 0x20", | |
265 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
266 | .exit_latency = 133, | |
267 | .target_residency = 400, | |
268 | .enter = &intel_idle }, | |
e022e7eb | 269 | { |
85a4d2d4 LB |
270 | .name = "C7s-HSW", |
271 | .desc = "MWAIT 0x32", | |
272 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
273 | .exit_latency = 166, | |
274 | .target_residency = 500, | |
275 | .enter = &intel_idle }, | |
e022e7eb LB |
276 | { |
277 | .enter = NULL } | |
85a4d2d4 LB |
278 | }; |
279 | ||
137ecc77 | 280 | static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 281 | { |
32e95180 | 282 | .name = "C1E-ATM", |
26717172 | 283 | .desc = "MWAIT 0x00", |
b1beab48 | 284 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
32e95180 LB |
285 | .exit_latency = 10, |
286 | .target_residency = 20, | |
26717172 | 287 | .enter = &intel_idle }, |
e022e7eb | 288 | { |
15e123e5 | 289 | .name = "C2-ATM", |
26717172 | 290 | .desc = "MWAIT 0x10", |
b1beab48 | 291 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, |
26717172 | 292 | .exit_latency = 20, |
26717172 LB |
293 | .target_residency = 80, |
294 | .enter = &intel_idle }, | |
e022e7eb | 295 | { |
15e123e5 | 296 | .name = "C4-ATM", |
26717172 | 297 | .desc = "MWAIT 0x30", |
b1beab48 | 298 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 299 | .exit_latency = 100, |
26717172 LB |
300 | .target_residency = 400, |
301 | .enter = &intel_idle }, | |
e022e7eb | 302 | { |
15e123e5 | 303 | .name = "C6-ATM", |
7fcca7d9 | 304 | .desc = "MWAIT 0x52", |
b1beab48 | 305 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
7fcca7d9 | 306 | .exit_latency = 140, |
7fcca7d9 LB |
307 | .target_residency = 560, |
308 | .enter = &intel_idle }, | |
e022e7eb LB |
309 | { |
310 | .enter = NULL } | |
26717172 LB |
311 | }; |
312 | ||
26717172 LB |
313 | /** |
314 | * intel_idle | |
315 | * @dev: cpuidle_device | |
46bcfad7 | 316 | * @drv: cpuidle driver |
e978aa7d | 317 | * @index: index of cpuidle state |
26717172 | 318 | * |
63ff07be | 319 | * Must be called under local_irq_disable(). |
26717172 | 320 | */ |
46bcfad7 DD |
321 | static int intel_idle(struct cpuidle_device *dev, |
322 | struct cpuidle_driver *drv, int index) | |
26717172 LB |
323 | { |
324 | unsigned long ecx = 1; /* break on interrupt flag */ | |
46bcfad7 | 325 | struct cpuidle_state *state = &drv->states[index]; |
b1beab48 | 326 | unsigned long eax = flg2MWAIT(state->flags); |
26717172 | 327 | unsigned int cstate; |
26717172 LB |
328 | int cpu = smp_processor_id(); |
329 | ||
330 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
331 | ||
6110a1f4 | 332 | /* |
c8381cc3 LB |
333 | * leave_mm() to avoid costly and often unnecessary wakeups |
334 | * for flushing the user TLB's associated with the active mm. | |
6110a1f4 | 335 | */ |
c8381cc3 | 336 | if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) |
6110a1f4 SS |
337 | leave_mm(cpu); |
338 | ||
26717172 LB |
339 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
340 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
341 | ||
26717172 | 342 | stop_critical_timings(); |
26717172 LB |
343 | if (!need_resched()) { |
344 | ||
345 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
346 | smp_mb(); | |
347 | if (!need_resched()) | |
348 | __mwait(eax, ecx); | |
349 | } | |
350 | ||
351 | start_critical_timings(); | |
352 | ||
26717172 LB |
353 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
354 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
355 | ||
e978aa7d | 356 | return index; |
26717172 LB |
357 | } |
358 | ||
2a2d31c8 SL |
359 | static void __setup_broadcast_timer(void *arg) |
360 | { | |
361 | unsigned long reason = (unsigned long)arg; | |
362 | int cpu = smp_processor_id(); | |
363 | ||
364 | reason = reason ? | |
365 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
366 | ||
367 | clockevents_notify(reason, &cpu); | |
368 | } | |
369 | ||
25ac7761 DL |
370 | static int cpu_hotplug_notify(struct notifier_block *n, |
371 | unsigned long action, void *hcpu) | |
2a2d31c8 SL |
372 | { |
373 | int hotcpu = (unsigned long)hcpu; | |
25ac7761 | 374 | struct cpuidle_device *dev; |
2a2d31c8 SL |
375 | |
376 | switch (action & 0xf) { | |
377 | case CPU_ONLINE: | |
25ac7761 DL |
378 | |
379 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
380 | smp_call_function_single(hotcpu, __setup_broadcast_timer, | |
381 | (void *)true, 1); | |
382 | ||
383 | /* | |
384 | * Some systems can hotplug a cpu at runtime after | |
385 | * the kernel has booted, we have to initialize the | |
386 | * driver in this case | |
387 | */ | |
388 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); | |
389 | if (!dev->registered) | |
390 | intel_idle_cpu_init(hotcpu); | |
391 | ||
2a2d31c8 | 392 | break; |
2a2d31c8 SL |
393 | } |
394 | return NOTIFY_OK; | |
395 | } | |
396 | ||
25ac7761 DL |
397 | static struct notifier_block cpu_hotplug_notifier = { |
398 | .notifier_call = cpu_hotplug_notify, | |
2a2d31c8 SL |
399 | }; |
400 | ||
14796fca LB |
401 | static void auto_demotion_disable(void *dummy) |
402 | { | |
403 | unsigned long long msr_bits; | |
404 | ||
405 | rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); | |
b66b8b9a | 406 | msr_bits &= ~(icpu->auto_demotion_disable_flags); |
14796fca LB |
407 | wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); |
408 | } | |
32e95180 LB |
409 | static void c1e_promotion_disable(void *dummy) |
410 | { | |
411 | unsigned long long msr_bits; | |
412 | ||
413 | rdmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
414 | msr_bits &= ~0x2; | |
415 | wrmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
416 | } | |
14796fca | 417 | |
b66b8b9a AK |
418 | static const struct idle_cpu idle_cpu_nehalem = { |
419 | .state_table = nehalem_cstates, | |
b66b8b9a | 420 | .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, |
32e95180 | 421 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
422 | }; |
423 | ||
424 | static const struct idle_cpu idle_cpu_atom = { | |
425 | .state_table = atom_cstates, | |
426 | }; | |
427 | ||
428 | static const struct idle_cpu idle_cpu_lincroft = { | |
429 | .state_table = atom_cstates, | |
430 | .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, | |
431 | }; | |
432 | ||
433 | static const struct idle_cpu idle_cpu_snb = { | |
434 | .state_table = snb_cstates, | |
32e95180 | 435 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
436 | }; |
437 | ||
6edab08c LB |
438 | static const struct idle_cpu idle_cpu_ivb = { |
439 | .state_table = ivb_cstates, | |
32e95180 | 440 | .disable_promotion_to_c1e = true, |
6edab08c LB |
441 | }; |
442 | ||
85a4d2d4 LB |
443 | static const struct idle_cpu idle_cpu_hsw = { |
444 | .state_table = hsw_cstates, | |
32e95180 | 445 | .disable_promotion_to_c1e = true, |
85a4d2d4 LB |
446 | }; |
447 | ||
b66b8b9a AK |
448 | #define ICPU(model, cpu) \ |
449 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | |
450 | ||
451 | static const struct x86_cpu_id intel_idle_ids[] = { | |
452 | ICPU(0x1a, idle_cpu_nehalem), | |
453 | ICPU(0x1e, idle_cpu_nehalem), | |
454 | ICPU(0x1f, idle_cpu_nehalem), | |
8bf11938 BH |
455 | ICPU(0x25, idle_cpu_nehalem), |
456 | ICPU(0x2c, idle_cpu_nehalem), | |
457 | ICPU(0x2e, idle_cpu_nehalem), | |
b66b8b9a AK |
458 | ICPU(0x1c, idle_cpu_atom), |
459 | ICPU(0x26, idle_cpu_lincroft), | |
8bf11938 | 460 | ICPU(0x2f, idle_cpu_nehalem), |
b66b8b9a AK |
461 | ICPU(0x2a, idle_cpu_snb), |
462 | ICPU(0x2d, idle_cpu_snb), | |
6edab08c | 463 | ICPU(0x3a, idle_cpu_ivb), |
23795e58 | 464 | ICPU(0x3e, idle_cpu_ivb), |
85a4d2d4 LB |
465 | ICPU(0x3c, idle_cpu_hsw), |
466 | ICPU(0x3f, idle_cpu_hsw), | |
467 | ICPU(0x45, idle_cpu_hsw), | |
0b15841b | 468 | ICPU(0x46, idle_cpu_hsw), |
b66b8b9a AK |
469 | {} |
470 | }; | |
471 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); | |
472 | ||
26717172 LB |
473 | /* |
474 | * intel_idle_probe() | |
475 | */ | |
476 | static int intel_idle_probe(void) | |
477 | { | |
c4236282 | 478 | unsigned int eax, ebx, ecx; |
b66b8b9a | 479 | const struct x86_cpu_id *id; |
26717172 LB |
480 | |
481 | if (max_cstate == 0) { | |
482 | pr_debug(PREFIX "disabled\n"); | |
483 | return -EPERM; | |
484 | } | |
485 | ||
b66b8b9a AK |
486 | id = x86_match_cpu(intel_idle_ids); |
487 | if (!id) { | |
488 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
489 | boot_cpu_data.x86 == 6) | |
490 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
491 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
26717172 | 492 | return -ENODEV; |
b66b8b9a | 493 | } |
26717172 LB |
494 | |
495 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
496 | return -ENODEV; | |
497 | ||
c4236282 | 498 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
499 | |
500 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
5c2a9f06 TR |
501 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || |
502 | !mwait_substates) | |
26717172 | 503 | return -ENODEV; |
26717172 | 504 | |
c4236282 | 505 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 | 506 | |
b66b8b9a AK |
507 | icpu = (const struct idle_cpu *)id->driver_data; |
508 | cpuidle_state_table = icpu->state_table; | |
26717172 | 509 | |
56b9aea3 | 510 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ |
2a2d31c8 | 511 | lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; |
25ac7761 | 512 | else |
39a74fde | 513 | on_each_cpu(__setup_broadcast_timer, (void *)true, 1); |
25ac7761 | 514 | |
26717172 LB |
515 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION |
516 | " model 0x%X\n", boot_cpu_data.x86_model); | |
517 | ||
518 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", | |
519 | lapic_timer_reliable_states); | |
520 | return 0; | |
521 | } | |
522 | ||
523 | /* | |
524 | * intel_idle_cpuidle_devices_uninit() | |
525 | * unregister, free cpuidle_devices | |
526 | */ | |
527 | static void intel_idle_cpuidle_devices_uninit(void) | |
528 | { | |
529 | int i; | |
530 | struct cpuidle_device *dev; | |
531 | ||
532 | for_each_online_cpu(i) { | |
533 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
534 | cpuidle_unregister_device(dev); | |
535 | } | |
536 | ||
537 | free_percpu(intel_idle_cpuidle_devices); | |
538 | return; | |
539 | } | |
46bcfad7 DD |
540 | /* |
541 | * intel_idle_cpuidle_driver_init() | |
542 | * allocate, initialize cpuidle_states | |
543 | */ | |
544 | static int intel_idle_cpuidle_driver_init(void) | |
545 | { | |
546 | int cstate; | |
547 | struct cpuidle_driver *drv = &intel_idle_driver; | |
548 | ||
549 | drv->state_count = 1; | |
550 | ||
e022e7eb LB |
551 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
552 | int num_substates, mwait_hint, mwait_cstate, mwait_substate; | |
46bcfad7 | 553 | |
e022e7eb LB |
554 | if (cpuidle_state_table[cstate].enter == NULL) |
555 | break; | |
556 | ||
557 | if (cstate + 1 > max_cstate) { | |
46bcfad7 DD |
558 | printk(PREFIX "max_cstate %d reached\n", |
559 | max_cstate); | |
560 | break; | |
561 | } | |
562 | ||
e022e7eb LB |
563 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
564 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
565 | mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); | |
566 | ||
46bcfad7 | 567 | /* does the state exist in CPUID.MWAIT? */ |
e022e7eb | 568 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
46bcfad7 | 569 | & MWAIT_SUBSTATE_MASK; |
e022e7eb LB |
570 | |
571 | /* if sub-state in table is not enumerated by CPUID */ | |
572 | if ((mwait_substate + 1) > num_substates) | |
46bcfad7 | 573 | continue; |
46bcfad7 | 574 | |
e022e7eb | 575 | if (((mwait_cstate + 1) > 2) && |
46bcfad7 DD |
576 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
577 | mark_tsc_unstable("TSC halts in idle" | |
578 | " states deeper than C2"); | |
579 | ||
580 | drv->states[drv->state_count] = /* structure copy */ | |
581 | cpuidle_state_table[cstate]; | |
582 | ||
583 | drv->state_count += 1; | |
584 | } | |
585 | ||
b66b8b9a | 586 | if (icpu->auto_demotion_disable_flags) |
39a74fde | 587 | on_each_cpu(auto_demotion_disable, NULL, 1); |
46bcfad7 | 588 | |
32e95180 LB |
589 | if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ |
590 | on_each_cpu(c1e_promotion_disable, NULL, 1); | |
591 | ||
46bcfad7 DD |
592 | return 0; |
593 | } | |
594 | ||
595 | ||
26717172 | 596 | /* |
65b7f839 | 597 | * intel_idle_cpu_init() |
26717172 | 598 | * allocate, initialize, register cpuidle_devices |
65b7f839 | 599 | * @cpu: cpu/core to initialize |
26717172 | 600 | */ |
25ac7761 | 601 | static int intel_idle_cpu_init(int cpu) |
26717172 | 602 | { |
65b7f839 | 603 | int cstate; |
26717172 LB |
604 | struct cpuidle_device *dev; |
605 | ||
65b7f839 | 606 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); |
26717172 | 607 | |
65b7f839 | 608 | dev->state_count = 1; |
26717172 | 609 | |
e022e7eb LB |
610 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
611 | int num_substates, mwait_hint, mwait_cstate, mwait_substate; | |
26717172 | 612 | |
e022e7eb LB |
613 | if (cpuidle_state_table[cstate].enter == NULL) |
614 | continue; | |
615 | ||
616 | if (cstate + 1 > max_cstate) { | |
dc716e96 | 617 | printk(PREFIX "max_cstate %d reached\n", max_cstate); |
65b7f839 TR |
618 | break; |
619 | } | |
26717172 | 620 | |
e022e7eb LB |
621 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
622 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
623 | mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); | |
624 | ||
65b7f839 | 625 | /* does the state exist in CPUID.MWAIT? */ |
e022e7eb LB |
626 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
627 | & MWAIT_SUBSTATE_MASK; | |
628 | ||
629 | /* if sub-state in table is not enumerated by CPUID */ | |
630 | if ((mwait_substate + 1) > num_substates) | |
65b7f839 | 631 | continue; |
26717172 | 632 | |
dc716e96 MPS |
633 | dev->state_count += 1; |
634 | } | |
635 | ||
65b7f839 | 636 | dev->cpu = cpu; |
26717172 | 637 | |
65b7f839 TR |
638 | if (cpuidle_register_device(dev)) { |
639 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); | |
640 | intel_idle_cpuidle_devices_uninit(); | |
641 | return -EIO; | |
26717172 LB |
642 | } |
643 | ||
b66b8b9a | 644 | if (icpu->auto_demotion_disable_flags) |
65b7f839 TR |
645 | smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); |
646 | ||
26717172 LB |
647 | return 0; |
648 | } | |
26717172 LB |
649 | |
650 | static int __init intel_idle_init(void) | |
651 | { | |
65b7f839 | 652 | int retval, i; |
26717172 | 653 | |
d1896049 TR |
654 | /* Do not load intel_idle at all for now if idle= is passed */ |
655 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
656 | return -ENODEV; | |
657 | ||
26717172 LB |
658 | retval = intel_idle_probe(); |
659 | if (retval) | |
660 | return retval; | |
661 | ||
46bcfad7 | 662 | intel_idle_cpuidle_driver_init(); |
26717172 LB |
663 | retval = cpuidle_register_driver(&intel_idle_driver); |
664 | if (retval) { | |
3735d524 | 665 | struct cpuidle_driver *drv = cpuidle_get_driver(); |
26717172 | 666 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", |
3735d524 | 667 | drv ? drv->name : "none"); |
26717172 LB |
668 | return retval; |
669 | } | |
670 | ||
65b7f839 TR |
671 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); |
672 | if (intel_idle_cpuidle_devices == NULL) | |
673 | return -ENOMEM; | |
674 | ||
675 | for_each_online_cpu(i) { | |
676 | retval = intel_idle_cpu_init(i); | |
677 | if (retval) { | |
678 | cpuidle_unregister_driver(&intel_idle_driver); | |
679 | return retval; | |
680 | } | |
26717172 | 681 | } |
6f8c2e79 | 682 | register_cpu_notifier(&cpu_hotplug_notifier); |
26717172 LB |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
687 | static void __exit intel_idle_exit(void) | |
688 | { | |
689 | intel_idle_cpuidle_devices_uninit(); | |
690 | cpuidle_unregister_driver(&intel_idle_driver); | |
691 | ||
25ac7761 DL |
692 | |
693 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
39a74fde | 694 | on_each_cpu(__setup_broadcast_timer, (void *)false, 1); |
25ac7761 | 695 | unregister_cpu_notifier(&cpu_hotplug_notifier); |
2a2d31c8 | 696 | |
26717172 LB |
697 | return; |
698 | } | |
699 | ||
700 | module_init(intel_idle_init); | |
701 | module_exit(intel_idle_exit); | |
702 | ||
26717172 | 703 | module_param(max_cstate, int, 0444); |
26717172 LB |
704 | |
705 | MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); | |
706 | MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); | |
707 | MODULE_LICENSE("GPL"); |