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1 | /* |
2 | * dv1394-private.h - DV input/output over IEEE 1394 on OHCI chips | |
3 | * Copyright (C)2001 Daniel Maas <dmaas@dcine.com> | |
4 | * receive by Dan Dennedy <dan@dennedy.org> | |
5 | * | |
6 | * based on: | |
7 | * video1394.h - driver for OHCI 1394 boards | |
8 | * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> | |
9 | * Peter Schlaile <udbz@rz.uni-karlsruhe.de> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software Foundation, | |
23 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
24 | */ | |
25 | ||
26 | #ifndef _DV_1394_PRIVATE_H | |
27 | #define _DV_1394_PRIVATE_H | |
28 | ||
29 | #include "ieee1394.h" | |
30 | #include "ohci1394.h" | |
31 | #include "dma.h" | |
32 | ||
33 | /* data structures private to the dv1394 driver */ | |
34 | /* none of this is exposed to user-space */ | |
35 | ||
36 | ||
37 | /* | |
38 | the 8-byte CIP (Common Isochronous Packet) header that precedes | |
39 | each packet of DV data. | |
40 | ||
41 | See the IEC 61883 standard. | |
42 | */ | |
43 | ||
44 | struct CIP_header { unsigned char b[8]; }; | |
45 | ||
46 | static inline void fill_cip_header(struct CIP_header *cip, | |
47 | unsigned char source_node_id, | |
48 | unsigned long counter, | |
49 | enum pal_or_ntsc format, | |
50 | unsigned long timestamp) | |
51 | { | |
52 | cip->b[0] = source_node_id; | |
53 | cip->b[1] = 0x78; /* packet size in quadlets (480/4) - even for empty packets! */ | |
54 | cip->b[2] = 0x00; | |
55 | cip->b[3] = counter; | |
56 | ||
57 | cip->b[4] = 0x80; /* const */ | |
58 | ||
59 | switch(format) { | |
60 | case DV1394_PAL: | |
61 | cip->b[5] = 0x80; | |
62 | break; | |
63 | case DV1394_NTSC: | |
64 | cip->b[5] = 0x00; | |
65 | break; | |
66 | } | |
67 | ||
68 | cip->b[6] = timestamp >> 8; | |
69 | cip->b[7] = timestamp & 0xFF; | |
70 | } | |
71 | ||
72 | ||
73 | ||
74 | /* | |
75 | DMA commands used to program the OHCI's DMA engine | |
76 | ||
77 | See the Texas Instruments OHCI 1394 chipset documentation. | |
78 | */ | |
79 | ||
80 | struct output_more_immediate { u32 q[8]; }; | |
81 | struct output_more { u32 q[4]; }; | |
82 | struct output_last { u32 q[4]; }; | |
83 | struct input_more { u32 q[4]; }; | |
84 | struct input_last { u32 q[4]; }; | |
85 | ||
86 | /* outputs */ | |
87 | ||
88 | static inline void fill_output_more_immediate(struct output_more_immediate *omi, | |
89 | unsigned char tag, | |
90 | unsigned char channel, | |
91 | unsigned char sync_tag, | |
92 | unsigned int payload_size) | |
93 | { | |
94 | omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */ | |
95 | omi->q[1] = 0; | |
96 | omi->q[2] = 0; | |
97 | omi->q[3] = 0; | |
98 | ||
99 | /* IT packet header */ | |
100 | omi->q[4] = cpu_to_le32( (0x0 << 16) /* IEEE1394_SPEED_100 */ | |
101 | | (tag << 14) | |
102 | | (channel << 8) | |
103 | | (TCODE_ISO_DATA << 4) | |
104 | | (sync_tag) ); | |
105 | ||
106 | /* reserved field; mimic behavior of my Sony DSR-40 */ | |
107 | omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0); | |
108 | ||
109 | omi->q[6] = 0; | |
110 | omi->q[7] = 0; | |
111 | } | |
112 | ||
113 | static inline void fill_output_more(struct output_more *om, | |
114 | unsigned int data_size, | |
115 | unsigned long data_phys_addr) | |
116 | { | |
117 | om->q[0] = cpu_to_le32(data_size); | |
118 | om->q[1] = cpu_to_le32(data_phys_addr); | |
119 | om->q[2] = 0; | |
120 | om->q[3] = 0; | |
121 | } | |
122 | ||
123 | static inline void fill_output_last(struct output_last *ol, | |
124 | int want_timestamp, | |
125 | int want_interrupt, | |
126 | unsigned int data_size, | |
127 | unsigned long data_phys_addr) | |
128 | { | |
129 | u32 temp = 0; | |
130 | temp |= 1 << 28; /* OUTPUT_LAST */ | |
131 | ||
132 | if (want_timestamp) /* controller will update timestamp at DMA time */ | |
133 | temp |= 1 << 27; | |
134 | ||
135 | if (want_interrupt) | |
136 | temp |= 3 << 20; | |
137 | ||
138 | temp |= 3 << 18; /* must take branch */ | |
139 | temp |= data_size; | |
140 | ||
141 | ol->q[0] = cpu_to_le32(temp); | |
142 | ol->q[1] = cpu_to_le32(data_phys_addr); | |
143 | ol->q[2] = 0; | |
144 | ol->q[3] = 0; | |
145 | } | |
146 | ||
147 | /* inputs */ | |
148 | ||
149 | static inline void fill_input_more(struct input_more *im, | |
150 | int want_interrupt, | |
151 | unsigned int data_size, | |
152 | unsigned long data_phys_addr) | |
153 | { | |
154 | u32 temp = 2 << 28; /* INPUT_MORE */ | |
155 | temp |= 8 << 24; /* s = 1, update xferStatus and resCount */ | |
156 | if (want_interrupt) | |
157 | temp |= 0 << 20; /* interrupts, i=0 in packet-per-buffer mode */ | |
158 | temp |= 0x0 << 16; /* disable branch to address for packet-per-buffer mode */ | |
159 | /* disable wait on sync field, not used in DV :-( */ | |
160 | temp |= data_size; | |
161 | ||
162 | im->q[0] = cpu_to_le32(temp); | |
163 | im->q[1] = cpu_to_le32(data_phys_addr); | |
164 | im->q[2] = 0; /* branchAddress and Z not use in packet-per-buffer mode */ | |
165 | im->q[3] = 0; /* xferStatus & resCount, resCount must be initialize to data_size */ | |
166 | } | |
167 | ||
168 | static inline void fill_input_last(struct input_last *il, | |
169 | int want_interrupt, | |
170 | unsigned int data_size, | |
171 | unsigned long data_phys_addr) | |
172 | { | |
173 | u32 temp = 3 << 28; /* INPUT_LAST */ | |
174 | temp |= 8 << 24; /* s = 1, update xferStatus and resCount */ | |
175 | if (want_interrupt) | |
176 | temp |= 3 << 20; /* enable interrupts */ | |
177 | temp |= 0xC << 16; /* enable branch to address */ | |
178 | /* disable wait on sync field, not used in DV :-( */ | |
179 | temp |= data_size; | |
180 | ||
181 | il->q[0] = cpu_to_le32(temp); | |
182 | il->q[1] = cpu_to_le32(data_phys_addr); | |
183 | il->q[2] = cpu_to_le32(1); /* branchAddress (filled in later) and Z = 1 descriptor in next block */ | |
184 | il->q[3] = cpu_to_le32(data_size); /* xferStatus & resCount, resCount must be initialize to data_size */ | |
185 | } | |
186 | ||
187 | ||
188 | ||
189 | /* | |
190 | A "DMA descriptor block" consists of several contiguous DMA commands. | |
191 | struct DMA_descriptor_block encapsulates all of the commands necessary | |
192 | to send one packet of DV data. | |
193 | ||
194 | There are three different types of these blocks: | |
195 | ||
196 | 1) command to send an empty packet (CIP header only, no DV data): | |
197 | ||
198 | OUTPUT_MORE-Immediate <-- contains the iso header in-line | |
199 | OUTPUT_LAST <-- points to the CIP header | |
200 | ||
201 | 2) command to send a full packet when the DV data payload does NOT | |
202 | cross a page boundary: | |
203 | ||
204 | OUTPUT_MORE-Immediate <-- contains the iso header in-line | |
205 | OUTPUT_MORE <-- points to the CIP header | |
206 | OUTPUT_LAST <-- points to entire DV data payload | |
207 | ||
208 | 3) command to send a full packet when the DV payload DOES cross | |
209 | a page boundary: | |
210 | ||
211 | OUTPUT_MORE-Immediate <-- contains the iso header in-line | |
212 | OUTPUT_MORE <-- points to the CIP header | |
213 | OUTPUT_MORE <-- points to first part of DV data payload | |
214 | OUTPUT_LAST <-- points to second part of DV data payload | |
215 | ||
216 | This struct describes all three block types using unions. | |
217 | ||
218 | !!! It is vital that an even number of these descriptor blocks fit on one | |
219 | page of memory, since a block cannot cross a page boundary !!! | |
220 | ||
221 | */ | |
222 | ||
223 | struct DMA_descriptor_block { | |
224 | ||
225 | union { | |
226 | struct { | |
227 | /* iso header, common to all output block types */ | |
228 | struct output_more_immediate omi; | |
229 | ||
230 | union { | |
231 | /* empty packet */ | |
232 | struct { | |
233 | struct output_last ol; /* CIP header */ | |
234 | } empty; | |
235 | ||
236 | /* full packet */ | |
237 | struct { | |
238 | struct output_more om; /* CIP header */ | |
239 | ||
240 | union { | |
241 | /* payload does not cross page boundary */ | |
242 | struct { | |
243 | struct output_last ol; /* data payload */ | |
244 | } nocross; | |
245 | ||
246 | /* payload crosses page boundary */ | |
247 | struct { | |
248 | struct output_more om; /* data payload */ | |
249 | struct output_last ol; /* data payload */ | |
250 | } cross; | |
251 | } u; | |
252 | ||
253 | } full; | |
254 | } u; | |
255 | } out; | |
256 | ||
257 | struct { | |
258 | struct input_last il; | |
259 | } in; | |
260 | ||
261 | } u; | |
262 | ||
263 | /* ensure that PAGE_SIZE % sizeof(struct DMA_descriptor_block) == 0 | |
264 | by padding out to 128 bytes */ | |
265 | u32 __pad__[12]; | |
266 | }; | |
267 | ||
268 | ||
269 | /* struct frame contains all data associated with one frame in the | |
270 | ringbuffer these are allocated when the DMA context is initialized | |
271 | do_dv1394_init(). They are re-used after the card finishes | |
272 | transmitting the frame. */ | |
273 | ||
274 | struct video_card; /* forward declaration */ | |
275 | ||
276 | struct frame { | |
277 | ||
278 | /* points to the struct video_card that owns this frame */ | |
279 | struct video_card *video; | |
280 | ||
281 | /* index of this frame in video_card->frames[] */ | |
282 | unsigned int frame_num; | |
283 | ||
284 | /* FRAME_CLEAR - DMA program not set up, waiting for data | |
285 | FRAME_READY - DMA program written, ready to transmit | |
286 | ||
287 | Changes to these should be locked against the interrupt | |
288 | */ | |
289 | enum { | |
290 | FRAME_CLEAR = 0, | |
291 | FRAME_READY | |
292 | } state; | |
293 | ||
294 | /* whether this frame has been DMA'ed already; used only from | |
295 | the IRQ handler to determine whether the frame can be reset */ | |
296 | int done; | |
297 | ||
298 | ||
299 | /* kernel virtual pointer to the start of this frame's data in | |
300 | the user ringbuffer. Use only for CPU access; to get the DMA | |
301 | bus address you must go through the video->user_dma mapping */ | |
302 | unsigned long data; | |
303 | ||
304 | /* Max # of packets per frame */ | |
305 | #define MAX_PACKETS 500 | |
306 | ||
307 | ||
308 | /* a PAGE_SIZE memory pool for allocating CIP headers | |
309 | !header_pool must be aligned to PAGE_SIZE! */ | |
310 | struct CIP_header *header_pool; | |
311 | dma_addr_t header_pool_dma; | |
312 | ||
313 | ||
314 | /* a physically contiguous memory pool for allocating DMA | |
315 | descriptor blocks; usually around 64KB in size | |
316 | !descriptor_pool must be aligned to PAGE_SIZE! */ | |
317 | struct DMA_descriptor_block *descriptor_pool; | |
318 | dma_addr_t descriptor_pool_dma; | |
319 | unsigned long descriptor_pool_size; | |
320 | ||
321 | ||
322 | /* # of packets allocated for this frame */ | |
323 | unsigned int n_packets; | |
324 | ||
325 | ||
326 | /* below are several pointers (kernel virtual addresses, not | |
327 | DMA bus addresses) to parts of the DMA program. These are | |
328 | set each time the DMA program is written in | |
329 | frame_prepare(). They are used later on, e.g. from the | |
330 | interrupt handler, to check the status of the frame */ | |
331 | ||
332 | /* points to status/timestamp field of first DMA packet */ | |
333 | /* (we'll check it later to monitor timestamp accuracy) */ | |
334 | u32 *frame_begin_timestamp; | |
335 | ||
336 | /* the timestamp we assigned to the first packet in the frame */ | |
337 | u32 assigned_timestamp; | |
338 | ||
339 | /* pointer to the first packet's CIP header (where the timestamp goes) */ | |
340 | struct CIP_header *cip_syt1; | |
341 | ||
342 | /* pointer to the second packet's CIP header | |
343 | (only set if the first packet was empty) */ | |
344 | struct CIP_header *cip_syt2; | |
345 | ||
346 | /* in order to figure out what caused an interrupt, | |
347 | store pointers to the status fields of the two packets | |
348 | that can cause interrupts. We'll check these from the | |
349 | interrupt handler. | |
350 | */ | |
351 | u32 *mid_frame_timestamp; | |
352 | u32 *frame_end_timestamp; | |
353 | ||
354 | /* branch address field of final packet. This is effectively | |
355 | the "tail" in the chain of DMA descriptor blocks. | |
356 | We will fill it with the address of the first DMA descriptor | |
357 | block in the subsequent frame, once it is ready. | |
358 | */ | |
359 | u32 *frame_end_branch; | |
360 | ||
361 | /* the number of descriptors in the first descriptor block | |
362 | of the frame. Needed to start DMA */ | |
363 | int first_n_descriptors; | |
364 | }; | |
365 | ||
366 | ||
367 | struct packet { | |
368 | u16 timestamp; | |
369 | u16 invalid; | |
370 | u16 iso_header; | |
371 | u16 data_length; | |
372 | u32 cip_h1; | |
373 | u32 cip_h2; | |
374 | unsigned char data[480]; | |
375 | unsigned char padding[16]; /* force struct size =512 for page alignment */ | |
376 | }; | |
377 | ||
378 | ||
379 | /* allocate/free a frame */ | |
380 | static struct frame* frame_new(unsigned int frame_num, struct video_card *video); | |
381 | static void frame_delete(struct frame *f); | |
382 | ||
383 | /* reset f so that it can be used again */ | |
384 | static void frame_reset(struct frame *f); | |
385 | ||
386 | /* struct video_card contains all data associated with one instance | |
387 | of the dv1394 driver | |
388 | */ | |
389 | enum modes { | |
390 | MODE_RECEIVE, | |
391 | MODE_TRANSMIT | |
392 | }; | |
393 | ||
394 | struct video_card { | |
395 | ||
396 | /* ohci card to which this instance corresponds */ | |
397 | struct ti_ohci *ohci; | |
398 | ||
399 | /* OHCI card id; the link between the VFS inode and a specific video_card | |
400 | (essentially the device minor number) */ | |
401 | int id; | |
402 | ||
403 | /* entry in dv1394_cards */ | |
404 | struct list_head list; | |
405 | ||
406 | /* OHCI card IT DMA context number, -1 if not in use */ | |
407 | int ohci_it_ctx; | |
408 | struct ohci1394_iso_tasklet it_tasklet; | |
409 | ||
410 | /* register offsets for current IT DMA context, 0 if not in use */ | |
411 | u32 ohci_IsoXmitContextControlSet; | |
412 | u32 ohci_IsoXmitContextControlClear; | |
413 | u32 ohci_IsoXmitCommandPtr; | |
414 | ||
415 | /* OHCI card IR DMA context number, -1 if not in use */ | |
416 | struct ohci1394_iso_tasklet ir_tasklet; | |
417 | int ohci_ir_ctx; | |
418 | ||
419 | /* register offsets for current IR DMA context, 0 if not in use */ | |
420 | u32 ohci_IsoRcvContextControlSet; | |
421 | u32 ohci_IsoRcvContextControlClear; | |
422 | u32 ohci_IsoRcvCommandPtr; | |
423 | u32 ohci_IsoRcvContextMatch; | |
424 | ||
425 | ||
426 | /* CONCURRENCY CONTROL */ | |
427 | ||
428 | /* there are THREE levels of locking associated with video_card. */ | |
429 | ||
430 | /* | |
431 | 1) the 'open' flag - this prevents more than one process from | |
432 | opening the device. (the driver currently assumes only one opener). | |
433 | This is a regular int, but use test_and_set_bit() (on bit zero) | |
434 | for atomicity. | |
435 | */ | |
436 | unsigned long open; | |
437 | ||
438 | /* | |
439 | 2) the spinlock - this provides mutual exclusion between the interrupt | |
440 | handler and process-context operations. Generally you must take the | |
441 | spinlock under the following conditions: | |
442 | 1) DMA (and hence the interrupt handler) may be running | |
443 | AND | |
444 | 2) you need to operate on the video_card, especially active_frame | |
445 | ||
446 | It is OK to play with video_card without taking the spinlock if | |
447 | you are certain that DMA is not running. Even if DMA is running, | |
448 | it is OK to *read* active_frame with the lock, then drop it | |
449 | immediately. This is safe because the interrupt handler will never | |
450 | advance active_frame onto a frame that is not READY (and the spinlock | |
451 | must be held while marking a frame READY). | |
452 | ||
453 | spinlock is also used to protect ohci_it_ctx and ohci_ir_ctx, | |
454 | which can be accessed from both process and interrupt context | |
455 | */ | |
456 | spinlock_t spinlock; | |
457 | ||
458 | /* flag to prevent spurious interrupts (which OHCI seems to | |
459 | generate a lot :) from accessing the struct */ | |
460 | int dma_running; | |
461 | ||
462 | /* | |
438bd525 | 463 | 3) the sleeping mutex 'mtx' - this is used from process context only, |
1da177e4 LT |
464 | to serialize various operations on the video_card. Even though only one |
465 | open() is allowed, we still need to prevent multiple threads of execution | |
466 | from entering calls like read, write, ioctl, etc. | |
467 | ||
468 | I honestly can't think of a good reason to use dv1394 from several threads | |
469 | at once, but we need to serialize anyway to prevent oopses =). | |
470 | ||
438bd525 | 471 | NOTE: if you need both spinlock and mtx, take mtx first to avoid deadlock! |
1da177e4 | 472 | */ |
438bd525 | 473 | struct mutex mtx; |
1da177e4 LT |
474 | |
475 | /* people waiting for buffer space, please form a line here... */ | |
476 | wait_queue_head_t waitq; | |
477 | ||
478 | /* support asynchronous I/O signals (SIGIO) */ | |
479 | struct fasync_struct *fasync; | |
480 | ||
481 | /* the large, non-contiguous (rvmalloc()) ringbuffer for DV | |
482 | data, exposed to user-space via mmap() */ | |
483 | unsigned long dv_buf_size; | |
484 | struct dma_region dv_buf; | |
485 | ||
486 | /* next byte in the ringbuffer that a write() call will fill */ | |
487 | size_t write_off; | |
488 | ||
489 | struct frame *frames[DV1394_MAX_FRAMES]; | |
490 | ||
491 | /* n_frames also serves as an indicator that this struct video_card is | |
492 | initialized and ready to run DMA buffers */ | |
493 | ||
494 | int n_frames; | |
495 | ||
496 | /* this is the frame that is currently "owned" by the OHCI DMA controller | |
497 | (set to -1 iff DMA is not running) | |
498 | ||
499 | ! must lock against the interrupt handler when accessing it ! | |
500 | ||
501 | RULES: | |
502 | ||
503 | Only the interrupt handler may change active_frame if DMA | |
504 | is running; if not, process may change it | |
505 | ||
506 | If the next frame is READY, the interrupt handler will advance | |
507 | active_frame when the current frame is finished. | |
508 | ||
509 | If the next frame is CLEAR, the interrupt handler will re-transmit | |
510 | the current frame, and the dropped_frames counter will be incremented. | |
511 | ||
512 | The interrupt handler will NEVER advance active_frame to a | |
513 | frame that is not READY. | |
514 | */ | |
515 | int active_frame; | |
516 | int first_run; | |
517 | ||
518 | /* the same locking rules apply to these three fields also: */ | |
519 | ||
520 | /* altered ONLY from process context. Must check first_clear_frame->state; | |
521 | if it's READY, that means the ringbuffer is full with READY frames; | |
522 | if it's CLEAR, that means one or more ringbuffer frames are CLEAR */ | |
523 | unsigned int first_clear_frame; | |
524 | ||
525 | /* altered both by process and interrupt */ | |
526 | unsigned int n_clear_frames; | |
527 | ||
528 | /* only altered by the interrupt */ | |
529 | unsigned int dropped_frames; | |
530 | ||
531 | ||
532 | ||
533 | /* the CIP accumulator and continuity counter are properties | |
534 | of the DMA stream as a whole (not a single frame), so they | |
535 | are stored here in the video_card */ | |
536 | ||
537 | unsigned long cip_accum; | |
538 | unsigned long cip_n, cip_d; | |
539 | unsigned int syt_offset; | |
540 | unsigned int continuity_counter; | |
541 | ||
542 | enum pal_or_ntsc pal_or_ntsc; | |
543 | ||
544 | /* redundant, but simplifies the code somewhat */ | |
545 | unsigned int frame_size; /* in bytes */ | |
546 | ||
547 | /* the isochronous channel to use, -1 if video card is inactive */ | |
548 | int channel; | |
549 | ||
550 | ||
551 | /* physically contiguous packet ringbuffer for receive */ | |
552 | struct dma_region packet_buf; | |
553 | unsigned long packet_buf_size; | |
554 | ||
555 | unsigned int current_packet; | |
556 | int first_frame; /* received first start frame marker? */ | |
557 | enum modes mode; | |
558 | }; | |
559 | ||
560 | /* | |
561 | if the video_card is not initialized, then the ONLY fields that are valid are: | |
562 | ohci | |
563 | open | |
564 | n_frames | |
565 | */ | |
566 | ||
567 | static inline int video_card_initialized(struct video_card *v) | |
568 | { | |
569 | return v->n_frames > 0; | |
570 | } | |
571 | ||
572 | static int do_dv1394_init(struct video_card *video, struct dv1394_init *init); | |
573 | static int do_dv1394_init_default(struct video_card *video); | |
574 | static void do_dv1394_shutdown(struct video_card *video, int free_user_buf); | |
575 | ||
576 | ||
577 | /* NTSC empty packet rate accurate to within 0.01%, | |
578 | calibrated against a Sony DSR-40 DVCAM deck */ | |
579 | ||
580 | #define CIP_N_NTSC 68000000 | |
581 | #define CIP_D_NTSC 1068000000 | |
582 | ||
583 | #define CIP_N_PAL 1 | |
584 | #define CIP_D_PAL 16 | |
585 | ||
586 | #endif /* _DV_1394_PRIVATE_H */ | |
587 |