[deliverable/linux.git] / drivers / ieee1394 / pcilynx.h

#ifndef __PCILYNX_H__
#define __PCILYNX_H__

#include <linux/config.h>

#define PCILYNX_DRIVER_NAME      "pcilynx"
#define PCILYNX_MAJOR            177

#define PCILYNX_MINOR_AUX_START  0
#define PCILYNX_MINOR_ROM_START  16
#define PCILYNX_MINOR_RAM_START  32

#define PCILYNX_MAX_REGISTER     0xfff
#define PCILYNX_MAX_MEMORY       0xffff

#define PCI_DEVICE_ID_TI_PCILYNX 0x8000
#define MAX_PCILYNX_CARDS        4
#define LOCALRAM_SIZE            4096

#define NUM_ISORCV_PCL           4
#define MAX_ISORCV_SIZE          2048
#define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
#define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)

#define CHANNEL_LOCALBUS         0
#define CHANNEL_ASYNC_RCV        1
#define CHANNEL_ISO_RCV          2
#define CHANNEL_ASYNC_SEND       3
#define CHANNEL_ISO_SEND         4

#define PCILYNX_CONFIG_ROM_LENGTH   1024

typedef int pcl_t;

struct ti_lynx {
        int id; /* sequential card number */

        spinlock_t lock;

        struct pci_dev *dev;

        struct {
                unsigned reg_1394a:1;
                u32 vendor;
                u32 product;
        } phyic;

        enum { clear, have_intr, have_aux_buf, have_pcl_mem,
               have_1394_buffers, have_iomappings, is_host } state;

        /* remapped memory spaces */
        void __iomem *registers;
        void __iomem *local_rom;
        void __iomem *local_ram;
        void __iomem *aux_port;
	quadlet_t bus_info_block[5];

        /*
         * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
         * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
         * the following is an allocation bitmap
         */
        u8 pcl_bmap[LOCALRAM_SIZE / 1024];

	/* point to PCLs memory area if needed */
	void *pcl_mem;
        dma_addr_t pcl_mem_dma;

        /* PCLs for local mem / aux transfers */
        pcl_t dmem_pcl;

        /* IEEE-1394 part follows */
        struct hpsb_host *host;

        int phyid, isroot;
        int selfid_size;
        int phy_reg0;

        spinlock_t phy_reg_lock;

        pcl_t rcv_pcl_start, rcv_pcl;
        void *rcv_page;
        dma_addr_t rcv_page_dma;
        int rcv_active;

        struct lynx_send_data {
                pcl_t pcl_start, pcl;
                struct list_head queue;
                struct list_head pcl_queue; /* this queue contains at most one packet */
                spinlock_t queue_lock;
                dma_addr_t header_dma, data_dma;
                int channel;
        } async, iso_send;

        struct {
                pcl_t pcl[NUM_ISORCV_PCL];
                u32 stat[NUM_ISORCV_PCL];
                void *page[ISORCV_PAGES];
                dma_addr_t page_dma[ISORCV_PAGES];
                pcl_t pcl_start;
                int chan_count;
                int next, last, used, running;
                struct tasklet_struct tq;
                spinlock_t lock;
        } iso_rcv;

	u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
};

/* the per-file data structure for mem space access */
struct memdata {
        struct ti_lynx *lynx;
        int cid;
        atomic_t aux_intr_last_seen;
	/* enum values are the same as LBUS_ADDR_SEL_* values below */
        enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
};


/*
 * Register read and write helper functions.
 */
static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
{
        writel(data, lynx->registers + offset);
}

static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
{
        return readl(lynx->registers + offset);
}

static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
                                u32 mask)
{
        reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
}

static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
                                  u32 mask)
{
        reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
}


/* chip register definitions follow */

#define PCI_LATENCY_CACHELINE             0x0c

#define MISC_CONTROL                      0x40
#define MISC_CONTROL_SWRESET              (1<<0)

#define SERIAL_EEPROM_CONTROL             0x44

#define PCI_INT_STATUS                    0x48
#define PCI_INT_ENABLE                    0x4c
/* status and enable have identical bit numbers */
#define PCI_INT_INT_PEND                  (1<<31)
#define PCI_INT_FORCED_INT                (1<<30)
#define PCI_INT_SLV_ADR_PERR              (1<<28)
#define PCI_INT_SLV_DAT_PERR              (1<<27)
#define PCI_INT_MST_DAT_PERR              (1<<26)
#define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
#define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
#define PCI_INT_AUX_TIMEOUT               (1<<18)
#define PCI_INT_AUX_INT                   (1<<17)
#define PCI_INT_1394                      (1<<16)
#define PCI_INT_DMA4_PCL                  (1<<9)
#define PCI_INT_DMA4_HLT                  (1<<8)
#define PCI_INT_DMA3_PCL                  (1<<7)
#define PCI_INT_DMA3_HLT                  (1<<6)
#define PCI_INT_DMA2_PCL                  (1<<5)
#define PCI_INT_DMA2_HLT                  (1<<4)
#define PCI_INT_DMA1_PCL                  (1<<3)
#define PCI_INT_DMA1_HLT                  (1<<2)
#define PCI_INT_DMA0_PCL                  (1<<1)
#define PCI_INT_DMA0_HLT                  (1<<0)
/* all DMA interrupts combined: */
#define PCI_INT_DMA_ALL                   0x3ff

#define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
#define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))

#define LBUS_ADDR                         0xb4
#define LBUS_ADDR_SEL_RAM                 (0x0<<16)
#define LBUS_ADDR_SEL_ROM                 (0x1<<16)
#define LBUS_ADDR_SEL_AUX                 (0x2<<16)
#define LBUS_ADDR_SEL_ZV                  (0x3<<16)

#define GPIO_CTRL_A                       0xb8
#define GPIO_CTRL_B                       0xbc
#define GPIO_DATA_BASE                    0xc0

#define DMA_BREG(base, chan)              (base + chan * 0x20)
#define DMA_SREG(base, chan)              (base + chan * 0x10)

#define DMA0_PREV_PCL                     0x100
#define DMA1_PREV_PCL                     0x120
#define DMA2_PREV_PCL                     0x140
#define DMA3_PREV_PCL                     0x160
#define DMA4_PREV_PCL                     0x180
#define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))

#define DMA0_CURRENT_PCL                  0x104
#define DMA1_CURRENT_PCL                  0x124
#define DMA2_CURRENT_PCL                  0x144
#define DMA3_CURRENT_PCL                  0x164
#define DMA4_CURRENT_PCL                  0x184
#define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))

#define DMA0_CHAN_STAT                    0x10c
#define DMA1_CHAN_STAT                    0x12c
#define DMA2_CHAN_STAT                    0x14c
#define DMA3_CHAN_STAT                    0x16c
#define DMA4_CHAN_STAT                    0x18c
#define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
/* CHAN_STATUS registers share bits */
#define DMA_CHAN_STAT_SELFID              (1<<31)
#define DMA_CHAN_STAT_ISOPKT              (1<<30)
#define DMA_CHAN_STAT_PCIERR              (1<<29)
#define DMA_CHAN_STAT_PKTERR              (1<<28)
#define DMA_CHAN_STAT_PKTCMPL             (1<<27)
#define DMA_CHAN_STAT_SPECIALACK          (1<<14)


#define DMA0_CHAN_CTRL                    0x110
#define DMA1_CHAN_CTRL                    0x130
#define DMA2_CHAN_CTRL                    0x150
#define DMA3_CHAN_CTRL                    0x170
#define DMA4_CHAN_CTRL                    0x190
#define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
/* CHAN_CTRL registers share bits */
#define DMA_CHAN_CTRL_ENABLE              (1<<31)
#define DMA_CHAN_CTRL_BUSY                (1<<30)
#define DMA_CHAN_CTRL_LINK                (1<<29)

#define DMA0_READY                        0x114
#define DMA1_READY                        0x134
#define DMA2_READY                        0x154
#define DMA3_READY                        0x174
#define DMA4_READY                        0x194
#define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))

#define DMA_GLOBAL_REGISTER               0x908

#define FIFO_SIZES                        0xa00

#define FIFO_CONTROL                      0xa10
#define FIFO_CONTROL_GRF_FLUSH            (1<<4)
#define FIFO_CONTROL_ITF_FLUSH            (1<<3)
#define FIFO_CONTROL_ATF_FLUSH            (1<<2)

#define FIFO_XMIT_THRESHOLD               0xa14

#define DMA0_WORD0_CMP_VALUE              0xb00
#define DMA1_WORD0_CMP_VALUE              0xb10
#define DMA2_WORD0_CMP_VALUE              0xb20
#define DMA3_WORD0_CMP_VALUE              0xb30
#define DMA4_WORD0_CMP_VALUE              0xb40
#define DMA_WORD0_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))

#define DMA0_WORD0_CMP_ENABLE             0xb04
#define DMA1_WORD0_CMP_ENABLE             0xb14
#define DMA2_WORD0_CMP_ENABLE             0xb24
#define DMA3_WORD0_CMP_ENABLE             0xb34
#define DMA4_WORD0_CMP_ENABLE             0xb44
#define DMA_WORD0_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))

#define DMA0_WORD1_CMP_VALUE              0xb08
#define DMA1_WORD1_CMP_VALUE              0xb18
#define DMA2_WORD1_CMP_VALUE              0xb28
#define DMA3_WORD1_CMP_VALUE              0xb38
#define DMA4_WORD1_CMP_VALUE              0xb48
#define DMA_WORD1_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))

#define DMA0_WORD1_CMP_ENABLE             0xb0c
#define DMA1_WORD1_CMP_ENABLE             0xb1c
#define DMA2_WORD1_CMP_ENABLE             0xb2c
#define DMA3_WORD1_CMP_ENABLE             0xb3c
#define DMA4_WORD1_CMP_ENABLE             0xb4c
#define DMA_WORD1_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
/* word 1 compare enable flags */
#define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
#define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
#define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
#define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
#define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
#define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
#define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)

#define LINK_ID                           0xf00
#define LINK_ID_BUS(id)                   (id<<22)
#define LINK_ID_NODE(id)                  (id<<16)

#define LINK_CONTROL                      0xf04
#define LINK_CONTROL_BUSY                 (1<<29)
#define LINK_CONTROL_TX_ISO_EN            (1<<26)
#define LINK_CONTROL_RX_ISO_EN            (1<<25)
#define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
#define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
#define LINK_CONTROL_RESET_TX             (1<<21)
#define LINK_CONTROL_RESET_RX             (1<<20)
#define LINK_CONTROL_CYCMASTER            (1<<11)
#define LINK_CONTROL_CYCSOURCE            (1<<10)
#define LINK_CONTROL_CYCTIMEREN           (1<<9)
#define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
#define LINK_CONTROL_SNOOP_ENABLE         (1<<6)

#define CYCLE_TIMER                       0xf08

#define LINK_PHY                          0xf0c
#define LINK_PHY_READ                     (1<<31)
#define LINK_PHY_WRITE                    (1<<30)
#define LINK_PHY_ADDR(addr)               (addr<<24)
#define LINK_PHY_WDATA(data)              (data<<16)
#define LINK_PHY_RADDR(addr)              (addr<<8)


#define LINK_INT_STATUS                   0xf14
#define LINK_INT_ENABLE                   0xf18
/* status and enable have identical bit numbers */
#define LINK_INT_LINK_INT                 (1<<31)
#define LINK_INT_PHY_TIMEOUT              (1<<30)
#define LINK_INT_PHY_REG_RCVD             (1<<29)
#define LINK_INT_PHY_BUSRESET             (1<<28)
#define LINK_INT_TX_RDY                   (1<<26)
#define LINK_INT_RX_DATA_RDY              (1<<25)
#define LINK_INT_ISO_STUCK                (1<<20)
#define LINK_INT_ASYNC_STUCK              (1<<19)
#define LINK_INT_SENT_REJECT              (1<<17)
#define LINK_INT_HDR_ERR                  (1<<16)
#define LINK_INT_TX_INVALID_TC            (1<<15)
#define LINK_INT_CYC_SECOND               (1<<11)
#define LINK_INT_CYC_START                (1<<10)
#define LINK_INT_CYC_DONE                 (1<<9)
#define LINK_INT_CYC_PENDING              (1<<8)
#define LINK_INT_CYC_LOST                 (1<<7)
#define LINK_INT_CYC_ARB_FAILED           (1<<6)
#define LINK_INT_GRF_OVERFLOW             (1<<5)
#define LINK_INT_ITF_UNDERFLOW            (1<<4)
#define LINK_INT_ATF_UNDERFLOW            (1<<3)
#define LINK_INT_ISOARB_FAILED            (1<<0)

/* PHY specifics */
#define PHY_VENDORID_TI                 0x800028
#define PHY_PRODUCTID_TSB41LV03         0x000000


/* this is the physical layout of a PCL, its size is 128 bytes */
struct ti_pcl {
        u32 next;
        u32 async_error_next;
        u32 user_data;
        u32 pcl_status;
        u32 remaining_transfer_count;
        u32 next_data_buffer;
        struct {
                u32 control;
                u32 pointer;
        } buffer[13] __attribute__ ((packed));
} __attribute__ ((packed));

#include <linux/stddef.h>
#define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))


static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                           const struct ti_pcl *pcl)
{
        memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
                    (u32 *)pcl, sizeof(struct ti_pcl));
}

static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                           struct ti_pcl *pcl)
{
        memcpy_le32((u32 *)pcl,
                    (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
                    sizeof(struct ti_pcl));
}

static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
{
        return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
}


#if defined (__BIG_ENDIAN)
typedef struct ti_pcl pcltmp_t;

static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                                      pcltmp_t *tmp)
{
        get_pcl(lynx, pclid, tmp);
        return tmp;
}

static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                              pcltmp_t *tmp)
{
        put_pcl(lynx, pclid, tmp);
}

#else
typedef int pcltmp_t; /* just a dummy */

static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                                      pcltmp_t *tmp)
{
        return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
}

static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                              pcltmp_t *tmp)
{
}
#endif


static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
                               int dmachan)
{
        reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
                  pcl_bus(lynx, pclid) + idx * 4);
        reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
                  DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
}

static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
{
        run_sub_pcl(lynx, pclid, 0, dmachan);
}

#define PCL_NEXT_INVALID (1<<0)

/* transfer commands */
#define PCL_CMD_RCV            (0x1<<24)
#define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
#define PCL_CMD_XMT            (0x2<<24)
#define PCL_CMD_UNFXMT         (0xc<<24)
#define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
#define PCL_CMD_LBUS_TO_PCI    (0x9<<24)

/* aux commands */
#define PCL_CMD_NOP            (0x0<<24)
#define PCL_CMD_LOAD           (0x3<<24)
#define PCL_CMD_STOREQ         (0x4<<24)
#define PCL_CMD_STORED         (0xb<<24)
#define PCL_CMD_STORE0         (0x5<<24)
#define PCL_CMD_STORE1         (0x6<<24)
#define PCL_CMD_COMPARE        (0xe<<24)
#define PCL_CMD_SWAP_COMPARE   (0xf<<24)
#define PCL_CMD_ADD            (0xd<<24)
#define PCL_CMD_BRANCH         (0x7<<24)

/* BRANCH condition codes */
#define PCL_COND_DMARDY_SET    (0x1<<20)
#define PCL_COND_DMARDY_CLEAR  (0x2<<20)

#define PCL_GEN_INTR           (1<<19)
#define PCL_LAST_BUFF          (1<<18)
#define PCL_LAST_CMD           (PCL_LAST_BUFF)
#define PCL_WAITSTAT           (1<<17)
#define PCL_BIGENDIAN          (1<<16)
#define PCL_ISOMODE            (1<<12)

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __PCILYNX_H__
	2	#define __PCILYNX_H__
	3
	4	#include <linux/config.h>
	5
	6	#define PCILYNX_DRIVER_NAME "pcilynx"
	7	#define PCILYNX_MAJOR 177
	8
	9	#define PCILYNX_MINOR_AUX_START 0
	10	#define PCILYNX_MINOR_ROM_START 16
	11	#define PCILYNX_MINOR_RAM_START 32
	12
	13	#define PCILYNX_MAX_REGISTER 0xfff
	14	#define PCILYNX_MAX_MEMORY 0xffff
	15
	16	#define PCI_DEVICE_ID_TI_PCILYNX 0x8000
	17	#define MAX_PCILYNX_CARDS 4
	18	#define LOCALRAM_SIZE 4096
	19
	20	#define NUM_ISORCV_PCL 4
	21	#define MAX_ISORCV_SIZE 2048
	22	#define ISORCV_PER_PAGE (PAGE_SIZE / MAX_ISORCV_SIZE)
	23	#define ISORCV_PAGES (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
	24
	25	#define CHANNEL_LOCALBUS 0
	26	#define CHANNEL_ASYNC_RCV 1
	27	#define CHANNEL_ISO_RCV 2
	28	#define CHANNEL_ASYNC_SEND 3
	29	#define CHANNEL_ISO_SEND 4
	30
	31	#define PCILYNX_CONFIG_ROM_LENGTH 1024
	32
	33	typedef int pcl_t;
	34
	35	struct ti_lynx {
	36	int id; /* sequential card number */
	37
	38	spinlock_t lock;
	39
	40	struct pci_dev *dev;
	41
	42	struct {
	43	unsigned reg_1394a:1;
	44	u32 vendor;
	45	u32 product;
	46	} phyic;
	47
	48	enum { clear, have_intr, have_aux_buf, have_pcl_mem,
	49	have_1394_buffers, have_iomappings, is_host } state;
	50
	51	/* remapped memory spaces */
	52	void __iomem *registers;
	53	void __iomem *local_rom;
	54	void __iomem *local_ram;
	55	void __iomem *aux_port;
	56	quadlet_t bus_info_block[5];
	57
1da177e4 LT	58	/*
	59	* use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
	60	* LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
	61	* the following is an allocation bitmap
	62	*/
	63	u8 pcl_bmap[LOCALRAM_SIZE / 1024];
	64
1da177e4 LT	65	/* point to PCLs memory area if needed */
	66	void *pcl_mem;
	67	dma_addr_t pcl_mem_dma;
1da177e4 LT	68
	69	/* PCLs for local mem / aux transfers */
	70	pcl_t dmem_pcl;
	71
	72	/* IEEE-1394 part follows */
	73	struct hpsb_host *host;
	74
	75	int phyid, isroot;
	76	int selfid_size;
	77	int phy_reg0;
	78
	79	spinlock_t phy_reg_lock;
	80
	81	pcl_t rcv_pcl_start, rcv_pcl;
	82	void *rcv_page;
	83	dma_addr_t rcv_page_dma;
	84	int rcv_active;
	85
	86	struct lynx_send_data {
	87	pcl_t pcl_start, pcl;
	88	struct list_head queue;
	89	struct list_head pcl_queue; /* this queue contains at most one packet */
	90	spinlock_t queue_lock;
	91	dma_addr_t header_dma, data_dma;
	92	int channel;
	93	} async, iso_send;
	94
	95	struct {
	96	pcl_t pcl[NUM_ISORCV_PCL];
	97	u32 stat[NUM_ISORCV_PCL];
	98	void *page[ISORCV_PAGES];
	99	dma_addr_t page_dma[ISORCV_PAGES];
	100	pcl_t pcl_start;
	101	int chan_count;
	102	int next, last, used, running;
	103	struct tasklet_struct tq;
	104	spinlock_t lock;
	105	} iso_rcv;
	106
	107	u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
	108	};
	109
	110	/* the per-file data structure for mem space access */
	111	struct memdata {
	112	struct ti_lynx *lynx;
	113	int cid;
	114	atomic_t aux_intr_last_seen;
	115	/* enum values are the same as LBUS_ADDR_SEL_* values below */
	116	enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
	117	};
	118
	119
	120
	121	/*
	122	* Register read and write helper functions.
	123	*/
	124	static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
	125	{
	126	writel(data, lynx->registers + offset);
	127	}
	128
	129	static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
	130	{
	131	return readl(lynx->registers + offset);
132	}
133
134	static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
135	u32 mask)
136	{
137	reg_write(lynx, offset, (reg_read(lynx, offset) \| mask));
138	}
139
140	static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
141	u32 mask)
142	{
143	reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
144	}
145
146
147
148	/* chip register definitions follow */
149
150	#define PCI_LATENCY_CACHELINE 0x0c
151
152	#define MISC_CONTROL 0x40
153	#define MISC_CONTROL_SWRESET (1<<0)
154
155	#define SERIAL_EEPROM_CONTROL 0x44
156
157	#define PCI_INT_STATUS 0x48
158	#define PCI_INT_ENABLE 0x4c
159	/* status and enable have identical bit numbers */
160	#define PCI_INT_INT_PEND (1<<31)
161	#define PCI_INT_FORCED_INT (1<<30)
162	#define PCI_INT_SLV_ADR_PERR (1<<28)
163	#define PCI_INT_SLV_DAT_PERR (1<<27)
164	#define PCI_INT_MST_DAT_PERR (1<<26)
165	#define PCI_INT_MST_DEV_TIMEOUT (1<<25)
166	#define PCI_INT_INTERNAL_SLV_TIMEOUT (1<<23)
167	#define PCI_INT_AUX_TIMEOUT (1<<18)
168	#define PCI_INT_AUX_INT (1<<17)
169	#define PCI_INT_1394 (1<<16)
170	#define PCI_INT_DMA4_PCL (1<<9)
171	#define PCI_INT_DMA4_HLT (1<<8)
172	#define PCI_INT_DMA3_PCL (1<<7)
173	#define PCI_INT_DMA3_HLT (1<<6)
174	#define PCI_INT_DMA2_PCL (1<<5)
175	#define PCI_INT_DMA2_HLT (1<<4)
176	#define PCI_INT_DMA1_PCL (1<<3)
177	#define PCI_INT_DMA1_HLT (1<<2)
178	#define PCI_INT_DMA0_PCL (1<<1)
179	#define PCI_INT_DMA0_HLT (1<<0)
180	/* all DMA interrupts combined: */
181	#define PCI_INT_DMA_ALL 0x3ff
182
183	#define PCI_INT_DMA_HLT(chan) (1 << (chan * 2))
184	#define PCI_INT_DMA_PCL(chan) (1 << (chan * 2 + 1))
185
186	#define LBUS_ADDR 0xb4
187	#define LBUS_ADDR_SEL_RAM (0x0<<16)
188	#define LBUS_ADDR_SEL_ROM (0x1<<16)
189	#define LBUS_ADDR_SEL_AUX (0x2<<16)
190	#define LBUS_ADDR_SEL_ZV (0x3<<16)
191
192	#define GPIO_CTRL_A 0xb8
193	#define GPIO_CTRL_B 0xbc
194	#define GPIO_DATA_BASE 0xc0
195
196	#define DMA_BREG(base, chan) (base + chan * 0x20)
197	#define DMA_SREG(base, chan) (base + chan * 0x10)
198
199	#define DMA0_PREV_PCL 0x100
200	#define DMA1_PREV_PCL 0x120
201	#define DMA2_PREV_PCL 0x140
202	#define DMA3_PREV_PCL 0x160
203	#define DMA4_PREV_PCL 0x180
204	#define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan))
205
206	#define DMA0_CURRENT_PCL 0x104
207	#define DMA1_CURRENT_PCL 0x124
208	#define DMA2_CURRENT_PCL 0x144
209	#define DMA3_CURRENT_PCL 0x164
210	#define DMA4_CURRENT_PCL 0x184
211	#define DMA_CURRENT_PCL(chan) (DMA_BREG(DMA0_CURRENT_PCL, chan))
212
213	#define DMA0_CHAN_STAT 0x10c
214	#define DMA1_CHAN_STAT 0x12c
215	#define DMA2_CHAN_STAT 0x14c
216	#define DMA3_CHAN_STAT 0x16c
217	#define DMA4_CHAN_STAT 0x18c
218	#define DMA_CHAN_STAT(chan) (DMA_BREG(DMA0_CHAN_STAT, chan))
219	/* CHAN_STATUS registers share bits */
220	#define DMA_CHAN_STAT_SELFID (1<<31)
221	#define DMA_CHAN_STAT_ISOPKT (1<<30)
222	#define DMA_CHAN_STAT_PCIERR (1<<29)
223	#define DMA_CHAN_STAT_PKTERR (1<<28)
224	#define DMA_CHAN_STAT_PKTCMPL (1<<27)
225	#define DMA_CHAN_STAT_SPECIALACK (1<<14)
226
227
228	#define DMA0_CHAN_CTRL 0x110
229	#define DMA1_CHAN_CTRL 0x130
230	#define DMA2_CHAN_CTRL 0x150
231	#define DMA3_CHAN_CTRL 0x170
232	#define DMA4_CHAN_CTRL 0x190
233	#define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan))
234	/* CHAN_CTRL registers share bits */
235	#define DMA_CHAN_CTRL_ENABLE (1<<31)
236	#define DMA_CHAN_CTRL_BUSY (1<<30)
237	#define DMA_CHAN_CTRL_LINK (1<<29)
238
239	#define DMA0_READY 0x114
240	#define DMA1_READY 0x134
241	#define DMA2_READY 0x154
242	#define DMA3_READY 0x174
243	#define DMA4_READY 0x194
244	#define DMA_READY(chan) (DMA_BREG(DMA0_READY, chan))
245
246	#define DMA_GLOBAL_REGISTER 0x908
247
248	#define FIFO_SIZES 0xa00
249
250	#define FIFO_CONTROL 0xa10
251	#define FIFO_CONTROL_GRF_FLUSH (1<<4)
252	#define FIFO_CONTROL_ITF_FLUSH (1<<3)
253	#define FIFO_CONTROL_ATF_FLUSH (1<<2)
254
255	#define FIFO_XMIT_THRESHOLD 0xa14
256
257	#define DMA0_WORD0_CMP_VALUE 0xb00
258	#define DMA1_WORD0_CMP_VALUE 0xb10
259	#define DMA2_WORD0_CMP_VALUE 0xb20
260	#define DMA3_WORD0_CMP_VALUE 0xb30
261	#define DMA4_WORD0_CMP_VALUE 0xb40
262	#define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
263
264	#define DMA0_WORD0_CMP_ENABLE 0xb04
265	#define DMA1_WORD0_CMP_ENABLE 0xb14
266	#define DMA2_WORD0_CMP_ENABLE 0xb24
267	#define DMA3_WORD0_CMP_ENABLE 0xb34
268	#define DMA4_WORD0_CMP_ENABLE 0xb44
269	#define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
270
271	#define DMA0_WORD1_CMP_VALUE 0xb08
272	#define DMA1_WORD1_CMP_VALUE 0xb18
273	#define DMA2_WORD1_CMP_VALUE 0xb28
274	#define DMA3_WORD1_CMP_VALUE 0xb38
275	#define DMA4_WORD1_CMP_VALUE 0xb48
276	#define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
277
278	#define DMA0_WORD1_CMP_ENABLE 0xb0c
279	#define DMA1_WORD1_CMP_ENABLE 0xb1c
280	#define DMA2_WORD1_CMP_ENABLE 0xb2c
281	#define DMA3_WORD1_CMP_ENABLE 0xb3c
282	#define DMA4_WORD1_CMP_ENABLE 0xb4c
283	#define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
284	/* word 1 compare enable flags */
285	#define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15)
286	#define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14)
287	#define DMA_WORD1_CMP_MATCH_BUS_BCAST (1<<13)
288	#define DMA_WORD1_CMP_MATCH_LOCAL_NODE (1<<12)
289	#define DMA_WORD1_CMP_MATCH_EXACT (1<<11)
290	#define DMA_WORD1_CMP_ENABLE_SELF_ID (1<<10)
291	#define DMA_WORD1_CMP_ENABLE_MASTER (1<<8)
292
293	#define LINK_ID 0xf00
294	#define LINK_ID_BUS(id) (id<<22)
295	#define LINK_ID_NODE(id) (id<<16)
296
297	#define LINK_CONTROL 0xf04
298	#define LINK_CONTROL_BUSY (1<<29)
299	#define LINK_CONTROL_TX_ISO_EN (1<<26)
300	#define LINK_CONTROL_RX_ISO_EN (1<<25)
301	#define LINK_CONTROL_TX_ASYNC_EN (1<<24)
302	#define LINK_CONTROL_RX_ASYNC_EN (1<<23)
303	#define LINK_CONTROL_RESET_TX (1<<21)
304	#define LINK_CONTROL_RESET_RX (1<<20)
305	#define LINK_CONTROL_CYCMASTER (1<<11)
306	#define LINK_CONTROL_CYCSOURCE (1<<10)
307	#define LINK_CONTROL_CYCTIMEREN (1<<9)
308	#define LINK_CONTROL_RCV_CMP_VALID (1<<7)
309	#define LINK_CONTROL_SNOOP_ENABLE (1<<6)
310
311	#define CYCLE_TIMER 0xf08
312
313	#define LINK_PHY 0xf0c
314	#define LINK_PHY_READ (1<<31)
315	#define LINK_PHY_WRITE (1<<30)
316	#define LINK_PHY_ADDR(addr) (addr<<24)
317	#define LINK_PHY_WDATA(data) (data<<16)
318	#define LINK_PHY_RADDR(addr) (addr<<8)
319
320
321	#define LINK_INT_STATUS 0xf14
322	#define LINK_INT_ENABLE 0xf18
323	/* status and enable have identical bit numbers */
324	#define LINK_INT_LINK_INT (1<<31)
325	#define LINK_INT_PHY_TIMEOUT (1<<30)
326	#define LINK_INT_PHY_REG_RCVD (1<<29)
327	#define LINK_INT_PHY_BUSRESET (1<<28)
328	#define LINK_INT_TX_RDY (1<<26)
329	#define LINK_INT_RX_DATA_RDY (1<<25)
330	#define LINK_INT_ISO_STUCK (1<<20)
331	#define LINK_INT_ASYNC_STUCK (1<<19)
332	#define LINK_INT_SENT_REJECT (1<<17)
333	#define LINK_INT_HDR_ERR (1<<16)
334	#define LINK_INT_TX_INVALID_TC (1<<15)
335	#define LINK_INT_CYC_SECOND (1<<11)
336	#define LINK_INT_CYC_START (1<<10)
337	#define LINK_INT_CYC_DONE (1<<9)
338	#define LINK_INT_CYC_PENDING (1<<8)
339	#define LINK_INT_CYC_LOST (1<<7)
340	#define LINK_INT_CYC_ARB_FAILED (1<<6)
341	#define LINK_INT_GRF_OVERFLOW (1<<5)
342	#define LINK_INT_ITF_UNDERFLOW (1<<4)
343	#define LINK_INT_ATF_UNDERFLOW (1<<3)
344	#define LINK_INT_ISOARB_FAILED (1<<0)
345
346	/* PHY specifics */
347	#define PHY_VENDORID_TI 0x800028
348	#define PHY_PRODUCTID_TSB41LV03 0x000000
349
350
351	/* this is the physical layout of a PCL, its size is 128 bytes */
352	struct ti_pcl {
353	u32 next;
354	u32 async_error_next;
355	u32 user_data;
356	u32 pcl_status;
357	u32 remaining_transfer_count;
358	u32 next_data_buffer;
359	struct {
360	u32 control;
361	u32 pointer;
362	} buffer[13] __attribute__ ((packed));
363	} __attribute__ ((packed));
364
365	#include <linux/stddef.h>
366	#define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
367
368
1da177e4 LT	369	static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
	370	const struct ti_pcl *pcl)
	371	{
	372	memcpy_le32((u32 )(lynx->pcl_mem + pclid sizeof(struct ti_pcl)),
	373	(u32 *)pcl, sizeof(struct ti_pcl));
	374	}
	375
	376	static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
	377	struct ti_pcl *pcl)
	378	{
	379	memcpy_le32((u32 *)pcl,
	380	(u32 )(lynx->pcl_mem + pclid sizeof(struct ti_pcl)),
	381	sizeof(struct ti_pcl));
	382	}
	383
	384	static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
	385	{
	386	return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
	387	}
	388
1da177e4	389
f72cd138	390	#if defined (__BIG_ENDIAN)
1da177e4 LT	391	typedef struct ti_pcl pcltmp_t;
	392
	393	static inline struct ti_pcl edit_pcl(const struct ti_lynx lynx, pcl_t pclid,
	394	pcltmp_t *tmp)
	395	{
	396	get_pcl(lynx, pclid, tmp);
	397	return tmp;
	398	}
	399
	400	static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
	401	pcltmp_t *tmp)
	402	{
	403	put_pcl(lynx, pclid, tmp);
	404	}
	405
	406	#else
	407	typedef int pcltmp_t; /* just a dummy */
	408
	409	static inline struct ti_pcl edit_pcl(const struct ti_lynx lynx, pcl_t pclid,
	410	pcltmp_t *tmp)
	411	{
	412	return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
	413	}
	414
	415	static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
	416	pcltmp_t *tmp)
	417	{
	418	}
	419	#endif
	420
	421
	422	static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
	423	int dmachan)
	424	{
	425	reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
	426	pcl_bus(lynx, pclid) + idx * 4);
	427	reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
	428	DMA_CHAN_CTRL_ENABLE \| DMA_CHAN_CTRL_LINK);
	429	}
	430
	431	static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
	432	{
	433	run_sub_pcl(lynx, pclid, 0, dmachan);
	434	}
	435
	436	#define PCL_NEXT_INVALID (1<<0)
	437
	438	/* transfer commands */
	439	#define PCL_CMD_RCV (0x1<<24)
	440	#define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
	441	#define PCL_CMD_XMT (0x2<<24)
	442	#define PCL_CMD_UNFXMT (0xc<<24)
	443	#define PCL_CMD_PCI_TO_LBUS (0x8<<24)
	444	#define PCL_CMD_LBUS_TO_PCI (0x9<<24)
	445
	446	/* aux commands */
	447	#define PCL_CMD_NOP (0x0<<24)
	448	#define PCL_CMD_LOAD (0x3<<24)
	449	#define PCL_CMD_STOREQ (0x4<<24)
	450	#define PCL_CMD_STORED (0xb<<24)
	451	#define PCL_CMD_STORE0 (0x5<<24)
	452	#define PCL_CMD_STORE1 (0x6<<24)
	453	#define PCL_CMD_COMPARE (0xe<<24)
	454	#define PCL_CMD_SWAP_COMPARE (0xf<<24)
455	#define PCL_CMD_ADD (0xd<<24)
456	#define PCL_CMD_BRANCH (0x7<<24)
457
458	/* BRANCH condition codes */
459	#define PCL_COND_DMARDY_SET (0x1<<20)
460	#define PCL_COND_DMARDY_CLEAR (0x2<<20)
461
462	#define PCL_GEN_INTR (1<<19)
463	#define PCL_LAST_BUFF (1<<18)
464	#define PCL_LAST_CMD (PCL_LAST_BUFF)
465	#define PCL_WAITSTAT (1<<17)
466	#define PCL_BIGENDIAN (1<<16)
467	#define PCL_ISOMODE (1<<12)
468
469	#endif