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thermal: fair_share: use the weight from the thermal instance
[deliverable/linux.git] / drivers / iio / accel / bmc150-accel.c
CommitLineData
bd7fe5b7 1/*
8ecbb3c3
LP		 2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
3 * - BMC150
4 * - BMI055
5 * - BMA255
6 * - BMA250E
7 * - BMA222E
8 * - BMA280
9 *
bd7fe5b7
SP		 10 * Copyright (c) 2014, Intel Corporation.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22#include <linux/module.h>
23#include <linux/i2c.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/acpi.h>
28#include <linux/gpio/consumer.h>
29#include <linux/pm.h>
30#include <linux/pm_runtime.h>
31#include <linux/iio/iio.h>
32#include <linux/iio/sysfs.h>
33#include <linux/iio/buffer.h>
34#include <linux/iio/events.h>
35#include <linux/iio/trigger.h>
36#include <linux/iio/trigger_consumer.h>
37#include <linux/iio/triggered_buffer.h>
38
39#define BMC150_ACCEL_DRV_NAME "bmc150_accel"
40#define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
41#define BMC150_ACCEL_GPIO_NAME "bmc150_accel_int"
42
43#define BMC150_ACCEL_REG_CHIP_ID 0x00
bd7fe5b7
SP		 44
45#define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
46#define BMC150_ACCEL_ANY_MOTION_MASK 0x07
8d5a9781
SP		 47#define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
48#define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
49#define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
bd7fe5b7
SP		 50#define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
51
52#define BMC150_ACCEL_REG_PMU_LPW 0x11
53#define BMC150_ACCEL_PMU_MODE_MASK 0xE0
54#define BMC150_ACCEL_PMU_MODE_SHIFT 5
55#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
56#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
57
58#define BMC150_ACCEL_REG_PMU_RANGE 0x0F
59
60#define BMC150_ACCEL_DEF_RANGE_2G 0x03
61#define BMC150_ACCEL_DEF_RANGE_4G 0x05
62#define BMC150_ACCEL_DEF_RANGE_8G 0x08
63#define BMC150_ACCEL_DEF_RANGE_16G 0x0C
64
65/* Default BW: 125Hz */
66#define BMC150_ACCEL_REG_PMU_BW 0x10
67#define BMC150_ACCEL_DEF_BW 125
68
69#define BMC150_ACCEL_REG_INT_MAP_0 0x19
70#define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
71
72#define BMC150_ACCEL_REG_INT_MAP_1 0x1A
3bbec977
OP		 73#define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
74#define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
75#define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
bd7fe5b7
SP		 76
77#define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
78#define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
79#define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
80#define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
81
82#define BMC150_ACCEL_REG_INT_EN_0 0x16
83#define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
84#define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
85#define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
86
87#define BMC150_ACCEL_REG_INT_EN_1 0x17
3bbec977
OP		 88#define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
89#define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
90#define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
bd7fe5b7
SP		 91
92#define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
93#define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
94
95#define BMC150_ACCEL_REG_INT_5 0x27
96#define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
97
98#define BMC150_ACCEL_REG_INT_6 0x28
99#define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
100
101/* Slope duration in terms of number of samples */
9e8e228f 102#define BMC150_ACCEL_DEF_SLOPE_DURATION 1
bd7fe5b7 103/* in terms of multiples of g's/LSB, based on range */
9e8e228f 104#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
bd7fe5b7
SP		 105
106#define BMC150_ACCEL_REG_XOUT_L 0x02
107
108#define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
109
110/* Sleep Duration values */
111#define BMC150_ACCEL_SLEEP_500_MICRO 0x05
112#define BMC150_ACCEL_SLEEP_1_MS 0x06
113#define BMC150_ACCEL_SLEEP_2_MS 0x07
114#define BMC150_ACCEL_SLEEP_4_MS 0x08
115#define BMC150_ACCEL_SLEEP_6_MS 0x09
116#define BMC150_ACCEL_SLEEP_10_MS 0x0A
117#define BMC150_ACCEL_SLEEP_25_MS 0x0B
118#define BMC150_ACCEL_SLEEP_50_MS 0x0C
119#define BMC150_ACCEL_SLEEP_100_MS 0x0D
120#define BMC150_ACCEL_SLEEP_500_MS 0x0E
121#define BMC150_ACCEL_SLEEP_1_SEC 0x0F
122
123#define BMC150_ACCEL_REG_TEMP 0x08
124#define BMC150_ACCEL_TEMP_CENTER_VAL 24
125
126#define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
127#define BMC150_AUTO_SUSPEND_DELAY_MS 2000
128
3bbec977
OP		 129#define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
130#define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
131#define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
132#define BMC150_ACCEL_REG_FIFO_DATA 0x3F
133#define BMC150_ACCEL_FIFO_LENGTH 32
134
bd7fe5b7
SP		 135enum bmc150_accel_axis {
136 AXIS_X,
137 AXIS_Y,
138 AXIS_Z,
139};
140
141enum bmc150_power_modes {
142 BMC150_ACCEL_SLEEP_MODE_NORMAL,
143 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
144 BMC150_ACCEL_SLEEP_MODE_LPM,
145 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
146};
147
8ecbb3c3
LP		 148struct bmc150_scale_info {
149 int scale;
150 u8 reg_range;
151};
152
153struct bmc150_accel_chip_info {
154 u8 chip_id;
155 const struct iio_chan_spec *channels;
156 int num_channels;
157 const struct bmc150_scale_info scale_table[4];
158};
159
3e825ec9
OP		 160struct bmc150_accel_interrupt {
161 const struct bmc150_accel_interrupt_info *info;
162 atomic_t users;
163};
164
7d963215
OP		 165struct bmc150_accel_trigger {
166 struct bmc150_accel_data *data;
167 struct iio_trigger *indio_trig;
168 int (*setup)(struct bmc150_accel_trigger *t, bool state);
169 int intr;
170 bool enabled;
171};
172
3e825ec9
OP		 173enum bmc150_accel_interrupt_id {
174 BMC150_ACCEL_INT_DATA_READY,
175 BMC150_ACCEL_INT_ANY_MOTION,
176 BMC150_ACCEL_INT_WATERMARK,
177 BMC150_ACCEL_INTERRUPTS,
178};
179
7d963215
OP		 180enum bmc150_accel_trigger_id {
181 BMC150_ACCEL_TRIGGER_DATA_READY,
182 BMC150_ACCEL_TRIGGER_ANY_MOTION,
183 BMC150_ACCEL_TRIGGERS,
184};
185
bd7fe5b7
SP		 186struct bmc150_accel_data {
187 struct i2c_client *client;
3e825ec9 188 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
3e825ec9 189 atomic_t active_intr;
7d963215 190 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
bd7fe5b7 191 struct mutex mutex;
3bbec977 192 u8 fifo_mode, watermark;
bd7fe5b7
SP		 193 s16 buffer[8];
194 u8 bw_bits;
195 u32 slope_dur;
196 u32 slope_thres;
197 u32 range;
198 int ev_enable_state;
3bbec977 199 int64_t timestamp, old_timestamp;
8ecbb3c3 200 const struct bmc150_accel_chip_info *chip_info;
bd7fe5b7
SP		 201};
202
203static const struct {
204 int val;
205 int val2;
206 u8 bw_bits;
0ba8da96
SK		 207} bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
208 {31, 260000, 0x09},
209 {62, 500000, 0x0A},
210 {125, 0, 0x0B},
211 {250, 0, 0x0C},
212 {500, 0, 0x0D},
213 {1000, 0, 0x0E},
214 {2000, 0, 0x0F} };
bd7fe5b7
SP		 215
216static const struct {
217 int bw_bits;
218 int msec;
219} bmc150_accel_sample_upd_time[] = { {0x08, 64},
220 {0x09, 32},
221 {0x0A, 16},
222 {0x0B, 8},
223 {0x0C, 4},
224 {0x0D, 2},
225 {0x0E, 1},
226 {0x0F, 1} };
227
bd7fe5b7
SP		 228static const struct {
229 int sleep_dur;
8ecbb3c3 230 u8 reg_value;
bd7fe5b7
SP		 231} bmc150_accel_sleep_value_table[] = { {0, 0},
232 {500, BMC150_ACCEL_SLEEP_500_MICRO},
233 {1000, BMC150_ACCEL_SLEEP_1_MS},
234 {2000, BMC150_ACCEL_SLEEP_2_MS},
235 {4000, BMC150_ACCEL_SLEEP_4_MS},
236 {6000, BMC150_ACCEL_SLEEP_6_MS},
237 {10000, BMC150_ACCEL_SLEEP_10_MS},
238 {25000, BMC150_ACCEL_SLEEP_25_MS},
239 {50000, BMC150_ACCEL_SLEEP_50_MS},
240 {100000, BMC150_ACCEL_SLEEP_100_MS},
241 {500000, BMC150_ACCEL_SLEEP_500_MS},
242 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
243
244
245static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
246 enum bmc150_power_modes mode,
247 int dur_us)
248{
249 int i;
250 int ret;
251 u8 lpw_bits;
252 int dur_val = -1;
253
254 if (dur_us > 0) {
255 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
256 ++i) {
257 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
258 dur_us)
259 dur_val =
260 bmc150_accel_sleep_value_table[i].reg_value;
261 }
262 } else
263 dur_val = 0;
264
265 if (dur_val < 0)
266 return -EINVAL;
267
268 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
269 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
270
271 dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits);
272
273 ret = i2c_smbus_write_byte_data(data->client,
274 BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
275 if (ret < 0) {
276 dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n");
277 return ret;
278 }
279
280 return 0;
281}
282
283static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
284 int val2)
285{
286 int i;
287 int ret;
288
289 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
290 if (bmc150_accel_samp_freq_table[i].val == val &&
291 bmc150_accel_samp_freq_table[i].val2 == val2) {
292 ret = i2c_smbus_write_byte_data(
293 data->client,
294 BMC150_ACCEL_REG_PMU_BW,
295 bmc150_accel_samp_freq_table[i].bw_bits);
296 if (ret < 0)
297 return ret;
298
299 data->bw_bits =
300 bmc150_accel_samp_freq_table[i].bw_bits;
301 return 0;
302 }
303 }
304
305 return -EINVAL;
306}
307
802a3aef
OP		 308static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
309{
310 int ret, val;
311
312 ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_6,
313 data->slope_thres);
314 if (ret < 0) {
315 dev_err(&data->client->dev, "Error writing reg_int_6\n");
316 return ret;
317 }
318
319 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5);
320 if (ret < 0) {
321 dev_err(&data->client->dev, "Error reading reg_int_5\n");
322 return ret;
323 }
324
325 val = (ret & ~BMC150_ACCEL_SLOPE_DUR_MASK) | data->slope_dur;
326 ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_5,
327 val);
328 if (ret < 0) {
329 dev_err(&data->client->dev, "Error write reg_int_5\n");
330 return ret;
331 }
332
333 dev_dbg(&data->client->dev, "%s: %x %x\n", __func__, data->slope_thres,
334 data->slope_dur);
335
336 return ret;
337}
338
7d963215
OP		 339static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
340 bool state)
341{
342 if (state)
343 return bmc150_accel_update_slope(t->data);
344
345 return 0;
346}
347
bd7fe5b7
SP		 348static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
349{
350 int ret;
351
352 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID);
353 if (ret < 0) {
354 dev_err(&data->client->dev,
355 "Error: Reading chip id\n");
356 return ret;
357 }
358
359 dev_dbg(&data->client->dev, "Chip Id %x\n", ret);
8ecbb3c3 360 if (ret != data->chip_info->chip_id) {
bd7fe5b7
SP		 361 dev_err(&data->client->dev, "Invalid chip %x\n", ret);
362 return -ENODEV;
363 }
364
365 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
366 if (ret < 0)
367 return ret;
368
369 /* Set Bandwidth */
370 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
371 if (ret < 0)
372 return ret;
373
374 /* Set Default Range */
375 ret = i2c_smbus_write_byte_data(data->client,
376 BMC150_ACCEL_REG_PMU_RANGE,
377 BMC150_ACCEL_DEF_RANGE_4G);
378 if (ret < 0) {
379 dev_err(&data->client->dev,
380 "Error writing reg_pmu_range\n");
381 return ret;
382 }
383
384 data->range = BMC150_ACCEL_DEF_RANGE_4G;
385
802a3aef 386 /* Set default slope duration and thresholds */
bd7fe5b7 387 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
802a3aef
OP		 388 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
389 ret = bmc150_accel_update_slope(data);
390 if (ret < 0)
391 return ret;
bd7fe5b7
SP		 392
393 /* Set default as latched interrupts */
394 ret = i2c_smbus_write_byte_data(data->client,
395 BMC150_ACCEL_REG_INT_RST_LATCH,
396 BMC150_ACCEL_INT_MODE_LATCH_INT |
397 BMC150_ACCEL_INT_MODE_LATCH_RESET);
398 if (ret < 0) {
399 dev_err(&data->client->dev,
400 "Error writing reg_int_rst_latch\n");
401 return ret;
402 }
403
404 return 0;
405}
406
bd7fe5b7
SP		 407static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
408 int *val2)
409{
410 int i;
411
412 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
413 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
414 *val = bmc150_accel_samp_freq_table[i].val;
415 *val2 = bmc150_accel_samp_freq_table[i].val2;
416 return IIO_VAL_INT_PLUS_MICRO;
417 }
418 }
419
420 return -EINVAL;
421}
422
6f0a13f2 423#ifdef CONFIG_PM
bd7fe5b7
SP		 424static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
425{
426 int i;
427
428 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
429 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
430 return bmc150_accel_sample_upd_time[i].msec;
431 }
432
433 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
434}
435
436static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
437{
438 int ret;
439
440 if (on)
441 ret = pm_runtime_get_sync(&data->client->dev);
442 else {
443 pm_runtime_mark_last_busy(&data->client->dev);
444 ret = pm_runtime_put_autosuspend(&data->client->dev);
445 }
446 if (ret < 0) {
447 dev_err(&data->client->dev,
448 "Failed: bmc150_accel_set_power_state for %d\n", on);
aaeecd80
SP		 449 if (on)
450 pm_runtime_put_noidle(&data->client->dev);
451
bd7fe5b7
SP		 452 return ret;
453 }
454
455 return 0;
456}
b31b05cf
LP		 457#else
458static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
459{
460 return 0;
461}
462#endif
bd7fe5b7 463
8e22f477
OP		 464static const struct bmc150_accel_interrupt_info {
465 u8 map_reg;
466 u8 map_bitmask;
467 u8 en_reg;
468 u8 en_bitmask;
3e825ec9 469} bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
8e22f477
OP		 470 { /* data ready interrupt */
471 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
472 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
473 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
474 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
475 },
476 { /* motion interrupt */
477 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
478 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
479 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
480 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
481 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
482 BMC150_ACCEL_INT_EN_BIT_SLP_Z
483 },
3bbec977
OP		 484 { /* fifo watermark interrupt */
485 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
486 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
487 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
488 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
489 },
8e22f477
OP		 490};
491
3e825ec9
OP		 492static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
493 struct bmc150_accel_data *data)
494{
495 int i;
496
497 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
498 data->interrupts[i].info = &bmc150_accel_interrupts[i];
499}
500
501static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
8e22f477
OP		 502 bool state)
503{
3e825ec9
OP		 504 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
505 const struct bmc150_accel_interrupt_info *info = intr->info;
8e22f477
OP		 506 int ret;
507
3e825ec9
OP		 508 if (state) {
509 if (atomic_inc_return(&intr->users) > 1)
510 return 0;
511 } else {
512 if (atomic_dec_return(&intr->users) > 0)
513 return 0;
514 }
515
8e22f477
OP		 516 /*
517 * We will expect the enable and disable to do operation in
518 * in reverse order. This will happen here anyway as our
519 * resume operation uses sync mode runtime pm calls, the
520 * suspend operation will be delayed by autosuspend delay
521 * So the disable operation will still happen in reverse of
522 * enable operation. When runtime pm is disabled the mode
523 * is always on so sequence doesn't matter
524 */
525 ret = bmc150_accel_set_power_state(data, state);
526 if (ret < 0)
527 return ret;
528
529 /* map the interrupt to the appropriate pins */
530 ret = i2c_smbus_read_byte_data(data->client, info->map_reg);
531 if (ret < 0) {
532 dev_err(&data->client->dev, "Error reading reg_int_map\n");
533 goto out_fix_power_state;
534 }
535 if (state)
536 ret |= info->map_bitmask;
537 else
538 ret &= ~info->map_bitmask;
539
540 ret = i2c_smbus_write_byte_data(data->client, info->map_reg,
541 ret);
542 if (ret < 0) {
543 dev_err(&data->client->dev, "Error writing reg_int_map\n");
544 goto out_fix_power_state;
545 }
546
547 /* enable/disable the interrupt */
548 ret = i2c_smbus_read_byte_data(data->client, info->en_reg);
549 if (ret < 0) {
550 dev_err(&data->client->dev, "Error reading reg_int_en\n");
551 goto out_fix_power_state;
552 }
553
554 if (state)
555 ret |= info->en_bitmask;
556 else
557 ret &= ~info->en_bitmask;
558
559 ret = i2c_smbus_write_byte_data(data->client, info->en_reg, ret);
560 if (ret < 0) {
561 dev_err(&data->client->dev, "Error writing reg_int_en\n");
562 goto out_fix_power_state;
563 }
564
3e825ec9
OP		 565 if (state)
566 atomic_inc(&data->active_intr);
567 else
568 atomic_dec(&data->active_intr);
569
8e22f477
OP		 570 return 0;
571
572out_fix_power_state:
573 bmc150_accel_set_power_state(data, false);
574 return ret;
575}
576
8e22f477 577
bd7fe5b7
SP		 578static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
579{
580 int ret, i;
581
8ecbb3c3
LP		 582 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
583 if (data->chip_info->scale_table[i].scale == val) {
bd7fe5b7 584 ret = i2c_smbus_write_byte_data(
8ecbb3c3
LP		 585 data->client,
586 BMC150_ACCEL_REG_PMU_RANGE,
587 data->chip_info->scale_table[i].reg_range);
bd7fe5b7
SP		 588 if (ret < 0) {
589 dev_err(&data->client->dev,
590 "Error writing pmu_range\n");
591 return ret;
592 }
593
8ecbb3c3 594 data->range = data->chip_info->scale_table[i].reg_range;
bd7fe5b7
SP		 595 return 0;
596 }
597 }
598
599 return -EINVAL;
600}
601
602static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
603{
604 int ret;
605
606 mutex_lock(&data->mutex);
607
608 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP);
609 if (ret < 0) {
610 dev_err(&data->client->dev, "Error reading reg_temp\n");
611 mutex_unlock(&data->mutex);
612 return ret;
613 }
614 *val = sign_extend32(ret, 7);
615
616 mutex_unlock(&data->mutex);
617
618 return IIO_VAL_INT;
619}
620
8ecbb3c3
LP		 621static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
622 struct iio_chan_spec const *chan,
bd7fe5b7
SP		 623 int *val)
624{
625 int ret;
8ecbb3c3 626 int axis = chan->scan_index;
bd7fe5b7
SP		 627
628 mutex_lock(&data->mutex);
629 ret = bmc150_accel_set_power_state(data, true);
630 if (ret < 0) {
631 mutex_unlock(&data->mutex);
632 return ret;
633 }
634
635 ret = i2c_smbus_read_word_data(data->client,
636 BMC150_ACCEL_AXIS_TO_REG(axis));
637 if (ret < 0) {
638 dev_err(&data->client->dev, "Error reading axis %d\n", axis);
639 bmc150_accel_set_power_state(data, false);
640 mutex_unlock(&data->mutex);
641 return ret;
642 }
8ecbb3c3
LP		 643 *val = sign_extend32(ret >> chan->scan_type.shift,
644 chan->scan_type.realbits - 1);
bd7fe5b7
SP		 645 ret = bmc150_accel_set_power_state(data, false);
646 mutex_unlock(&data->mutex);
647 if (ret < 0)
648 return ret;
649
650 return IIO_VAL_INT;
651}
652
653static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
654 struct iio_chan_spec const *chan,
655 int *val, int *val2, long mask)
656{
657 struct bmc150_accel_data *data = iio_priv(indio_dev);
658 int ret;
659
660 switch (mask) {
661 case IIO_CHAN_INFO_RAW:
662 switch (chan->type) {
663 case IIO_TEMP:
664 return bmc150_accel_get_temp(data, val);
665 case IIO_ACCEL:
666 if (iio_buffer_enabled(indio_dev))
667 return -EBUSY;
668 else
8ecbb3c3 669 return bmc150_accel_get_axis(data, chan, val);
bd7fe5b7
SP		 670 default:
671 return -EINVAL;
672 }
673 case IIO_CHAN_INFO_OFFSET:
674 if (chan->type == IIO_TEMP) {
675 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
676 return IIO_VAL_INT;
677 } else
678 return -EINVAL;
679 case IIO_CHAN_INFO_SCALE:
680 *val = 0;
681 switch (chan->type) {
682 case IIO_TEMP:
683 *val2 = 500000;
684 return IIO_VAL_INT_PLUS_MICRO;
685 case IIO_ACCEL:
686 {
687 int i;
8ecbb3c3
LP		 688 const struct bmc150_scale_info *si;
689 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
bd7fe5b7 690
8ecbb3c3
LP		 691 for (i = 0; i < st_size; ++i) {
692 si = &data->chip_info->scale_table[i];
693 if (si->reg_range == data->range) {
694 *val2 = si->scale;
bd7fe5b7
SP		 695 return IIO_VAL_INT_PLUS_MICRO;
696 }
697 }
698 return -EINVAL;
699 }
700 default:
701 return -EINVAL;
702 }
703 case IIO_CHAN_INFO_SAMP_FREQ:
704 mutex_lock(&data->mutex);
705 ret = bmc150_accel_get_bw(data, val, val2);
706 mutex_unlock(&data->mutex);
707 return ret;
708 default:
709 return -EINVAL;
710 }
711}
712
713static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
714 struct iio_chan_spec const *chan,
715 int val, int val2, long mask)
716{
717 struct bmc150_accel_data *data = iio_priv(indio_dev);
718 int ret;
719
720 switch (mask) {
721 case IIO_CHAN_INFO_SAMP_FREQ:
722 mutex_lock(&data->mutex);
723 ret = bmc150_accel_set_bw(data, val, val2);
724 mutex_unlock(&data->mutex);
725 break;
726 case IIO_CHAN_INFO_SCALE:
727 if (val)
728 return -EINVAL;
729
730 mutex_lock(&data->mutex);
731 ret = bmc150_accel_set_scale(data, val2);
732 mutex_unlock(&data->mutex);
733 return ret;
734 default:
735 ret = -EINVAL;
736 }
737
738 return ret;
739}
740
741static int bmc150_accel_read_event(struct iio_dev *indio_dev,
742 const struct iio_chan_spec *chan,
743 enum iio_event_type type,
744 enum iio_event_direction dir,
745 enum iio_event_info info,
746 int *val, int *val2)
747{
748 struct bmc150_accel_data *data = iio_priv(indio_dev);
749
750 *val2 = 0;
751 switch (info) {
752 case IIO_EV_INFO_VALUE:
753 *val = data->slope_thres;
754 break;
755 case IIO_EV_INFO_PERIOD:
802a3aef 756 *val = data->slope_dur;
bd7fe5b7
SP		 757 break;
758 default:
759 return -EINVAL;
760 }
761
762 return IIO_VAL_INT;
763}
764
765static int bmc150_accel_write_event(struct iio_dev *indio_dev,
766 const struct iio_chan_spec *chan,
767 enum iio_event_type type,
768 enum iio_event_direction dir,
769 enum iio_event_info info,
770 int val, int val2)
771{
772 struct bmc150_accel_data *data = iio_priv(indio_dev);
773
774 if (data->ev_enable_state)
775 return -EBUSY;
776
777 switch (info) {
778 case IIO_EV_INFO_VALUE:
802a3aef 779 data->slope_thres = val & 0xFF;
bd7fe5b7
SP		 780 break;
781 case IIO_EV_INFO_PERIOD:
802a3aef 782 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
bd7fe5b7
SP		 783 break;
784 default:
785 return -EINVAL;
786 }
787
788 return 0;
789}
790
791static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
792 const struct iio_chan_spec *chan,
793 enum iio_event_type type,
794 enum iio_event_direction dir)
795{
796
797 struct bmc150_accel_data *data = iio_priv(indio_dev);
798
799 return data->ev_enable_state;
800}
801
802static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
803 const struct iio_chan_spec *chan,
804 enum iio_event_type type,
805 enum iio_event_direction dir,
806 int state)
807{
808 struct bmc150_accel_data *data = iio_priv(indio_dev);
809 int ret;
810
14ee64f4 811 if (state == data->ev_enable_state)
bd7fe5b7
SP		 812 return 0;
813
814 mutex_lock(&data->mutex);
815
3e825ec9
OP		 816 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
817 state);
bd7fe5b7
SP		 818 if (ret < 0) {
819 mutex_unlock(&data->mutex);
820 return ret;
821 }
822
823 data->ev_enable_state = state;
824 mutex_unlock(&data->mutex);
825
826 return 0;
827}
828
829static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
830 struct iio_trigger *trig)
831{
832 struct bmc150_accel_data *data = iio_priv(indio_dev);
7d963215 833 int i;
bd7fe5b7 834
7d963215
OP		 835 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
836 if (data->triggers[i].indio_trig == trig)
837 return 0;
838 }
bd7fe5b7 839
7d963215 840 return -EINVAL;
bd7fe5b7
SP		 841}
842
3bbec977
OP		 843static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
844 struct device_attribute *attr,
845 char *buf)
846{
847 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
848 struct bmc150_accel_data *data = iio_priv(indio_dev);
849 int wm;
850
851 mutex_lock(&data->mutex);
852 wm = data->watermark;
853 mutex_unlock(&data->mutex);
854
855 return sprintf(buf, "%d\n", wm);
856}
857
858static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
859 struct device_attribute *attr,
860 char *buf)
861{
862 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
863 struct bmc150_accel_data *data = iio_priv(indio_dev);
864 bool state;
865
866 mutex_lock(&data->mutex);
867 state = data->fifo_mode;
868 mutex_unlock(&data->mutex);
869
870 return sprintf(buf, "%d\n", state);
871}
872
873static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
874static IIO_CONST_ATTR(hwfifo_watermark_max,
875 __stringify(BMC150_ACCEL_FIFO_LENGTH));
876static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
877 bmc150_accel_get_fifo_state, NULL, 0);
878static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
879 bmc150_accel_get_fifo_watermark, NULL, 0);
880
881static const struct attribute *bmc150_accel_fifo_attributes[] = {
882 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
883 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
884 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
885 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
886 NULL,
887};
888
889static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
890{
891 struct bmc150_accel_data *data = iio_priv(indio_dev);
892
893 if (val > BMC150_ACCEL_FIFO_LENGTH)
894 val = BMC150_ACCEL_FIFO_LENGTH;
895
896 mutex_lock(&data->mutex);
897 data->watermark = val;
898 mutex_unlock(&data->mutex);
899
900 return 0;
901}
902
903/*
904 * We must read at least one full frame in one burst, otherwise the rest of the
905 * frame data is discarded.
906 */
907static int bmc150_accel_fifo_transfer(const struct i2c_client *client,
908 char *buffer, int samples)
909{
910 int sample_length = 3 * 2;
911 u8 reg_fifo_data = BMC150_ACCEL_REG_FIFO_DATA;
912 int ret = -EIO;
913
914 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
915 struct i2c_msg msg[2] = {
916 {
917 .addr = client->addr,
918 .flags = 0,
919 .buf = &reg_fifo_data,
920 .len = sizeof(reg_fifo_data),
921 },
922 {
923 .addr = client->addr,
924 .flags = I2C_M_RD,
925 .buf = (u8 *)buffer,
926 .len = samples * sample_length,
927 }
928 };
929
930 ret = i2c_transfer(client->adapter, msg, 2);
931 if (ret != 2)
932 ret = -EIO;
933 else
934 ret = 0;
935 } else {
936 int i, step = I2C_SMBUS_BLOCK_MAX / sample_length;
937
938 for (i = 0; i < samples * sample_length; i += step) {
939 ret = i2c_smbus_read_i2c_block_data(client,
940 reg_fifo_data, step,
941 &buffer[i]);
942 if (ret != step) {
943 ret = -EIO;
944 break;
945 }
946
947 ret = 0;
948 }
949 }
950
951 if (ret)
952 dev_err(&client->dev, "Error transferring data from fifo\n");
953
954 return ret;
955}
956
957static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
958 unsigned samples, bool irq)
959{
960 struct bmc150_accel_data *data = iio_priv(indio_dev);
961 int ret, i;
962 u8 count;
963 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
964 int64_t tstamp;
965 uint64_t sample_period;
966 ret = i2c_smbus_read_byte_data(data->client,
967 BMC150_ACCEL_REG_FIFO_STATUS);
968 if (ret < 0) {
969 dev_err(&data->client->dev, "Error reading reg_fifo_status\n");
970 return ret;
971 }
972
973 count = ret & 0x7F;
974
975 if (!count)
976 return 0;
977
978 /*
979 * If we getting called from IRQ handler we know the stored timestamp is
980 * fairly accurate for the last stored sample. Otherwise, if we are
981 * called as a result of a read operation from userspace and hence
982 * before the watermark interrupt was triggered, take a timestamp
983 * now. We can fall anywhere in between two samples so the error in this
984 * case is at most one sample period.
985 */
986 if (!irq) {
987 data->old_timestamp = data->timestamp;
988 data->timestamp = iio_get_time_ns();
989 }
990
991 /*
992 * Approximate timestamps for each of the sample based on the sampling
993 * frequency, timestamp for last sample and number of samples.
994 *
995 * Note that we can't use the current bandwidth settings to compute the
996 * sample period because the sample rate varies with the device
997 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
998 * small variation adds when we store a large number of samples and
999 * creates significant jitter between the last and first samples in
1000 * different batches (e.g. 32ms vs 21ms).
1001 *
1002 * To avoid this issue we compute the actual sample period ourselves
1003 * based on the timestamp delta between the last two flush operations.
1004 */
1005 sample_period = (data->timestamp - data->old_timestamp);
1006 do_div(sample_period, count);
1007 tstamp = data->timestamp - (count - 1) * sample_period;
1008
1009 if (samples && count > samples)
1010 count = samples;
1011
1012 ret = bmc150_accel_fifo_transfer(data->client, (u8 *)buffer, count);
1013 if (ret)
1014 return ret;
1015
1016 /*
1017 * Ideally we want the IIO core to handle the demux when running in fifo
1018 * mode but not when running in triggered buffer mode. Unfortunately
1019 * this does not seem to be possible, so stick with driver demux for
1020 * now.
1021 */
1022 for (i = 0; i < count; i++) {
1023 u16 sample[8];
1024 int j, bit;
1025
1026 j = 0;
1027 for_each_set_bit(bit, indio_dev->active_scan_mask,
1028 indio_dev->masklength)
1029 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
1030
1031 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
1032
1033 tstamp += sample_period;
1034 }
1035
1036 return count;
1037}
1038
1039static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
1040{
1041 struct bmc150_accel_data *data = iio_priv(indio_dev);
1042 int ret;
1043
1044 mutex_lock(&data->mutex);
1045 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
1046 mutex_unlock(&data->mutex);
1047
1048 return ret;
1049}
1050
bd7fe5b7 1051static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
0ba8da96 1052 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
bd7fe5b7
SP		 1053
1054static struct attribute *bmc150_accel_attributes[] = {
1055 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1056 NULL,
1057};
1058
1059static const struct attribute_group bmc150_accel_attrs_group = {
1060 .attrs = bmc150_accel_attributes,
1061};
1062
1063static const struct iio_event_spec bmc150_accel_event = {
1064 .type = IIO_EV_TYPE_ROC,
1174124c 1065 .dir = IIO_EV_DIR_EITHER,
bd7fe5b7
SP		 1066 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1067 BIT(IIO_EV_INFO_ENABLE) |
1068 BIT(IIO_EV_INFO_PERIOD)
1069};
1070
8ecbb3c3 1071#define BMC150_ACCEL_CHANNEL(_axis, bits) { \
bd7fe5b7
SP		 1072 .type = IIO_ACCEL, \
1073 .modified = 1, \
1074 .channel2 = IIO_MOD_##_axis, \
1075 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1076 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
1077 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1078 .scan_index = AXIS_##_axis, \
1079 .scan_type = { \
1080 .sign = 's', \
8ecbb3c3 1081 .realbits = (bits), \
bd7fe5b7 1082 .storagebits = 16, \
8ecbb3c3 1083 .shift = 16 - (bits), \
bd7fe5b7
SP		 1084 }, \
1085 .event_spec = &bmc150_accel_event, \
1086 .num_event_specs = 1 \
1087}
1088
8ecbb3c3
LP		 1089#define BMC150_ACCEL_CHANNELS(bits) { \
1090 { \
1091 .type = IIO_TEMP, \
1092 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1093 BIT(IIO_CHAN_INFO_SCALE) | \
1094 BIT(IIO_CHAN_INFO_OFFSET), \
1095 .scan_index = -1, \
1096 }, \
1097 BMC150_ACCEL_CHANNEL(X, bits), \
1098 BMC150_ACCEL_CHANNEL(Y, bits), \
1099 BMC150_ACCEL_CHANNEL(Z, bits), \
1100 IIO_CHAN_SOFT_TIMESTAMP(3), \
1101}
1102
1103static const struct iio_chan_spec bma222e_accel_channels[] =
1104 BMC150_ACCEL_CHANNELS(8);
1105static const struct iio_chan_spec bma250e_accel_channels[] =
1106 BMC150_ACCEL_CHANNELS(10);
1107static const struct iio_chan_spec bmc150_accel_channels[] =
1108 BMC150_ACCEL_CHANNELS(12);
1109static const struct iio_chan_spec bma280_accel_channels[] =
1110 BMC150_ACCEL_CHANNELS(14);
1111
1112enum {
1113 bmc150,
1114 bmi055,
1115 bma255,
1116 bma250e,
1117 bma222e,
1118 bma280,
1119};
1120
1121static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1122 [bmc150] = {
1123 .chip_id = 0xFA,
1124 .channels = bmc150_accel_channels,
1125 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1126 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1127 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1128 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1129 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1130 },
1131 [bmi055] = {
1132 .chip_id = 0xFA,
1133 .channels = bmc150_accel_channels,
1134 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1135 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1136 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1137 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1138 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1139 },
1140 [bma255] = {
1141 .chip_id = 0xFA,
1142 .channels = bmc150_accel_channels,
1143 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1144 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1145 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1146 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1147 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1148 },
1149 [bma250e] = {
1150 .chip_id = 0xF9,
1151 .channels = bma250e_accel_channels,
1152 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1153 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1154 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1155 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1156 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1157 },
1158 [bma222e] = {
1159 .chip_id = 0xF8,
1160 .channels = bma222e_accel_channels,
1161 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1162 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1163 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1164 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1165 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1166 },
1167 [bma280] = {
1168 .chip_id = 0xFB,
1169 .channels = bma280_accel_channels,
1170 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1171 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1172 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1173 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1174 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
bd7fe5b7 1175 },
bd7fe5b7
SP		 1176};
1177
1178static const struct iio_info bmc150_accel_info = {
1179 .attrs = &bmc150_accel_attrs_group,
1180 .read_raw = bmc150_accel_read_raw,
1181 .write_raw = bmc150_accel_write_raw,
1182 .read_event_value = bmc150_accel_read_event,
1183 .write_event_value = bmc150_accel_write_event,
1184 .write_event_config = bmc150_accel_write_event_config,
1185 .read_event_config = bmc150_accel_read_event_config,
1186 .validate_trigger = bmc150_accel_validate_trigger,
1187 .driver_module = THIS_MODULE,
1188};
1189
3bbec977
OP		 1190static const struct iio_info bmc150_accel_info_fifo = {
1191 .attrs = &bmc150_accel_attrs_group,
1192 .read_raw = bmc150_accel_read_raw,
1193 .write_raw = bmc150_accel_write_raw,
1194 .read_event_value = bmc150_accel_read_event,
1195 .write_event_value = bmc150_accel_write_event,
1196 .write_event_config = bmc150_accel_write_event_config,
1197 .read_event_config = bmc150_accel_read_event_config,
1198 .validate_trigger = bmc150_accel_validate_trigger,
1199 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1200 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1201 .driver_module = THIS_MODULE,
1202};
1203
bd7fe5b7
SP		 1204static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1205{
1206 struct iio_poll_func *pf = p;
1207 struct iio_dev *indio_dev = pf->indio_dev;
1208 struct bmc150_accel_data *data = iio_priv(indio_dev);
1209 int bit, ret, i = 0;
1210
1211 mutex_lock(&data->mutex);
70dddeee 1212 for_each_set_bit(bit, indio_dev->active_scan_mask,
bd7fe5b7
SP		 1213 indio_dev->masklength) {
1214 ret = i2c_smbus_read_word_data(data->client,
1215 BMC150_ACCEL_AXIS_TO_REG(bit));
1216 if (ret < 0) {
1217 mutex_unlock(&data->mutex);
1218 goto err_read;
1219 }
1220 data->buffer[i++] = ret;
1221 }
1222 mutex_unlock(&data->mutex);
1223
1224 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1225 data->timestamp);
1226err_read:
1227 iio_trigger_notify_done(indio_dev->trig);
1228
1229 return IRQ_HANDLED;
1230}
1231
1232static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1233{
7d963215
OP		 1234 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1235 struct bmc150_accel_data *data = t->data;
bd7fe5b7
SP		 1236 int ret;
1237
1238 /* new data interrupts don't need ack */
7d963215 1239 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
bd7fe5b7
SP		 1240 return 0;
1241
1242 mutex_lock(&data->mutex);
1243 /* clear any latched interrupt */
1244 ret = i2c_smbus_write_byte_data(data->client,
1245 BMC150_ACCEL_REG_INT_RST_LATCH,
1246 BMC150_ACCEL_INT_MODE_LATCH_INT |
1247 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1248 mutex_unlock(&data->mutex);
1249 if (ret < 0) {
1250 dev_err(&data->client->dev,
1251 "Error writing reg_int_rst_latch\n");
1252 return ret;
1253 }
1254
1255 return 0;
1256}
1257
7d963215 1258static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
bd7fe5b7
SP		 1259 bool state)
1260{
7d963215
OP		 1261 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1262 struct bmc150_accel_data *data = t->data;
bd7fe5b7
SP		 1263 int ret;
1264
1265 mutex_lock(&data->mutex);
1266
7d963215
OP		 1267 if (t->enabled == state) {
1268 mutex_unlock(&data->mutex);
1269 return 0;
1270 }
1271
1272 if (t->setup) {
1273 ret = t->setup(t, state);
1274 if (ret < 0) {
14ee64f4 1275 mutex_unlock(&data->mutex);
7d963215 1276 return ret;
14ee64f4
OP		 1277 }
1278 }
1279
7d963215 1280 ret = bmc150_accel_set_interrupt(data, t->intr, state);
bd7fe5b7
SP		 1281 if (ret < 0) {
1282 mutex_unlock(&data->mutex);
1283 return ret;
1284 }
7d963215
OP		 1285
1286 t->enabled = state;
bd7fe5b7
SP		 1287
1288 mutex_unlock(&data->mutex);
1289
1290 return ret;
1291}
1292
1293static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
7d963215 1294 .set_trigger_state = bmc150_accel_trigger_set_state,
bd7fe5b7
SP		 1295 .try_reenable = bmc150_accel_trig_try_reen,
1296 .owner = THIS_MODULE,
1297};
1298
3bbec977 1299static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
bd7fe5b7 1300{
bd7fe5b7 1301 struct bmc150_accel_data *data = iio_priv(indio_dev);
bd7fe5b7 1302 int dir;
3bbec977 1303 int ret;
bd7fe5b7
SP		 1304
1305 ret = i2c_smbus_read_byte_data(data->client,
1306 BMC150_ACCEL_REG_INT_STATUS_2);
1307 if (ret < 0) {
1308 dev_err(&data->client->dev, "Error reading reg_int_status_2\n");
3bbec977 1309 return ret;
bd7fe5b7
SP		 1310 }
1311
1312 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1313 dir = IIO_EV_DIR_FALLING;
1314 else
1315 dir = IIO_EV_DIR_RISING;
1316
8d5a9781 1317 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X)
bd7fe5b7
SP		 1318 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
1319 0,
8d5a9781 1320 IIO_MOD_X,
bd7fe5b7 1321 IIO_EV_TYPE_ROC,
8d5a9781
SP		 1322 dir),
1323 data->timestamp);
1324 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1325 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
1326 0,
1327 IIO_MOD_Y,
1328 IIO_EV_TYPE_ROC,
1329 dir),
1330 data->timestamp);
1331 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1332 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
1333 0,
1334 IIO_MOD_Z,
1335 IIO_EV_TYPE_ROC,
1336 dir),
bd7fe5b7 1337 data->timestamp);
3bbec977
OP		 1338 return ret;
1339}
1340
1341static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1342{
1343 struct iio_dev *indio_dev = private;
1344 struct bmc150_accel_data *data = iio_priv(indio_dev);
1345 bool ack = false;
1346 int ret;
1347
1348 mutex_lock(&data->mutex);
1349
1350 if (data->fifo_mode) {
1351 ret = __bmc150_accel_fifo_flush(indio_dev,
1352 BMC150_ACCEL_FIFO_LENGTH, true);
1353 if (ret > 0)
1354 ack = true;
1355 }
1356
1357 if (data->ev_enable_state) {
1358 ret = bmc150_accel_handle_roc_event(indio_dev);
1359 if (ret > 0)
1360 ack = true;
1361 }
1362
1363 if (ack) {
bd7fe5b7
SP		 1364 ret = i2c_smbus_write_byte_data(data->client,
1365 BMC150_ACCEL_REG_INT_RST_LATCH,
1366 BMC150_ACCEL_INT_MODE_LATCH_INT |
1367 BMC150_ACCEL_INT_MODE_LATCH_RESET);
3bbec977
OP		 1368 if (ret)
1369 dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n");
1370 ret = IRQ_HANDLED;
1371 } else {
1372 ret = IRQ_NONE;
1373 }
bd7fe5b7 1374
3bbec977
OP		 1375 mutex_unlock(&data->mutex);
1376
1377 return ret;
bd7fe5b7
SP		 1378}
1379
3bbec977 1380static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
bd7fe5b7
SP		 1381{
1382 struct iio_dev *indio_dev = private;
1383 struct bmc150_accel_data *data = iio_priv(indio_dev);
3bbec977 1384 bool ack = false;
7d963215 1385 int i;
bd7fe5b7 1386
3bbec977 1387 data->old_timestamp = data->timestamp;
bd7fe5b7
SP		 1388 data->timestamp = iio_get_time_ns();
1389
7d963215
OP		 1390 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1391 if (data->triggers[i].enabled) {
1392 iio_trigger_poll(data->triggers[i].indio_trig);
3bbec977 1393 ack = true;
7d963215
OP		 1394 break;
1395 }
1396 }
bd7fe5b7 1397
3bbec977 1398 if (data->ev_enable_state || data->fifo_mode)
bd7fe5b7 1399 return IRQ_WAKE_THREAD;
3bbec977
OP		 1400
1401 if (ack)
bd7fe5b7 1402 return IRQ_HANDLED;
3bbec977
OP		 1403
1404 return IRQ_NONE;
bd7fe5b7
SP		 1405}
1406
8ecbb3c3 1407static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data)
bd7fe5b7
SP		 1408{
1409 const struct acpi_device_id *id;
8ecbb3c3
LP		 1410
1411 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1412
1413 if (!id)
1414 return NULL;
1415
1416 *data = (int) id->driver_data;
1417
1418 return dev_name(dev);
1419}
1420
1421static int bmc150_accel_gpio_probe(struct i2c_client *client,
1422 struct bmc150_accel_data *data)
1423{
bd7fe5b7
SP		 1424 struct device *dev;
1425 struct gpio_desc *gpio;
1426 int ret;
1427
1428 if (!client)
1429 return -EINVAL;
1430
1431 dev = &client->dev;
bd7fe5b7
SP		 1432
1433 /* data ready gpio interrupt pin */
b457f53a 1434 gpio = devm_gpiod_get_index(dev, BMC150_ACCEL_GPIO_NAME, 0, GPIOD_IN);
bd7fe5b7 1435 if (IS_ERR(gpio)) {
8ecbb3c3 1436 dev_err(dev, "Failed: gpio get index\n");
bd7fe5b7
SP		 1437 return PTR_ERR(gpio);
1438 }
1439
bd7fe5b7
SP		 1440 ret = gpiod_to_irq(gpio);
1441
1442 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
1443
1444 return ret;
1445}
1446
7d963215
OP		 1447static const struct {
1448 int intr;
1449 const char *name;
1450 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1451} bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1452 {
1453 .intr = 0,
1454 .name = "%s-dev%d",
1455 },
1456 {
1457 .intr = 1,
1458 .name = "%s-any-motion-dev%d",
1459 .setup = bmc150_accel_any_motion_setup,
1460 },
1461};
1462
1463static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1464 int from)
1465{
1466 int i;
1467
1468 for (i = from; i >= 0; i++) {
1469 if (data->triggers[i].indio_trig) {
1470 iio_trigger_unregister(data->triggers[i].indio_trig);
1471 data->triggers[i].indio_trig = NULL;
1472 }
1473 }
1474}
1475
1476static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1477 struct bmc150_accel_data *data)
1478{
1479 int i, ret;
1480
1481 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1482 struct bmc150_accel_trigger *t = &data->triggers[i];
1483
1484 t->indio_trig = devm_iio_trigger_alloc(&data->client->dev,
1485 bmc150_accel_triggers[i].name,
1486 indio_dev->name,
1487 indio_dev->id);
1488 if (!t->indio_trig) {
1489 ret = -ENOMEM;
1490 break;
1491 }
1492
1493 t->indio_trig->dev.parent = &data->client->dev;
1494 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1495 t->intr = bmc150_accel_triggers[i].intr;
1496 t->data = data;
1497 t->setup = bmc150_accel_triggers[i].setup;
1498 iio_trigger_set_drvdata(t->indio_trig, t);
1499
1500 ret = iio_trigger_register(t->indio_trig);
1501 if (ret)
1502 break;
1503 }
1504
1505 if (ret)
1506 bmc150_accel_unregister_triggers(data, i - 1);
1507
1508 return ret;
1509}
1510
3bbec977
OP		 1511#define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1512#define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1513#define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1514
1515static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1516{
1517 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1518 int ret;
1519
1520 ret = i2c_smbus_write_byte_data(data->client, reg, data->fifo_mode);
1521 if (ret < 0) {
1522 dev_err(&data->client->dev, "Error writing reg_fifo_config1\n");
1523 return ret;
1524 }
1525
1526 if (!data->fifo_mode)
1527 return 0;
1528
1529 ret = i2c_smbus_write_byte_data(data->client,
1530 BMC150_ACCEL_REG_FIFO_CONFIG0,
1531 data->watermark);
1532 if (ret < 0)
1533 dev_err(&data->client->dev, "Error writing reg_fifo_config0\n");
1534
1535 return ret;
1536}
1537
1538static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1539{
1540 struct bmc150_accel_data *data = iio_priv(indio_dev);
1541 int ret = 0;
1542
1543 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1544 return iio_triggered_buffer_postenable(indio_dev);
1545
1546 mutex_lock(&data->mutex);
1547
1548 if (!data->watermark)
1549 goto out;
1550
1551 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1552 true);
1553 if (ret)
1554 goto out;
1555
1556 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1557
1558 ret = bmc150_accel_fifo_set_mode(data);
1559 if (ret) {
1560 data->fifo_mode = 0;
1561 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1562 false);
1563 }
1564
1565out:
1566 mutex_unlock(&data->mutex);
1567
1568 return ret;
1569}
1570
1571static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1572{
1573 struct bmc150_accel_data *data = iio_priv(indio_dev);
1574
1575 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1576 return iio_triggered_buffer_predisable(indio_dev);
1577
1578 mutex_lock(&data->mutex);
1579
1580 if (!data->fifo_mode)
1581 goto out;
1582
1583 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1584 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1585 data->fifo_mode = 0;
1586 bmc150_accel_fifo_set_mode(data);
1587
1588out:
1589 mutex_unlock(&data->mutex);
1590
1591 return 0;
1592}
1593
1594static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1595 .postenable = bmc150_accel_buffer_postenable,
1596 .predisable = bmc150_accel_buffer_predisable,
1597};
1598
bd7fe5b7
SP		 1599static int bmc150_accel_probe(struct i2c_client *client,
1600 const struct i2c_device_id *id)
1601{
1602 struct bmc150_accel_data *data;
1603 struct iio_dev *indio_dev;
1604 int ret;
8ecbb3c3
LP		 1605 const char *name = NULL;
1606 int chip_id = 0;
bd7fe5b7
SP		 1607
1608 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1609 if (!indio_dev)
1610 return -ENOMEM;
1611
1612 data = iio_priv(indio_dev);
1613 i2c_set_clientdata(client, indio_dev);
1614 data->client = client;
1615
8ecbb3c3
LP		 1616 if (id) {
1617 name = id->name;
1618 chip_id = id->driver_data;
1619 }
1620
1621 if (ACPI_HANDLE(&client->dev))
1622 name = bmc150_accel_match_acpi_device(&client->dev, &chip_id);
1623
1624 data->chip_info = &bmc150_accel_chip_info_tbl[chip_id];
1625
bd7fe5b7
SP		 1626 ret = bmc150_accel_chip_init(data);
1627 if (ret < 0)
1628 return ret;
1629
1630 mutex_init(&data->mutex);
1631
1632 indio_dev->dev.parent = &client->dev;
8ecbb3c3
LP		 1633 indio_dev->channels = data->chip_info->channels;
1634 indio_dev->num_channels = data->chip_info->num_channels;
1635 indio_dev->name = name;
bd7fe5b7
SP		 1636 indio_dev->modes = INDIO_DIRECT_MODE;
1637 indio_dev->info = &bmc150_accel_info;
1638
1639 if (client->irq < 0)
8ecbb3c3 1640 client->irq = bmc150_accel_gpio_probe(client, data);
bd7fe5b7
SP		 1641
1642 if (client->irq >= 0) {
1643 ret = devm_request_threaded_irq(
1644 &client->dev, client->irq,
3bbec977
OP		 1645 bmc150_accel_irq_handler,
1646 bmc150_accel_irq_thread_handler,
bd7fe5b7
SP		 1647 IRQF_TRIGGER_RISING,
1648 BMC150_ACCEL_IRQ_NAME,
1649 indio_dev);
1650 if (ret)
1651 return ret;
1652
8e22f477
OP		 1653 /*
1654 * Set latched mode interrupt. While certain interrupts are
1655 * non-latched regardless of this settings (e.g. new data) we
1656 * want to use latch mode when we can to prevent interrupt
1657 * flooding.
1658 */
1659 ret = i2c_smbus_write_byte_data(data->client,
1660 BMC150_ACCEL_REG_INT_RST_LATCH,
1661 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1662 if (ret < 0) {
1663 dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n");
1664 return ret;
1665 }
1666
3e825ec9
OP		 1667 bmc150_accel_interrupts_setup(indio_dev, data);
1668
7d963215 1669 ret = bmc150_accel_triggers_setup(indio_dev, data);
bd7fe5b7
SP		 1670 if (ret)
1671 return ret;
1672
bd7fe5b7
SP		 1673 ret = iio_triggered_buffer_setup(indio_dev,
1674 &iio_pollfunc_store_time,
1675 bmc150_accel_trigger_handler,
3bbec977 1676 &bmc150_accel_buffer_ops);
bd7fe5b7
SP		 1677 if (ret < 0) {
1678 dev_err(&client->dev,
1679 "Failed: iio triggered buffer setup\n");
1680 goto err_trigger_unregister;
1681 }
3bbec977
OP		 1682
1683 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) ||
1684 i2c_check_functionality(client->adapter,
1685 I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
1686 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1687 indio_dev->info = &bmc150_accel_info_fifo;
1688 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1689 }
bd7fe5b7
SP		 1690 }
1691
1692 ret = iio_device_register(indio_dev);
1693 if (ret < 0) {
1694 dev_err(&client->dev, "Unable to register iio device\n");
1695 goto err_buffer_cleanup;
1696 }
1697
1698 ret = pm_runtime_set_active(&client->dev);
1699 if (ret)
1700 goto err_iio_unregister;
1701
1702 pm_runtime_enable(&client->dev);
1703 pm_runtime_set_autosuspend_delay(&client->dev,
1704 BMC150_AUTO_SUSPEND_DELAY_MS);
1705 pm_runtime_use_autosuspend(&client->dev);
1706
1707 return 0;
1708
1709err_iio_unregister:
1710 iio_device_unregister(indio_dev);
1711err_buffer_cleanup:
7d963215 1712 if (indio_dev->pollfunc)
bd7fe5b7
SP		 1713 iio_triggered_buffer_cleanup(indio_dev);
1714err_trigger_unregister:
7d963215 1715 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
bd7fe5b7
SP		 1716
1717 return ret;
1718}
1719
1720static int bmc150_accel_remove(struct i2c_client *client)
1721{
1722 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1723 struct bmc150_accel_data *data = iio_priv(indio_dev);
1724
1725 pm_runtime_disable(&client->dev);
1726 pm_runtime_set_suspended(&client->dev);
1727 pm_runtime_put_noidle(&client->dev);
1728
1729 iio_device_unregister(indio_dev);
1730
7d963215 1731 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
bd7fe5b7
SP		 1732
1733 mutex_lock(&data->mutex);
1734 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1735 mutex_unlock(&data->mutex);
1736
1737 return 0;
1738}
1739
1740#ifdef CONFIG_PM_SLEEP
1741static int bmc150_accel_suspend(struct device *dev)
1742{
1743 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1744 struct bmc150_accel_data *data = iio_priv(indio_dev);
1745
1746 mutex_lock(&data->mutex);
1747 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1748 mutex_unlock(&data->mutex);
1749
1750 return 0;
1751}
1752
1753static int bmc150_accel_resume(struct device *dev)
1754{
1755 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1756 struct bmc150_accel_data *data = iio_priv(indio_dev);
1757
1758 mutex_lock(&data->mutex);
3e825ec9 1759 if (atomic_read(&data->active_intr))
bd7fe5b7 1760 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
3bbec977 1761 bmc150_accel_fifo_set_mode(data);
bd7fe5b7
SP		 1762 mutex_unlock(&data->mutex);
1763
1764 return 0;
1765}
1766#endif
1767
6f0a13f2 1768#ifdef CONFIG_PM
bd7fe5b7
SP		 1769static int bmc150_accel_runtime_suspend(struct device *dev)
1770{
1771 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1772 struct bmc150_accel_data *data = iio_priv(indio_dev);
aaeecd80 1773 int ret;
bd7fe5b7
SP		 1774
1775 dev_dbg(&data->client->dev, __func__);
aaeecd80
SP		 1776 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1777 if (ret < 0)
1778 return -EAGAIN;
bd7fe5b7 1779
aaeecd80 1780 return 0;
bd7fe5b7
SP		 1781}
1782
1783static int bmc150_accel_runtime_resume(struct device *dev)
1784{
1785 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1786 struct bmc150_accel_data *data = iio_priv(indio_dev);
1787 int ret;
1788 int sleep_val;
1789
1790 dev_dbg(&data->client->dev, __func__);
1791
1792 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
3bbec977
OP		 1793 if (ret < 0)
1794 return ret;
1795 ret = bmc150_accel_fifo_set_mode(data);
bd7fe5b7
SP		 1796 if (ret < 0)
1797 return ret;
1798
1799 sleep_val = bmc150_accel_get_startup_times(data);
1800 if (sleep_val < 20)
1801 usleep_range(sleep_val * 1000, 20000);
1802 else
1803 msleep_interruptible(sleep_val);
1804
1805 return 0;
1806}
1807#endif
1808
1809static const struct dev_pm_ops bmc150_accel_pm_ops = {
1810 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1811 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1812 bmc150_accel_runtime_resume, NULL)
1813};
1814
1815static const struct acpi_device_id bmc150_accel_acpi_match[] = {
8ecbb3c3
LP		 1816 {"BSBA0150", bmc150},
1817 {"BMC150A", bmc150},
1818 {"BMI055A", bmi055},
1819 {"BMA0255", bma255},
1820 {"BMA250E", bma250e},
1821 {"BMA222E", bma222e},
1822 {"BMA0280", bma280},
bd7fe5b7
SP		 1823 { },
1824};
1825MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match);
1826
1827static const struct i2c_device_id bmc150_accel_id[] = {
8ecbb3c3
LP		 1828 {"bmc150_accel", bmc150},
1829 {"bmi055_accel", bmi055},
1830 {"bma255", bma255},
1831 {"bma250e", bma250e},
1832 {"bma222e", bma222e},
1833 {"bma280", bma280},
bd7fe5b7
SP		 1834 {}
1835};
1836
1837MODULE_DEVICE_TABLE(i2c, bmc150_accel_id);
1838
1839static struct i2c_driver bmc150_accel_driver = {
1840 .driver = {
1841 .name = BMC150_ACCEL_DRV_NAME,
1842 .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match),
1843 .pm = &bmc150_accel_pm_ops,
1844 },
1845 .probe = bmc150_accel_probe,
1846 .remove = bmc150_accel_remove,
1847 .id_table = bmc150_accel_id,
1848};
1849module_i2c_driver(bmc150_accel_driver);
1850
1851MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1852MODULE_LICENSE("GPL v2");
1853MODULE_DESCRIPTION("BMC150 accelerometer driver");
Linux kernel - Deliverables
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