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staging: iio: light: isl29018: add ACPI support
[deliverable/linux.git] / drivers / iio / accel / bmc150-accel.c
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bd7fe5b7
SP		 1/*
2 * BMC150 3-axis accelerometer driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/module.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/slab.h>
20#include <linux/acpi.h>
21#include <linux/gpio/consumer.h>
22#include <linux/pm.h>
23#include <linux/pm_runtime.h>
24#include <linux/iio/iio.h>
25#include <linux/iio/sysfs.h>
26#include <linux/iio/buffer.h>
27#include <linux/iio/events.h>
28#include <linux/iio/trigger.h>
29#include <linux/iio/trigger_consumer.h>
30#include <linux/iio/triggered_buffer.h>
31
32#define BMC150_ACCEL_DRV_NAME "bmc150_accel"
33#define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
34#define BMC150_ACCEL_GPIO_NAME "bmc150_accel_int"
35
36#define BMC150_ACCEL_REG_CHIP_ID 0x00
37#define BMC150_ACCEL_CHIP_ID_VAL 0xFA
38
39#define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
40#define BMC150_ACCEL_ANY_MOTION_MASK 0x07
41#define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
42
43#define BMC150_ACCEL_REG_PMU_LPW 0x11
44#define BMC150_ACCEL_PMU_MODE_MASK 0xE0
45#define BMC150_ACCEL_PMU_MODE_SHIFT 5
46#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
47#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
48
49#define BMC150_ACCEL_REG_PMU_RANGE 0x0F
50
51#define BMC150_ACCEL_DEF_RANGE_2G 0x03
52#define BMC150_ACCEL_DEF_RANGE_4G 0x05
53#define BMC150_ACCEL_DEF_RANGE_8G 0x08
54#define BMC150_ACCEL_DEF_RANGE_16G 0x0C
55
56/* Default BW: 125Hz */
57#define BMC150_ACCEL_REG_PMU_BW 0x10
58#define BMC150_ACCEL_DEF_BW 125
59
60#define BMC150_ACCEL_REG_INT_MAP_0 0x19
61#define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
62
63#define BMC150_ACCEL_REG_INT_MAP_1 0x1A
64#define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
65
66#define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
67#define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
68#define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
69#define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
70
71#define BMC150_ACCEL_REG_INT_EN_0 0x16
72#define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
73#define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
74#define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
75
76#define BMC150_ACCEL_REG_INT_EN_1 0x17
77#define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
78
79#define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
80#define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
81
82#define BMC150_ACCEL_REG_INT_5 0x27
83#define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
84
85#define BMC150_ACCEL_REG_INT_6 0x28
86#define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
87
88/* Slope duration in terms of number of samples */
89#define BMC150_ACCEL_DEF_SLOPE_DURATION 2
90/* in terms of multiples of g's/LSB, based on range */
91#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 5
92
93#define BMC150_ACCEL_REG_XOUT_L 0x02
94
95#define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
96
97/* Sleep Duration values */
98#define BMC150_ACCEL_SLEEP_500_MICRO 0x05
99#define BMC150_ACCEL_SLEEP_1_MS 0x06
100#define BMC150_ACCEL_SLEEP_2_MS 0x07
101#define BMC150_ACCEL_SLEEP_4_MS 0x08
102#define BMC150_ACCEL_SLEEP_6_MS 0x09
103#define BMC150_ACCEL_SLEEP_10_MS 0x0A
104#define BMC150_ACCEL_SLEEP_25_MS 0x0B
105#define BMC150_ACCEL_SLEEP_50_MS 0x0C
106#define BMC150_ACCEL_SLEEP_100_MS 0x0D
107#define BMC150_ACCEL_SLEEP_500_MS 0x0E
108#define BMC150_ACCEL_SLEEP_1_SEC 0x0F
109
110#define BMC150_ACCEL_REG_TEMP 0x08
111#define BMC150_ACCEL_TEMP_CENTER_VAL 24
112
113#define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
114#define BMC150_AUTO_SUSPEND_DELAY_MS 2000
115
116enum bmc150_accel_axis {
117 AXIS_X,
118 AXIS_Y,
119 AXIS_Z,
120};
121
122enum bmc150_power_modes {
123 BMC150_ACCEL_SLEEP_MODE_NORMAL,
124 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
125 BMC150_ACCEL_SLEEP_MODE_LPM,
126 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
127};
128
129struct bmc150_accel_data {
130 struct i2c_client *client;
131 struct iio_trigger *dready_trig;
132 struct iio_trigger *motion_trig;
133 struct mutex mutex;
134 s16 buffer[8];
135 u8 bw_bits;
136 u32 slope_dur;
137 u32 slope_thres;
138 u32 range;
139 int ev_enable_state;
140 bool dready_trigger_on;
141 bool motion_trigger_on;
142 int64_t timestamp;
143};
144
145static const struct {
146 int val;
147 int val2;
148 u8 bw_bits;
149} bmc150_accel_samp_freq_table[] = { {7, 810000, 0x08},
150 {15, 630000, 0x09},
151 {31, 250000, 0x0A},
152 {62, 500000, 0x0B},
153 {125, 0, 0x0C},
154 {250, 0, 0x0D},
155 {500, 0, 0x0E},
156 {1000, 0, 0x0F} };
157
158static const struct {
159 int bw_bits;
160 int msec;
161} bmc150_accel_sample_upd_time[] = { {0x08, 64},
162 {0x09, 32},
163 {0x0A, 16},
164 {0x0B, 8},
165 {0x0C, 4},
166 {0x0D, 2},
167 {0x0E, 1},
168 {0x0F, 1} };
169
170static const struct {
171 int scale;
172 int range;
173} bmc150_accel_scale_table[] = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
174 {19122, BMC150_ACCEL_DEF_RANGE_4G},
175 {38344, BMC150_ACCEL_DEF_RANGE_8G},
823615e2 176 {76590, BMC150_ACCEL_DEF_RANGE_16G} };
bd7fe5b7
SP		 177
178static const struct {
179 int sleep_dur;
180 int reg_value;
181} bmc150_accel_sleep_value_table[] = { {0, 0},
182 {500, BMC150_ACCEL_SLEEP_500_MICRO},
183 {1000, BMC150_ACCEL_SLEEP_1_MS},
184 {2000, BMC150_ACCEL_SLEEP_2_MS},
185 {4000, BMC150_ACCEL_SLEEP_4_MS},
186 {6000, BMC150_ACCEL_SLEEP_6_MS},
187 {10000, BMC150_ACCEL_SLEEP_10_MS},
188 {25000, BMC150_ACCEL_SLEEP_25_MS},
189 {50000, BMC150_ACCEL_SLEEP_50_MS},
190 {100000, BMC150_ACCEL_SLEEP_100_MS},
191 {500000, BMC150_ACCEL_SLEEP_500_MS},
192 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
193
194
195static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
196 enum bmc150_power_modes mode,
197 int dur_us)
198{
199 int i;
200 int ret;
201 u8 lpw_bits;
202 int dur_val = -1;
203
204 if (dur_us > 0) {
205 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
206 ++i) {
207 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
208 dur_us)
209 dur_val =
210 bmc150_accel_sleep_value_table[i].reg_value;
211 }
212 } else
213 dur_val = 0;
214
215 if (dur_val < 0)
216 return -EINVAL;
217
218 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
219 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
220
221 dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits);
222
223 ret = i2c_smbus_write_byte_data(data->client,
224 BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
225 if (ret < 0) {
226 dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n");
227 return ret;
228 }
229
230 return 0;
231}
232
233static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
234 int val2)
235{
236 int i;
237 int ret;
238
239 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
240 if (bmc150_accel_samp_freq_table[i].val == val &&
241 bmc150_accel_samp_freq_table[i].val2 == val2) {
242 ret = i2c_smbus_write_byte_data(
243 data->client,
244 BMC150_ACCEL_REG_PMU_BW,
245 bmc150_accel_samp_freq_table[i].bw_bits);
246 if (ret < 0)
247 return ret;
248
249 data->bw_bits =
250 bmc150_accel_samp_freq_table[i].bw_bits;
251 return 0;
252 }
253 }
254
255 return -EINVAL;
256}
257
258static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
259{
260 int ret;
261
262 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID);
263 if (ret < 0) {
264 dev_err(&data->client->dev,
265 "Error: Reading chip id\n");
266 return ret;
267 }
268
269 dev_dbg(&data->client->dev, "Chip Id %x\n", ret);
270 if (ret != BMC150_ACCEL_CHIP_ID_VAL) {
271 dev_err(&data->client->dev, "Invalid chip %x\n", ret);
272 return -ENODEV;
273 }
274
275 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
276 if (ret < 0)
277 return ret;
278
279 /* Set Bandwidth */
280 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
281 if (ret < 0)
282 return ret;
283
284 /* Set Default Range */
285 ret = i2c_smbus_write_byte_data(data->client,
286 BMC150_ACCEL_REG_PMU_RANGE,
287 BMC150_ACCEL_DEF_RANGE_4G);
288 if (ret < 0) {
289 dev_err(&data->client->dev,
290 "Error writing reg_pmu_range\n");
291 return ret;
292 }
293
294 data->range = BMC150_ACCEL_DEF_RANGE_4G;
295
296 /* Set default slope duration */
297 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5);
298 if (ret < 0) {
299 dev_err(&data->client->dev, "Error reading reg_int_5\n");
300 return ret;
301 }
302 data->slope_dur |= BMC150_ACCEL_DEF_SLOPE_DURATION;
303 ret = i2c_smbus_write_byte_data(data->client,
304 BMC150_ACCEL_REG_INT_5,
305 data->slope_dur);
306 if (ret < 0) {
307 dev_err(&data->client->dev, "Error writing reg_int_5\n");
308 return ret;
309 }
310 dev_dbg(&data->client->dev, "slope_dur %x\n", data->slope_dur);
311
312 /* Set default slope thresholds */
313 ret = i2c_smbus_write_byte_data(data->client,
314 BMC150_ACCEL_REG_INT_6,
315 BMC150_ACCEL_DEF_SLOPE_THRESHOLD);
316 if (ret < 0) {
317 dev_err(&data->client->dev, "Error writing reg_int_6\n");
318 return ret;
319 }
320 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
321 dev_dbg(&data->client->dev, "slope_thres %x\n", data->slope_thres);
322
323 /* Set default as latched interrupts */
324 ret = i2c_smbus_write_byte_data(data->client,
325 BMC150_ACCEL_REG_INT_RST_LATCH,
326 BMC150_ACCEL_INT_MODE_LATCH_INT |
327 BMC150_ACCEL_INT_MODE_LATCH_RESET);
328 if (ret < 0) {
329 dev_err(&data->client->dev,
330 "Error writing reg_int_rst_latch\n");
331 return ret;
332 }
333
334 return 0;
335}
336
337static int bmc150_accel_setup_any_motion_interrupt(
338 struct bmc150_accel_data *data,
339 bool status)
340{
341 int ret;
342
343 /* Enable/Disable INT1 mapping */
344 ret = i2c_smbus_read_byte_data(data->client,
345 BMC150_ACCEL_REG_INT_MAP_0);
346 if (ret < 0) {
347 dev_err(&data->client->dev, "Error reading reg_int_map_0\n");
348 return ret;
349 }
350 if (status)
351 ret |= BMC150_ACCEL_INT_MAP_0_BIT_SLOPE;
352 else
353 ret &= ~BMC150_ACCEL_INT_MAP_0_BIT_SLOPE;
354
355 ret = i2c_smbus_write_byte_data(data->client,
356 BMC150_ACCEL_REG_INT_MAP_0,
357 ret);
358 if (ret < 0) {
359 dev_err(&data->client->dev, "Error writing reg_int_map_0\n");
360 return ret;
361 }
362
363 if (status) {
364 /* Set slope duration (no of samples) */
365 ret = i2c_smbus_write_byte_data(data->client,
366 BMC150_ACCEL_REG_INT_5,
367 data->slope_dur);
368 if (ret < 0) {
369 dev_err(&data->client->dev, "Error write reg_int_5\n");
370 return ret;
371 }
372
373 /* Set slope thresholds */
374 ret = i2c_smbus_write_byte_data(data->client,
375 BMC150_ACCEL_REG_INT_6,
376 data->slope_thres);
377 if (ret < 0) {
378 dev_err(&data->client->dev, "Error write reg_int_6\n");
379 return ret;
380 }
381
382 /*
383 * New data interrupt is always non-latched,
384 * which will have higher priority, so no need
385 * to set latched mode, we will be flooded anyway with INTR
386 */
387 if (!data->dready_trigger_on) {
388 ret = i2c_smbus_write_byte_data(data->client,
389 BMC150_ACCEL_REG_INT_RST_LATCH,
390 BMC150_ACCEL_INT_MODE_LATCH_INT |
391 BMC150_ACCEL_INT_MODE_LATCH_RESET);
392 if (ret < 0) {
393 dev_err(&data->client->dev,
394 "Error writing reg_int_rst_latch\n");
395 return ret;
396 }
397 }
398
399 ret = i2c_smbus_write_byte_data(data->client,
400 BMC150_ACCEL_REG_INT_EN_0,
401 BMC150_ACCEL_INT_EN_BIT_SLP_X |
402 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
403 BMC150_ACCEL_INT_EN_BIT_SLP_Z);
404 } else
405 ret = i2c_smbus_write_byte_data(data->client,
406 BMC150_ACCEL_REG_INT_EN_0,
407 0);
408
409 if (ret < 0) {
410 dev_err(&data->client->dev, "Error writing reg_int_en_0\n");
411 return ret;
412 }
413
414 return 0;
415}
416
417static int bmc150_accel_setup_new_data_interrupt(struct bmc150_accel_data *data,
418 bool status)
419{
420 int ret;
421
422 /* Enable/Disable INT1 mapping */
423 ret = i2c_smbus_read_byte_data(data->client,
424 BMC150_ACCEL_REG_INT_MAP_1);
425 if (ret < 0) {
426 dev_err(&data->client->dev, "Error reading reg_int_map_1\n");
427 return ret;
428 }
429 if (status)
430 ret |= BMC150_ACCEL_INT_MAP_1_BIT_DATA;
431 else
432 ret &= ~BMC150_ACCEL_INT_MAP_1_BIT_DATA;
433
434 ret = i2c_smbus_write_byte_data(data->client,
435 BMC150_ACCEL_REG_INT_MAP_1,
436 ret);
437 if (ret < 0) {
438 dev_err(&data->client->dev, "Error writing reg_int_map_1\n");
439 return ret;
440 }
441
442 if (status) {
443 /*
444 * Set non latched mode interrupt and clear any latched
445 * interrupt
446 */
447 ret = i2c_smbus_write_byte_data(data->client,
448 BMC150_ACCEL_REG_INT_RST_LATCH,
449 BMC150_ACCEL_INT_MODE_NON_LATCH_INT |
450 BMC150_ACCEL_INT_MODE_LATCH_RESET);
451 if (ret < 0) {
452 dev_err(&data->client->dev,
453 "Error writing reg_int_rst_latch\n");
454 return ret;
455 }
456
457 ret = i2c_smbus_write_byte_data(data->client,
458 BMC150_ACCEL_REG_INT_EN_1,
459 BMC150_ACCEL_INT_EN_BIT_DATA_EN);
460
461 } else {
462 /* Restore default interrupt mode */
463 ret = i2c_smbus_write_byte_data(data->client,
464 BMC150_ACCEL_REG_INT_RST_LATCH,
465 BMC150_ACCEL_INT_MODE_LATCH_INT |
466 BMC150_ACCEL_INT_MODE_LATCH_RESET);
467 if (ret < 0) {
468 dev_err(&data->client->dev,
469 "Error writing reg_int_rst_latch\n");
470 return ret;
471 }
472
473 ret = i2c_smbus_write_byte_data(data->client,
474 BMC150_ACCEL_REG_INT_EN_1,
475 0);
476 }
477
478 if (ret < 0) {
479 dev_err(&data->client->dev, "Error writing reg_int_en_1\n");
480 return ret;
481 }
482
483 return 0;
484}
485
486static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
487 int *val2)
488{
489 int i;
490
491 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
492 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
493 *val = bmc150_accel_samp_freq_table[i].val;
494 *val2 = bmc150_accel_samp_freq_table[i].val2;
495 return IIO_VAL_INT_PLUS_MICRO;
496 }
497 }
498
499 return -EINVAL;
500}
501
b31b05cf 502#ifdef CONFIG_PM_RUNTIME
bd7fe5b7
SP		 503static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
504{
505 int i;
506
507 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
508 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
509 return bmc150_accel_sample_upd_time[i].msec;
510 }
511
512 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
513}
514
515static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
516{
517 int ret;
518
519 if (on)
520 ret = pm_runtime_get_sync(&data->client->dev);
521 else {
522 pm_runtime_mark_last_busy(&data->client->dev);
523 ret = pm_runtime_put_autosuspend(&data->client->dev);
524 }
525 if (ret < 0) {
526 dev_err(&data->client->dev,
527 "Failed: bmc150_accel_set_power_state for %d\n", on);
528 return ret;
529 }
530
531 return 0;
532}
b31b05cf
LP		 533#else
534static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
535{
536 return 0;
537}
538#endif
bd7fe5b7
SP		 539
540static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
541{
542 int ret, i;
543
544 for (i = 0; i < ARRAY_SIZE(bmc150_accel_scale_table); ++i) {
545 if (bmc150_accel_scale_table[i].scale == val) {
546 ret = i2c_smbus_write_byte_data(
547 data->client,
548 BMC150_ACCEL_REG_PMU_RANGE,
549 bmc150_accel_scale_table[i].range);
550 if (ret < 0) {
551 dev_err(&data->client->dev,
552 "Error writing pmu_range\n");
553 return ret;
554 }
555
556 data->range = bmc150_accel_scale_table[i].range;
557 return 0;
558 }
559 }
560
561 return -EINVAL;
562}
563
564static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
565{
566 int ret;
567
568 mutex_lock(&data->mutex);
569
570 ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP);
571 if (ret < 0) {
572 dev_err(&data->client->dev, "Error reading reg_temp\n");
573 mutex_unlock(&data->mutex);
574 return ret;
575 }
576 *val = sign_extend32(ret, 7);
577
578 mutex_unlock(&data->mutex);
579
580 return IIO_VAL_INT;
581}
582
583static int bmc150_accel_get_axis(struct bmc150_accel_data *data, int axis,
584 int *val)
585{
586 int ret;
587
588 mutex_lock(&data->mutex);
589 ret = bmc150_accel_set_power_state(data, true);
590 if (ret < 0) {
591 mutex_unlock(&data->mutex);
592 return ret;
593 }
594
595 ret = i2c_smbus_read_word_data(data->client,
596 BMC150_ACCEL_AXIS_TO_REG(axis));
597 if (ret < 0) {
598 dev_err(&data->client->dev, "Error reading axis %d\n", axis);
599 bmc150_accel_set_power_state(data, false);
600 mutex_unlock(&data->mutex);
601 return ret;
602 }
603 *val = sign_extend32(ret >> 4, 11);
604 ret = bmc150_accel_set_power_state(data, false);
605 mutex_unlock(&data->mutex);
606 if (ret < 0)
607 return ret;
608
609 return IIO_VAL_INT;
610}
611
612static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
613 struct iio_chan_spec const *chan,
614 int *val, int *val2, long mask)
615{
616 struct bmc150_accel_data *data = iio_priv(indio_dev);
617 int ret;
618
619 switch (mask) {
620 case IIO_CHAN_INFO_RAW:
621 switch (chan->type) {
622 case IIO_TEMP:
623 return bmc150_accel_get_temp(data, val);
624 case IIO_ACCEL:
625 if (iio_buffer_enabled(indio_dev))
626 return -EBUSY;
627 else
628 return bmc150_accel_get_axis(data,
629 chan->scan_index,
630 val);
631 default:
632 return -EINVAL;
633 }
634 case IIO_CHAN_INFO_OFFSET:
635 if (chan->type == IIO_TEMP) {
636 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
637 return IIO_VAL_INT;
638 } else
639 return -EINVAL;
640 case IIO_CHAN_INFO_SCALE:
641 *val = 0;
642 switch (chan->type) {
643 case IIO_TEMP:
644 *val2 = 500000;
645 return IIO_VAL_INT_PLUS_MICRO;
646 case IIO_ACCEL:
647 {
648 int i;
649
650 for (i = 0; i < ARRAY_SIZE(bmc150_accel_scale_table);
651 ++i) {
652 if (bmc150_accel_scale_table[i].range ==
653 data->range) {
654 *val2 =
655 bmc150_accel_scale_table[i].scale;
656 return IIO_VAL_INT_PLUS_MICRO;
657 }
658 }
659 return -EINVAL;
660 }
661 default:
662 return -EINVAL;
663 }
664 case IIO_CHAN_INFO_SAMP_FREQ:
665 mutex_lock(&data->mutex);
666 ret = bmc150_accel_get_bw(data, val, val2);
667 mutex_unlock(&data->mutex);
668 return ret;
669 default:
670 return -EINVAL;
671 }
672}
673
674static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
675 struct iio_chan_spec const *chan,
676 int val, int val2, long mask)
677{
678 struct bmc150_accel_data *data = iio_priv(indio_dev);
679 int ret;
680
681 switch (mask) {
682 case IIO_CHAN_INFO_SAMP_FREQ:
683 mutex_lock(&data->mutex);
684 ret = bmc150_accel_set_bw(data, val, val2);
685 mutex_unlock(&data->mutex);
686 break;
687 case IIO_CHAN_INFO_SCALE:
688 if (val)
689 return -EINVAL;
690
691 mutex_lock(&data->mutex);
692 ret = bmc150_accel_set_scale(data, val2);
693 mutex_unlock(&data->mutex);
694 return ret;
695 default:
696 ret = -EINVAL;
697 }
698
699 return ret;
700}
701
702static int bmc150_accel_read_event(struct iio_dev *indio_dev,
703 const struct iio_chan_spec *chan,
704 enum iio_event_type type,
705 enum iio_event_direction dir,
706 enum iio_event_info info,
707 int *val, int *val2)
708{
709 struct bmc150_accel_data *data = iio_priv(indio_dev);
710
711 *val2 = 0;
712 switch (info) {
713 case IIO_EV_INFO_VALUE:
714 *val = data->slope_thres;
715 break;
716 case IIO_EV_INFO_PERIOD:
717 *val = data->slope_dur & BMC150_ACCEL_SLOPE_DUR_MASK;
718 break;
719 default:
720 return -EINVAL;
721 }
722
723 return IIO_VAL_INT;
724}
725
726static int bmc150_accel_write_event(struct iio_dev *indio_dev,
727 const struct iio_chan_spec *chan,
728 enum iio_event_type type,
729 enum iio_event_direction dir,
730 enum iio_event_info info,
731 int val, int val2)
732{
733 struct bmc150_accel_data *data = iio_priv(indio_dev);
734
735 if (data->ev_enable_state)
736 return -EBUSY;
737
738 switch (info) {
739 case IIO_EV_INFO_VALUE:
740 data->slope_thres = val;
741 break;
742 case IIO_EV_INFO_PERIOD:
743 data->slope_dur &= ~BMC150_ACCEL_SLOPE_DUR_MASK;
744 data->slope_dur |= val & BMC150_ACCEL_SLOPE_DUR_MASK;
745 break;
746 default:
747 return -EINVAL;
748 }
749
750 return 0;
751}
752
753static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
754 const struct iio_chan_spec *chan,
755 enum iio_event_type type,
756 enum iio_event_direction dir)
757{
758
759 struct bmc150_accel_data *data = iio_priv(indio_dev);
760
761 return data->ev_enable_state;
762}
763
764static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
765 const struct iio_chan_spec *chan,
766 enum iio_event_type type,
767 enum iio_event_direction dir,
768 int state)
769{
770 struct bmc150_accel_data *data = iio_priv(indio_dev);
771 int ret;
772
773 if (state && data->ev_enable_state)
774 return 0;
775
776 mutex_lock(&data->mutex);
777
778 if (!state && data->motion_trigger_on) {
779 data->ev_enable_state = 0;
780 mutex_unlock(&data->mutex);
781 return 0;
782 }
783
784 /*
785 * We will expect the enable and disable to do operation in
786 * in reverse order. This will happen here anyway as our
787 * resume operation uses sync mode runtime pm calls, the
788 * suspend operation will be delayed by autosuspend delay
789 * So the disable operation will still happen in reverse of
790 * enable operation. When runtime pm is disabled the mode
791 * is always on so sequence doesn't matter
792 */
793
794 ret = bmc150_accel_set_power_state(data, state);
795 if (ret < 0) {
796 mutex_unlock(&data->mutex);
797 return ret;
798 }
799
800 ret = bmc150_accel_setup_any_motion_interrupt(data, state);
801 if (ret < 0) {
802 mutex_unlock(&data->mutex);
803 return ret;
804 }
805
806 data->ev_enable_state = state;
807 mutex_unlock(&data->mutex);
808
809 return 0;
810}
811
812static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
813 struct iio_trigger *trig)
814{
815 struct bmc150_accel_data *data = iio_priv(indio_dev);
816
817 if (data->dready_trig != trig && data->motion_trig != trig)
818 return -EINVAL;
819
820 return 0;
821}
822
823static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
824 "7.810000 15.630000 31.250000 62.500000 125 250 500 1000");
825
826static struct attribute *bmc150_accel_attributes[] = {
827 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
828 NULL,
829};
830
831static const struct attribute_group bmc150_accel_attrs_group = {
832 .attrs = bmc150_accel_attributes,
833};
834
835static const struct iio_event_spec bmc150_accel_event = {
836 .type = IIO_EV_TYPE_ROC,
837 .dir = IIO_EV_DIR_RISING | IIO_EV_DIR_FALLING,
838 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
839 BIT(IIO_EV_INFO_ENABLE) |
840 BIT(IIO_EV_INFO_PERIOD)
841};
842
843#define BMC150_ACCEL_CHANNEL(_axis) { \
844 .type = IIO_ACCEL, \
845 .modified = 1, \
846 .channel2 = IIO_MOD_##_axis, \
847 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
848 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
849 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
850 .scan_index = AXIS_##_axis, \
851 .scan_type = { \
852 .sign = 's', \
853 .realbits = 12, \
854 .storagebits = 16, \
855 .shift = 4, \
856 }, \
857 .event_spec = &bmc150_accel_event, \
858 .num_event_specs = 1 \
859}
860
861static const struct iio_chan_spec bmc150_accel_channels[] = {
862 {
863 .type = IIO_TEMP,
864 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
865 BIT(IIO_CHAN_INFO_SCALE) |
866 BIT(IIO_CHAN_INFO_OFFSET),
867 .scan_index = -1,
868 },
869 BMC150_ACCEL_CHANNEL(X),
870 BMC150_ACCEL_CHANNEL(Y),
871 BMC150_ACCEL_CHANNEL(Z),
872 IIO_CHAN_SOFT_TIMESTAMP(3),
873};
874
875static const struct iio_info bmc150_accel_info = {
876 .attrs = &bmc150_accel_attrs_group,
877 .read_raw = bmc150_accel_read_raw,
878 .write_raw = bmc150_accel_write_raw,
879 .read_event_value = bmc150_accel_read_event,
880 .write_event_value = bmc150_accel_write_event,
881 .write_event_config = bmc150_accel_write_event_config,
882 .read_event_config = bmc150_accel_read_event_config,
883 .validate_trigger = bmc150_accel_validate_trigger,
884 .driver_module = THIS_MODULE,
885};
886
887static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
888{
889 struct iio_poll_func *pf = p;
890 struct iio_dev *indio_dev = pf->indio_dev;
891 struct bmc150_accel_data *data = iio_priv(indio_dev);
892 int bit, ret, i = 0;
893
894 mutex_lock(&data->mutex);
895 for_each_set_bit(bit, indio_dev->buffer->scan_mask,
896 indio_dev->masklength) {
897 ret = i2c_smbus_read_word_data(data->client,
898 BMC150_ACCEL_AXIS_TO_REG(bit));
899 if (ret < 0) {
900 mutex_unlock(&data->mutex);
901 goto err_read;
902 }
903 data->buffer[i++] = ret;
904 }
905 mutex_unlock(&data->mutex);
906
907 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
908 data->timestamp);
909err_read:
910 iio_trigger_notify_done(indio_dev->trig);
911
912 return IRQ_HANDLED;
913}
914
915static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
916{
917 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
918 struct bmc150_accel_data *data = iio_priv(indio_dev);
919 int ret;
920
921 /* new data interrupts don't need ack */
922 if (data->dready_trigger_on)
923 return 0;
924
925 mutex_lock(&data->mutex);
926 /* clear any latched interrupt */
927 ret = i2c_smbus_write_byte_data(data->client,
928 BMC150_ACCEL_REG_INT_RST_LATCH,
929 BMC150_ACCEL_INT_MODE_LATCH_INT |
930 BMC150_ACCEL_INT_MODE_LATCH_RESET);
931 mutex_unlock(&data->mutex);
932 if (ret < 0) {
933 dev_err(&data->client->dev,
934 "Error writing reg_int_rst_latch\n");
935 return ret;
936 }
937
938 return 0;
939}
940
941static int bmc150_accel_data_rdy_trigger_set_state(struct iio_trigger *trig,
942 bool state)
943{
944 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
945 struct bmc150_accel_data *data = iio_priv(indio_dev);
946 int ret;
947
948 mutex_lock(&data->mutex);
949
950 if (!state && data->ev_enable_state && data->motion_trigger_on) {
951 data->motion_trigger_on = false;
952 mutex_unlock(&data->mutex);
953 return 0;
954 }
955
956 /*
957 * Refer to comment in bmc150_accel_write_event_config for
958 * enable/disable operation order
959 */
960 ret = bmc150_accel_set_power_state(data, state);
961 if (ret < 0) {
962 mutex_unlock(&data->mutex);
963 return ret;
964 }
965 if (data->motion_trig == trig)
966 ret = bmc150_accel_setup_any_motion_interrupt(data, state);
967 else
968 ret = bmc150_accel_setup_new_data_interrupt(data, state);
969 if (ret < 0) {
970 mutex_unlock(&data->mutex);
971 return ret;
972 }
973 if (data->motion_trig == trig)
974 data->motion_trigger_on = state;
975 else
976 data->dready_trigger_on = state;
977
978 mutex_unlock(&data->mutex);
979
980 return ret;
981}
982
983static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
984 .set_trigger_state = bmc150_accel_data_rdy_trigger_set_state,
985 .try_reenable = bmc150_accel_trig_try_reen,
986 .owner = THIS_MODULE,
987};
988
989static irqreturn_t bmc150_accel_event_handler(int irq, void *private)
990{
991 struct iio_dev *indio_dev = private;
992 struct bmc150_accel_data *data = iio_priv(indio_dev);
993 int ret;
994 int dir;
995
996 ret = i2c_smbus_read_byte_data(data->client,
997 BMC150_ACCEL_REG_INT_STATUS_2);
998 if (ret < 0) {
999 dev_err(&data->client->dev, "Error reading reg_int_status_2\n");
1000 goto ack_intr_status;
1001 }
1002
1003 if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1004 dir = IIO_EV_DIR_FALLING;
1005 else
1006 dir = IIO_EV_DIR_RISING;
1007
1008 if (ret & BMC150_ACCEL_ANY_MOTION_MASK)
1009 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
1010 0,
1011 IIO_MOD_X_OR_Y_OR_Z,
1012 IIO_EV_TYPE_ROC,
1013 IIO_EV_DIR_EITHER),
1014 data->timestamp);
1015ack_intr_status:
1016 if (!data->dready_trigger_on)
1017 ret = i2c_smbus_write_byte_data(data->client,
1018 BMC150_ACCEL_REG_INT_RST_LATCH,
1019 BMC150_ACCEL_INT_MODE_LATCH_INT |
1020 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1021
1022 return IRQ_HANDLED;
1023}
1024
1025static irqreturn_t bmc150_accel_data_rdy_trig_poll(int irq, void *private)
1026{
1027 struct iio_dev *indio_dev = private;
1028 struct bmc150_accel_data *data = iio_priv(indio_dev);
1029
1030 data->timestamp = iio_get_time_ns();
1031
1032 if (data->dready_trigger_on)
1033 iio_trigger_poll(data->dready_trig);
1034 else if (data->motion_trigger_on)
1035 iio_trigger_poll(data->motion_trig);
1036
1037 if (data->ev_enable_state)
1038 return IRQ_WAKE_THREAD;
1039 else
1040 return IRQ_HANDLED;
1041}
1042
1043static int bmc150_accel_acpi_gpio_probe(struct i2c_client *client,
1044 struct bmc150_accel_data *data)
1045{
1046 const struct acpi_device_id *id;
1047 struct device *dev;
1048 struct gpio_desc *gpio;
1049 int ret;
1050
1051 if (!client)
1052 return -EINVAL;
1053
1054 dev = &client->dev;
1055 if (!ACPI_HANDLE(dev))
1056 return -ENODEV;
1057
1058 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1059 if (!id)
1060 return -ENODEV;
1061
1062 /* data ready gpio interrupt pin */
1063 gpio = devm_gpiod_get_index(dev, BMC150_ACCEL_GPIO_NAME, 0);
1064 if (IS_ERR(gpio)) {
1065 dev_err(dev, "Failed: acpi gpio get index\n");
1066 return PTR_ERR(gpio);
1067 }
1068
1069 ret = gpiod_direction_input(gpio);
1070 if (ret)
1071 return ret;
1072
1073 ret = gpiod_to_irq(gpio);
1074
1075 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
1076
1077 return ret;
1078}
1079
1080static int bmc150_accel_probe(struct i2c_client *client,
1081 const struct i2c_device_id *id)
1082{
1083 struct bmc150_accel_data *data;
1084 struct iio_dev *indio_dev;
1085 int ret;
1086
1087 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1088 if (!indio_dev)
1089 return -ENOMEM;
1090
1091 data = iio_priv(indio_dev);
1092 i2c_set_clientdata(client, indio_dev);
1093 data->client = client;
1094
1095 ret = bmc150_accel_chip_init(data);
1096 if (ret < 0)
1097 return ret;
1098
1099 mutex_init(&data->mutex);
1100
1101 indio_dev->dev.parent = &client->dev;
1102 indio_dev->channels = bmc150_accel_channels;
1103 indio_dev->num_channels = ARRAY_SIZE(bmc150_accel_channels);
1104 indio_dev->name = BMC150_ACCEL_DRV_NAME;
1105 indio_dev->modes = INDIO_DIRECT_MODE;
1106 indio_dev->info = &bmc150_accel_info;
1107
1108 if (client->irq < 0)
1109 client->irq = bmc150_accel_acpi_gpio_probe(client, data);
1110
1111 if (client->irq >= 0) {
1112 ret = devm_request_threaded_irq(
1113 &client->dev, client->irq,
1114 bmc150_accel_data_rdy_trig_poll,
1115 bmc150_accel_event_handler,
1116 IRQF_TRIGGER_RISING,
1117 BMC150_ACCEL_IRQ_NAME,
1118 indio_dev);
1119 if (ret)
1120 return ret;
1121
1122 data->dready_trig = devm_iio_trigger_alloc(&client->dev,
1123 "%s-dev%d",
1124 indio_dev->name,
1125 indio_dev->id);
1126 if (!data->dready_trig)
1127 return -ENOMEM;
1128
1129 data->motion_trig = devm_iio_trigger_alloc(&client->dev,
1130 "%s-any-motion-dev%d",
1131 indio_dev->name,
1132 indio_dev->id);
1133 if (!data->motion_trig)
1134 return -ENOMEM;
1135
1136 data->dready_trig->dev.parent = &client->dev;
1137 data->dready_trig->ops = &bmc150_accel_trigger_ops;
1138 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1139 ret = iio_trigger_register(data->dready_trig);
1140 if (ret)
1141 return ret;
1142
1143 data->motion_trig->dev.parent = &client->dev;
1144 data->motion_trig->ops = &bmc150_accel_trigger_ops;
1145 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1146 ret = iio_trigger_register(data->motion_trig);
1147 if (ret) {
1148 data->motion_trig = NULL;
1149 goto err_trigger_unregister;
1150 }
1151
1152 ret = iio_triggered_buffer_setup(indio_dev,
1153 &iio_pollfunc_store_time,
1154 bmc150_accel_trigger_handler,
1155 NULL);
1156 if (ret < 0) {
1157 dev_err(&client->dev,
1158 "Failed: iio triggered buffer setup\n");
1159 goto err_trigger_unregister;
1160 }
1161 }
1162
1163 ret = iio_device_register(indio_dev);
1164 if (ret < 0) {
1165 dev_err(&client->dev, "Unable to register iio device\n");
1166 goto err_buffer_cleanup;
1167 }
1168
1169 ret = pm_runtime_set_active(&client->dev);
1170 if (ret)
1171 goto err_iio_unregister;
1172
1173 pm_runtime_enable(&client->dev);
1174 pm_runtime_set_autosuspend_delay(&client->dev,
1175 BMC150_AUTO_SUSPEND_DELAY_MS);
1176 pm_runtime_use_autosuspend(&client->dev);
1177
1178 return 0;
1179
1180err_iio_unregister:
1181 iio_device_unregister(indio_dev);
1182err_buffer_cleanup:
1183 if (data->dready_trig)
1184 iio_triggered_buffer_cleanup(indio_dev);
1185err_trigger_unregister:
1186 if (data->dready_trig)
1187 iio_trigger_unregister(data->dready_trig);
1188 if (data->motion_trig)
1189 iio_trigger_unregister(data->motion_trig);
1190
1191 return ret;
1192}
1193
1194static int bmc150_accel_remove(struct i2c_client *client)
1195{
1196 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1197 struct bmc150_accel_data *data = iio_priv(indio_dev);
1198
1199 pm_runtime_disable(&client->dev);
1200 pm_runtime_set_suspended(&client->dev);
1201 pm_runtime_put_noidle(&client->dev);
1202
1203 iio_device_unregister(indio_dev);
1204
1205 if (data->dready_trig) {
1206 iio_triggered_buffer_cleanup(indio_dev);
1207 iio_trigger_unregister(data->dready_trig);
1208 iio_trigger_unregister(data->motion_trig);
1209 }
1210
1211 mutex_lock(&data->mutex);
1212 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1213 mutex_unlock(&data->mutex);
1214
1215 return 0;
1216}
1217
1218#ifdef CONFIG_PM_SLEEP
1219static int bmc150_accel_suspend(struct device *dev)
1220{
1221 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1222 struct bmc150_accel_data *data = iio_priv(indio_dev);
1223
1224 mutex_lock(&data->mutex);
1225 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1226 mutex_unlock(&data->mutex);
1227
1228 return 0;
1229}
1230
1231static int bmc150_accel_resume(struct device *dev)
1232{
1233 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1234 struct bmc150_accel_data *data = iio_priv(indio_dev);
1235
1236 mutex_lock(&data->mutex);
1237 if (data->dready_trigger_on || data->motion_trigger_on ||
1238 data->ev_enable_state)
1239 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1240 mutex_unlock(&data->mutex);
1241
1242 return 0;
1243}
1244#endif
1245
1246#ifdef CONFIG_PM_RUNTIME
1247static int bmc150_accel_runtime_suspend(struct device *dev)
1248{
1249 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1250 struct bmc150_accel_data *data = iio_priv(indio_dev);
1251
1252 dev_dbg(&data->client->dev, __func__);
1253
1254 return bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1255}
1256
1257static int bmc150_accel_runtime_resume(struct device *dev)
1258{
1259 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1260 struct bmc150_accel_data *data = iio_priv(indio_dev);
1261 int ret;
1262 int sleep_val;
1263
1264 dev_dbg(&data->client->dev, __func__);
1265
1266 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1267 if (ret < 0)
1268 return ret;
1269
1270 sleep_val = bmc150_accel_get_startup_times(data);
1271 if (sleep_val < 20)
1272 usleep_range(sleep_val * 1000, 20000);
1273 else
1274 msleep_interruptible(sleep_val);
1275
1276 return 0;
1277}
1278#endif
1279
1280static const struct dev_pm_ops bmc150_accel_pm_ops = {
1281 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1282 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1283 bmc150_accel_runtime_resume, NULL)
1284};
1285
1286static const struct acpi_device_id bmc150_accel_acpi_match[] = {
1287 {"BSBA0150", 0},
1288 {"BMC150A", 0},
1289 { },
1290};
1291MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match);
1292
1293static const struct i2c_device_id bmc150_accel_id[] = {
1294 {"bmc150_accel", 0},
1295 {}
1296};
1297
1298MODULE_DEVICE_TABLE(i2c, bmc150_accel_id);
1299
1300static struct i2c_driver bmc150_accel_driver = {
1301 .driver = {
1302 .name = BMC150_ACCEL_DRV_NAME,
1303 .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match),
1304 .pm = &bmc150_accel_pm_ops,
1305 },
1306 .probe = bmc150_accel_probe,
1307 .remove = bmc150_accel_remove,
1308 .id_table = bmc150_accel_id,
1309};
1310module_i2c_driver(bmc150_accel_driver);
1311
1312MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1313MODULE_LICENSE("GPL v2");
1314MODULE_DESCRIPTION("BMC150 accelerometer driver");
Linux kernel - Deliverables
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