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drm/modes: drop __drm_framebuffer_unregister.
[deliverable/linux.git] / drivers / iio / accel / kxcjk-1013.c
CommitLineData
1a4fbf6a
SP		 1/*
2 * KXCJK-1013 3-axis accelerometer driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/module.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/bitops.h>
20#include <linux/slab.h>
21#include <linux/string.h>
22#include <linux/acpi.h>
23#include <linux/gpio/consumer.h>
124e1b1d
SP		 24#include <linux/pm.h>
25#include <linux/pm_runtime.h>
1a4fbf6a
SP		 26#include <linux/iio/iio.h>
27#include <linux/iio/sysfs.h>
28#include <linux/iio/buffer.h>
29#include <linux/iio/trigger.h>
b4b491c0 30#include <linux/iio/events.h>
1a4fbf6a
SP		 31#include <linux/iio/trigger_consumer.h>
32#include <linux/iio/triggered_buffer.h>
33#include <linux/iio/accel/kxcjk_1013.h>
34
35#define KXCJK1013_DRV_NAME "kxcjk1013"
36#define KXCJK1013_IRQ_NAME "kxcjk1013_event"
37
38#define KXCJK1013_REG_XOUT_L 0x06
39/*
40 * From low byte X axis register, all the other addresses of Y and Z can be
41 * obtained by just applying axis offset. The following axis defines are just
42 * provide clarity, but not used.
43 */
44#define KXCJK1013_REG_XOUT_H 0x07
45#define KXCJK1013_REG_YOUT_L 0x08
46#define KXCJK1013_REG_YOUT_H 0x09
47#define KXCJK1013_REG_ZOUT_L 0x0A
48#define KXCJK1013_REG_ZOUT_H 0x0B
49
50#define KXCJK1013_REG_DCST_RESP 0x0C
51#define KXCJK1013_REG_WHO_AM_I 0x0F
52#define KXCJK1013_REG_INT_SRC1 0x16
53#define KXCJK1013_REG_INT_SRC2 0x17
54#define KXCJK1013_REG_STATUS_REG 0x18
55#define KXCJK1013_REG_INT_REL 0x1A
56#define KXCJK1013_REG_CTRL1 0x1B
57#define KXCJK1013_REG_CTRL2 0x1D
58#define KXCJK1013_REG_INT_CTRL1 0x1E
59#define KXCJK1013_REG_INT_CTRL2 0x1F
60#define KXCJK1013_REG_DATA_CTRL 0x21
61#define KXCJK1013_REG_WAKE_TIMER 0x29
62#define KXCJK1013_REG_SELF_TEST 0x3A
63#define KXCJK1013_REG_WAKE_THRES 0x6A
64
65#define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
66#define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
67#define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
68#define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
69#define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
70#define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
71#define KXCJK1013_REG_INT_REG1_BIT_IEA BIT(4)
72#define KXCJK1013_REG_INT_REG1_BIT_IEN BIT(5)
73
74#define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
75#define KXCJK1013_MAX_STARTUP_TIME_US 100000
76
124e1b1d
SP		 77#define KXCJK1013_SLEEP_DELAY_MS 2000
78
b4b491c0
SP		 79#define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
80#define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
81#define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
82#define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
83#define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
84#define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
85
86#define KXCJK1013_DEFAULT_WAKE_THRES 1
87
c6861377
DB		 88enum kx_chipset {
89 KXCJK1013,
90 KXCJ91008,
91 KXTJ21009,
92 KX_MAX_CHIPS /* this must be last */
93};
94
1a4fbf6a
SP		 95struct kxcjk1013_data {
96 struct i2c_client *client;
b4b491c0
SP		 97 struct iio_trigger *dready_trig;
98 struct iio_trigger *motion_trig;
1a4fbf6a
SP		 99 struct mutex mutex;
100 s16 buffer[8];
1a4fbf6a 101 u8 odr_bits;
a735e3d7 102 u8 range;
b4b491c0
SP		 103 int wake_thres;
104 int wake_dur;
1a4fbf6a 105 bool active_high_intr;
b4b491c0
SP		 106 bool dready_trigger_on;
107 int ev_enable_state;
108 bool motion_trigger_on;
109 int64_t timestamp;
c6861377 110 enum kx_chipset chipset;
3bfa74f8 111 bool is_smo8500_device;
1a4fbf6a
SP		 112};
113
114enum kxcjk1013_axis {
115 AXIS_X,
116 AXIS_Y,
117 AXIS_Z,
118};
119
120enum kxcjk1013_mode {
121 STANDBY,
122 OPERATION,
123};
124
a735e3d7
SP		 125enum kxcjk1013_range {
126 KXCJK1013_RANGE_2G,
127 KXCJK1013_RANGE_4G,
128 KXCJK1013_RANGE_8G,
129};
130
1a4fbf6a
SP		 131static const struct {
132 int val;
133 int val2;
134 int odr_bits;
135} samp_freq_table[] = { {0, 781000, 0x08}, {1, 563000, 0x09},
f0ca9749 136 {3, 125000, 0x0A}, {6, 250000, 0x0B}, {12, 500000, 0},
1a4fbf6a
SP		 137 {25, 0, 0x01}, {50, 0, 0x02}, {100, 0, 0x03},
138 {200, 0, 0x04}, {400, 0, 0x05}, {800, 0, 0x06},
139 {1600, 0, 0x07} };
140
141/* Refer to section 4 of the specification */
142static const struct {
143 int odr_bits;
144 int usec;
c6861377
DB		 145} odr_start_up_times[KX_MAX_CHIPS][12] = {
146 /* KXCJK-1013 */
147 {
148 {0x08, 100000},
149 {0x09, 100000},
150 {0x0A, 100000},
151 {0x0B, 100000},
152 {0, 80000},
153 {0x01, 41000},
154 {0x02, 21000},
155 {0x03, 11000},
156 {0x04, 6400},
157 {0x05, 3900},
158 {0x06, 2700},
159 {0x07, 2100},
160 },
161 /* KXCJ9-1008 */
162 {
163 {0x08, 100000},
164 {0x09, 100000},
165 {0x0A, 100000},
166 {0x0B, 100000},
167 {0, 80000},
168 {0x01, 41000},
169 {0x02, 21000},
170 {0x03, 11000},
171 {0x04, 6400},
172 {0x05, 3900},
173 {0x06, 2700},
174 {0x07, 2100},
175 },
176 /* KXCTJ2-1009 */
177 {
178 {0x08, 1240000},
179 {0x09, 621000},
180 {0x0A, 309000},
181 {0x0B, 151000},
182 {0, 80000},
183 {0x01, 41000},
184 {0x02, 21000},
185 {0x03, 11000},
186 {0x04, 6000},
187 {0x05, 4000},
188 {0x06, 3000},
189 {0x07, 2000},
190 },
191};
1a4fbf6a 192
a735e3d7
SP		 193static const struct {
194 u16 scale;
195 u8 gsel_0;
196 u8 gsel_1;
197} KXCJK1013_scale_table[] = { {9582, 0, 0},
198 {19163, 1, 0},
199 {38326, 0, 1} };
200
b4b491c0
SP		 201static const struct {
202 int val;
203 int val2;
204 int odr_bits;
205} wake_odr_data_rate_table[] = { {0, 781000, 0x00},
206 {1, 563000, 0x01},
207 {3, 125000, 0x02},
208 {6, 250000, 0x03},
209 {12, 500000, 0x04},
210 {25, 0, 0x05},
211 {50, 0, 0x06},
212 {100, 0, 0x06},
213 {200, 0, 0x06},
214 {400, 0, 0x06},
215 {800, 0, 0x06},
216 {1600, 0, 0x06} };
217
1a4fbf6a
SP		 218static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
219 enum kxcjk1013_mode mode)
220{
221 int ret;
222
223 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
224 if (ret < 0) {
225 dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
226 return ret;
227 }
228
229 if (mode == STANDBY)
230 ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
231 else
232 ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
233
234 ret = i2c_smbus_write_byte_data(data->client,
235 KXCJK1013_REG_CTRL1, ret);
236 if (ret < 0) {
237 dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
238 return ret;
239 }
240
241 return 0;
242}
243
124e1b1d
SP		 244static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
245 enum kxcjk1013_mode *mode)
246{
247 int ret;
248
249 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
250 if (ret < 0) {
251 dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
252 return ret;
253 }
254
255 if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
256 *mode = OPERATION;
257 else
258 *mode = STANDBY;
259
260 return 0;
261}
262
a735e3d7
SP		 263static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
264{
265 int ret;
266
267 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
268 if (ret < 0) {
269 dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
270 return ret;
271 }
272
e90dea6a
DB		 273 ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
274 KXCJK1013_REG_CTRL1_BIT_GSEL1);
a735e3d7
SP		 275 ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
276 ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
277
278 ret = i2c_smbus_write_byte_data(data->client,
279 KXCJK1013_REG_CTRL1,
280 ret);
281 if (ret < 0) {
282 dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
283 return ret;
284 }
285
286 data->range = range_index;
287
288 return 0;
289}
290
1a4fbf6a
SP		 291static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
292{
293 int ret;
294
295 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
296 if (ret < 0) {
297 dev_err(&data->client->dev, "Error reading who_am_i\n");
298 return ret;
299 }
300
301 dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
302
303 ret = kxcjk1013_set_mode(data, STANDBY);
304 if (ret < 0)
305 return ret;
306
307 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
308 if (ret < 0) {
309 dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
310 return ret;
311 }
312
1a4fbf6a
SP		 313 /* Set 12 bit mode */
314 ret |= KXCJK1013_REG_CTRL1_BIT_RES;
315
316 ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL1,
317 ret);
318 if (ret < 0) {
319 dev_err(&data->client->dev, "Error reading reg_ctrl\n");
320 return ret;
321 }
322
a735e3d7
SP		 323 /* Setting range to 4G */
324 ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
325 if (ret < 0)
326 return ret;
327
1a4fbf6a
SP		 328 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_DATA_CTRL);
329 if (ret < 0) {
330 dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
331 return ret;
332 }
333
334 data->odr_bits = ret;
335
336 /* Set up INT polarity */
337 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
338 if (ret < 0) {
339 dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
340 return ret;
341 }
342
343 if (data->active_high_intr)
344 ret |= KXCJK1013_REG_INT_REG1_BIT_IEA;
345 else
346 ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEA;
347
348 ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
349 ret);
350 if (ret < 0) {
351 dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
352 return ret;
353 }
354
124e1b1d
SP		 355 ret = kxcjk1013_set_mode(data, OPERATION);
356 if (ret < 0)
357 return ret;
358
b4b491c0
SP		 359 data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
360
124e1b1d
SP		 361 return 0;
362}
363
6f0a13f2 364#ifdef CONFIG_PM
124e1b1d
SP		 365static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
366{
367 int i;
c6861377 368 int idx = data->chipset;
124e1b1d 369
c6861377
DB		 370 for (i = 0; i < ARRAY_SIZE(odr_start_up_times[idx]); ++i) {
371 if (odr_start_up_times[idx][i].odr_bits == data->odr_bits)
372 return odr_start_up_times[idx][i].usec;
124e1b1d
SP		 373 }
374
375 return KXCJK1013_MAX_STARTUP_TIME_US;
376}
c9bf2373 377#endif
124e1b1d
SP		 378
379static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
380{
c75b8dc8 381#ifdef CONFIG_PM
124e1b1d
SP		 382 int ret;
383
384 if (on)
385 ret = pm_runtime_get_sync(&data->client->dev);
386 else {
387 pm_runtime_mark_last_busy(&data->client->dev);
388 ret = pm_runtime_put_autosuspend(&data->client->dev);
389 }
390 if (ret < 0) {
391 dev_err(&data->client->dev,
392 "Failed: kxcjk1013_set_power_state for %d\n", on);
fbd123e9
IT		 393 if (on)
394 pm_runtime_put_noidle(&data->client->dev);
124e1b1d
SP		 395 return ret;
396 }
c75b8dc8 397#endif
124e1b1d 398
1a4fbf6a
SP		 399 return 0;
400}
401
b4b491c0
SP		 402static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
403{
404 int ret;
405
406 ret = i2c_smbus_write_byte_data(data->client,
407 KXCJK1013_REG_WAKE_TIMER,
408 data->wake_dur);
409 if (ret < 0) {
410 dev_err(&data->client->dev,
411 "Error writing reg_wake_timer\n");
412 return ret;
413 }
414
415 ret = i2c_smbus_write_byte_data(data->client,
416 KXCJK1013_REG_WAKE_THRES,
417 data->wake_thres);
418 if (ret < 0) {
419 dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
420 return ret;
421 }
422
423 return 0;
424}
425
426static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
427 bool status)
428{
429 int ret;
430 enum kxcjk1013_mode store_mode;
431
432 ret = kxcjk1013_get_mode(data, &store_mode);
433 if (ret < 0)
434 return ret;
435
436 /* This is requirement by spec to change state to STANDBY */
437 ret = kxcjk1013_set_mode(data, STANDBY);
438 if (ret < 0)
439 return ret;
440
441 ret = kxcjk1013_chip_update_thresholds(data);
442 if (ret < 0)
443 return ret;
444
445 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
446 if (ret < 0) {
447 dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
448 return ret;
449 }
450
451 if (status)
452 ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
453 else
454 ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
455
456 ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
457 ret);
458 if (ret < 0) {
459 dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
460 return ret;
461 }
462
463 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
464 if (ret < 0) {
465 dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
466 return ret;
467 }
468
469 if (status)
470 ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
471 else
472 ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
473
474 ret = i2c_smbus_write_byte_data(data->client,
475 KXCJK1013_REG_CTRL1, ret);
476 if (ret < 0) {
477 dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
478 return ret;
479 }
480
481 if (store_mode == OPERATION) {
482 ret = kxcjk1013_set_mode(data, OPERATION);
483 if (ret < 0)
484 return ret;
485 }
486
487 return 0;
488}
489
490static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
491 bool status)
1a4fbf6a
SP		 492{
493 int ret;
124e1b1d
SP		 494 enum kxcjk1013_mode store_mode;
495
496 ret = kxcjk1013_get_mode(data, &store_mode);
497 if (ret < 0)
498 return ret;
1a4fbf6a
SP		 499
500 /* This is requirement by spec to change state to STANDBY */
501 ret = kxcjk1013_set_mode(data, STANDBY);
502 if (ret < 0)
503 return ret;
504
505 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
506 if (ret < 0) {
507 dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
508 return ret;
509 }
510
511 if (status)
512 ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
513 else
514 ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
515
516 ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
517 ret);
518 if (ret < 0) {
519 dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
520 return ret;
521 }
522
523 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
524 if (ret < 0) {
525 dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
526 return ret;
527 }
528
529 if (status)
530 ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
531 else
532 ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
533
534 ret = i2c_smbus_write_byte_data(data->client,
535 KXCJK1013_REG_CTRL1, ret);
536 if (ret < 0) {
537 dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
538 return ret;
539 }
540
124e1b1d
SP		 541 if (store_mode == OPERATION) {
542 ret = kxcjk1013_set_mode(data, OPERATION);
543 if (ret < 0)
544 return ret;
545 }
546
547 return 0;
1a4fbf6a
SP		 548}
549
550static int kxcjk1013_convert_freq_to_bit(int val, int val2)
551{
552 int i;
553
554 for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
555 if (samp_freq_table[i].val == val &&
556 samp_freq_table[i].val2 == val2) {
557 return samp_freq_table[i].odr_bits;
558 }
559 }
560
561 return -EINVAL;
562}
563
b4b491c0
SP		 564static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2)
565{
566 int i;
567
568 for (i = 0; i < ARRAY_SIZE(wake_odr_data_rate_table); ++i) {
569 if (wake_odr_data_rate_table[i].val == val &&
570 wake_odr_data_rate_table[i].val2 == val2) {
571 return wake_odr_data_rate_table[i].odr_bits;
572 }
573 }
574
575 return -EINVAL;
576}
577
1a4fbf6a
SP		 578static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
579{
580 int ret;
581 int odr_bits;
124e1b1d
SP		 582 enum kxcjk1013_mode store_mode;
583
584 ret = kxcjk1013_get_mode(data, &store_mode);
585 if (ret < 0)
586 return ret;
1a4fbf6a
SP		 587
588 odr_bits = kxcjk1013_convert_freq_to_bit(val, val2);
589 if (odr_bits < 0)
590 return odr_bits;
591
592 /* To change ODR, the chip must be set to STANDBY as per spec */
593 ret = kxcjk1013_set_mode(data, STANDBY);
594 if (ret < 0)
595 return ret;
596
597 ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL,
598 odr_bits);
599 if (ret < 0) {
600 dev_err(&data->client->dev, "Error writing data_ctrl\n");
601 return ret;
602 }
603
604 data->odr_bits = odr_bits;
605
b4b491c0
SP		 606 odr_bits = kxcjk1013_convert_wake_odr_to_bit(val, val2);
607 if (odr_bits < 0)
608 return odr_bits;
609
610 ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2,
611 odr_bits);
612 if (ret < 0) {
613 dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
614 return ret;
615 }
616
124e1b1d 617 if (store_mode == OPERATION) {
1a4fbf6a
SP		 618 ret = kxcjk1013_set_mode(data, OPERATION);
619 if (ret < 0)
620 return ret;
621 }
622
623 return 0;
624}
625
626static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
627{
628 int i;
629
630 for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
631 if (samp_freq_table[i].odr_bits == data->odr_bits) {
632 *val = samp_freq_table[i].val;
633 *val2 = samp_freq_table[i].val2;
634 return IIO_VAL_INT_PLUS_MICRO;
635 }
636 }
637
638 return -EINVAL;
639}
640
641static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
642{
643 u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
644 int ret;
645
646 ret = i2c_smbus_read_word_data(data->client, reg);
647 if (ret < 0) {
648 dev_err(&data->client->dev,
649 "failed to read accel_%c registers\n", 'x' + axis);
650 return ret;
651 }
652
653 return ret;
654}
655
a735e3d7
SP		 656static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
657{
658 int ret, i;
659 enum kxcjk1013_mode store_mode;
660
a735e3d7
SP		 661 for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
662 if (KXCJK1013_scale_table[i].scale == val) {
a735e3d7
SP		 663 ret = kxcjk1013_get_mode(data, &store_mode);
664 if (ret < 0)
665 return ret;
666
667 ret = kxcjk1013_set_mode(data, STANDBY);
668 if (ret < 0)
669 return ret;
670
671 ret = kxcjk1013_set_range(data, i);
672 if (ret < 0)
673 return ret;
674
675 if (store_mode == OPERATION) {
676 ret = kxcjk1013_set_mode(data, OPERATION);
677 if (ret)
678 return ret;
679 }
680
681 return 0;
682 }
683 }
684
685 return -EINVAL;
686}
687
1a4fbf6a
SP		 688static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
689 struct iio_chan_spec const *chan, int *val,
690 int *val2, long mask)
691{
692 struct kxcjk1013_data *data = iio_priv(indio_dev);
693 int ret;
694
695 switch (mask) {
696 case IIO_CHAN_INFO_RAW:
697 mutex_lock(&data->mutex);
698 if (iio_buffer_enabled(indio_dev))
699 ret = -EBUSY;
700 else {
124e1b1d 701 ret = kxcjk1013_set_power_state(data, true);
88f6da77
SP		 702 if (ret < 0) {
703 mutex_unlock(&data->mutex);
1a4fbf6a 704 return ret;
88f6da77 705 }
1a4fbf6a 706 ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
124e1b1d
SP		 707 if (ret < 0) {
708 kxcjk1013_set_power_state(data, false);
709 mutex_unlock(&data->mutex);
710 return ret;
711 }
712 *val = sign_extend32(ret >> 4, 11);
713 ret = kxcjk1013_set_power_state(data, false);
1a4fbf6a
SP		 714 }
715 mutex_unlock(&data->mutex);
716
717 if (ret < 0)
718 return ret;
719
1a4fbf6a
SP		 720 return IIO_VAL_INT;
721
722 case IIO_CHAN_INFO_SCALE:
723 *val = 0;
a735e3d7 724 *val2 = KXCJK1013_scale_table[data->range].scale;
1a4fbf6a
SP		 725 return IIO_VAL_INT_PLUS_MICRO;
726
727 case IIO_CHAN_INFO_SAMP_FREQ:
728 mutex_lock(&data->mutex);
729 ret = kxcjk1013_get_odr(data, val, val2);
730 mutex_unlock(&data->mutex);
731 return ret;
732
733 default:
734 return -EINVAL;
735 }
736}
737
738static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
739 struct iio_chan_spec const *chan, int val,
740 int val2, long mask)
741{
742 struct kxcjk1013_data *data = iio_priv(indio_dev);
743 int ret;
744
745 switch (mask) {
746 case IIO_CHAN_INFO_SAMP_FREQ:
747 mutex_lock(&data->mutex);
748 ret = kxcjk1013_set_odr(data, val, val2);
749 mutex_unlock(&data->mutex);
750 break;
a735e3d7
SP		 751 case IIO_CHAN_INFO_SCALE:
752 if (val)
753 return -EINVAL;
754
755 mutex_lock(&data->mutex);
756 ret = kxcjk1013_set_scale(data, val2);
757 mutex_unlock(&data->mutex);
758 break;
1a4fbf6a
SP		 759 default:
760 ret = -EINVAL;
761 }
762
763 return ret;
764}
765
b4b491c0
SP		 766static int kxcjk1013_read_event(struct iio_dev *indio_dev,
767 const struct iio_chan_spec *chan,
768 enum iio_event_type type,
769 enum iio_event_direction dir,
770 enum iio_event_info info,
771 int *val, int *val2)
772{
773 struct kxcjk1013_data *data = iio_priv(indio_dev);
774
775 *val2 = 0;
776 switch (info) {
777 case IIO_EV_INFO_VALUE:
778 *val = data->wake_thres;
779 break;
780 case IIO_EV_INFO_PERIOD:
781 *val = data->wake_dur;
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 return IIO_VAL_INT;
788}
789
790static int kxcjk1013_write_event(struct iio_dev *indio_dev,
791 const struct iio_chan_spec *chan,
792 enum iio_event_type type,
793 enum iio_event_direction dir,
794 enum iio_event_info info,
795 int val, int val2)
796{
797 struct kxcjk1013_data *data = iio_priv(indio_dev);
798
799 if (data->ev_enable_state)
800 return -EBUSY;
801
802 switch (info) {
803 case IIO_EV_INFO_VALUE:
804 data->wake_thres = val;
805 break;
806 case IIO_EV_INFO_PERIOD:
807 data->wake_dur = val;
808 break;
809 default:
810 return -EINVAL;
811 }
812
813 return 0;
814}
815
816static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
817 const struct iio_chan_spec *chan,
818 enum iio_event_type type,
819 enum iio_event_direction dir)
820{
b4b491c0
SP		 821 struct kxcjk1013_data *data = iio_priv(indio_dev);
822
823 return data->ev_enable_state;
824}
825
826static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
827 const struct iio_chan_spec *chan,
828 enum iio_event_type type,
829 enum iio_event_direction dir,
830 int state)
831{
832 struct kxcjk1013_data *data = iio_priv(indio_dev);
833 int ret;
834
835 if (state && data->ev_enable_state)
836 return 0;
837
838 mutex_lock(&data->mutex);
839
840 if (!state && data->motion_trigger_on) {
841 data->ev_enable_state = 0;
842 mutex_unlock(&data->mutex);
843 return 0;
844 }
845
846 /*
847 * We will expect the enable and disable to do operation in
848 * in reverse order. This will happen here anyway as our
849 * resume operation uses sync mode runtime pm calls, the
850 * suspend operation will be delayed by autosuspend delay
851 * So the disable operation will still happen in reverse of
852 * enable operation. When runtime pm is disabled the mode
853 * is always on so sequence doesn't matter
854 */
855 ret = kxcjk1013_set_power_state(data, state);
856 if (ret < 0) {
857 mutex_unlock(&data->mutex);
858 return ret;
859 }
860
861 ret = kxcjk1013_setup_any_motion_interrupt(data, state);
862 if (ret < 0) {
fbd123e9
IT		 863 kxcjk1013_set_power_state(data, false);
864 data->ev_enable_state = 0;
b4b491c0
SP		 865 mutex_unlock(&data->mutex);
866 return ret;
867 }
868
869 data->ev_enable_state = state;
870 mutex_unlock(&data->mutex);
871
872 return 0;
873}
874
a25691c1 875static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev)
1a4fbf6a
SP		 876{
877 struct kxcjk1013_data *data = iio_priv(indio_dev);
878
a25691c1
VD		 879 return kxcjk1013_set_power_state(data, true);
880}
1a4fbf6a 881
a25691c1
VD		 882static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
883{
884 struct kxcjk1013_data *data = iio_priv(indio_dev);
885
886 return kxcjk1013_set_power_state(data, false);
1a4fbf6a
SP		 887}
888
889static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
890 "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600");
891
a735e3d7
SP		 892static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
893
1a4fbf6a
SP		 894static struct attribute *kxcjk1013_attributes[] = {
895 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
a735e3d7 896 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
1a4fbf6a
SP		 897 NULL,
898};
899
900static const struct attribute_group kxcjk1013_attrs_group = {
901 .attrs = kxcjk1013_attributes,
902};
903
b4b491c0
SP		 904static const struct iio_event_spec kxcjk1013_event = {
905 .type = IIO_EV_TYPE_THRESH,
25afffe1 906 .dir = IIO_EV_DIR_EITHER,
b4b491c0
SP		 907 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
908 BIT(IIO_EV_INFO_ENABLE) |
909 BIT(IIO_EV_INFO_PERIOD)
910};
911
1a4fbf6a
SP		 912#define KXCJK1013_CHANNEL(_axis) { \
913 .type = IIO_ACCEL, \
914 .modified = 1, \
915 .channel2 = IIO_MOD_##_axis, \
916 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
917 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
918 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
919 .scan_index = AXIS_##_axis, \
920 .scan_type = { \
921 .sign = 's', \
922 .realbits = 12, \
923 .storagebits = 16, \
924 .shift = 4, \
f4e2f94d 925 .endianness = IIO_CPU, \
1a4fbf6a 926 }, \
b4b491c0
SP		 927 .event_spec = &kxcjk1013_event, \
928 .num_event_specs = 1 \
1a4fbf6a
SP		 929}
930
931static const struct iio_chan_spec kxcjk1013_channels[] = {
932 KXCJK1013_CHANNEL(X),
933 KXCJK1013_CHANNEL(Y),
934 KXCJK1013_CHANNEL(Z),
935 IIO_CHAN_SOFT_TIMESTAMP(3),
936};
937
a25691c1
VD		 938static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = {
939 .preenable = kxcjk1013_buffer_preenable,
940 .postenable = iio_triggered_buffer_postenable,
941 .postdisable = kxcjk1013_buffer_postdisable,
942 .predisable = iio_triggered_buffer_predisable,
943};
944
1a4fbf6a
SP		 945static const struct iio_info kxcjk1013_info = {
946 .attrs = &kxcjk1013_attrs_group,
947 .read_raw = kxcjk1013_read_raw,
948 .write_raw = kxcjk1013_write_raw,
b4b491c0
SP		 949 .read_event_value = kxcjk1013_read_event,
950 .write_event_value = kxcjk1013_write_event,
951 .write_event_config = kxcjk1013_write_event_config,
952 .read_event_config = kxcjk1013_read_event_config,
1a4fbf6a
SP		 953 .driver_module = THIS_MODULE,
954};
955
956static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
957{
958 struct iio_poll_func *pf = p;
959 struct iio_dev *indio_dev = pf->indio_dev;
960 struct kxcjk1013_data *data = iio_priv(indio_dev);
961 int bit, ret, i = 0;
962
963 mutex_lock(&data->mutex);
964
70dddeee 965 for_each_set_bit(bit, indio_dev->active_scan_mask,
1a4fbf6a
SP		 966 indio_dev->masklength) {
967 ret = kxcjk1013_get_acc_reg(data, bit);
968 if (ret < 0) {
1a4fbf6a
SP		 969 mutex_unlock(&data->mutex);
970 goto err;
971 }
972 data->buffer[i++] = ret;
973 }
1a4fbf6a
SP		 974 mutex_unlock(&data->mutex);
975
976 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
b4b491c0 977 data->timestamp);
1a4fbf6a
SP		 978err:
979 iio_trigger_notify_done(indio_dev->trig);
980
981 return IRQ_HANDLED;
982}
983
59bfeaba
SP		 984static int kxcjk1013_trig_try_reen(struct iio_trigger *trig)
985{
986 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
987 struct kxcjk1013_data *data = iio_priv(indio_dev);
988 int ret;
989
990 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
991 if (ret < 0) {
992 dev_err(&data->client->dev, "Error reading reg_int_rel\n");
993 return ret;
994 }
995
996 return 0;
997}
998
1a4fbf6a
SP		 999static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
1000 bool state)
1001{
1002 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1003 struct kxcjk1013_data *data = iio_priv(indio_dev);
124e1b1d
SP		 1004 int ret;
1005
b4b491c0
SP		 1006 mutex_lock(&data->mutex);
1007
1008 if (!state && data->ev_enable_state && data->motion_trigger_on) {
1009 data->motion_trigger_on = false;
1010 mutex_unlock(&data->mutex);
124e1b1d 1011 return 0;
b4b491c0 1012 }
1a4fbf6a 1013
b4b491c0
SP		 1014 ret = kxcjk1013_set_power_state(data, state);
1015 if (ret < 0) {
1016 mutex_unlock(&data->mutex);
1017 return ret;
1a4fbf6a 1018 }
b4b491c0
SP		 1019 if (data->motion_trig == trig)
1020 ret = kxcjk1013_setup_any_motion_interrupt(data, state);
1021 else
1022 ret = kxcjk1013_setup_new_data_interrupt(data, state);
1023 if (ret < 0) {
fbd123e9 1024 kxcjk1013_set_power_state(data, false);
b4b491c0
SP		 1025 mutex_unlock(&data->mutex);
1026 return ret;
1027 }
1028 if (data->motion_trig == trig)
1029 data->motion_trigger_on = state;
1030 else
1031 data->dready_trigger_on = state;
1032
1a4fbf6a
SP		 1033 mutex_unlock(&data->mutex);
1034
1035 return 0;
1036}
1037
1038static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
1039 .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
59bfeaba 1040 .try_reenable = kxcjk1013_trig_try_reen,
1a4fbf6a
SP		 1041 .owner = THIS_MODULE,
1042};
1043
b4b491c0
SP		 1044static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
1045{
1046 struct iio_dev *indio_dev = private;
1047 struct kxcjk1013_data *data = iio_priv(indio_dev);
1048 int ret;
1049
1050 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_SRC1);
1051 if (ret < 0) {
1052 dev_err(&data->client->dev, "Error reading reg_int_src1\n");
1053 goto ack_intr;
1054 }
1055
1056 if (ret & 0x02) {
1057 ret = i2c_smbus_read_byte_data(data->client,
1058 KXCJK1013_REG_INT_SRC2);
1059 if (ret < 0) {
1060 dev_err(&data->client->dev,
1061 "Error reading reg_int_src2\n");
1062 goto ack_intr;
1063 }
1064
1065 if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
1066 iio_push_event(indio_dev,
1067 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1068 0,
1069 IIO_MOD_X,
1070 IIO_EV_TYPE_THRESH,
1071 IIO_EV_DIR_FALLING),
1072 data->timestamp);
1073 if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
1074 iio_push_event(indio_dev,
1075 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1076 0,
1077 IIO_MOD_X,
1078 IIO_EV_TYPE_THRESH,
1079 IIO_EV_DIR_RISING),
1080 data->timestamp);
1081
1082
1083 if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
1084 iio_push_event(indio_dev,
1085 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1086 0,
1087 IIO_MOD_Y,
1088 IIO_EV_TYPE_THRESH,
1089 IIO_EV_DIR_FALLING),
1090 data->timestamp);
1091 if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
1092 iio_push_event(indio_dev,
1093 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1094 0,
1095 IIO_MOD_Y,
1096 IIO_EV_TYPE_THRESH,
1097 IIO_EV_DIR_RISING),
1098 data->timestamp);
1099
1100 if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
1101 iio_push_event(indio_dev,
1102 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1103 0,
1104 IIO_MOD_Z,
1105 IIO_EV_TYPE_THRESH,
1106 IIO_EV_DIR_FALLING),
1107 data->timestamp);
1108 if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
1109 iio_push_event(indio_dev,
1110 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1111 0,
1112 IIO_MOD_Z,
1113 IIO_EV_TYPE_THRESH,
1114 IIO_EV_DIR_RISING),
1115 data->timestamp);
1116 }
1117
1118ack_intr:
1119 if (data->dready_trigger_on)
1120 return IRQ_HANDLED;
1121
1122 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
1123 if (ret < 0)
1124 dev_err(&data->client->dev, "Error reading reg_int_rel\n");
1125
1126 return IRQ_HANDLED;
1127}
1128
1129static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
1130{
1131 struct iio_dev *indio_dev = private;
1132 struct kxcjk1013_data *data = iio_priv(indio_dev);
1133
1134 data->timestamp = iio_get_time_ns();
1135
1136 if (data->dready_trigger_on)
1137 iio_trigger_poll(data->dready_trig);
1138 else if (data->motion_trigger_on)
1139 iio_trigger_poll(data->motion_trig);
1140
1141 if (data->ev_enable_state)
1142 return IRQ_WAKE_THREAD;
1143 else
1144 return IRQ_HANDLED;
1145}
1146
c6861377 1147static const char *kxcjk1013_match_acpi_device(struct device *dev,
3bfa74f8
BN		 1148 enum kx_chipset *chipset,
1149 bool *is_smo8500_device)
1a4fbf6a
SP		 1150{
1151 const struct acpi_device_id *id;
b0868df4 1152
c6861377
DB		 1153 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1154 if (!id)
1155 return NULL;
e693e15e 1156
3bfa74f8
BN		 1157 if (strcmp(id->id, "SMO8500") == 0)
1158 *is_smo8500_device = true;
e693e15e 1159
c6861377
DB		 1160 *chipset = (enum kx_chipset)id->driver_data;
1161
1162 return dev_name(dev);
1163}
1164
1a4fbf6a
SP		 1165static int kxcjk1013_probe(struct i2c_client *client,
1166 const struct i2c_device_id *id)
1167{
1168 struct kxcjk1013_data *data;
1169 struct iio_dev *indio_dev;
1a4fbf6a 1170 struct kxcjk_1013_platform_data *pdata;
c6861377 1171 const char *name;
1a4fbf6a
SP		 1172 int ret;
1173
1174 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1175 if (!indio_dev)
1176 return -ENOMEM;
1177
1178 data = iio_priv(indio_dev);
1179 i2c_set_clientdata(client, indio_dev);
1180 data->client = client;
1181
1182 pdata = dev_get_platdata(&client->dev);
1183 if (pdata)
1184 data->active_high_intr = pdata->active_high_intr;
1185 else
1186 data->active_high_intr = true; /* default polarity */
1187
c6861377
DB		 1188 if (id) {
1189 data->chipset = (enum kx_chipset)(id->driver_data);
1190 name = id->name;
1191 } else if (ACPI_HANDLE(&client->dev)) {
1192 name = kxcjk1013_match_acpi_device(&client->dev,
3bfa74f8
BN		 1193 &data->chipset,
1194 &data->is_smo8500_device);
c6861377
DB		 1195 } else
1196 return -ENODEV;
1197
1a4fbf6a
SP		 1198 ret = kxcjk1013_chip_init(data);
1199 if (ret < 0)
1200 return ret;
1201
1202 mutex_init(&data->mutex);
1203
1204 indio_dev->dev.parent = &client->dev;
1205 indio_dev->channels = kxcjk1013_channels;
1206 indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
c6861377 1207 indio_dev->name = name;
1a4fbf6a
SP		 1208 indio_dev->modes = INDIO_DIRECT_MODE;
1209 indio_dev->info = &kxcjk1013_info;
1210
0f079650 1211 if (client->irq > 0 && !data->is_smo8500_device) {
b4b491c0
SP		 1212 ret = devm_request_threaded_irq(&client->dev, client->irq,
1213 kxcjk1013_data_rdy_trig_poll,
1214 kxcjk1013_event_handler,
1215 IRQF_TRIGGER_RISING,
1216 KXCJK1013_IRQ_NAME,
1217 indio_dev);
1218 if (ret)
9d02daf7 1219 goto err_poweroff;
1a4fbf6a 1220
b4b491c0
SP		 1221 data->dready_trig = devm_iio_trigger_alloc(&client->dev,
1222 "%s-dev%d",
1223 indio_dev->name,
1224 indio_dev->id);
9d02daf7
IT		 1225 if (!data->dready_trig) {
1226 ret = -ENOMEM;
1227 goto err_poweroff;
1228 }
1a4fbf6a 1229
b4b491c0
SP		 1230 data->motion_trig = devm_iio_trigger_alloc(&client->dev,
1231 "%s-any-motion-dev%d",
1232 indio_dev->name,
1233 indio_dev->id);
9d02daf7
IT		 1234 if (!data->motion_trig) {
1235 ret = -ENOMEM;
1236 goto err_poweroff;
1237 }
1a4fbf6a 1238
b4b491c0
SP		 1239 data->dready_trig->dev.parent = &client->dev;
1240 data->dready_trig->ops = &kxcjk1013_trigger_ops;
1241 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1242 indio_dev->trig = data->dready_trig;
c1288b83 1243 iio_trigger_get(indio_dev->trig);
b4b491c0 1244 ret = iio_trigger_register(data->dready_trig);
1a4fbf6a 1245 if (ret)
9d02daf7 1246 goto err_poweroff;
b4b491c0
SP		 1247
1248 data->motion_trig->dev.parent = &client->dev;
1249 data->motion_trig->ops = &kxcjk1013_trigger_ops;
1250 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1251 ret = iio_trigger_register(data->motion_trig);
1252 if (ret) {
1253 data->motion_trig = NULL;
1254 goto err_trigger_unregister;
1255 }
a25691c1 1256 }
1a4fbf6a 1257
a25691c1
VD		 1258 ret = iio_triggered_buffer_setup(indio_dev,
1259 &iio_pollfunc_store_time,
1260 kxcjk1013_trigger_handler,
1261 &kxcjk1013_buffer_setup_ops);
1262 if (ret < 0) {
1263 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1264 goto err_trigger_unregister;
1a4fbf6a
SP		 1265 }
1266
124e1b1d
SP		 1267 ret = pm_runtime_set_active(&client->dev);
1268 if (ret)
7d0ead5c 1269 goto err_buffer_cleanup;
124e1b1d
SP		 1270
1271 pm_runtime_enable(&client->dev);
1272 pm_runtime_set_autosuspend_delay(&client->dev,
1273 KXCJK1013_SLEEP_DELAY_MS);
1274 pm_runtime_use_autosuspend(&client->dev);
1275
7d0ead5c
AR		 1276 ret = iio_device_register(indio_dev);
1277 if (ret < 0) {
1278 dev_err(&client->dev, "unable to register iio device\n");
1279 goto err_buffer_cleanup;
1280 }
1281
1a4fbf6a
SP		 1282 return 0;
1283
1284err_buffer_cleanup:
b4b491c0 1285 if (data->dready_trig)
1a4fbf6a
SP		 1286 iio_triggered_buffer_cleanup(indio_dev);
1287err_trigger_unregister:
b4b491c0
SP		 1288 if (data->dready_trig)
1289 iio_trigger_unregister(data->dready_trig);
1290 if (data->motion_trig)
1291 iio_trigger_unregister(data->motion_trig);
9d02daf7
IT		 1292err_poweroff:
1293 kxcjk1013_set_mode(data, STANDBY);
1a4fbf6a
SP		 1294
1295 return ret;
1296}
1297
1298static int kxcjk1013_remove(struct i2c_client *client)
1299{
1300 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1301 struct kxcjk1013_data *data = iio_priv(indio_dev);
1302
7d0ead5c
AR		 1303 iio_device_unregister(indio_dev);
1304
124e1b1d
SP		 1305 pm_runtime_disable(&client->dev);
1306 pm_runtime_set_suspended(&client->dev);
1307 pm_runtime_put_noidle(&client->dev);
1308
b4b491c0 1309 if (data->dready_trig) {
1a4fbf6a 1310 iio_triggered_buffer_cleanup(indio_dev);
b4b491c0
SP		 1311 iio_trigger_unregister(data->dready_trig);
1312 iio_trigger_unregister(data->motion_trig);
1a4fbf6a
SP		 1313 }
1314
1315 mutex_lock(&data->mutex);
1316 kxcjk1013_set_mode(data, STANDBY);
1317 mutex_unlock(&data->mutex);
1318
1319 return 0;
1320}
1321
1322#ifdef CONFIG_PM_SLEEP
1323static int kxcjk1013_suspend(struct device *dev)
1324{
1325 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1326 struct kxcjk1013_data *data = iio_priv(indio_dev);
124e1b1d 1327 int ret;
1a4fbf6a
SP		 1328
1329 mutex_lock(&data->mutex);
124e1b1d 1330 ret = kxcjk1013_set_mode(data, STANDBY);
1a4fbf6a
SP		 1331 mutex_unlock(&data->mutex);
1332
124e1b1d 1333 return ret;
1a4fbf6a
SP		 1334}
1335
1336static int kxcjk1013_resume(struct device *dev)
1337{
1338 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1339 struct kxcjk1013_data *data = iio_priv(indio_dev);
124e1b1d 1340 int ret = 0;
1a4fbf6a
SP		 1341
1342 mutex_lock(&data->mutex);
d3653d09 1343 ret = kxcjk1013_set_mode(data, OPERATION);
124e1b1d 1344 mutex_unlock(&data->mutex);
1a4fbf6a 1345
124e1b1d
SP		 1346 return ret;
1347}
1348#endif
1a4fbf6a 1349
6f0a13f2 1350#ifdef CONFIG_PM
124e1b1d
SP		 1351static int kxcjk1013_runtime_suspend(struct device *dev)
1352{
1353 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1354 struct kxcjk1013_data *data = iio_priv(indio_dev);
fbd123e9 1355 int ret;
1a4fbf6a 1356
fbd123e9
IT		 1357 ret = kxcjk1013_set_mode(data, STANDBY);
1358 if (ret < 0) {
1359 dev_err(&data->client->dev, "powering off device failed\n");
1360 return -EAGAIN;
1361 }
1362 return 0;
1a4fbf6a
SP		 1363}
1364
124e1b1d
SP		 1365static int kxcjk1013_runtime_resume(struct device *dev)
1366{
1367 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1368 struct kxcjk1013_data *data = iio_priv(indio_dev);
1369 int ret;
1370 int sleep_val;
1371
1372 ret = kxcjk1013_set_mode(data, OPERATION);
1373 if (ret < 0)
1374 return ret;
1375
1376 sleep_val = kxcjk1013_get_startup_times(data);
1377 if (sleep_val < 20000)
1378 usleep_range(sleep_val, 20000);
1379 else
1380 msleep_interruptible(sleep_val/1000);
1381
1382 return 0;
1383}
1a4fbf6a
SP		 1384#endif
1385
124e1b1d
SP		 1386static const struct dev_pm_ops kxcjk1013_pm_ops = {
1387 SET_SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
1388 SET_RUNTIME_PM_OPS(kxcjk1013_runtime_suspend,
1389 kxcjk1013_runtime_resume, NULL)
1390};
1391
1a4fbf6a 1392static const struct acpi_device_id kx_acpi_match[] = {
c6861377
DB		 1393 {"KXCJ1013", KXCJK1013},
1394 {"KXCJ1008", KXCJ91008},
61e2c70d 1395 {"KXCJ9000", KXCJ91008},
c6861377 1396 {"KXTJ1009", KXTJ21009},
3bfa74f8 1397 {"SMO8500", KXCJ91008},
1a4fbf6a
SP		 1398 { },
1399};
1400MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
1401
1402static const struct i2c_device_id kxcjk1013_id[] = {
c6861377
DB		 1403 {"kxcjk1013", KXCJK1013},
1404 {"kxcj91008", KXCJ91008},
1405 {"kxtj21009", KXTJ21009},
3bfa74f8 1406 {"SMO8500", KXCJ91008},
1a4fbf6a
SP		 1407 {}
1408};
1409
1410MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
1411
1412static struct i2c_driver kxcjk1013_driver = {
1413 .driver = {
1414 .name = KXCJK1013_DRV_NAME,
1415 .acpi_match_table = ACPI_PTR(kx_acpi_match),
124e1b1d 1416 .pm = &kxcjk1013_pm_ops,
1a4fbf6a
SP		 1417 },
1418 .probe = kxcjk1013_probe,
1419 .remove = kxcjk1013_remove,
1420 .id_table = kxcjk1013_id,
1421};
1422module_i2c_driver(kxcjk1013_driver);
1423
1424MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1425MODULE_LICENSE("GPL v2");
1426MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");
Linux kernel - Deliverables
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