[deliverable/linux.git] / drivers / iio / accel / mxc4005.c

/*
 * 3-axis accelerometer driver for MXC4005XC Memsic sensor
 *
 * Copyright (c) 2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>

#define MXC4005_DRV_NAME		"mxc4005"
#define MXC4005_IRQ_NAME		"mxc4005_event"
#define MXC4005_REGMAP_NAME		"mxc4005_regmap"

#define MXC4005_REG_XOUT_UPPER		0x03
#define MXC4005_REG_XOUT_LOWER		0x04
#define MXC4005_REG_YOUT_UPPER		0x05
#define MXC4005_REG_YOUT_LOWER		0x06
#define MXC4005_REG_ZOUT_UPPER		0x07
#define MXC4005_REG_ZOUT_LOWER		0x08

#define MXC4005_REG_INT_MASK1		0x0B
#define MXC4005_REG_INT_MASK1_BIT_DRDYE	0x01

#define MXC4005_REG_INT_CLR1		0x01
#define MXC4005_REG_INT_CLR1_BIT_DRDYC	0x01

#define MXC4005_REG_CONTROL		0x0D
#define MXC4005_REG_CONTROL_MASK_FSR	GENMASK(6, 5)
#define MXC4005_CONTROL_FSR_SHIFT	5

#define MXC4005_REG_DEVICE_ID		0x0E

enum mxc4005_axis {
	AXIS_X,
	AXIS_Y,
	AXIS_Z,
};

enum mxc4005_range {
	MXC4005_RANGE_2G,
	MXC4005_RANGE_4G,
	MXC4005_RANGE_8G,
};

struct mxc4005_data {
	struct device *dev;
	struct mutex mutex;
	struct regmap *regmap;
	struct iio_trigger *dready_trig;
	__be16 buffer[8];
	bool trigger_enabled;
};

/*
 * MXC4005 can operate in the following ranges:
 * +/- 2G, 4G, 8G (the default +/-2G)
 *
 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
 */
static const struct {
	u8 range;
	int scale;
} mxc4005_scale_table[] = {
	{MXC4005_RANGE_2G, 9582},
	{MXC4005_RANGE_4G, 19164},
	{MXC4005_RANGE_8G, 38329},
};


static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");

static struct attribute *mxc4005_attributes[] = {
	&iio_const_attr_in_accel_scale_available.dev_attr.attr,
	NULL,
};

static const struct attribute_group mxc4005_attrs_group = {
	.attrs = mxc4005_attributes,
};

static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case MXC4005_REG_XOUT_UPPER:
	case MXC4005_REG_XOUT_LOWER:
	case MXC4005_REG_YOUT_UPPER:
	case MXC4005_REG_YOUT_LOWER:
	case MXC4005_REG_ZOUT_UPPER:
	case MXC4005_REG_ZOUT_LOWER:
	case MXC4005_REG_DEVICE_ID:
	case MXC4005_REG_CONTROL:
		return true;
	default:
		return false;
	}
}

static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case MXC4005_REG_INT_CLR1:
	case MXC4005_REG_INT_MASK1:
	case MXC4005_REG_CONTROL:
		return true;
	default:
		return false;
	}
}

static const struct regmap_config mxc4005_regmap_config = {
	.name = MXC4005_REGMAP_NAME,

	.reg_bits = 8,
	.val_bits = 8,

	.max_register = MXC4005_REG_DEVICE_ID,

	.readable_reg = mxc4005_is_readable_reg,
	.writeable_reg = mxc4005_is_writeable_reg,
};

static int mxc4005_read_xyz(struct mxc4005_data *data)
{
	int ret;

	ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
			       (u8 *) data->buffer, sizeof(data->buffer));
	if (ret < 0) {
		dev_err(data->dev, "failed to read axes\n");
		return ret;
	}

	return 0;
}

static int mxc4005_read_axis(struct mxc4005_data *data,
			     unsigned int addr)
{
	__be16 reg;
	int ret;

	ret = regmap_bulk_read(data->regmap, addr, (u8 *) &reg, sizeof(reg));
	if (ret < 0) {
		dev_err(data->dev, "failed to read reg %02x\n", addr);
		return ret;
	}

	return be16_to_cpu(reg);
}

static int mxc4005_read_scale(struct mxc4005_data *data)
{
	unsigned int reg;
	int ret;
	int i;

	ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &reg);
	if (ret < 0) {
		dev_err(data->dev, "failed to read reg_control\n");
		return ret;
	}

	i = reg >> MXC4005_CONTROL_FSR_SHIFT;

	if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
		return -EINVAL;

	return mxc4005_scale_table[i].scale;
}

static int mxc4005_set_scale(struct mxc4005_data *data, int val)
{
	unsigned int reg;
	int i;
	int ret;

	for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
		if (mxc4005_scale_table[i].scale == val) {
			reg = i << MXC4005_CONTROL_FSR_SHIFT;
			ret = regmap_update_bits(data->regmap,
						 MXC4005_REG_CONTROL,
						 MXC4005_REG_CONTROL_MASK_FSR,
						 reg);
			if (ret < 0)
				dev_err(data->dev,
					"failed to write reg_control\n");
			return ret;
		}
	}

	return -EINVAL;
}

static int mxc4005_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int *val, int *val2, long mask)
{
	struct mxc4005_data *data = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		switch (chan->type) {
		case IIO_ACCEL:
			if (iio_buffer_enabled(indio_dev))
				return -EBUSY;

			ret = mxc4005_read_axis(data, chan->address);
			if (ret < 0)
				return ret;
			*val = sign_extend32(ret >> chan->scan_type.shift,
					     chan->scan_type.realbits - 1);
			return IIO_VAL_INT;
		default:
			return -EINVAL;
		}
	case IIO_CHAN_INFO_SCALE:
		ret = mxc4005_read_scale(data);
		if (ret < 0)
			return ret;

		*val = 0;
		*val2 = ret;
		return IIO_VAL_INT_PLUS_MICRO;
	default:
		return -EINVAL;
	}
}

static int mxc4005_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int val, int val2, long mask)
{
	struct mxc4005_data *data = iio_priv(indio_dev);

	switch (mask) {
	case IIO_CHAN_INFO_SCALE:
		if (val != 0)
			return -EINVAL;

		return mxc4005_set_scale(data, val2);
	default:
		return -EINVAL;
	}
}

static const struct iio_info mxc4005_info = {
	.driver_module	= THIS_MODULE,
	.read_raw	= mxc4005_read_raw,
	.write_raw	= mxc4005_write_raw,
	.attrs		= &mxc4005_attrs_group,
};

static const unsigned long mxc4005_scan_masks[] = {
	BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
	0
};

#define MXC4005_CHANNEL(_axis, _addr) {				\
	.type = IIO_ACCEL,					\
	.modified = 1,						\
	.channel2 = IIO_MOD_##_axis,				\
	.address = _addr,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
	.scan_index = AXIS_##_axis,				\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 12,					\
		.storagebits = 16,				\
		.shift = 4,					\
		.endianness = IIO_BE,				\
	},							\
}

static const struct iio_chan_spec mxc4005_channels[] = {
	MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
	MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
	MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
	IIO_CHAN_SOFT_TIMESTAMP(3),
};

static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
{
	struct iio_poll_func *pf = private;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct mxc4005_data *data = iio_priv(indio_dev);
	int ret;

	ret = mxc4005_read_xyz(data);
	if (ret < 0)
		goto err;

	iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
					   pf->timestamp);

err:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int mxc4005_clr_intr(struct mxc4005_data *data)
{
	int ret;

	/* clear interrupt */
	ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
			   MXC4005_REG_INT_CLR1_BIT_DRDYC);
	if (ret < 0) {
		dev_err(data->dev, "failed to write to reg_int_clr1\n");
		return ret;
	}

	return 0;
}

static int mxc4005_set_trigger_state(struct iio_trigger *trig,
				     bool state)
{
	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
	struct mxc4005_data *data = iio_priv(indio_dev);
	int ret;

	mutex_lock(&data->mutex);
	if (state) {
		ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
				   MXC4005_REG_INT_MASK1_BIT_DRDYE);
	} else {
		ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
				   ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
	}

	if (ret < 0) {
		mutex_unlock(&data->mutex);
		dev_err(data->dev, "failed to update reg_int_mask1");
		return ret;
	}

	data->trigger_enabled = state;
	mutex_unlock(&data->mutex);

	return 0;
}

static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
{
	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
	struct mxc4005_data *data = iio_priv(indio_dev);

	if (!data->dready_trig)
		return 0;

	return mxc4005_clr_intr(data);
}

static const struct iio_trigger_ops mxc4005_trigger_ops = {
	.set_trigger_state = mxc4005_set_trigger_state,
	.try_reenable = mxc4005_trigger_try_reen,
	.owner = THIS_MODULE,
};

static int mxc4005_gpio_probe(struct i2c_client *client,
			      struct mxc4005_data *data)
{
	struct device *dev;
	struct gpio_desc *gpio;
	int ret;

	if (!client)
		return -EINVAL;

	dev = &client->dev;

	gpio = devm_gpiod_get_index(dev, "mxc4005_int", 0, GPIOD_IN);
	if (IS_ERR(gpio)) {
		dev_err(dev, "failed to get acpi gpio index\n");
		return PTR_ERR(gpio);
	}

	ret = gpiod_to_irq(gpio);

	dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);

	return ret;
}

static int mxc4005_chip_init(struct mxc4005_data *data)
{
	int ret;
	unsigned int reg;

	ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, &reg);
	if (ret < 0) {
		dev_err(data->dev, "failed to read chip id\n");
		return ret;
	}

	dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);

	return 0;
}

static int mxc4005_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct mxc4005_data *data;
	struct iio_dev *indio_dev;
	struct regmap *regmap;
	int ret;

	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	if (!indio_dev)
		return -ENOMEM;

	regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
	if (IS_ERR(regmap)) {
		dev_err(&client->dev, "failed to initialize regmap\n");
		return PTR_ERR(regmap);
	}

	data = iio_priv(indio_dev);
	i2c_set_clientdata(client, indio_dev);
	data->dev = &client->dev;
	data->regmap = regmap;

	ret = mxc4005_chip_init(data);
	if (ret < 0) {
		dev_err(&client->dev, "failed to initialize chip\n");
		return ret;
	}

	mutex_init(&data->mutex);

	indio_dev->dev.parent = &client->dev;
	indio_dev->channels = mxc4005_channels;
	indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
	indio_dev->available_scan_masks = mxc4005_scan_masks;
	indio_dev->name = MXC4005_DRV_NAME;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->info = &mxc4005_info;

	ret = iio_triggered_buffer_setup(indio_dev,
					 iio_pollfunc_store_time,
					 mxc4005_trigger_handler,
					 NULL);
	if (ret < 0) {
		dev_err(&client->dev,
			"failed to setup iio triggered buffer\n");
		return ret;
	}

	if (client->irq < 0)
		client->irq = mxc4005_gpio_probe(client, data);

	if (client->irq > 0) {
		data->dready_trig = devm_iio_trigger_alloc(&client->dev,
							   "%s-dev%d",
							   indio_dev->name,
							   indio_dev->id);
		if (!data->dready_trig)
			return -ENOMEM;

		ret = devm_request_threaded_irq(&client->dev, client->irq,
						iio_trigger_generic_data_rdy_poll,
						NULL,
						IRQF_TRIGGER_FALLING |
						IRQF_ONESHOT,
						MXC4005_IRQ_NAME,
						data->dready_trig);
		if (ret) {
			dev_err(&client->dev,
				"failed to init threaded irq\n");
			goto err_buffer_cleanup;
		}

		data->dready_trig->dev.parent = &client->dev;
		data->dready_trig->ops = &mxc4005_trigger_ops;
		iio_trigger_set_drvdata(data->dready_trig, indio_dev);
		indio_dev->trig = data->dready_trig;
		iio_trigger_get(indio_dev->trig);
		ret = iio_trigger_register(data->dready_trig);
		if (ret) {
			dev_err(&client->dev,
				"failed to register trigger\n");
			goto err_trigger_unregister;
		}
	}

	ret = iio_device_register(indio_dev);
	if (ret < 0) {
		dev_err(&client->dev,
			"unable to register iio device %d\n", ret);
		goto err_buffer_cleanup;
	}

	return 0;

err_trigger_unregister:
	iio_trigger_unregister(data->dready_trig);
err_buffer_cleanup:
	iio_triggered_buffer_cleanup(indio_dev);

	return ret;
}

static int mxc4005_remove(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct mxc4005_data *data = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);

	iio_triggered_buffer_cleanup(indio_dev);
	if (data->dready_trig)
		iio_trigger_unregister(data->dready_trig);

	return 0;
}

static const struct acpi_device_id mxc4005_acpi_match[] = {
	{"MXC4005",	0},
	{ },
};
MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);

static const struct i2c_device_id mxc4005_id[] = {
	{"mxc4005",	0},
	{ },
};
MODULE_DEVICE_TABLE(i2c, mxc4005_id);

static struct i2c_driver mxc4005_driver = {
	.driver = {
		.name = MXC4005_DRV_NAME,
		.acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
	},
	.probe		= mxc4005_probe,
	.remove		= mxc4005_remove,
	.id_table	= mxc4005_id,
};

module_i2c_driver(mxc4005_driver);

MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");
Commit	Line	Data
077377fc TB	1	/*
	2	* 3-axis accelerometer driver for MXC4005XC Memsic sensor
	3	*
	4	* Copyright (c) 2014, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/i2c.h>
	18	#include <linux/iio/iio.h>
	19	#include <linux/acpi.h>
47196620	20	#include <linux/gpio/consumer.h>
077377fc TB	21	#include <linux/regmap.h>
077377fc TB	22	#include <linux/iio/sysfs.h>
47196620	23	#include <linux/iio/trigger.h>
1ce0eda0 TB	24	#include <linux/iio/buffer.h>
	25	#include <linux/iio/triggered_buffer.h>
	26	#include <linux/iio/trigger_consumer.h>
077377fc TB	27
077377fc TB	28	#define MXC4005_DRV_NAME "mxc4005"
47196620	29	#define MXC4005_IRQ_NAME "mxc4005_event"
077377fc TB	30	#define MXC4005_REGMAP_NAME "mxc4005_regmap"
	31
	32	#define MXC4005_REG_XOUT_UPPER 0x03
	33	#define MXC4005_REG_XOUT_LOWER 0x04
	34	#define MXC4005_REG_YOUT_UPPER 0x05
	35	#define MXC4005_REG_YOUT_LOWER 0x06
	36	#define MXC4005_REG_ZOUT_UPPER 0x07
	37	#define MXC4005_REG_ZOUT_LOWER 0x08
	38
47196620 TB	39	#define MXC4005_REG_INT_MASK1 0x0B
	40	#define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
	41
	42	#define MXC4005_REG_INT_CLR1 0x01
	43	#define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01
	44
077377fc TB	45	#define MXC4005_REG_CONTROL 0x0D
	46	#define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5)
	47	#define MXC4005_CONTROL_FSR_SHIFT 5
	48
	49	#define MXC4005_REG_DEVICE_ID 0x0E
	50
	51	enum mxc4005_axis {
	52	AXIS_X,
	53	AXIS_Y,
	54	AXIS_Z,
	55	};
	56
	57	enum mxc4005_range {
	58	MXC4005_RANGE_2G,
	59	MXC4005_RANGE_4G,
	60	MXC4005_RANGE_8G,
	61	};
	62
	63	struct mxc4005_data {
	64	struct device *dev;
	65	struct mutex mutex;
	66	struct regmap *regmap;
47196620	67	struct iio_trigger *dready_trig;
1ce0eda0	68	__be16 buffer[8];
47196620	69	bool trigger_enabled;
077377fc TB	70	};
	71
	72	/*
	73	* MXC4005 can operate in the following ranges:
	74	* +/- 2G, 4G, 8G (the default +/-2G)
	75	*
	76	* (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
	77	* (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
	78	* (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
	79	*/
	80	static const struct {
	81	u8 range;
	82	int scale;
	83	} mxc4005_scale_table[] = {
	84	{MXC4005_RANGE_2G, 9582},
	85	{MXC4005_RANGE_4G, 19164},
	86	{MXC4005_RANGE_8G, 38329},
	87	};
	88
	89
	90	static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
	91
	92	static struct attribute *mxc4005_attributes[] = {
	93	&iio_const_attr_in_accel_scale_available.dev_attr.attr,
	94	NULL,
	95	};
	96
	97	static const struct attribute_group mxc4005_attrs_group = {
	98	.attrs = mxc4005_attributes,
	99	};
	100
	101	static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
	102	{
	103	switch (reg) {
	104	case MXC4005_REG_XOUT_UPPER:
	105	case MXC4005_REG_XOUT_LOWER:
	106	case MXC4005_REG_YOUT_UPPER:
	107	case MXC4005_REG_YOUT_LOWER:
	108	case MXC4005_REG_ZOUT_UPPER:
	109	case MXC4005_REG_ZOUT_LOWER:
	110	case MXC4005_REG_DEVICE_ID:
	111	case MXC4005_REG_CONTROL:
	112	return true;
	113	default:
	114	return false;
	115	}
	116	}
	117
	118	static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
	119	{
	120	switch (reg) {
47196620 TB	121	case MXC4005_REG_INT_CLR1:
47196620 TB	122	case MXC4005_REG_INT_MASK1:
077377fc TB	123	case MXC4005_REG_CONTROL:
	124	return true;
	125	default:
	126	return false;
	127	}
	128	}
	129
	130	static const struct regmap_config mxc4005_regmap_config = {
	131	.name = MXC4005_REGMAP_NAME,
	132
	133	.reg_bits = 8,
	134	.val_bits = 8,
	135
	136	.max_register = MXC4005_REG_DEVICE_ID,
	137
	138	.readable_reg = mxc4005_is_readable_reg,
	139	.writeable_reg = mxc4005_is_writeable_reg,
	140	};
	141
1ce0eda0 TB	142	static int mxc4005_read_xyz(struct mxc4005_data *data)
	143	{
	144	int ret;
	145
	146	ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
	147	(u8 *) data->buffer, sizeof(data->buffer));
	148	if (ret < 0) {
	149	dev_err(data->dev, "failed to read axes\n");
	150	return ret;
	151	}
	152
	153	return 0;
	154	}
	155
077377fc TB	156	static int mxc4005_read_axis(struct mxc4005_data *data,
	157	unsigned int addr)
	158	{
	159	__be16 reg;
	160	int ret;
	161
	162	ret = regmap_bulk_read(data->regmap, addr, (u8 *) &reg, sizeof(reg));
	163	if (ret < 0) {
	164	dev_err(data->dev, "failed to read reg %02x\n", addr);
	165	return ret;
	166	}
	167
	168	return be16_to_cpu(reg);
	169	}
	170
	171	static int mxc4005_read_scale(struct mxc4005_data *data)
	172	{
	173	unsigned int reg;
	174	int ret;
	175	int i;
	176
	177	ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &reg);
	178	if (ret < 0) {
	179	dev_err(data->dev, "failed to read reg_control\n");
	180	return ret;
	181	}
	182
	183	i = reg >> MXC4005_CONTROL_FSR_SHIFT;
	184
	185	if (i < 0 \|\| i >= ARRAY_SIZE(mxc4005_scale_table))
	186	return -EINVAL;
	187
	188	return mxc4005_scale_table[i].scale;
	189	}
	190
	191	static int mxc4005_set_scale(struct mxc4005_data *data, int val)
	192	{
	193	unsigned int reg;
	194	int i;
	195	int ret;
	196
	197	for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
	198	if (mxc4005_scale_table[i].scale == val) {
	199	reg = i << MXC4005_CONTROL_FSR_SHIFT;
	200	ret = regmap_update_bits(data->regmap,
	201	MXC4005_REG_CONTROL,
	202	MXC4005_REG_CONTROL_MASK_FSR,
	203	reg);
	204	if (ret < 0)
	205	dev_err(data->dev,
	206	"failed to write reg_control\n");
	207	return ret;
	208	}
	209	}
	210
	211	return -EINVAL;
	212	}
	213
	214	static int mxc4005_read_raw(struct iio_dev *indio_dev,
	215	struct iio_chan_spec const *chan,
	216	int val, int val2, long mask)
	217	{
	218	struct mxc4005_data *data = iio_priv(indio_dev);
	219	int ret;
220
221	switch (mask) {
222	case IIO_CHAN_INFO_RAW:
223	switch (chan->type) {
224	case IIO_ACCEL:
225	if (iio_buffer_enabled(indio_dev))
226	return -EBUSY;
227
228	ret = mxc4005_read_axis(data, chan->address);
229	if (ret < 0)
230	return ret;
1ce0eda0 TB	231	*val = sign_extend32(ret >> chan->scan_type.shift,
1ce0eda0 TB	232	chan->scan_type.realbits - 1);
077377fc TB	233	return IIO_VAL_INT;
	234	default:
	235	return -EINVAL;
	236	}
	237	case IIO_CHAN_INFO_SCALE:
	238	ret = mxc4005_read_scale(data);
	239	if (ret < 0)
	240	return ret;
	241
	242	*val = 0;
	243	*val2 = ret;
	244	return IIO_VAL_INT_PLUS_MICRO;
	245	default:
	246	return -EINVAL;
	247	}
	248	}
	249
	250	static int mxc4005_write_raw(struct iio_dev *indio_dev,
	251	struct iio_chan_spec const *chan,
	252	int val, int val2, long mask)
	253	{
	254	struct mxc4005_data *data = iio_priv(indio_dev);
	255
	256	switch (mask) {
	257	case IIO_CHAN_INFO_SCALE:
	258	if (val != 0)
	259	return -EINVAL;
	260
	261	return mxc4005_set_scale(data, val2);
	262	default:
	263	return -EINVAL;
	264	}
	265	}
	266
	267	static const struct iio_info mxc4005_info = {
	268	.driver_module = THIS_MODULE,
	269	.read_raw = mxc4005_read_raw,
	270	.write_raw = mxc4005_write_raw,
	271	.attrs = &mxc4005_attrs_group,
	272	};
	273
1ce0eda0 TB	274	static const unsigned long mxc4005_scan_masks[] = {
	275	BIT(AXIS_X) \| BIT(AXIS_Y) \| BIT(AXIS_Z),
	276	0
	277	};
	278
077377fc TB	279	#define MXC4005_CHANNEL(_axis, _addr) { \
	280	.type = IIO_ACCEL, \
	281	.modified = 1, \
	282	.channel2 = IIO_MOD_##_axis, \
	283	.address = _addr, \
	284	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
	285	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1ce0eda0 TB	286	.scan_index = AXIS_##_axis, \
	287	.scan_type = { \
	288	.sign = 's', \
	289	.realbits = 12, \
	290	.storagebits = 16, \
	291	.shift = 4, \
	292	.endianness = IIO_BE, \
	293	}, \
077377fc TB	294	}
	295
	296	static const struct iio_chan_spec mxc4005_channels[] = {
	297	MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
	298	MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
	299	MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
1ce0eda0	300	IIO_CHAN_SOFT_TIMESTAMP(3),
077377fc TB	301	};
077377fc TB	302
1ce0eda0 TB	303	static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
	304	{
	305	struct iio_poll_func *pf = private;
	306	struct iio_dev *indio_dev = pf->indio_dev;
	307	struct mxc4005_data *data = iio_priv(indio_dev);
	308	int ret;
	309
	310	ret = mxc4005_read_xyz(data);
	311	if (ret < 0)
	312	goto err;
	313
	314	iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
	315	pf->timestamp);
	316
	317	err:
	318	iio_trigger_notify_done(indio_dev->trig);
	319
	320	return IRQ_HANDLED;
	321	}
	322
47196620 TB	323	static int mxc4005_clr_intr(struct mxc4005_data *data)
	324	{
	325	int ret;
	326
	327	/* clear interrupt */
	328	ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
	329	MXC4005_REG_INT_CLR1_BIT_DRDYC);
	330	if (ret < 0) {
	331	dev_err(data->dev, "failed to write to reg_int_clr1\n");
	332	return ret;
	333	}
	334
	335	return 0;
	336	}
	337
	338	static int mxc4005_set_trigger_state(struct iio_trigger *trig,
	339	bool state)
	340	{
	341	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
	342	struct mxc4005_data *data = iio_priv(indio_dev);
	343	int ret;
	344
	345	mutex_lock(&data->mutex);
	346	if (state) {
	347	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
	348	MXC4005_REG_INT_MASK1_BIT_DRDYE);
	349	} else {
	350	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
	351	~MXC4005_REG_INT_MASK1_BIT_DRDYE);
	352	}
	353
	354	if (ret < 0) {
	355	mutex_unlock(&data->mutex);
	356	dev_err(data->dev, "failed to update reg_int_mask1");
	357	return ret;
	358	}
	359
	360	data->trigger_enabled = state;
	361	mutex_unlock(&data->mutex);
	362
	363	return 0;
	364	}
	365
	366	static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
	367	{
	368	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
	369	struct mxc4005_data *data = iio_priv(indio_dev);
	370
	371	if (!data->dready_trig)
	372	return 0;
	373
	374	return mxc4005_clr_intr(data);
	375	}
	376
	377	static const struct iio_trigger_ops mxc4005_trigger_ops = {
	378	.set_trigger_state = mxc4005_set_trigger_state,
	379	.try_reenable = mxc4005_trigger_try_reen,
	380	.owner = THIS_MODULE,
	381	};
	382
	383	static int mxc4005_gpio_probe(struct i2c_client *client,
	384	struct mxc4005_data *data)
	385	{
	386	struct device *dev;
387	struct gpio_desc *gpio;
388	int ret;
389
390	if (!client)
391	return -EINVAL;
392
393	dev = &client->dev;
394
395	gpio = devm_gpiod_get_index(dev, "mxc4005_int", 0, GPIOD_IN);
396	if (IS_ERR(gpio)) {
397	dev_err(dev, "failed to get acpi gpio index\n");
398	return PTR_ERR(gpio);
399	}
400
401	ret = gpiod_to_irq(gpio);
402
403	dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
404
405	return ret;
406	}
407
077377fc TB	408	static int mxc4005_chip_init(struct mxc4005_data *data)
	409	{
	410	int ret;
	411	unsigned int reg;
	412
	413	ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, &reg);
	414	if (ret < 0) {
	415	dev_err(data->dev, "failed to read chip id\n");
	416	return ret;
	417	}
	418
	419	dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
	420
	421	return 0;
	422	}
	423
	424	static int mxc4005_probe(struct i2c_client *client,
	425	const struct i2c_device_id *id)
	426	{
	427	struct mxc4005_data *data;
	428	struct iio_dev *indio_dev;
	429	struct regmap *regmap;
	430	int ret;
	431
	432	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	433	if (!indio_dev)
	434	return -ENOMEM;
	435
	436	regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
	437	if (IS_ERR(regmap)) {
	438	dev_err(&client->dev, "failed to initialize regmap\n");
	439	return PTR_ERR(regmap);
	440	}
	441
	442	data = iio_priv(indio_dev);
	443	i2c_set_clientdata(client, indio_dev);
	444	data->dev = &client->dev;
	445	data->regmap = regmap;
	446
	447	ret = mxc4005_chip_init(data);
	448	if (ret < 0) {
	449	dev_err(&client->dev, "failed to initialize chip\n");
	450	return ret;
	451	}
	452
	453	mutex_init(&data->mutex);
	454
	455	indio_dev->dev.parent = &client->dev;
	456	indio_dev->channels = mxc4005_channels;
	457	indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
1ce0eda0	458	indio_dev->available_scan_masks = mxc4005_scan_masks;
077377fc TB	459	indio_dev->name = MXC4005_DRV_NAME;
	460	indio_dev->modes = INDIO_DIRECT_MODE;
	461	indio_dev->info = &mxc4005_info;
	462
1ce0eda0	463	ret = iio_triggered_buffer_setup(indio_dev,
47196620	464	iio_pollfunc_store_time,
1ce0eda0 TB	465	mxc4005_trigger_handler,
	466	NULL);
	467	if (ret < 0) {
	468	dev_err(&client->dev,
	469	"failed to setup iio triggered buffer\n");
	470	return ret;
	471	}
	472
47196620 TB	473	if (client->irq < 0)
	474	client->irq = mxc4005_gpio_probe(client, data);
	475
	476	if (client->irq > 0) {
	477	data->dready_trig = devm_iio_trigger_alloc(&client->dev,
	478	"%s-dev%d",
	479	indio_dev->name,
	480	indio_dev->id);
	481	if (!data->dready_trig)
	482	return -ENOMEM;
	483
	484	ret = devm_request_threaded_irq(&client->dev, client->irq,
	485	iio_trigger_generic_data_rdy_poll,
	486	NULL,
	487	IRQF_TRIGGER_FALLING \|
	488	IRQF_ONESHOT,
	489	MXC4005_IRQ_NAME,
	490	data->dready_trig);
	491	if (ret) {
	492	dev_err(&client->dev,
	493	"failed to init threaded irq\n");
	494	goto err_buffer_cleanup;
	495	}
	496
	497	data->dready_trig->dev.parent = &client->dev;
	498	data->dready_trig->ops = &mxc4005_trigger_ops;
	499	iio_trigger_set_drvdata(data->dready_trig, indio_dev);
	500	indio_dev->trig = data->dready_trig;
	501	iio_trigger_get(indio_dev->trig);
	502	ret = iio_trigger_register(data->dready_trig);
	503	if (ret) {
	504	dev_err(&client->dev,
	505	"failed to register trigger\n");
	506	goto err_trigger_unregister;
	507	}
	508	}
	509
077377fc TB	510	ret = iio_device_register(indio_dev);
	511	if (ret < 0) {
	512	dev_err(&client->dev,
	513	"unable to register iio device %d\n", ret);
1ce0eda0	514	goto err_buffer_cleanup;
077377fc TB	515	}
	516
	517	return 0;
1ce0eda0	518
47196620 TB	519	err_trigger_unregister:
47196620 TB	520	iio_trigger_unregister(data->dready_trig);
1ce0eda0 TB	521	err_buffer_cleanup:
	522	iio_triggered_buffer_cleanup(indio_dev);
	523
	524	return ret;
077377fc TB	525	}
	526
	527	static int mxc4005_remove(struct i2c_client *client)
	528	{
1ce0eda0	529	struct iio_dev *indio_dev = i2c_get_clientdata(client);
47196620	530	struct mxc4005_data *data = iio_priv(indio_dev);
1ce0eda0 TB	531
	532	iio_device_unregister(indio_dev);
	533
	534	iio_triggered_buffer_cleanup(indio_dev);
47196620 TB	535	if (data->dready_trig)
47196620 TB	536	iio_trigger_unregister(data->dready_trig);
077377fc TB	537
	538	return 0;
	539	}
	540
	541	static const struct acpi_device_id mxc4005_acpi_match[] = {
	542	{"MXC4005", 0},
	543	{ },
	544	};
	545	MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
	546
	547	static const struct i2c_device_id mxc4005_id[] = {
	548	{"mxc4005", 0},
	549	{ },
	550	};
	551	MODULE_DEVICE_TABLE(i2c, mxc4005_id);
	552
	553	static struct i2c_driver mxc4005_driver = {
	554	.driver = {
	555	.name = MXC4005_DRV_NAME,
	556	.acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
	557	},
	558	.probe = mxc4005_probe,
	559	.remove = mxc4005_remove,
	560	.id_table = mxc4005_id,
	561	};
	562
	563	module_i2c_driver(mxc4005_driver);
	564
	565	MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
	566	MODULE_LICENSE("GPL v2");
	567	MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");