[deliverable/linux.git] / drivers / iio / adc / ad7298.c

/*
 * AD7298 SPI ADC driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include <linux/platform_data/ad7298.h>

#define AD7298_WRITE	(1 << 15) /* write to the control register */
#define AD7298_REPEAT	(1 << 14) /* repeated conversion enable */
#define AD7298_CH(x)	(1 << (13 - (x))) /* channel select */
#define AD7298_TSENSE	(1 << 5) /* temperature conversion enable */
#define AD7298_EXTREF	(1 << 2) /* external reference enable */
#define AD7298_TAVG	(1 << 1) /* temperature sensor averaging enable */
#define AD7298_PDD	(1 << 0) /* partial power down enable */

#define AD7298_MAX_CHAN		8
#define AD7298_BITS		12
#define AD7298_STORAGE_BITS	16
#define AD7298_INTREF_mV	2500

#define AD7298_CH_TEMP		9

#define RES_MASK(bits)	((1 << (bits)) - 1)

struct ad7298_state {
	struct spi_device		*spi;
	struct regulator		*reg;
	unsigned			ext_ref;
	struct spi_transfer		ring_xfer[10];
	struct spi_transfer		scan_single_xfer[3];
	struct spi_message		ring_msg;
	struct spi_message		scan_single_msg;
	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */
	__be16				rx_buf[12] ____cacheline_aligned;
	__be16				tx_buf[2];
};

#define AD7298_V_CHAN(index)						\
	{								\
		.type = IIO_VOLTAGE,					\
		.indexed = 1,						\
		.channel = index,					\
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
		.address = index,					\
		.scan_index = index,					\
		.scan_type = {						\
			.sign = 'u',					\
			.realbits = 12,					\
			.storagebits = 16,				\
			.endianness = IIO_BE,				\
		},							\
	}

static const struct iio_chan_spec ad7298_channels[] = {
	{
		.type = IIO_TEMP,
		.indexed = 1,
		.channel = 0,
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
			BIT(IIO_CHAN_INFO_SCALE) |
			BIT(IIO_CHAN_INFO_OFFSET),
		.address = AD7298_CH_TEMP,
		.scan_index = -1,
		.scan_type = {
			.sign = 's',
			.realbits = 32,
			.storagebits = 32,
		},
	},
	AD7298_V_CHAN(0),
	AD7298_V_CHAN(1),
	AD7298_V_CHAN(2),
	AD7298_V_CHAN(3),
	AD7298_V_CHAN(4),
	AD7298_V_CHAN(5),
	AD7298_V_CHAN(6),
	AD7298_V_CHAN(7),
	IIO_CHAN_SOFT_TIMESTAMP(8),
};

/**
 * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
 **/
static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
	const unsigned long *active_scan_mask)
{
	struct ad7298_state *st = iio_priv(indio_dev);
	int i, m;
	unsigned short command;
	int scan_count;

	/* Now compute overall size */
	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);

	command = AD7298_WRITE | st->ext_ref;

	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
		if (test_bit(i, active_scan_mask))
			command |= m;

	st->tx_buf[0] = cpu_to_be16(command);

	/* build spi ring message */
	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	st->ring_xfer[0].len = 2;
	st->ring_xfer[0].cs_change = 1;
	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
	st->ring_xfer[1].len = 2;
	st->ring_xfer[1].cs_change = 1;

	spi_message_init(&st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);

	for (i = 0; i < scan_count; i++) {
		st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
		st->ring_xfer[i + 2].len = 2;
		st->ring_xfer[i + 2].cs_change = 1;
		spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
	}
	/* make sure last transfer cs_change is not set */
	st->ring_xfer[i + 1].cs_change = 0;

	return 0;
}

/**
 * ad7298_trigger_handler() bh of trigger launched polling to ring buffer
 *
 * Currently there is no option in this driver to disable the saving of
 * timestamps within the ring.
 **/
static irqreturn_t ad7298_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7298_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, &st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
		iio_get_time_ns());

done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
{
	int ret;
	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
				   (AD7298_CH(0) >> ch));

	ret = spi_sync(st->spi, &st->scan_single_msg);
	if (ret)
		return ret;

	return be16_to_cpu(st->rx_buf[0]);
}

static int ad7298_scan_temp(struct ad7298_state *st, int *val)
{
	int ret;
	__be16 buf;

	buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
			  AD7298_TAVG | st->ext_ref);

	ret = spi_write(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	buf = cpu_to_be16(0);

	ret = spi_write(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	usleep_range(101, 1000); /* sleep > 100us */

	ret = spi_read(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	*val = sign_extend32(be16_to_cpu(buf), 11);

	return 0;
}

static int ad7298_get_ref_voltage(struct ad7298_state *st)
{
	int vref;

	if (st->ext_ref) {
		vref = regulator_get_voltage(st->reg);
		if (vref < 0)
			return vref;

		return vref / 1000;
	} else {
		return AD7298_INTREF_mV;
	}
}

static int ad7298_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7298_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&indio_dev->mlock);
		if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
			ret = -EBUSY;
		} else {
			if (chan->address == AD7298_CH_TEMP)
				ret = ad7298_scan_temp(st, val);
			else
				ret = ad7298_scan_direct(st, chan->address);
		}
		mutex_unlock(&indio_dev->mlock);

		if (ret < 0)
			return ret;

		if (chan->address != AD7298_CH_TEMP)
			*val = ret & RES_MASK(AD7298_BITS);

		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		switch (chan->type) {
		case IIO_VOLTAGE:
			*val = ad7298_get_ref_voltage(st);
			*val2 = chan->scan_type.realbits;
			return IIO_VAL_FRACTIONAL_LOG2;
		case IIO_TEMP:
			*val = ad7298_get_ref_voltage(st);
			*val2 = 10;
			return IIO_VAL_FRACTIONAL;
		default:
			return -EINVAL;
		}
	case IIO_CHAN_INFO_OFFSET:
		*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
		return IIO_VAL_INT;
	}
	return -EINVAL;
}

static const struct iio_info ad7298_info = {
	.read_raw = &ad7298_read_raw,
	.update_scan_mode = ad7298_update_scan_mode,
	.driver_module = THIS_MODULE,
};

static int ad7298_probe(struct spi_device *spi)
{
	struct ad7298_platform_data *pdata = spi->dev.platform_data;
	struct ad7298_state *st;
	struct iio_dev *indio_dev;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	if (pdata && pdata->ext_ref)
		st->ext_ref = AD7298_EXTREF;

	if (st->ext_ref) {
		st->reg = devm_regulator_get(&spi->dev, "vref");
		if (IS_ERR(st->reg))
			return PTR_ERR(st->reg);

		ret = regulator_enable(st->reg);
		if (ret)
			return ret;
	}

	spi_set_drvdata(spi, indio_dev);

	st->spi = spi;

	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->dev.parent = &spi->dev;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = ad7298_channels;
	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
	indio_dev->info = &ad7298_info;

	/* Setup default message */

	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	st->scan_single_xfer[0].len = 2;
	st->scan_single_xfer[0].cs_change = 1;
	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
	st->scan_single_xfer[1].len = 2;
	st->scan_single_xfer[1].cs_change = 1;
	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
	st->scan_single_xfer[2].len = 2;

	spi_message_init(&st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);

	ret = iio_triggered_buffer_setup(indio_dev, NULL,
			&ad7298_trigger_handler, NULL);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_cleanup_ring;

	return 0;

error_cleanup_ring:
	iio_triggered_buffer_cleanup(indio_dev);
error_disable_reg:
	if (st->ext_ref)
		regulator_disable(st->reg);

	return ret;
}

static int ad7298_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad7298_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	if (st->ext_ref)
		regulator_disable(st->reg);

	return 0;
}

static const struct spi_device_id ad7298_id[] = {
	{"ad7298", 0},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7298_id);

static struct spi_driver ad7298_driver = {
	.driver = {
		.name	= "ad7298",
		.owner	= THIS_MODULE,
	},
	.probe		= ad7298_probe,
	.remove		= ad7298_remove,
	.id_table	= ad7298_id,
};
module_spi_driver(ad7298_driver);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
7c31b984 MH	1	/*
	2	* AD7298 SPI ADC driver
	3	*
	4	* Copyright 2011 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2.
	7	*/
	8
7c31b984 MH	9	#include <linux/device.h>
	10	#include <linux/kernel.h>
	11	#include <linux/slab.h>
	12	#include <linux/sysfs.h>
	13	#include <linux/spi/spi.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/err.h>
	16	#include <linux/delay.h>
99c97852	17	#include <linux/module.h>
dc4871ad	18	#include <linux/interrupt.h>
7c31b984	19
06458e27 JC	20	#include <linux/iio/iio.h>
	21	#include <linux/iio/sysfs.h>
	22	#include <linux/iio/buffer.h>
dc4871ad LPC	23	#include <linux/iio/trigger_consumer.h>
dc4871ad LPC	24	#include <linux/iio/triggered_buffer.h>
7c31b984	25
709ab36e	26	#include <linux/platform_data/ad7298.h>
7c31b984	27
dc4871ad LPC	28	#define AD7298_WRITE (1 << 15) /* write to the control register */
	29	#define AD7298_REPEAT (1 << 14) /* repeated conversion enable */
	30	#define AD7298_CH(x) (1 << (13 - (x))) /* channel select */
	31	#define AD7298_TSENSE (1 << 5) /* temperature conversion enable */
	32	#define AD7298_EXTREF (1 << 2) /* external reference enable */
	33	#define AD7298_TAVG (1 << 1) /* temperature sensor averaging enable */
	34	#define AD7298_PDD (1 << 0) /* partial power down enable */
	35
	36	#define AD7298_MAX_CHAN 8
	37	#define AD7298_BITS 12
	38	#define AD7298_STORAGE_BITS 16
	39	#define AD7298_INTREF_mV 2500
	40
	41	#define AD7298_CH_TEMP 9
	42
	43	#define RES_MASK(bits) ((1 << (bits)) - 1)
	44
	45	struct ad7298_state {
	46	struct spi_device *spi;
	47	struct regulator *reg;
	48	unsigned ext_ref;
	49	struct spi_transfer ring_xfer[10];
	50	struct spi_transfer scan_single_xfer[3];
	51	struct spi_message ring_msg;
	52	struct spi_message scan_single_msg;
	53	/*
	54	* DMA (thus cache coherency maintenance) requires the
	55	* transfer buffers to live in their own cache lines.
	56	*/
be7fd3b8 JC	57	__be16 rx_buf[12] ____cacheline_aligned;
be7fd3b8 JC	58	__be16 tx_buf[2];
dc4871ad LPC	59	};
dc4871ad LPC	60
95e48f77 JC	61	#define AD7298_V_CHAN(index) \
	62	{ \
	63	.type = IIO_VOLTAGE, \
	64	.indexed = 1, \
	65	.channel = index, \
40dd676d JC	66	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
40dd676d JC	67	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
95e48f77 JC	68	.address = index, \
	69	.scan_index = index, \
	70	.scan_type = { \
	71	.sign = 'u', \
	72	.realbits = 12, \
	73	.storagebits = 16, \
ca654638	74	.endianness = IIO_BE, \
95e48f77 JC	75	}, \
	76	}
	77
f4e4b955	78	static const struct iio_chan_spec ad7298_channels[] = {
95e48f77 JC	79	{
	80	.type = IIO_TEMP,
	81	.indexed = 1,
	82	.channel = 0,
40dd676d JC	83	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \|
	84	BIT(IIO_CHAN_INFO_SCALE) \|
	85	BIT(IIO_CHAN_INFO_OFFSET),
d045b9d2 LPC	86	.address = AD7298_CH_TEMP,
d045b9d2 LPC	87	.scan_index = -1,
95e48f77 JC	88	.scan_type = {
	89	.sign = 's',
	90	.realbits = 32,
	91	.storagebits = 32,
	92	},
	93	},
	94	AD7298_V_CHAN(0),
	95	AD7298_V_CHAN(1),
	96	AD7298_V_CHAN(2),
	97	AD7298_V_CHAN(3),
	98	AD7298_V_CHAN(4),
	99	AD7298_V_CHAN(5),
	100	AD7298_V_CHAN(6),
	101	AD7298_V_CHAN(7),
01a99e18 MH	102	IIO_CHAN_SOFT_TIMESTAMP(8),
	103	};
	104
dc4871ad LPC	105	/**
	106	* ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
	107	**/
	108	static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
	109	const unsigned long *active_scan_mask)
	110	{
	111	struct ad7298_state *st = iio_priv(indio_dev);
	112	int i, m;
	113	unsigned short command;
	114	int scan_count;
	115
	116	/* Now compute overall size */
	117	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
	118
	119	command = AD7298_WRITE \| st->ext_ref;
	120
	121	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
	122	if (test_bit(i, active_scan_mask))
	123	command \|= m;
	124
	125	st->tx_buf[0] = cpu_to_be16(command);
	126
	127	/* build spi ring message */
	128	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	129	st->ring_xfer[0].len = 2;
	130	st->ring_xfer[0].cs_change = 1;
	131	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
	132	st->ring_xfer[1].len = 2;
	133	st->ring_xfer[1].cs_change = 1;
	134
	135	spi_message_init(&st->ring_msg);
	136	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	137	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
	138
	139	for (i = 0; i < scan_count; i++) {
	140	st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
	141	st->ring_xfer[i + 2].len = 2;
	142	st->ring_xfer[i + 2].cs_change = 1;
	143	spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
	144	}
	145	/* make sure last transfer cs_change is not set */
	146	st->ring_xfer[i + 1].cs_change = 0;
	147
	148	return 0;
	149	}
	150
	151	/**
	152	* ad7298_trigger_handler() bh of trigger launched polling to ring buffer
	153	*
	154	* Currently there is no option in this driver to disable the saving of
	155	* timestamps within the ring.
	156	**/
	157	static irqreturn_t ad7298_trigger_handler(int irq, void *p)
	158	{
	159	struct iio_poll_func *pf = p;
	160	struct iio_dev *indio_dev = pf->indio_dev;
	161	struct ad7298_state *st = iio_priv(indio_dev);
dc4871ad LPC	162	int b_sent;
	163
	164	b_sent = spi_sync(st->spi, &st->ring_msg);
	165	if (b_sent)
	166	goto done;
	167
85ec2372 LPC	168	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
85ec2372 LPC	169	iio_get_time_ns());
dc4871ad LPC	170
	171	done:
	172	iio_trigger_notify_done(indio_dev->trig);
	173
	174	return IRQ_HANDLED;
	175	}
	176
7c31b984 MH	177	static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
	178	{
	179	int ret;
	180	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE \| st->ext_ref \|
	181	(AD7298_CH(0) >> ch));
	182
	183	ret = spi_sync(st->spi, &st->scan_single_msg);
	184	if (ret)
	185	return ret;
	186
	187	return be16_to_cpu(st->rx_buf[0]);
	188	}
	189
01a99e18	190	static int ad7298_scan_temp(struct ad7298_state st, int val)
7c31b984	191	{
01a10e04	192	int ret;
c1a75288	193	__be16 buf;
7c31b984	194
c1a75288	195	buf = cpu_to_be16(AD7298_WRITE \| AD7298_TSENSE \|
01a99e18	196	AD7298_TAVG \| st->ext_ref);
7c31b984	197
c1a75288	198	ret = spi_write(st->spi, (u8 *)&buf, 2);
01a99e18	199	if (ret)
7c31b984 MH	200	return ret;
7c31b984 MH	201
c1a75288	202	buf = cpu_to_be16(0);
7c31b984	203
c1a75288	204	ret = spi_write(st->spi, (u8 *)&buf, 2);
01a99e18 MH	205	if (ret)
01a99e18 MH	206	return ret;
7c31b984	207
7c31b984	208	usleep_range(101, 1000); /* sleep > 100us */
01a99e18	209
c1a75288	210	ret = spi_read(st->spi, (u8 *)&buf, 2);
01a99e18 MH	211	if (ret)
01a99e18 MH	212	return ret;
7c31b984	213
01a10e04	214	*val = sign_extend32(be16_to_cpu(buf), 11);
7c31b984	215
01a10e04 LPC	216	return 0;
	217	}
	218
	219	static int ad7298_get_ref_voltage(struct ad7298_state *st)
	220	{
	221	int vref;
7c31b984	222
01a10e04 LPC	223	if (st->ext_ref) {
	224	vref = regulator_get_voltage(st->reg);
	225	if (vref < 0)
	226	return vref;
7c31b984	227
01a10e04	228	return vref / 1000;
7c31b984	229	} else {
01a10e04	230	return AD7298_INTREF_mV;
7c31b984	231	}
01a99e18	232	}
7c31b984	233
84f79ecb	234	static int ad7298_read_raw(struct iio_dev *indio_dev,
01a99e18 MH	235	struct iio_chan_spec const *chan,
	236	int *val,
	237	int *val2,
	238	long m)
7c31b984	239	{
01a99e18	240	int ret;
84f79ecb	241	struct ad7298_state *st = iio_priv(indio_dev);
01a99e18 MH	242
01a99e18 MH	243	switch (m) {
b11f98ff	244	case IIO_CHAN_INFO_RAW:
84f79ecb	245	mutex_lock(&indio_dev->mlock);
389ac488 JC	246	if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
389ac488 JC	247	ret = -EBUSY;
01a99e18 MH	248	} else {
	249	if (chan->address == AD7298_CH_TEMP)
	250	ret = ad7298_scan_temp(st, val);
	251	else
	252	ret = ad7298_scan_direct(st, chan->address);
	253	}
84f79ecb	254	mutex_unlock(&indio_dev->mlock);
01a99e18 MH	255
	256	if (ret < 0)
	257	return ret;
	258
	259	if (chan->address != AD7298_CH_TEMP)
	260	*val = ret & RES_MASK(AD7298_BITS);
	261
	262	return IIO_VAL_INT;
c8a9f805 JC	263	case IIO_CHAN_INFO_SCALE:
	264	switch (chan->type) {
	265	case IIO_VOLTAGE:
01a10e04	266	*val = ad7298_get_ref_voltage(st);
2e334600 LPC	267	*val2 = chan->scan_type.realbits;
2e334600 LPC	268	return IIO_VAL_FRACTIONAL_LOG2;
c8a9f805	269	case IIO_TEMP:
01a10e04 LPC	270	*val = ad7298_get_ref_voltage(st);
	271	*val2 = 10;
	272	return IIO_VAL_FRACTIONAL;
c8a9f805 JC	273	default:
	274	return -EINVAL;
	275	}
01a10e04 LPC	276	case IIO_CHAN_INFO_OFFSET:
	277	*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
	278	return IIO_VAL_INT;
01a99e18 MH	279	}
01a99e18 MH	280	return -EINVAL;
7c31b984	281	}
7c31b984	282
6fe8135f JC	283	static const struct iio_info ad7298_info = {
6fe8135f JC	284	.read_raw = &ad7298_read_raw,
d045b9d2	285	.update_scan_mode = ad7298_update_scan_mode,
6fe8135f JC	286	.driver_module = THIS_MODULE,
	287	};
	288
fc52692c	289	static int ad7298_probe(struct spi_device *spi)
7c31b984 MH	290	{
	291	struct ad7298_platform_data *pdata = spi->dev.platform_data;
	292	struct ad7298_state *st;
7abe9007	293	struct iio_dev *indio_dev;
2e334600	294	int ret;
7c31b984	295
7abe9007	296	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
cc4a48e4 MH	297	if (indio_dev == NULL)
	298	return -ENOMEM;
	299
	300	st = iio_priv(indio_dev);
7c31b984	301
2e334600 LPC	302	if (pdata && pdata->ext_ref)
	303	st->ext_ref = AD7298_EXTREF;
	304
	305	if (st->ext_ref) {
7abe9007 SK	306	st->reg = devm_regulator_get(&spi->dev, "vref");
	307	if (IS_ERR(st->reg))
	308	return PTR_ERR(st->reg);
	309
7c31b984 MH	310	ret = regulator_enable(st->reg);
7c31b984 MH	311	if (ret)
7abe9007	312	return ret;
7c31b984 MH	313	}
7c31b984 MH	314
cc4a48e4	315	spi_set_drvdata(spi, indio_dev);
7c31b984	316
7c31b984 MH	317	st->spi = spi;
7c31b984 MH	318
cc4a48e4 MH	319	indio_dev->name = spi_get_device_id(spi)->name;
cc4a48e4 MH	320	indio_dev->dev.parent = &spi->dev;
cc4a48e4 MH	321	indio_dev->modes = INDIO_DIRECT_MODE;
	322	indio_dev->channels = ad7298_channels;
	323	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
6fe8135f	324	indio_dev->info = &ad7298_info;
7c31b984 MH	325
	326	/* Setup default message */
	327
	328	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	329	st->scan_single_xfer[0].len = 2;
	330	st->scan_single_xfer[0].cs_change = 1;
	331	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
	332	st->scan_single_xfer[1].len = 2;
	333	st->scan_single_xfer[1].cs_change = 1;
	334	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
	335	st->scan_single_xfer[2].len = 2;
	336
	337	spi_message_init(&st->scan_single_msg);
	338	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	339	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	340	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
	341
dc4871ad LPC	342	ret = iio_triggered_buffer_setup(indio_dev, NULL,
dc4871ad LPC	343	&ad7298_trigger_handler, NULL);
7c31b984	344	if (ret)
cc4a48e4	345	goto error_disable_reg;
7c31b984	346
26d25ae3 JC	347	ret = iio_device_register(indio_dev);
26d25ae3 JC	348	if (ret)
d045b9d2	349	goto error_cleanup_ring;
cc4a48e4	350
7c31b984 MH	351	return 0;
	352
	353	error_cleanup_ring:
dc4871ad	354	iio_triggered_buffer_cleanup(indio_dev);
7c31b984	355	error_disable_reg:
2e334600	356	if (st->ext_ref)
7c31b984	357	regulator_disable(st->reg);
cc4a48e4	358
7c31b984 MH	359	return ret;
	360	}
	361
fc52692c	362	static int ad7298_remove(struct spi_device *spi)
7c31b984	363	{
cc4a48e4 MH	364	struct iio_dev *indio_dev = spi_get_drvdata(spi);
cc4a48e4 MH	365	struct ad7298_state *st = iio_priv(indio_dev);
7c31b984	366
d2fffd6c	367	iio_device_unregister(indio_dev);
dc4871ad	368	iio_triggered_buffer_cleanup(indio_dev);
7abe9007	369	if (st->ext_ref)
7c31b984	370	regulator_disable(st->reg);
cc4a48e4	371
7c31b984 MH	372	return 0;
	373	}
	374
	375	static const struct spi_device_id ad7298_id[] = {
	376	{"ad7298", 0},
	377	{}
	378	};
55e4390c	379	MODULE_DEVICE_TABLE(spi, ad7298_id);
7c31b984 MH	380
	381	static struct spi_driver ad7298_driver = {
	382	.driver = {
	383	.name = "ad7298",
7c31b984 MH	384	.owner = THIS_MODULE,
	385	},
	386	.probe = ad7298_probe,
fc52692c	387	.remove = ad7298_remove,
7c31b984 MH	388	.id_table = ad7298_id,
7c31b984 MH	389	};
ae6ae6fe	390	module_spi_driver(ad7298_driver);
7c31b984 MH	391
	392	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
	393	MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
	394	MODULE_LICENSE("GPL v2");