[deliverable/linux.git] / drivers / iio / adc / ad7887.c

/*
 * AD7887 SPI ADC driver
 *
 * Copyright 2010-2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>

#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include <linux/platform_data/ad7887.h>

#define AD7887_REF_DIS		BIT(5)	/* on-chip reference disable */
#define AD7887_DUAL		BIT(4)	/* dual-channel mode */
#define AD7887_CH_AIN1		BIT(3)	/* convert on channel 1, DUAL=1 */
#define AD7887_CH_AIN0		0	/* convert on channel 0, DUAL=0,1 */
#define AD7887_PM_MODE1		0	/* CS based shutdown */
#define AD7887_PM_MODE2		1	/* full on */
#define AD7887_PM_MODE3		2	/* auto shutdown after conversion */
#define AD7887_PM_MODE4		3	/* standby mode */

enum ad7887_channels {
	AD7887_CH0,
	AD7887_CH0_CH1,
	AD7887_CH1,
};

/**
 * struct ad7887_chip_info - chip specifc information
 * @int_vref_mv:	the internal reference voltage
 * @channel:		channel specification
 */
struct ad7887_chip_info {
	u16				int_vref_mv;
	struct iio_chan_spec		channel[3];
};

struct ad7887_state {
	struct spi_device		*spi;
	const struct ad7887_chip_info	*chip_info;
	struct regulator		*reg;
	struct spi_transfer		xfer[4];
	struct spi_message		msg[3];
	struct spi_message		*ring_msg;
	unsigned char			tx_cmd_buf[4];

	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 * Buffer needs to be large enough to hold two 16 bit samples and a
	 * 64 bit aligned 64 bit timestamp.
	 */
	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
		____cacheline_aligned;
};

enum ad7887_supported_device_ids {
	ID_AD7887
};

static int ad7887_ring_preenable(struct iio_dev *indio_dev)
{
	struct ad7887_state *st = iio_priv(indio_dev);

	/* We know this is a single long so can 'cheat' */
	switch (*indio_dev->active_scan_mask) {
	case (1 << 0):
		st->ring_msg = &st->msg[AD7887_CH0];
		break;
	case (1 << 1):
		st->ring_msg = &st->msg[AD7887_CH1];
		/* Dummy read: push CH1 setting down to hardware */
		spi_sync(st->spi, st->ring_msg);
		break;
	case ((1 << 1) | (1 << 0)):
		st->ring_msg = &st->msg[AD7887_CH0_CH1];
		break;
	}

	return 0;
}

static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
{
	struct ad7887_state *st = iio_priv(indio_dev);

	/* dummy read: restore default CH0 settin */
	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
}

/**
 * ad7887_trigger_handler() bh of trigger launched polling to ring buffer
 *
 * Currently there is no option in this driver to disable the saving of
 * timestamps within the ring.
 **/
static irqreturn_t ad7887_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7887_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
		iio_get_time_ns());
done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
	.preenable = &ad7887_ring_preenable,
	.postenable = &iio_triggered_buffer_postenable,
	.predisable = &iio_triggered_buffer_predisable,
	.postdisable = &ad7887_ring_postdisable,
};

static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
{
	int ret = spi_sync(st->spi, &st->msg[ch]);
	if (ret)
		return ret;

	return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
}

static int ad7887_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7887_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&indio_dev->mlock);
		if (iio_buffer_enabled(indio_dev))
			ret = -EBUSY;
		else
			ret = ad7887_scan_direct(st, chan->address);
		mutex_unlock(&indio_dev->mlock);

		if (ret < 0)
			return ret;
		*val = ret >> chan->scan_type.shift;
		*val &= GENMASK(chan->scan_type.realbits - 1, 0);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		if (st->reg) {
			*val = regulator_get_voltage(st->reg);
			if (*val < 0)
				return *val;
			*val /= 1000;
		} else {
			*val = st->chip_info->int_vref_mv;
		}

		*val2 = chan->scan_type.realbits;

		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}


static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
	/*
	 * More devices added in future
	 */
	[ID_AD7887] = {
		.channel[0] = {
			.type = IIO_VOLTAGE,
			.indexed = 1,
			.channel = 1,
			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
			.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
			.address = 1,
			.scan_index = 1,
			.scan_type = {
				.sign = 'u',
				.realbits = 12,
				.storagebits = 16,
				.shift = 0,
				.endianness = IIO_BE,
			},
		},
		.channel[1] = {
			.type = IIO_VOLTAGE,
			.indexed = 1,
			.channel = 0,
			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
			.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
			.address = 0,
			.scan_index = 0,
			.scan_type = {
				.sign = 'u',
				.realbits = 12,
				.storagebits = 16,
				.shift = 0,
				.endianness = IIO_BE,
			},
		},
		.channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
		.int_vref_mv = 2500,
	},
};

static const struct iio_info ad7887_info = {
	.read_raw = &ad7887_read_raw,
	.driver_module = THIS_MODULE,
};

static int ad7887_probe(struct spi_device *spi)
{
	struct ad7887_platform_data *pdata = spi->dev.platform_data;
	struct ad7887_state *st;
	struct iio_dev *indio_dev;
	uint8_t mode;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	if (!pdata || !pdata->use_onchip_ref) {
		st->reg = devm_regulator_get(&spi->dev, "vref");
		if (IS_ERR(st->reg))
			return PTR_ERR(st->reg);

		ret = regulator_enable(st->reg);
		if (ret)
			return ret;
	}

	st->chip_info =
		&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];

	spi_set_drvdata(spi, indio_dev);
	st->spi = spi;

	/* Estabilish that the iio_dev is a child of the spi device */
	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad7887_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	/* Setup default message */

	mode = AD7887_PM_MODE4;
	if (!pdata || !pdata->use_onchip_ref)
		mode |= AD7887_REF_DIS;
	if (pdata && pdata->en_dual)
		mode |= AD7887_DUAL;

	st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;

	st->xfer[0].rx_buf = &st->data[0];
	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
	st->xfer[0].len = 2;

	spi_message_init(&st->msg[AD7887_CH0]);
	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);

	if (pdata && pdata->en_dual) {
		st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;

		st->xfer[1].rx_buf = &st->data[0];
		st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
		st->xfer[1].len = 2;

		st->xfer[2].rx_buf = &st->data[2];
		st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
		st->xfer[2].len = 2;

		spi_message_init(&st->msg[AD7887_CH0_CH1]);
		spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
		spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);

		st->xfer[3].rx_buf = &st->data[2];
		st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
		st->xfer[3].len = 2;

		spi_message_init(&st->msg[AD7887_CH1]);
		spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);

		indio_dev->channels = st->chip_info->channel;
		indio_dev->num_channels = 3;
	} else {
		indio_dev->channels = &st->chip_info->channel[1];
		indio_dev->num_channels = 2;
	}

	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
			&ad7887_trigger_handler, &ad7887_ring_setup_ops);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_unregister_ring;

	return 0;
error_unregister_ring:
	iio_triggered_buffer_cleanup(indio_dev);
error_disable_reg:
	if (st->reg)
		regulator_disable(st->reg);

	return ret;
}

static int ad7887_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad7887_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	if (st->reg)
		regulator_disable(st->reg);

	return 0;
}

static const struct spi_device_id ad7887_id[] = {
	{"ad7887", ID_AD7887},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7887_id);

static struct spi_driver ad7887_driver = {
	.driver = {
		.name	= "ad7887",
	},
	.probe		= ad7887_probe,
	.remove		= ad7887_remove,
	.id_table	= ad7887_id,
};
module_spi_driver(ad7887_driver);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2b4756aa MH	1	/*
	2	* AD7887 SPI ADC driver
	3	*
596d0609	4	* Copyright 2010-2011 Analog Devices Inc.
2b4756aa	5	*
596d0609	6	* Licensed under the GPL-2.
2b4756aa MH	7	*/
2b4756aa MH	8
2b4756aa MH	9	#include <linux/device.h>
	10	#include <linux/kernel.h>
	11	#include <linux/slab.h>
	12	#include <linux/sysfs.h>
2b4756aa MH	13	#include <linux/spi/spi.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/err.h>
99c97852	16	#include <linux/module.h>
65dd3d3d	17	#include <linux/interrupt.h>
09a1737e	18	#include <linux/bitops.h>
2b4756aa	19
06458e27 JC	20	#include <linux/iio/iio.h>
	21	#include <linux/iio/sysfs.h>
	22	#include <linux/iio/buffer.h>
cdf38709	23
65dd3d3d LPC	24	#include <linux/iio/trigger_consumer.h>
65dd3d3d LPC	25	#include <linux/iio/triggered_buffer.h>
2b4756aa	26
4eb3ccf1	27	#include <linux/platform_data/ad7887.h>
2b4756aa	28
09a1737e PM	29	#define AD7887_REF_DIS BIT(5) /* on-chip reference disable */
	30	#define AD7887_DUAL BIT(4) /* dual-channel mode */
	31	#define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
	32	#define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
	33	#define AD7887_PM_MODE1 0 /* CS based shutdown */
	34	#define AD7887_PM_MODE2 1 /* full on */
	35	#define AD7887_PM_MODE3 2 /* auto shutdown after conversion */
	36	#define AD7887_PM_MODE4 3 /* standby mode */
65dd3d3d LPC	37
	38	enum ad7887_channels {
	39	AD7887_CH0,
	40	AD7887_CH0_CH1,
	41	AD7887_CH1,
	42	};
	43
65dd3d3d LPC	44	/**
	45	* struct ad7887_chip_info - chip specifc information
	46	* @int_vref_mv: the internal reference voltage
	47	* @channel: channel specification
	48	*/
	49	struct ad7887_chip_info {
	50	u16 int_vref_mv;
	51	struct iio_chan_spec channel[3];
	52	};
	53
	54	struct ad7887_state {
	55	struct spi_device *spi;
	56	const struct ad7887_chip_info *chip_info;
	57	struct regulator *reg;
	58	struct spi_transfer xfer[4];
	59	struct spi_message msg[3];
	60	struct spi_message *ring_msg;
fce7c3ea	61	unsigned char tx_cmd_buf[4];
65dd3d3d LPC	62
	63	/*
	64	* DMA (thus cache coherency maintenance) requires the
	65	* transfer buffers to live in their own cache lines.
	66	* Buffer needs to be large enough to hold two 16 bit samples and a
	67	* 64 bit aligned 64 bit timestamp.
	68	*/
	69	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
	70	____cacheline_aligned;
	71	};
	72
	73	enum ad7887_supported_device_ids {
	74	ID_AD7887
	75	};
	76
	77	static int ad7887_ring_preenable(struct iio_dev *indio_dev)
	78	{
	79	struct ad7887_state *st = iio_priv(indio_dev);
65dd3d3d LPC	80
	81	/* We know this is a single long so can 'cheat' */
	82	switch (*indio_dev->active_scan_mask) {
	83	case (1 << 0):
	84	st->ring_msg = &st->msg[AD7887_CH0];
	85	break;
	86	case (1 << 1):
	87	st->ring_msg = &st->msg[AD7887_CH1];
	88	/* Dummy read: push CH1 setting down to hardware */
	89	spi_sync(st->spi, st->ring_msg);
	90	break;
	91	case ((1 << 1) \| (1 << 0)):
	92	st->ring_msg = &st->msg[AD7887_CH0_CH1];
	93	break;
	94	}
	95
	96	return 0;
	97	}
	98
	99	static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
	100	{
	101	struct ad7887_state *st = iio_priv(indio_dev);
	102
	103	/* dummy read: restore default CH0 settin */
	104	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
	105	}
	106
	107	/**
	108	* ad7887_trigger_handler() bh of trigger launched polling to ring buffer
	109	*
	110	* Currently there is no option in this driver to disable the saving of
	111	* timestamps within the ring.
	112	**/
	113	static irqreturn_t ad7887_trigger_handler(int irq, void *p)
	114	{
	115	struct iio_poll_func *pf = p;
	116	struct iio_dev *indio_dev = pf->indio_dev;
	117	struct ad7887_state *st = iio_priv(indio_dev);
65dd3d3d LPC	118	int b_sent;
	119
	120	b_sent = spi_sync(st->spi, st->ring_msg);
	121	if (b_sent)
	122	goto done;
	123
5afd602b LPC	124	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
5afd602b LPC	125	iio_get_time_ns());
65dd3d3d LPC	126	done:
	127	iio_trigger_notify_done(indio_dev->trig);
	128
	129	return IRQ_HANDLED;
	130	}
	131
	132	static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
	133	.preenable = &ad7887_ring_preenable,
	134	.postenable = &iio_triggered_buffer_postenable,
	135	.predisable = &iio_triggered_buffer_predisable,
	136	.postdisable = &ad7887_ring_postdisable,
	137	};
	138
2b4756aa MH	139	static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
	140	{
	141	int ret = spi_sync(st->spi, &st->msg[ch]);
	142	if (ret)
	143	return ret;
	144
	145	return (st->data[(ch * 2)] << 8) \| st->data[(ch * 2) + 1];
	146	}
	147
84f79ecb	148	static int ad7887_read_raw(struct iio_dev *indio_dev,
596d0609 MH	149	struct iio_chan_spec const *chan,
	150	int *val,
	151	int *val2,
	152	long m)
2b4756aa	153	{
2b4756aa	154	int ret;
84f79ecb	155	struct ad7887_state *st = iio_priv(indio_dev);
2b4756aa	156
596d0609	157	switch (m) {
b11f98ff	158	case IIO_CHAN_INFO_RAW:
84f79ecb JC	159	mutex_lock(&indio_dev->mlock);
84f79ecb JC	160	if (iio_buffer_enabled(indio_dev))
790d8759	161	ret = -EBUSY;
596d0609 MH	162	else
596d0609 MH	163	ret = ad7887_scan_direct(st, chan->address);
84f79ecb	164	mutex_unlock(&indio_dev->mlock);
596d0609 MH	165
	166	if (ret < 0)
	167	return ret;
98efb70a	168	*val = ret >> chan->scan_type.shift;
09a1737e	169	*val &= GENMASK(chan->scan_type.realbits - 1, 0);
596d0609	170	return IIO_VAL_INT;
c8a9f805	171	case IIO_CHAN_INFO_SCALE:
bf5d2613 LPC	172	if (st->reg) {
	173	*val = regulator_get_voltage(st->reg);
	174	if (*val < 0)
	175	return *val;
	176	*val /= 1000;
	177	} else {
	178	*val = st->chip_info->int_vref_mv;
	179	}
	180
98efb70a	181	*val2 = chan->scan_type.realbits;
bf5d2613 LPC	182
bf5d2613 LPC	183	return IIO_VAL_FRACTIONAL_LOG2;
596d0609 MH	184	}
596d0609 MH	185	return -EINVAL;
2b4756aa MH	186	}
2b4756aa MH	187
2b4756aa MH	188
	189	static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
	190	/*
	191	* More devices added in future
	192	*/
	193	[ID_AD7887] = {
31bf47d5 JC	194	.channel[0] = {
	195	.type = IIO_VOLTAGE,
	196	.indexed = 1,
	197	.channel = 1,
16d186b1 JC	198	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
16d186b1 JC	199	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
31bf47d5 JC	200	.address = 1,
31bf47d5 JC	201	.scan_index = 1,
e39d9905 JC	202	.scan_type = {
	203	.sign = 'u',
	204	.realbits = 12,
	205	.storagebits = 16,
	206	.shift = 0,
	207	.endianness = IIO_BE,
	208	},
31bf47d5 JC	209	},
	210	.channel[1] = {
	211	.type = IIO_VOLTAGE,
	212	.indexed = 1,
	213	.channel = 0,
16d186b1 JC	214	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
16d186b1 JC	215	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
31bf47d5 JC	216	.address = 0,
31bf47d5 JC	217	.scan_index = 0,
e39d9905 JC	218	.scan_type = {
	219	.sign = 'u',
	220	.realbits = 12,
	221	.storagebits = 16,
	222	.shift = 0,
	223	.endianness = IIO_BE,
	224	},
31bf47d5	225	},
596d0609	226	.channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
2b4756aa MH	227	.int_vref_mv = 2500,
	228	},
	229	};
	230
6fe8135f JC	231	static const struct iio_info ad7887_info = {
	232	.read_raw = &ad7887_read_raw,
	233	.driver_module = THIS_MODULE,
	234	};
	235
fc52692c	236	static int ad7887_probe(struct spi_device *spi)
2b4756aa MH	237	{
	238	struct ad7887_platform_data *pdata = spi->dev.platform_data;
	239	struct ad7887_state *st;
82429e0d	240	struct iio_dev *indio_dev;
fce7c3ea	241	uint8_t mode;
bf5d2613	242	int ret;
2b4756aa	243
82429e0d	244	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
f39e086a MH	245	if (indio_dev == NULL)
	246	return -ENOMEM;
	247
	248	st = iio_priv(indio_dev);
2b4756aa	249
bf5d2613	250	if (!pdata \|\| !pdata->use_onchip_ref) {
82429e0d SK	251	st->reg = devm_regulator_get(&spi->dev, "vref");
	252	if (IS_ERR(st->reg))
	253	return PTR_ERR(st->reg);
bf5d2613	254
2b4756aa MH	255	ret = regulator_enable(st->reg);
2b4756aa MH	256	if (ret)
82429e0d	257	return ret;
2b4756aa MH	258	}
	259
	260	st->chip_info =
	261	&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
	262
f39e086a	263	spi_set_drvdata(spi, indio_dev);
2b4756aa MH	264	st->spi = spi;
2b4756aa MH	265
2b4756aa	266	/* Estabilish that the iio_dev is a child of the spi device */
f39e086a MH	267	indio_dev->dev.parent = &spi->dev;
f39e086a MH	268	indio_dev->name = spi_get_device_id(spi)->name;
6fe8135f	269	indio_dev->info = &ad7887_info;
f39e086a	270	indio_dev->modes = INDIO_DIRECT_MODE;
2b4756aa MH	271
	272	/* Setup default message */
	273
fce7c3ea LPC	274	mode = AD7887_PM_MODE4;
	275	if (!pdata \|\| !pdata->use_onchip_ref)
	276	mode \|= AD7887_REF_DIS;
	277	if (pdata && pdata->en_dual)
	278	mode \|= AD7887_DUAL;
	279
	280	st->tx_cmd_buf[0] = AD7887_CH_AIN0 \| mode;
2b4756aa MH	281
	282	st->xfer[0].rx_buf = &st->data[0];
	283	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
	284	st->xfer[0].len = 2;
	285
	286	spi_message_init(&st->msg[AD7887_CH0]);
	287	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
	288
	289	if (pdata && pdata->en_dual) {
fce7c3ea	290	st->tx_cmd_buf[2] = AD7887_CH_AIN1 \| mode;
2b4756aa MH	291
	292	st->xfer[1].rx_buf = &st->data[0];
	293	st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
	294	st->xfer[1].len = 2;
	295
	296	st->xfer[2].rx_buf = &st->data[2];
fce7c3ea	297	st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
2b4756aa MH	298	st->xfer[2].len = 2;
	299
	300	spi_message_init(&st->msg[AD7887_CH0_CH1]);
	301	spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
	302	spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
	303
fce7c3ea LPC	304	st->xfer[3].rx_buf = &st->data[2];
fce7c3ea LPC	305	st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
2b4756aa MH	306	st->xfer[3].len = 2;
	307
	308	spi_message_init(&st->msg[AD7887_CH1]);
	309	spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
	310
f39e086a MH	311	indio_dev->channels = st->chip_info->channel;
f39e086a MH	312	indio_dev->num_channels = 3;
2b4756aa	313	} else {
f39e086a MH	314	indio_dev->channels = &st->chip_info->channel[1];
f39e086a MH	315	indio_dev->num_channels = 2;
596d0609	316	}
2b4756aa	317
65dd3d3d LPC	318	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
65dd3d3d LPC	319	&ad7887_trigger_handler, &ad7887_ring_setup_ops);
2b4756aa	320	if (ret)
f39e086a	321	goto error_disable_reg;
2b4756aa	322
26d25ae3 JC	323	ret = iio_device_register(indio_dev);
	324	if (ret)
	325	goto error_unregister_ring;
	326
	327	return 0;
	328	error_unregister_ring:
65dd3d3d	329	iio_triggered_buffer_cleanup(indio_dev);
2b4756aa	330	error_disable_reg:
bf5d2613	331	if (st->reg)
2b4756aa	332	regulator_disable(st->reg);
f39e086a	333
2b4756aa MH	334	return ret;
	335	}
	336
fc52692c	337	static int ad7887_remove(struct spi_device *spi)
2b4756aa	338	{
f39e086a MH	339	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	340	struct ad7887_state *st = iio_priv(indio_dev);
	341
d2fffd6c	342	iio_device_unregister(indio_dev);
65dd3d3d	343	iio_triggered_buffer_cleanup(indio_dev);
82429e0d	344	if (st->reg)
2b4756aa	345	regulator_disable(st->reg);
f39e086a	346
2b4756aa MH	347	return 0;
	348	}
	349
	350	static const struct spi_device_id ad7887_id[] = {
	351	{"ad7887", ID_AD7887},
	352	{}
	353	};
55e4390c	354	MODULE_DEVICE_TABLE(spi, ad7887_id);
2b4756aa MH	355
	356	static struct spi_driver ad7887_driver = {
	357	.driver = {
	358	.name = "ad7887",
2b4756aa MH	359	},
2b4756aa MH	360	.probe = ad7887_probe,
fc52692c	361	.remove = ad7887_remove,
2b4756aa MH	362	.id_table = ad7887_id,
2b4756aa MH	363	};
ae6ae6fe	364	module_spi_driver(ad7887_driver);
2b4756aa MH	365
	366	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
	367	MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
	368	MODULE_LICENSE("GPL v2");