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0e589d5f MR |
1 | /* |
2 | * Driver for the ADC present in the Atmel AT91 evaluation boards. | |
3 | * | |
4 | * Copyright 2011 Free Electrons | |
5 | * | |
6 | * Licensed under the GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/bitmap.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
e364185f MR |
18 | #include <linux/of.h> |
19 | #include <linux/of_device.h> | |
0e589d5f MR |
20 | #include <linux/platform_device.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/wait.h> | |
24 | ||
25 | #include <linux/platform_data/at91_adc.h> | |
26 | ||
27 | #include <linux/iio/iio.h> | |
28 | #include <linux/iio/buffer.h> | |
0e589d5f MR |
29 | #include <linux/iio/trigger.h> |
30 | #include <linux/iio/trigger_consumer.h> | |
90032e4e | 31 | #include <linux/iio/triggered_buffer.h> |
0e589d5f MR |
32 | |
33 | #include <mach/at91_adc.h> | |
34 | ||
35 | #define AT91_ADC_CHAN(st, ch) \ | |
36 | (st->registers->channel_base + (ch * 4)) | |
37 | #define at91_adc_readl(st, reg) \ | |
38 | (readl_relaxed(st->reg_base + reg)) | |
39 | #define at91_adc_writel(st, reg, val) \ | |
40 | (writel_relaxed(val, st->reg_base + reg)) | |
41 | ||
42 | struct at91_adc_state { | |
43 | struct clk *adc_clk; | |
44 | u16 *buffer; | |
45 | unsigned long channels_mask; | |
46 | struct clk *clk; | |
47 | bool done; | |
48 | int irq; | |
49 | bool irq_enabled; | |
50 | u16 last_value; | |
51 | struct mutex lock; | |
52 | u8 num_channels; | |
53 | void __iomem *reg_base; | |
54 | struct at91_adc_reg_desc *registers; | |
55 | u8 startup_time; | |
56 | struct iio_trigger **trig; | |
57 | struct at91_adc_trigger *trigger_list; | |
58 | u32 trigger_number; | |
59 | bool use_external; | |
60 | u32 vref_mv; | |
61 | wait_queue_head_t wq_data_avail; | |
62 | }; | |
63 | ||
64 | static irqreturn_t at91_adc_trigger_handler(int irq, void *p) | |
65 | { | |
66 | struct iio_poll_func *pf = p; | |
67 | struct iio_dev *idev = pf->indio_dev; | |
68 | struct at91_adc_state *st = iio_priv(idev); | |
69 | struct iio_buffer *buffer = idev->buffer; | |
70 | int i, j = 0; | |
71 | ||
72 | for (i = 0; i < idev->masklength; i++) { | |
73 | if (!test_bit(i, idev->active_scan_mask)) | |
74 | continue; | |
75 | st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i)); | |
76 | j++; | |
77 | } | |
78 | ||
79 | if (idev->scan_timestamp) { | |
80 | s64 *timestamp = (s64 *)((u8 *)st->buffer + | |
81 | ALIGN(j, sizeof(s64))); | |
82 | *timestamp = pf->timestamp; | |
83 | } | |
84 | ||
85 | buffer->access->store_to(buffer, (u8 *)st->buffer, pf->timestamp); | |
86 | ||
87 | iio_trigger_notify_done(idev->trig); | |
88 | st->irq_enabled = true; | |
89 | ||
90 | /* Needed to ACK the DRDY interruption */ | |
91 | at91_adc_readl(st, AT91_ADC_LCDR); | |
92 | ||
93 | enable_irq(st->irq); | |
94 | ||
95 | return IRQ_HANDLED; | |
96 | } | |
97 | ||
98 | static irqreturn_t at91_adc_eoc_trigger(int irq, void *private) | |
99 | { | |
100 | struct iio_dev *idev = private; | |
101 | struct at91_adc_state *st = iio_priv(idev); | |
102 | u32 status = at91_adc_readl(st, st->registers->status_register); | |
103 | ||
104 | if (!(status & st->registers->drdy_mask)) | |
105 | return IRQ_HANDLED; | |
106 | ||
107 | if (iio_buffer_enabled(idev)) { | |
108 | disable_irq_nosync(irq); | |
109 | st->irq_enabled = false; | |
110 | iio_trigger_poll(idev->trig, iio_get_time_ns()); | |
111 | } else { | |
112 | st->last_value = at91_adc_readl(st, AT91_ADC_LCDR); | |
113 | st->done = true; | |
114 | wake_up_interruptible(&st->wq_data_avail); | |
115 | } | |
116 | ||
117 | return IRQ_HANDLED; | |
118 | } | |
119 | ||
120 | static int at91_adc_channel_init(struct iio_dev *idev) | |
121 | { | |
122 | struct at91_adc_state *st = iio_priv(idev); | |
123 | struct iio_chan_spec *chan_array, *timestamp; | |
124 | int bit, idx = 0; | |
125 | ||
126 | idev->num_channels = bitmap_weight(&st->channels_mask, | |
127 | st->num_channels) + 1; | |
128 | ||
129 | chan_array = devm_kzalloc(&idev->dev, | |
130 | ((idev->num_channels + 1) * | |
131 | sizeof(struct iio_chan_spec)), | |
132 | GFP_KERNEL); | |
133 | ||
134 | if (!chan_array) | |
135 | return -ENOMEM; | |
136 | ||
137 | for_each_set_bit(bit, &st->channels_mask, st->num_channels) { | |
138 | struct iio_chan_spec *chan = chan_array + idx; | |
139 | ||
140 | chan->type = IIO_VOLTAGE; | |
141 | chan->indexed = 1; | |
142 | chan->channel = bit; | |
143 | chan->scan_index = idx; | |
144 | chan->scan_type.sign = 'u'; | |
145 | chan->scan_type.realbits = 10; | |
146 | chan->scan_type.storagebits = 16; | |
147 | chan->info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT | | |
148 | IIO_CHAN_INFO_RAW_SEPARATE_BIT; | |
149 | idx++; | |
150 | } | |
151 | timestamp = chan_array + idx; | |
152 | ||
153 | timestamp->type = IIO_TIMESTAMP; | |
154 | timestamp->channel = -1; | |
155 | timestamp->scan_index = idx; | |
156 | timestamp->scan_type.sign = 's'; | |
157 | timestamp->scan_type.realbits = 64; | |
158 | timestamp->scan_type.storagebits = 64; | |
159 | ||
160 | idev->channels = chan_array; | |
161 | return idev->num_channels; | |
162 | } | |
163 | ||
164 | static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev, | |
165 | struct at91_adc_trigger *triggers, | |
166 | const char *trigger_name) | |
167 | { | |
168 | struct at91_adc_state *st = iio_priv(idev); | |
169 | u8 value = 0; | |
170 | int i; | |
171 | ||
172 | for (i = 0; i < st->trigger_number; i++) { | |
173 | char *name = kasprintf(GFP_KERNEL, | |
174 | "%s-dev%d-%s", | |
175 | idev->name, | |
176 | idev->id, | |
177 | triggers[i].name); | |
178 | if (!name) | |
179 | return -ENOMEM; | |
180 | ||
181 | if (strcmp(trigger_name, name) == 0) { | |
182 | value = triggers[i].value; | |
183 | kfree(name); | |
184 | break; | |
185 | } | |
186 | ||
187 | kfree(name); | |
188 | } | |
189 | ||
190 | return value; | |
191 | } | |
192 | ||
193 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | |
194 | { | |
195 | struct iio_dev *idev = trig->private_data; | |
196 | struct at91_adc_state *st = iio_priv(idev); | |
197 | struct iio_buffer *buffer = idev->buffer; | |
198 | struct at91_adc_reg_desc *reg = st->registers; | |
199 | u32 status = at91_adc_readl(st, reg->trigger_register); | |
200 | u8 value; | |
201 | u8 bit; | |
202 | ||
203 | value = at91_adc_get_trigger_value_by_name(idev, | |
204 | st->trigger_list, | |
205 | idev->trig->name); | |
206 | if (value == 0) | |
207 | return -EINVAL; | |
208 | ||
209 | if (state) { | |
210 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); | |
211 | if (st->buffer == NULL) | |
212 | return -ENOMEM; | |
213 | ||
214 | at91_adc_writel(st, reg->trigger_register, | |
215 | status | value); | |
216 | ||
217 | for_each_set_bit(bit, buffer->scan_mask, | |
218 | st->num_channels) { | |
219 | struct iio_chan_spec const *chan = idev->channels + bit; | |
220 | at91_adc_writel(st, AT91_ADC_CHER, | |
221 | AT91_ADC_CH(chan->channel)); | |
222 | } | |
223 | ||
224 | at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); | |
225 | ||
226 | } else { | |
227 | at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); | |
228 | ||
229 | at91_adc_writel(st, reg->trigger_register, | |
230 | status & ~value); | |
231 | ||
232 | for_each_set_bit(bit, buffer->scan_mask, | |
233 | st->num_channels) { | |
234 | struct iio_chan_spec const *chan = idev->channels + bit; | |
235 | at91_adc_writel(st, AT91_ADC_CHDR, | |
236 | AT91_ADC_CH(chan->channel)); | |
237 | } | |
238 | kfree(st->buffer); | |
239 | } | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | |
245 | .owner = THIS_MODULE, | |
246 | .set_trigger_state = &at91_adc_configure_trigger, | |
247 | }; | |
248 | ||
249 | static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, | |
250 | struct at91_adc_trigger *trigger) | |
251 | { | |
252 | struct iio_trigger *trig; | |
253 | int ret; | |
254 | ||
255 | trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, | |
256 | idev->id, trigger->name); | |
257 | if (trig == NULL) | |
258 | return NULL; | |
259 | ||
260 | trig->dev.parent = idev->dev.parent; | |
261 | trig->private_data = idev; | |
262 | trig->ops = &at91_adc_trigger_ops; | |
263 | ||
264 | ret = iio_trigger_register(trig); | |
265 | if (ret) | |
266 | return NULL; | |
267 | ||
268 | return trig; | |
269 | } | |
270 | ||
271 | static int at91_adc_trigger_init(struct iio_dev *idev) | |
272 | { | |
273 | struct at91_adc_state *st = iio_priv(idev); | |
274 | int i, ret; | |
275 | ||
276 | st->trig = devm_kzalloc(&idev->dev, | |
277 | st->trigger_number * sizeof(st->trig), | |
278 | GFP_KERNEL); | |
279 | ||
280 | if (st->trig == NULL) { | |
281 | ret = -ENOMEM; | |
282 | goto error_ret; | |
283 | } | |
284 | ||
285 | for (i = 0; i < st->trigger_number; i++) { | |
286 | if (st->trigger_list[i].is_external && !(st->use_external)) | |
287 | continue; | |
288 | ||
289 | st->trig[i] = at91_adc_allocate_trigger(idev, | |
290 | st->trigger_list + i); | |
291 | if (st->trig[i] == NULL) { | |
292 | dev_err(&idev->dev, | |
293 | "Could not allocate trigger %d\n", i); | |
294 | ret = -ENOMEM; | |
295 | goto error_trigger; | |
296 | } | |
297 | } | |
298 | ||
299 | return 0; | |
300 | ||
301 | error_trigger: | |
302 | for (i--; i >= 0; i--) { | |
303 | iio_trigger_unregister(st->trig[i]); | |
304 | iio_trigger_free(st->trig[i]); | |
305 | } | |
306 | error_ret: | |
307 | return ret; | |
308 | } | |
309 | ||
310 | static void at91_adc_trigger_remove(struct iio_dev *idev) | |
311 | { | |
312 | struct at91_adc_state *st = iio_priv(idev); | |
313 | int i; | |
314 | ||
315 | for (i = 0; i < st->trigger_number; i++) { | |
316 | iio_trigger_unregister(st->trig[i]); | |
317 | iio_trigger_free(st->trig[i]); | |
318 | } | |
319 | } | |
320 | ||
0e589d5f MR |
321 | static int at91_adc_buffer_init(struct iio_dev *idev) |
322 | { | |
90032e4e LPC |
323 | return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
324 | &at91_adc_trigger_handler, NULL); | |
0e589d5f MR |
325 | } |
326 | ||
327 | static void at91_adc_buffer_remove(struct iio_dev *idev) | |
328 | { | |
90032e4e | 329 | iio_triggered_buffer_cleanup(idev); |
0e589d5f MR |
330 | } |
331 | ||
332 | static int at91_adc_read_raw(struct iio_dev *idev, | |
333 | struct iio_chan_spec const *chan, | |
334 | int *val, int *val2, long mask) | |
335 | { | |
336 | struct at91_adc_state *st = iio_priv(idev); | |
337 | int ret; | |
338 | ||
339 | switch (mask) { | |
340 | case IIO_CHAN_INFO_RAW: | |
341 | mutex_lock(&st->lock); | |
342 | ||
343 | at91_adc_writel(st, AT91_ADC_CHER, | |
344 | AT91_ADC_CH(chan->channel)); | |
345 | at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask); | |
346 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); | |
347 | ||
348 | ret = wait_event_interruptible_timeout(st->wq_data_avail, | |
349 | st->done, | |
350 | msecs_to_jiffies(1000)); | |
351 | if (ret == 0) | |
90e6dc7c LPC |
352 | ret = -ETIMEDOUT; |
353 | if (ret < 0) { | |
354 | mutex_unlock(&st->lock); | |
0e589d5f | 355 | return ret; |
90e6dc7c | 356 | } |
0e589d5f MR |
357 | |
358 | *val = st->last_value; | |
359 | ||
360 | at91_adc_writel(st, AT91_ADC_CHDR, | |
361 | AT91_ADC_CH(chan->channel)); | |
362 | at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask); | |
363 | ||
364 | st->last_value = 0; | |
365 | st->done = false; | |
366 | mutex_unlock(&st->lock); | |
367 | return IIO_VAL_INT; | |
368 | ||
369 | case IIO_CHAN_INFO_SCALE: | |
370 | *val = (st->vref_mv * 1000) >> chan->scan_type.realbits; | |
371 | *val2 = 0; | |
372 | return IIO_VAL_INT_PLUS_MICRO; | |
373 | default: | |
374 | break; | |
375 | } | |
376 | return -EINVAL; | |
377 | } | |
378 | ||
e364185f MR |
379 | static int at91_adc_probe_dt(struct at91_adc_state *st, |
380 | struct platform_device *pdev) | |
381 | { | |
382 | struct iio_dev *idev = iio_priv_to_dev(st); | |
383 | struct device_node *node = pdev->dev.of_node; | |
384 | struct device_node *trig_node; | |
385 | int i = 0, ret; | |
386 | u32 prop; | |
387 | ||
388 | if (!node) | |
389 | return -EINVAL; | |
390 | ||
391 | st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); | |
392 | ||
393 | if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { | |
394 | dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); | |
395 | ret = -EINVAL; | |
396 | goto error_ret; | |
397 | } | |
398 | st->channels_mask = prop; | |
399 | ||
400 | if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) { | |
401 | dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n"); | |
402 | ret = -EINVAL; | |
403 | goto error_ret; | |
404 | } | |
405 | st->num_channels = prop; | |
406 | ||
407 | if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { | |
408 | dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); | |
409 | ret = -EINVAL; | |
410 | goto error_ret; | |
411 | } | |
412 | st->startup_time = prop; | |
413 | ||
414 | ||
415 | if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { | |
416 | dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); | |
417 | ret = -EINVAL; | |
418 | goto error_ret; | |
419 | } | |
420 | st->vref_mv = prop; | |
421 | ||
422 | st->registers = devm_kzalloc(&idev->dev, | |
423 | sizeof(struct at91_adc_reg_desc), | |
424 | GFP_KERNEL); | |
425 | if (!st->registers) { | |
426 | dev_err(&idev->dev, "Could not allocate register memory.\n"); | |
427 | ret = -ENOMEM; | |
428 | goto error_ret; | |
429 | } | |
430 | ||
431 | if (of_property_read_u32(node, "atmel,adc-channel-base", &prop)) { | |
432 | dev_err(&idev->dev, "Missing adc-channel-base property in the DT.\n"); | |
433 | ret = -EINVAL; | |
434 | goto error_ret; | |
435 | } | |
436 | st->registers->channel_base = prop; | |
437 | ||
438 | if (of_property_read_u32(node, "atmel,adc-drdy-mask", &prop)) { | |
439 | dev_err(&idev->dev, "Missing adc-drdy-mask property in the DT.\n"); | |
440 | ret = -EINVAL; | |
441 | goto error_ret; | |
442 | } | |
443 | st->registers->drdy_mask = prop; | |
444 | ||
445 | if (of_property_read_u32(node, "atmel,adc-status-register", &prop)) { | |
446 | dev_err(&idev->dev, "Missing adc-status-register property in the DT.\n"); | |
447 | ret = -EINVAL; | |
448 | goto error_ret; | |
449 | } | |
450 | st->registers->status_register = prop; | |
451 | ||
452 | if (of_property_read_u32(node, "atmel,adc-trigger-register", &prop)) { | |
453 | dev_err(&idev->dev, "Missing adc-trigger-register property in the DT.\n"); | |
454 | ret = -EINVAL; | |
455 | goto error_ret; | |
456 | } | |
457 | st->registers->trigger_register = prop; | |
458 | ||
459 | st->trigger_number = of_get_child_count(node); | |
460 | st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number * | |
461 | sizeof(struct at91_adc_trigger), | |
462 | GFP_KERNEL); | |
463 | if (!st->trigger_list) { | |
464 | dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); | |
465 | ret = -ENOMEM; | |
466 | goto error_ret; | |
467 | } | |
468 | ||
469 | for_each_child_of_node(node, trig_node) { | |
470 | struct at91_adc_trigger *trig = st->trigger_list + i; | |
471 | const char *name; | |
472 | ||
473 | if (of_property_read_string(trig_node, "trigger-name", &name)) { | |
474 | dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); | |
475 | ret = -EINVAL; | |
476 | goto error_ret; | |
477 | } | |
478 | trig->name = name; | |
479 | ||
480 | if (of_property_read_u32(trig_node, "trigger-value", &prop)) { | |
481 | dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); | |
482 | ret = -EINVAL; | |
483 | goto error_ret; | |
484 | } | |
485 | trig->value = prop; | |
486 | trig->is_external = of_property_read_bool(trig_node, "trigger-external"); | |
487 | i++; | |
488 | } | |
489 | ||
490 | return 0; | |
491 | ||
492 | error_ret: | |
493 | return ret; | |
494 | } | |
495 | ||
0e589d5f MR |
496 | static int at91_adc_probe_pdata(struct at91_adc_state *st, |
497 | struct platform_device *pdev) | |
498 | { | |
499 | struct at91_adc_data *pdata = pdev->dev.platform_data; | |
500 | ||
501 | if (!pdata) | |
502 | return -EINVAL; | |
503 | ||
504 | st->use_external = pdata->use_external_triggers; | |
505 | st->vref_mv = pdata->vref; | |
506 | st->channels_mask = pdata->channels_used; | |
507 | st->num_channels = pdata->num_channels; | |
508 | st->startup_time = pdata->startup_time; | |
509 | st->trigger_number = pdata->trigger_number; | |
510 | st->trigger_list = pdata->trigger_list; | |
511 | st->registers = pdata->registers; | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | static const struct iio_info at91_adc_info = { | |
517 | .driver_module = THIS_MODULE, | |
518 | .read_raw = &at91_adc_read_raw, | |
519 | }; | |
520 | ||
521 | static int __devinit at91_adc_probe(struct platform_device *pdev) | |
522 | { | |
523 | unsigned int prsc, mstrclk, ticks, adc_clk; | |
524 | int ret; | |
525 | struct iio_dev *idev; | |
526 | struct at91_adc_state *st; | |
527 | struct resource *res; | |
528 | ||
529 | idev = iio_device_alloc(sizeof(struct at91_adc_state)); | |
530 | if (idev == NULL) { | |
531 | ret = -ENOMEM; | |
532 | goto error_ret; | |
533 | } | |
534 | ||
535 | st = iio_priv(idev); | |
536 | ||
e364185f MR |
537 | if (pdev->dev.of_node) |
538 | ret = at91_adc_probe_dt(st, pdev); | |
539 | else | |
540 | ret = at91_adc_probe_pdata(st, pdev); | |
541 | ||
0e589d5f MR |
542 | if (ret) { |
543 | dev_err(&pdev->dev, "No platform data available.\n"); | |
544 | ret = -EINVAL; | |
545 | goto error_free_device; | |
546 | } | |
547 | ||
0e589d5f MR |
548 | platform_set_drvdata(pdev, idev); |
549 | ||
550 | idev->dev.parent = &pdev->dev; | |
551 | idev->name = dev_name(&pdev->dev); | |
552 | idev->modes = INDIO_DIRECT_MODE; | |
553 | idev->info = &at91_adc_info; | |
554 | ||
555 | st->irq = platform_get_irq(pdev, 0); | |
556 | if (st->irq < 0) { | |
557 | dev_err(&pdev->dev, "No IRQ ID is designated\n"); | |
558 | ret = -ENODEV; | |
559 | goto error_free_device; | |
560 | } | |
561 | ||
390d75c1 | 562 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
0e589d5f | 563 | |
390d75c1 | 564 | st->reg_base = devm_request_and_ioremap(&pdev->dev, res); |
0e589d5f | 565 | if (!st->reg_base) { |
0e589d5f | 566 | ret = -ENOMEM; |
390d75c1 | 567 | goto error_free_device; |
0e589d5f MR |
568 | } |
569 | ||
570 | /* | |
571 | * Disable all IRQs before setting up the handler | |
572 | */ | |
573 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); | |
574 | at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); | |
575 | ret = request_irq(st->irq, | |
576 | at91_adc_eoc_trigger, | |
577 | 0, | |
578 | pdev->dev.driver->name, | |
579 | idev); | |
580 | if (ret) { | |
581 | dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); | |
390d75c1 | 582 | goto error_free_device; |
0e589d5f MR |
583 | } |
584 | ||
390d75c1 | 585 | st->clk = devm_clk_get(&pdev->dev, "adc_clk"); |
0e589d5f MR |
586 | if (IS_ERR(st->clk)) { |
587 | dev_err(&pdev->dev, "Failed to get the clock.\n"); | |
588 | ret = PTR_ERR(st->clk); | |
589 | goto error_free_irq; | |
590 | } | |
591 | ||
592 | ret = clk_prepare(st->clk); | |
593 | if (ret) { | |
594 | dev_err(&pdev->dev, "Could not prepare the clock.\n"); | |
390d75c1 | 595 | goto error_free_irq; |
0e589d5f MR |
596 | } |
597 | ||
598 | ret = clk_enable(st->clk); | |
599 | if (ret) { | |
600 | dev_err(&pdev->dev, "Could not enable the clock.\n"); | |
601 | goto error_unprepare_clk; | |
602 | } | |
603 | ||
390d75c1 | 604 | st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); |
0e589d5f MR |
605 | if (IS_ERR(st->adc_clk)) { |
606 | dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); | |
607 | ret = PTR_ERR(st->clk); | |
608 | goto error_disable_clk; | |
609 | } | |
610 | ||
611 | ret = clk_prepare(st->adc_clk); | |
612 | if (ret) { | |
613 | dev_err(&pdev->dev, "Could not prepare the ADC clock.\n"); | |
390d75c1 | 614 | goto error_disable_clk; |
0e589d5f MR |
615 | } |
616 | ||
617 | ret = clk_enable(st->adc_clk); | |
618 | if (ret) { | |
619 | dev_err(&pdev->dev, "Could not enable the ADC clock.\n"); | |
620 | goto error_unprepare_adc_clk; | |
621 | } | |
622 | ||
623 | /* | |
624 | * Prescaler rate computation using the formula from the Atmel's | |
625 | * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being | |
626 | * specified by the electrical characteristics of the board. | |
627 | */ | |
628 | mstrclk = clk_get_rate(st->clk); | |
629 | adc_clk = clk_get_rate(st->adc_clk); | |
630 | prsc = (mstrclk / (2 * adc_clk)) - 1; | |
631 | ||
632 | if (!st->startup_time) { | |
633 | dev_err(&pdev->dev, "No startup time available.\n"); | |
634 | ret = -EINVAL; | |
635 | goto error_disable_adc_clk; | |
636 | } | |
637 | ||
638 | /* | |
639 | * Number of ticks needed to cover the startup time of the ADC as | |
640 | * defined in the electrical characteristics of the board, divided by 8. | |
641 | * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock | |
642 | */ | |
643 | ticks = round_up((st->startup_time * adc_clk / | |
644 | 1000000) - 1, 8) / 8; | |
645 | at91_adc_writel(st, AT91_ADC_MR, | |
646 | (AT91_ADC_PRESCAL_(prsc) & AT91_ADC_PRESCAL) | | |
647 | (AT91_ADC_STARTUP_(ticks) & AT91_ADC_STARTUP)); | |
648 | ||
649 | /* Setup the ADC channels available on the board */ | |
650 | ret = at91_adc_channel_init(idev); | |
651 | if (ret < 0) { | |
652 | dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); | |
653 | goto error_disable_adc_clk; | |
654 | } | |
655 | ||
656 | init_waitqueue_head(&st->wq_data_avail); | |
657 | mutex_init(&st->lock); | |
658 | ||
659 | ret = at91_adc_buffer_init(idev); | |
660 | if (ret < 0) { | |
661 | dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); | |
662 | goto error_disable_adc_clk; | |
663 | } | |
664 | ||
665 | ret = at91_adc_trigger_init(idev); | |
666 | if (ret < 0) { | |
667 | dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); | |
668 | goto error_unregister_buffer; | |
669 | } | |
670 | ||
671 | ret = iio_device_register(idev); | |
672 | if (ret < 0) { | |
673 | dev_err(&pdev->dev, "Couldn't register the device.\n"); | |
674 | goto error_remove_triggers; | |
675 | } | |
676 | ||
677 | return 0; | |
678 | ||
679 | error_remove_triggers: | |
680 | at91_adc_trigger_remove(idev); | |
681 | error_unregister_buffer: | |
682 | at91_adc_buffer_remove(idev); | |
683 | error_disable_adc_clk: | |
684 | clk_disable(st->adc_clk); | |
685 | error_unprepare_adc_clk: | |
686 | clk_unprepare(st->adc_clk); | |
0e589d5f MR |
687 | error_disable_clk: |
688 | clk_disable(st->clk); | |
689 | error_unprepare_clk: | |
690 | clk_unprepare(st->clk); | |
0e589d5f MR |
691 | error_free_irq: |
692 | free_irq(st->irq, idev); | |
0e589d5f MR |
693 | error_free_device: |
694 | iio_device_free(idev); | |
695 | error_ret: | |
696 | return ret; | |
697 | } | |
698 | ||
699 | static int __devexit at91_adc_remove(struct platform_device *pdev) | |
700 | { | |
701 | struct iio_dev *idev = platform_get_drvdata(pdev); | |
0e589d5f MR |
702 | struct at91_adc_state *st = iio_priv(idev); |
703 | ||
704 | iio_device_unregister(idev); | |
705 | at91_adc_trigger_remove(idev); | |
706 | at91_adc_buffer_remove(idev); | |
707 | clk_disable_unprepare(st->adc_clk); | |
0e589d5f MR |
708 | clk_disable(st->clk); |
709 | clk_unprepare(st->clk); | |
0e589d5f | 710 | free_irq(st->irq, idev); |
0e589d5f MR |
711 | iio_device_free(idev); |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
e364185f MR |
716 | static const struct of_device_id at91_adc_dt_ids[] = { |
717 | { .compatible = "atmel,at91sam9260-adc" }, | |
718 | {}, | |
719 | }; | |
720 | MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); | |
721 | ||
0e589d5f MR |
722 | static struct platform_driver at91_adc_driver = { |
723 | .probe = at91_adc_probe, | |
724 | .remove = __devexit_p(at91_adc_remove), | |
725 | .driver = { | |
726 | .name = "at91_adc", | |
e364185f | 727 | .of_match_table = of_match_ptr(at91_adc_dt_ids), |
0e589d5f MR |
728 | }, |
729 | }; | |
730 | ||
731 | module_platform_driver(at91_adc_driver); | |
732 | ||
733 | MODULE_LICENSE("GPL"); | |
734 | MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); | |
735 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |