[deliverable/linux.git] / drivers / iio / adc / exynos_adc.c

/*
 *  exynos_adc.c - Support for ADC in EXYNOS SoCs
 *
 *  8 ~ 10 channel, 10/12-bit ADC
 *
 *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/regulator/consumer.h>
#include <linux/of_platform.h>
#include <linux/err.h>

#include <linux/iio/iio.h>
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>

enum adc_version {
	ADC_V1,
	ADC_V2
};

/* EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x)		((x) + 0x00)
#define ADC_V1_DLY(x)		((x) + 0x08)
#define ADC_V1_DATX(x)		((x) + 0x0C)
#define ADC_V1_INTCLR(x)	((x) + 0x18)
#define ADC_V1_MUX(x)		((x) + 0x1c)

/* Future ADC_V2 registers definitions */
#define ADC_V2_CON1(x)		((x) + 0x00)
#define ADC_V2_CON2(x)		((x) + 0x04)
#define ADC_V2_STAT(x)		((x) + 0x08)
#define ADC_V2_INT_EN(x)	((x) + 0x10)
#define ADC_V2_INT_ST(x)	((x) + 0x14)
#define ADC_V2_VER(x)		((x) + 0x20)

/* Bit definitions for ADC_V1 */
#define ADC_V1_CON_RES		(1u << 16)
#define ADC_V1_CON_PRSCEN	(1u << 14)
#define ADC_V1_CON_PRSCLV(x)	(((x) & 0xFF) << 6)
#define ADC_V1_CON_STANDBY	(1u << 2)

/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET	(1u << 2)

#define ADC_V2_CON2_OSEL	(1u << 10)
#define ADC_V2_CON2_ESEL	(1u << 9)
#define ADC_V2_CON2_HIGHF	(1u << 8)
#define ADC_V2_CON2_C_TIME(x)	(((x) & 7) << 4)
#define ADC_V2_CON2_ACH_SEL(x)	(((x) & 0xF) << 0)
#define ADC_V2_CON2_ACH_MASK	0xF

#define MAX_ADC_V2_CHANNELS	10
#define MAX_ADC_V1_CHANNELS	8

/* Bit definitions common for ADC_V1 and ADC_V2 */
#define ADC_CON_EN_START	(1u << 0)
#define ADC_DATX_MASK		0xFFF

#define EXYNOS_ADC_TIMEOUT	(msecs_to_jiffies(1000))

struct exynos_adc {
	void __iomem		*regs;
	void __iomem		*enable_reg;
	struct clk		*clk;
	unsigned int		irq;
	struct regulator	*vdd;

	struct completion	completion;

	u32			value;
	unsigned int            version;
};

static const struct of_device_id exynos_adc_match[] = {
	{ .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 },
	{ .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 },
	{},
};
MODULE_DEVICE_TABLE(of, exynos_adc_match);

static inline unsigned int exynos_adc_get_version(struct platform_device *pdev)
{
	const struct of_device_id *match;

	match = of_match_node(exynos_adc_match, pdev->dev.of_node);
	return (unsigned int)match->data;
}

static int exynos_read_raw(struct iio_dev *indio_dev,
				struct iio_chan_spec const *chan,
				int *val,
				int *val2,
				long mask)
{
	struct exynos_adc *info = iio_priv(indio_dev);
	unsigned long timeout;
	u32 con1, con2;

	if (mask != IIO_CHAN_INFO_RAW)
		return -EINVAL;

	mutex_lock(&indio_dev->mlock);

	/* Select the channel to be used and Trigger conversion */
	if (info->version == ADC_V2) {
		con2 = readl(ADC_V2_CON2(info->regs));
		con2 &= ~ADC_V2_CON2_ACH_MASK;
		con2 |= ADC_V2_CON2_ACH_SEL(chan->address);
		writel(con2, ADC_V2_CON2(info->regs));

		con1 = readl(ADC_V2_CON1(info->regs));
		writel(con1 | ADC_CON_EN_START,
				ADC_V2_CON1(info->regs));
	} else {
		writel(chan->address, ADC_V1_MUX(info->regs));

		con1 = readl(ADC_V1_CON(info->regs));
		writel(con1 | ADC_CON_EN_START,
				ADC_V1_CON(info->regs));
	}

	timeout = wait_for_completion_interruptible_timeout
			(&info->completion, EXYNOS_ADC_TIMEOUT);
	*val = info->value;

	mutex_unlock(&indio_dev->mlock);

	if (timeout == 0)
		return -ETIMEDOUT;

	return IIO_VAL_INT;
}

static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
{
	struct exynos_adc *info = (struct exynos_adc *)dev_id;

	/* Read value */
	info->value = readl(ADC_V1_DATX(info->regs)) &
						ADC_DATX_MASK;
	/* clear irq */
	if (info->version == ADC_V2)
		writel(1, ADC_V2_INT_ST(info->regs));
	else
		writel(1, ADC_V1_INTCLR(info->regs));

	complete(&info->completion);

	return IRQ_HANDLED;
}

static int exynos_adc_reg_access(struct iio_dev *indio_dev,
			      unsigned reg, unsigned writeval,
			      unsigned *readval)
{
	struct exynos_adc *info = iio_priv(indio_dev);

	if (readval == NULL)
		return -EINVAL;

	*readval = readl(info->regs + reg);

	return 0;
}

static const struct iio_info exynos_adc_iio_info = {
	.read_raw = &exynos_read_raw,
	.debugfs_reg_access = &exynos_adc_reg_access,
	.driver_module = THIS_MODULE,
};

#define ADC_CHANNEL(_index, _id) {			\
	.type = IIO_VOLTAGE,				\
	.indexed = 1,					\
	.channel = _index,				\
	.address = _index,				\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
	.datasheet_name = _id,				\
}

static const struct iio_chan_spec exynos_adc_iio_channels[] = {
	ADC_CHANNEL(0, "adc0"),
	ADC_CHANNEL(1, "adc1"),
	ADC_CHANNEL(2, "adc2"),
	ADC_CHANNEL(3, "adc3"),
	ADC_CHANNEL(4, "adc4"),
	ADC_CHANNEL(5, "adc5"),
	ADC_CHANNEL(6, "adc6"),
	ADC_CHANNEL(7, "adc7"),
	ADC_CHANNEL(8, "adc8"),
	ADC_CHANNEL(9, "adc9"),
};

static int exynos_adc_remove_devices(struct device *dev, void *c)
{
	struct platform_device *pdev = to_platform_device(dev);

	platform_device_unregister(pdev);

	return 0;
}

static void exynos_adc_hw_init(struct exynos_adc *info)
{
	u32 con1, con2;

	if (info->version == ADC_V2) {
		con1 = ADC_V2_CON1_SOFT_RESET;
		writel(con1, ADC_V2_CON1(info->regs));

		con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
			ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
		writel(con2, ADC_V2_CON2(info->regs));

		/* Enable interrupts */
		writel(1, ADC_V2_INT_EN(info->regs));
	} else {
		/* set default prescaler values and Enable prescaler */
		con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;

		/* Enable 12-bit ADC resolution */
		con1 |= ADC_V1_CON_RES;
		writel(con1, ADC_V1_CON(info->regs));
	}
}

static int exynos_adc_probe(struct platform_device *pdev)
{
	struct exynos_adc *info = NULL;
	struct device_node *np = pdev->dev.of_node;
	struct iio_dev *indio_dev = NULL;
	struct resource	*mem;
	int ret = -ENODEV;
	int irq;

	if (!np)
		return ret;

	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
	if (!indio_dev) {
		dev_err(&pdev->dev, "failed allocating iio device\n");
		return -ENOMEM;
	}

	info = iio_priv(indio_dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	info->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(info->regs))
		return PTR_ERR(info->regs);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(info->enable_reg))
		return PTR_ERR(info->enable_reg);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return irq;
	}

	info->irq = irq;

	init_completion(&info->completion);

	ret = request_irq(info->irq, exynos_adc_isr,
					0, dev_name(&pdev->dev), info);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
							info->irq);
		return ret;
	}

	writel(1, info->enable_reg);

	info->clk = devm_clk_get(&pdev->dev, "adc");
	if (IS_ERR(info->clk)) {
		dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
							PTR_ERR(info->clk));
		ret = PTR_ERR(info->clk);
		goto err_irq;
	}

	info->vdd = devm_regulator_get(&pdev->dev, "vdd");
	if (IS_ERR(info->vdd)) {
		dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
							PTR_ERR(info->vdd));
		ret = PTR_ERR(info->vdd);
		goto err_irq;
	}

	info->version = exynos_adc_get_version(pdev);

	platform_set_drvdata(pdev, indio_dev);

	indio_dev->name = dev_name(&pdev->dev);
	indio_dev->dev.parent = &pdev->dev;
	indio_dev->dev.of_node = pdev->dev.of_node;
	indio_dev->info = &exynos_adc_iio_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = exynos_adc_iio_channels;

	if (info->version == ADC_V1)
		indio_dev->num_channels = MAX_ADC_V1_CHANNELS;
	else
		indio_dev->num_channels = MAX_ADC_V2_CHANNELS;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto err_irq;

	ret = regulator_enable(info->vdd);
	if (ret)
		goto err_iio_dev;

	clk_prepare_enable(info->clk);

	exynos_adc_hw_init(info);

	ret = of_platform_populate(np, exynos_adc_match, NULL, &pdev->dev);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed adding child nodes\n");
		goto err_of_populate;
	}

	return 0;

err_of_populate:
	device_for_each_child(&pdev->dev, NULL,
				exynos_adc_remove_devices);
	regulator_disable(info->vdd);
	clk_disable_unprepare(info->clk);
err_iio_dev:
	iio_device_unregister(indio_dev);
err_irq:
	free_irq(info->irq, info);
	return ret;
}

static int exynos_adc_remove(struct platform_device *pdev)
{
	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
	struct exynos_adc *info = iio_priv(indio_dev);

	device_for_each_child(&pdev->dev, NULL,
				exynos_adc_remove_devices);
	regulator_disable(info->vdd);
	clk_disable_unprepare(info->clk);
	writel(0, info->enable_reg);
	iio_device_unregister(indio_dev);
	free_irq(info->irq, info);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int exynos_adc_suspend(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct exynos_adc *info = iio_priv(indio_dev);
	u32 con;

	if (info->version == ADC_V2) {
		con = readl(ADC_V2_CON1(info->regs));
		con &= ~ADC_CON_EN_START;
		writel(con, ADC_V2_CON1(info->regs));
	} else {
		con = readl(ADC_V1_CON(info->regs));
		con |= ADC_V1_CON_STANDBY;
		writel(con, ADC_V1_CON(info->regs));
	}

	clk_disable_unprepare(info->clk);
	writel(0, info->enable_reg);
	regulator_disable(info->vdd);

	return 0;
}

static int exynos_adc_resume(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct exynos_adc *info = iio_priv(indio_dev);
	int ret;

	ret = regulator_enable(info->vdd);
	if (ret)
		return ret;

	writel(1, info->enable_reg);
	clk_prepare_enable(info->clk);

	exynos_adc_hw_init(info);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
			exynos_adc_suspend,
			exynos_adc_resume);

static struct platform_driver exynos_adc_driver = {
	.probe		= exynos_adc_probe,
	.remove		= exynos_adc_remove,
	.driver		= {
		.name	= "exynos-adc",
		.owner	= THIS_MODULE,
		.of_match_table = exynos_adc_match,
		.pm	= &exynos_adc_pm_ops,
	},
};

module_platform_driver(exynos_adc_driver);

MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
10f5b148 NKC	1	/*
	2	* exynos_adc.c - Support for ADC in EXYNOS SoCs
	3	*
	4	* 8 ~ 10 channel, 10/12-bit ADC
	5	*
	6	* Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/delay.h>
	27	#include <linux/kernel.h>
	28	#include <linux/slab.h>
	29	#include <linux/io.h>
	30	#include <linux/clk.h>
	31	#include <linux/completion.h>
	32	#include <linux/of.h>
	33	#include <linux/of_irq.h>
	34	#include <linux/regulator/consumer.h>
	35	#include <linux/of_platform.h>
ebeb021a	36	#include <linux/err.h>
10f5b148 NKC	37
	38	#include <linux/iio/iio.h>
	39	#include <linux/iio/machine.h>
	40	#include <linux/iio/driver.h>
	41
	42	enum adc_version {
	43	ADC_V1,
	44	ADC_V2
	45	};
	46
	47	/* EXYNOS4412/5250 ADC_V1 registers definitions */
	48	#define ADC_V1_CON(x) ((x) + 0x00)
	49	#define ADC_V1_DLY(x) ((x) + 0x08)
	50	#define ADC_V1_DATX(x) ((x) + 0x0C)
	51	#define ADC_V1_INTCLR(x) ((x) + 0x18)
	52	#define ADC_V1_MUX(x) ((x) + 0x1c)
	53
	54	/* Future ADC_V2 registers definitions */
	55	#define ADC_V2_CON1(x) ((x) + 0x00)
	56	#define ADC_V2_CON2(x) ((x) + 0x04)
	57	#define ADC_V2_STAT(x) ((x) + 0x08)
	58	#define ADC_V2_INT_EN(x) ((x) + 0x10)
	59	#define ADC_V2_INT_ST(x) ((x) + 0x14)
	60	#define ADC_V2_VER(x) ((x) + 0x20)
	61
	62	/* Bit definitions for ADC_V1 */
	63	#define ADC_V1_CON_RES (1u << 16)
	64	#define ADC_V1_CON_PRSCEN (1u << 14)
	65	#define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
	66	#define ADC_V1_CON_STANDBY (1u << 2)
	67
	68	/* Bit definitions for ADC_V2 */
	69	#define ADC_V2_CON1_SOFT_RESET (1u << 2)
	70
	71	#define ADC_V2_CON2_OSEL (1u << 10)
	72	#define ADC_V2_CON2_ESEL (1u << 9)
	73	#define ADC_V2_CON2_HIGHF (1u << 8)
	74	#define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
	75	#define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
	76	#define ADC_V2_CON2_ACH_MASK 0xF
	77
	78	#define MAX_ADC_V2_CHANNELS 10
	79	#define MAX_ADC_V1_CHANNELS 8
	80
	81	/* Bit definitions common for ADC_V1 and ADC_V2 */
	82	#define ADC_CON_EN_START (1u << 0)
	83	#define ADC_DATX_MASK 0xFFF
	84
	85	#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(1000))
	86
	87	struct exynos_adc {
	88	void __iomem *regs;
bb916ebb	89	void __iomem *enable_reg;
10f5b148 NKC	90	struct clk *clk;
	91	unsigned int irq;
	92	struct regulator *vdd;
	93
	94	struct completion completion;
	95
	96	u32 value;
	97	unsigned int version;
	98	};
	99
	100	static const struct of_device_id exynos_adc_match[] = {
	101	{ .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 },
	102	{ .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 },
	103	{},
	104	};
	105	MODULE_DEVICE_TABLE(of, exynos_adc_match);
	106
	107	static inline unsigned int exynos_adc_get_version(struct platform_device *pdev)
	108	{
	109	const struct of_device_id *match;
	110
	111	match = of_match_node(exynos_adc_match, pdev->dev.of_node);
	112	return (unsigned int)match->data;
	113	}
	114
	115	static int exynos_read_raw(struct iio_dev *indio_dev,
	116	struct iio_chan_spec const *chan,
	117	int *val,
	118	int *val2,
	119	long mask)
	120	{
	121	struct exynos_adc *info = iio_priv(indio_dev);
	122	unsigned long timeout;
	123	u32 con1, con2;
	124
	125	if (mask != IIO_CHAN_INFO_RAW)
	126	return -EINVAL;
	127
	128	mutex_lock(&indio_dev->mlock);
	129
	130	/* Select the channel to be used and Trigger conversion */
	131	if (info->version == ADC_V2) {
	132	con2 = readl(ADC_V2_CON2(info->regs));
	133	con2 &= ~ADC_V2_CON2_ACH_MASK;
	134	con2 \|= ADC_V2_CON2_ACH_SEL(chan->address);
	135	writel(con2, ADC_V2_CON2(info->regs));
	136
	137	con1 = readl(ADC_V2_CON1(info->regs));
	138	writel(con1 \| ADC_CON_EN_START,
	139	ADC_V2_CON1(info->regs));
	140	} else {
	141	writel(chan->address, ADC_V1_MUX(info->regs));
	142
	143	con1 = readl(ADC_V1_CON(info->regs));
	144	writel(con1 \| ADC_CON_EN_START,
	145	ADC_V1_CON(info->regs));
	146	}
	147
	148	timeout = wait_for_completion_interruptible_timeout
	149	(&info->completion, EXYNOS_ADC_TIMEOUT);
	150	*val = info->value;
	151
	152	mutex_unlock(&indio_dev->mlock);
	153
154	if (timeout == 0)
155	return -ETIMEDOUT;
156
157	return IIO_VAL_INT;
158	}
159
160	static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
161	{
162	struct exynos_adc info = (struct exynos_adc )dev_id;
163
164	/* Read value */
165	info->value = readl(ADC_V1_DATX(info->regs)) &
166	ADC_DATX_MASK;
167	/* clear irq */
168	if (info->version == ADC_V2)
169	writel(1, ADC_V2_INT_ST(info->regs));
170	else
171	writel(1, ADC_V1_INTCLR(info->regs));
172
173	complete(&info->completion);
174
175	return IRQ_HANDLED;
176	}
177
178	static int exynos_adc_reg_access(struct iio_dev *indio_dev,
179	unsigned reg, unsigned writeval,
180	unsigned *readval)
181	{
182	struct exynos_adc *info = iio_priv(indio_dev);
183
184	if (readval == NULL)
185	return -EINVAL;
186
187	*readval = readl(info->regs + reg);
188
189	return 0;
190	}
191
192	static const struct iio_info exynos_adc_iio_info = {
193	.read_raw = &exynos_read_raw,
194	.debugfs_reg_access = &exynos_adc_reg_access,
195	.driver_module = THIS_MODULE,
196	};
197
198	#define ADC_CHANNEL(_index, _id) { \
199	.type = IIO_VOLTAGE, \
200	.indexed = 1, \
201	.channel = _index, \
202	.address = _index, \
0d23d328	203	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
10f5b148 NKC	204	.datasheet_name = _id, \
	205	}
	206
	207	static const struct iio_chan_spec exynos_adc_iio_channels[] = {
	208	ADC_CHANNEL(0, "adc0"),
	209	ADC_CHANNEL(1, "adc1"),
	210	ADC_CHANNEL(2, "adc2"),
	211	ADC_CHANNEL(3, "adc3"),
	212	ADC_CHANNEL(4, "adc4"),
	213	ADC_CHANNEL(5, "adc5"),
	214	ADC_CHANNEL(6, "adc6"),
	215	ADC_CHANNEL(7, "adc7"),
	216	ADC_CHANNEL(8, "adc8"),
	217	ADC_CHANNEL(9, "adc9"),
	218	};
	219
	220	static int exynos_adc_remove_devices(struct device dev, void c)
	221	{
	222	struct platform_device *pdev = to_platform_device(dev);
	223
	224	platform_device_unregister(pdev);
	225
	226	return 0;
	227	}
	228
	229	static void exynos_adc_hw_init(struct exynos_adc *info)
	230	{
	231	u32 con1, con2;
	232
	233	if (info->version == ADC_V2) {
	234	con1 = ADC_V2_CON1_SOFT_RESET;
	235	writel(con1, ADC_V2_CON1(info->regs));
	236
	237	con2 = ADC_V2_CON2_OSEL \| ADC_V2_CON2_ESEL \|
	238	ADC_V2_CON2_HIGHF \| ADC_V2_CON2_C_TIME(0);
	239	writel(con2, ADC_V2_CON2(info->regs));
	240
	241	/* Enable interrupts */
	242	writel(1, ADC_V2_INT_EN(info->regs));
	243	} else {
	244	/* set default prescaler values and Enable prescaler */
	245	con1 = ADC_V1_CON_PRSCLV(49) \| ADC_V1_CON_PRSCEN;
	246
	247	/* Enable 12-bit ADC resolution */
	248	con1 \|= ADC_V1_CON_RES;
	249	writel(con1, ADC_V1_CON(info->regs));
	250	}
	251	}
	252
	253	static int exynos_adc_probe(struct platform_device *pdev)
	254	{
	255	struct exynos_adc *info = NULL;
	256	struct device_node *np = pdev->dev.of_node;
	257	struct iio_dev *indio_dev = NULL;
	258	struct resource *mem;
	259	int ret = -ENODEV;
	260	int irq;
	261
	262	if (!np)
	263	return ret;
	264
ebeb021a	265	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
10f5b148 NKC	266	if (!indio_dev) {
	267	dev_err(&pdev->dev, "failed allocating iio device\n");
	268	return -ENOMEM;
	269	}
	270
	271	info = iio_priv(indio_dev);
	272
	273	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c619653d	274	info->regs = devm_ioremap_resource(&pdev->dev, mem);
ebeb021a SK	275	if (IS_ERR(info->regs))
ebeb021a SK	276	return PTR_ERR(info->regs);
10f5b148	277
bb916ebb	278	mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
c619653d	279	info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
ebeb021a SK	280	if (IS_ERR(info->enable_reg))
ebeb021a SK	281	return PTR_ERR(info->enable_reg);
bb916ebb	282
10f5b148 NKC	283	irq = platform_get_irq(pdev, 0);
	284	if (irq < 0) {
	285	dev_err(&pdev->dev, "no irq resource?\n");
ebeb021a	286	return irq;
10f5b148 NKC	287	}
	288
	289	info->irq = irq;
	290
	291	init_completion(&info->completion);
	292
	293	ret = request_irq(info->irq, exynos_adc_isr,
	294	0, dev_name(&pdev->dev), info);
	295	if (ret < 0) {
	296	dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
	297	info->irq);
ebeb021a	298	return ret;
10f5b148 NKC	299	}
10f5b148 NKC	300
bb916ebb DA	301	writel(1, info->enable_reg);
bb916ebb DA	302
10f5b148 NKC	303	info->clk = devm_clk_get(&pdev->dev, "adc");
	304	if (IS_ERR(info->clk)) {
	305	dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
	306	PTR_ERR(info->clk));
	307	ret = PTR_ERR(info->clk);
	308	goto err_irq;
	309	}
	310
	311	info->vdd = devm_regulator_get(&pdev->dev, "vdd");
	312	if (IS_ERR(info->vdd)) {
	313	dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
	314	PTR_ERR(info->vdd));
	315	ret = PTR_ERR(info->vdd);
	316	goto err_irq;
	317	}
	318
	319	info->version = exynos_adc_get_version(pdev);
	320
	321	platform_set_drvdata(pdev, indio_dev);
	322
	323	indio_dev->name = dev_name(&pdev->dev);
	324	indio_dev->dev.parent = &pdev->dev;
	325	indio_dev->dev.of_node = pdev->dev.of_node;
	326	indio_dev->info = &exynos_adc_iio_info;
	327	indio_dev->modes = INDIO_DIRECT_MODE;
	328	indio_dev->channels = exynos_adc_iio_channels;
	329
	330	if (info->version == ADC_V1)
	331	indio_dev->num_channels = MAX_ADC_V1_CHANNELS;
	332	else
	333	indio_dev->num_channels = MAX_ADC_V2_CHANNELS;
	334
	335	ret = iio_device_register(indio_dev);
	336	if (ret)
	337	goto err_irq;
	338
	339	ret = regulator_enable(info->vdd);
	340	if (ret)
	341	goto err_iio_dev;
	342
	343	clk_prepare_enable(info->clk);
	344
	345	exynos_adc_hw_init(info);
	346
	347	ret = of_platform_populate(np, exynos_adc_match, NULL, &pdev->dev);
	348	if (ret < 0) {
	349	dev_err(&pdev->dev, "failed adding child nodes\n");
	350	goto err_of_populate;
	351	}
	352
	353	return 0;
	354
	355	err_of_populate:
	356	device_for_each_child(&pdev->dev, NULL,
	357	exynos_adc_remove_devices);
	358	regulator_disable(info->vdd);
	359	clk_disable_unprepare(info->clk);
	360	err_iio_dev:
	361	iio_device_unregister(indio_dev);
	362	err_irq:
	363	free_irq(info->irq, info);
10f5b148 NKC	364	return ret;
	365	}
	366
	367	static int exynos_adc_remove(struct platform_device *pdev)
	368	{
	369	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
	370	struct exynos_adc *info = iio_priv(indio_dev);
	371
	372	device_for_each_child(&pdev->dev, NULL,
	373	exynos_adc_remove_devices);
	374	regulator_disable(info->vdd);
	375	clk_disable_unprepare(info->clk);
bb916ebb	376	writel(0, info->enable_reg);
10f5b148 NKC	377	iio_device_unregister(indio_dev);
10f5b148 NKC	378	free_irq(info->irq, info);
10f5b148 NKC	379
	380	return 0;
	381	}
	382
	383	#ifdef CONFIG_PM_SLEEP
	384	static int exynos_adc_suspend(struct device *dev)
	385	{
927b4dc3 NKC	386	struct iio_dev *indio_dev = dev_get_drvdata(dev);
927b4dc3 NKC	387	struct exynos_adc *info = iio_priv(indio_dev);
10f5b148 NKC	388	u32 con;
	389
	390	if (info->version == ADC_V2) {
	391	con = readl(ADC_V2_CON1(info->regs));
	392	con &= ~ADC_CON_EN_START;
	393	writel(con, ADC_V2_CON1(info->regs));
	394	} else {
	395	con = readl(ADC_V1_CON(info->regs));
	396	con \|= ADC_V1_CON_STANDBY;
	397	writel(con, ADC_V1_CON(info->regs));
	398	}
	399
	400	clk_disable_unprepare(info->clk);
bb916ebb	401	writel(0, info->enable_reg);
10f5b148 NKC	402	regulator_disable(info->vdd);
	403
	404	return 0;
	405	}
	406
	407	static int exynos_adc_resume(struct device *dev)
	408	{
927b4dc3 NKC	409	struct iio_dev *indio_dev = dev_get_drvdata(dev);
927b4dc3 NKC	410	struct exynos_adc *info = iio_priv(indio_dev);
10f5b148 NKC	411	int ret;
	412
	413	ret = regulator_enable(info->vdd);
	414	if (ret)
	415	return ret;
	416
bb916ebb	417	writel(1, info->enable_reg);
10f5b148 NKC	418	clk_prepare_enable(info->clk);
	419
	420	exynos_adc_hw_init(info);
	421
	422	return 0;
	423	}
	424	#endif
	425
	426	static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
	427	exynos_adc_suspend,
	428	exynos_adc_resume);
	429
	430	static struct platform_driver exynos_adc_driver = {
	431	.probe = exynos_adc_probe,
	432	.remove = exynos_adc_remove,
	433	.driver = {
	434	.name = "exynos-adc",
	435	.owner = THIS_MODULE,
1ba0686b	436	.of_match_table = exynos_adc_match,
10f5b148 NKC	437	.pm = &exynos_adc_pm_ops,
	438	},
	439	};
	440
	441	module_platform_driver(exynos_adc_driver);
	442
	443	MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
	444	MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
	445	MODULE_LICENSE("GPL v2");