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c43a102e MT |
1 | /* |
2 | * INA2XX Current and Power Monitors | |
3 | * | |
4 | * Copyright 2015 Baylibre SAS. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Based on linux/drivers/iio/adc/ad7291.c | |
11 | * Copyright 2010-2011 Analog Devices Inc. | |
12 | * | |
13 | * Based on linux/drivers/hwmon/ina2xx.c | |
14 | * Copyright 2012 Lothar Felten <l-felten@ti.com> | |
15 | * | |
16 | * Licensed under the GPL-2 or later. | |
17 | * | |
18 | * IIO driver for INA219-220-226-230-231 | |
19 | * | |
20 | * Configurable 7-bit I2C slave address from 0x40 to 0x4F | |
21 | */ | |
7906dd52 | 22 | |
c43a102e | 23 | #include <linux/delay.h> |
7906dd52 | 24 | #include <linux/i2c.h> |
c43a102e MT |
25 | #include <linux/iio/kfifo_buf.h> |
26 | #include <linux/iio/sysfs.h> | |
7906dd52 AD |
27 | #include <linux/kthread.h> |
28 | #include <linux/module.h> | |
c43a102e | 29 | #include <linux/regmap.h> |
c43a102e MT |
30 | #include <linux/util_macros.h> |
31 | ||
7906dd52 AD |
32 | #include <linux/platform_data/ina2xx.h> |
33 | ||
c43a102e MT |
34 | /* INA2XX registers definition */ |
35 | #define INA2XX_CONFIG 0x00 | |
36 | #define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */ | |
37 | #define INA2XX_BUS_VOLTAGE 0x02 /* readonly */ | |
38 | #define INA2XX_POWER 0x03 /* readonly */ | |
39 | #define INA2XX_CURRENT 0x04 /* readonly */ | |
40 | #define INA2XX_CALIBRATION 0x05 | |
41 | ||
7906dd52 | 42 | #define INA226_ALERT_MASK GENMASK(2, 1) |
c43a102e MT |
43 | #define INA266_CVRF BIT(3) |
44 | ||
45 | #define INA2XX_MAX_REGISTERS 8 | |
46 | ||
47 | /* settings - depend on use case */ | |
48 | #define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */ | |
49 | #define INA226_CONFIG_DEFAULT 0x4327 | |
50 | #define INA226_DEFAULT_AVG 4 | |
51 | #define INA226_DEFAULT_IT 1110 | |
52 | ||
53 | #define INA2XX_RSHUNT_DEFAULT 10000 | |
54 | ||
55 | /* | |
56 | * bit mask for reading the averaging setting in the configuration register | |
57 | * FIXME: use regmap_fields. | |
58 | */ | |
59 | #define INA2XX_MODE_MASK GENMASK(3, 0) | |
60 | ||
61 | #define INA226_AVG_MASK GENMASK(11, 9) | |
62 | #define INA226_SHIFT_AVG(val) ((val) << 9) | |
63 | ||
64 | /* Integration time for VBus */ | |
65 | #define INA226_ITB_MASK GENMASK(8, 6) | |
66 | #define INA226_SHIFT_ITB(val) ((val) << 6) | |
67 | ||
68 | /* Integration time for VShunt */ | |
69 | #define INA226_ITS_MASK GENMASK(5, 3) | |
70 | #define INA226_SHIFT_ITS(val) ((val) << 3) | |
71 | ||
72 | /* Cosmetic macro giving the sampling period for a full P=UxI cycle */ | |
73 | #define SAMPLING_PERIOD(c) ((c->int_time_vbus + c->int_time_vshunt) \ | |
74 | * c->avg) | |
75 | ||
76 | static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg) | |
77 | { | |
78 | return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT); | |
79 | } | |
80 | ||
81 | static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg) | |
82 | { | |
83 | return (reg != INA2XX_CONFIG); | |
84 | } | |
85 | ||
86 | static inline bool is_signed_reg(unsigned int reg) | |
87 | { | |
88 | return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT); | |
89 | } | |
90 | ||
91 | static const struct regmap_config ina2xx_regmap_config = { | |
92 | .reg_bits = 8, | |
93 | .val_bits = 16, | |
94 | .max_register = INA2XX_MAX_REGISTERS, | |
95 | .writeable_reg = ina2xx_is_writeable_reg, | |
96 | .volatile_reg = ina2xx_is_volatile_reg, | |
97 | }; | |
98 | ||
99 | enum ina2xx_ids { ina219, ina226 }; | |
100 | ||
101 | struct ina2xx_config { | |
102 | u16 config_default; | |
103 | int calibration_factor; | |
104 | int shunt_div; | |
105 | int bus_voltage_shift; | |
106 | int bus_voltage_lsb; /* uV */ | |
107 | int power_lsb; /* uW */ | |
108 | }; | |
109 | ||
110 | struct ina2xx_chip_info { | |
111 | struct regmap *regmap; | |
112 | struct task_struct *task; | |
113 | const struct ina2xx_config *config; | |
114 | struct mutex state_lock; | |
b17dc401 | 115 | unsigned int shunt_resistor; |
c43a102e | 116 | int avg; |
7906dd52 | 117 | s64 prev_ns; /* track buffer capture time, check for underruns */ |
c43a102e MT |
118 | int int_time_vbus; /* Bus voltage integration time uS */ |
119 | int int_time_vshunt; /* Shunt voltage integration time uS */ | |
f9993c07 | 120 | bool allow_async_readout; |
c43a102e MT |
121 | }; |
122 | ||
123 | static const struct ina2xx_config ina2xx_config[] = { | |
124 | [ina219] = { | |
7906dd52 AD |
125 | .config_default = INA219_CONFIG_DEFAULT, |
126 | .calibration_factor = 40960000, | |
127 | .shunt_div = 100, | |
128 | .bus_voltage_shift = 3, | |
129 | .bus_voltage_lsb = 4000, | |
130 | .power_lsb = 20000, | |
131 | }, | |
c43a102e | 132 | [ina226] = { |
7906dd52 AD |
133 | .config_default = INA226_CONFIG_DEFAULT, |
134 | .calibration_factor = 5120000, | |
135 | .shunt_div = 400, | |
136 | .bus_voltage_shift = 0, | |
137 | .bus_voltage_lsb = 1250, | |
138 | .power_lsb = 25000, | |
139 | }, | |
c43a102e MT |
140 | }; |
141 | ||
142 | static int ina2xx_read_raw(struct iio_dev *indio_dev, | |
143 | struct iio_chan_spec const *chan, | |
144 | int *val, int *val2, long mask) | |
145 | { | |
146 | int ret; | |
147 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
148 | unsigned int regval; | |
149 | ||
150 | switch (mask) { | |
151 | case IIO_CHAN_INFO_RAW: | |
152 | ret = regmap_read(chip->regmap, chan->address, ®val); | |
7906dd52 | 153 | if (ret) |
c43a102e MT |
154 | return ret; |
155 | ||
156 | if (is_signed_reg(chan->address)) | |
157 | *val = (s16) regval; | |
158 | else | |
159 | *val = regval; | |
160 | ||
161 | return IIO_VAL_INT; | |
162 | ||
163 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: | |
164 | *val = chip->avg; | |
165 | return IIO_VAL_INT; | |
166 | ||
167 | case IIO_CHAN_INFO_INT_TIME: | |
168 | *val = 0; | |
169 | if (chan->address == INA2XX_SHUNT_VOLTAGE) | |
170 | *val2 = chip->int_time_vshunt; | |
171 | else | |
172 | *val2 = chip->int_time_vbus; | |
173 | ||
174 | return IIO_VAL_INT_PLUS_MICRO; | |
175 | ||
176 | case IIO_CHAN_INFO_SAMP_FREQ: | |
177 | /* | |
178 | * Sample freq is read only, it is a consequence of | |
179 | * 1/AVG*(CT_bus+CT_shunt). | |
180 | */ | |
181 | *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip)); | |
182 | ||
183 | return IIO_VAL_INT; | |
184 | ||
185 | case IIO_CHAN_INFO_SCALE: | |
186 | switch (chan->address) { | |
187 | case INA2XX_SHUNT_VOLTAGE: | |
eaa3476a | 188 | /* processed (mV) = raw/shunt_div */ |
c43a102e | 189 | *val2 = chip->config->shunt_div; |
eaa3476a | 190 | *val = 1; |
c43a102e MT |
191 | return IIO_VAL_FRACTIONAL; |
192 | ||
193 | case INA2XX_BUS_VOLTAGE: | |
194 | /* processed (mV) = raw*lsb (uV) / (1000 << shift) */ | |
195 | *val = chip->config->bus_voltage_lsb; | |
196 | *val2 = 1000 << chip->config->bus_voltage_shift; | |
197 | return IIO_VAL_FRACTIONAL; | |
198 | ||
199 | case INA2XX_POWER: | |
200 | /* processed (mW) = raw*lsb (uW) / 1000 */ | |
201 | *val = chip->config->power_lsb; | |
202 | *val2 = 1000; | |
203 | return IIO_VAL_FRACTIONAL; | |
204 | ||
205 | case INA2XX_CURRENT: | |
206 | /* processed (mA) = raw (mA) */ | |
207 | *val = 1; | |
208 | return IIO_VAL_INT; | |
209 | } | |
210 | } | |
211 | ||
212 | return -EINVAL; | |
213 | } | |
214 | ||
215 | /* | |
216 | * Available averaging rates for ina226. The indices correspond with | |
217 | * the bit values expected by the chip (according to the ina226 datasheet, | |
218 | * table 3 AVG bit settings, found at | |
219 | * http://www.ti.com/lit/ds/symlink/ina226.pdf. | |
220 | */ | |
221 | static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 }; | |
222 | ||
223 | static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val, | |
224 | unsigned int *config) | |
225 | { | |
226 | int bits; | |
227 | ||
228 | if (val > 1024 || val < 1) | |
229 | return -EINVAL; | |
230 | ||
231 | bits = find_closest(val, ina226_avg_tab, | |
232 | ARRAY_SIZE(ina226_avg_tab)); | |
233 | ||
234 | chip->avg = ina226_avg_tab[bits]; | |
235 | ||
236 | *config &= ~INA226_AVG_MASK; | |
237 | *config |= INA226_SHIFT_AVG(bits) & INA226_AVG_MASK; | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | /* Conversion times in uS */ | |
243 | static const int ina226_conv_time_tab[] = { 140, 204, 332, 588, 1100, | |
244 | 2116, 4156, 8244 }; | |
245 | ||
246 | static int ina226_set_int_time_vbus(struct ina2xx_chip_info *chip, | |
247 | unsigned int val_us, unsigned int *config) | |
248 | { | |
249 | int bits; | |
250 | ||
251 | if (val_us > 8244 || val_us < 140) | |
252 | return -EINVAL; | |
253 | ||
254 | bits = find_closest(val_us, ina226_conv_time_tab, | |
7906dd52 | 255 | ARRAY_SIZE(ina226_conv_time_tab)); |
c43a102e MT |
256 | |
257 | chip->int_time_vbus = ina226_conv_time_tab[bits]; | |
258 | ||
259 | *config &= ~INA226_ITB_MASK; | |
260 | *config |= INA226_SHIFT_ITB(bits) & INA226_ITB_MASK; | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip, | |
266 | unsigned int val_us, unsigned int *config) | |
267 | { | |
268 | int bits; | |
269 | ||
270 | if (val_us > 8244 || val_us < 140) | |
271 | return -EINVAL; | |
272 | ||
273 | bits = find_closest(val_us, ina226_conv_time_tab, | |
7906dd52 | 274 | ARRAY_SIZE(ina226_conv_time_tab)); |
c43a102e MT |
275 | |
276 | chip->int_time_vshunt = ina226_conv_time_tab[bits]; | |
277 | ||
278 | *config &= ~INA226_ITS_MASK; | |
279 | *config |= INA226_SHIFT_ITS(bits) & INA226_ITS_MASK; | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | static int ina2xx_write_raw(struct iio_dev *indio_dev, | |
285 | struct iio_chan_spec const *chan, | |
286 | int val, int val2, long mask) | |
287 | { | |
288 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
c43a102e | 289 | unsigned int config, tmp; |
7906dd52 | 290 | int ret; |
c43a102e MT |
291 | |
292 | if (iio_buffer_enabled(indio_dev)) | |
293 | return -EBUSY; | |
294 | ||
295 | mutex_lock(&chip->state_lock); | |
296 | ||
297 | ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config); | |
7906dd52 AD |
298 | if (ret) |
299 | goto err; | |
c43a102e MT |
300 | |
301 | tmp = config; | |
302 | ||
303 | switch (mask) { | |
304 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: | |
305 | ret = ina226_set_average(chip, val, &tmp); | |
306 | break; | |
307 | ||
308 | case IIO_CHAN_INFO_INT_TIME: | |
309 | if (chan->address == INA2XX_SHUNT_VOLTAGE) | |
310 | ret = ina226_set_int_time_vshunt(chip, val2, &tmp); | |
311 | else | |
312 | ret = ina226_set_int_time_vbus(chip, val2, &tmp); | |
313 | break; | |
7906dd52 | 314 | |
c43a102e MT |
315 | default: |
316 | ret = -EINVAL; | |
317 | } | |
318 | ||
319 | if (!ret && (tmp != config)) | |
320 | ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp); | |
7906dd52 | 321 | err: |
c43a102e MT |
322 | mutex_unlock(&chip->state_lock); |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
f9993c07 MT |
327 | static ssize_t ina2xx_allow_async_readout_show(struct device *dev, |
328 | struct device_attribute *attr, | |
329 | char *buf) | |
330 | { | |
331 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); | |
332 | ||
333 | return sprintf(buf, "%d\n", chip->allow_async_readout); | |
334 | } | |
335 | ||
336 | static ssize_t ina2xx_allow_async_readout_store(struct device *dev, | |
337 | struct device_attribute *attr, | |
338 | const char *buf, size_t len) | |
339 | { | |
340 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); | |
341 | bool val; | |
342 | int ret; | |
343 | ||
344 | ret = strtobool((const char *) buf, &val); | |
345 | if (ret) | |
346 | return ret; | |
347 | ||
348 | chip->allow_async_readout = val; | |
349 | ||
350 | return len; | |
351 | } | |
352 | ||
d1ef4f2c MT |
353 | /* |
354 | * Set current LSB to 1mA, shunt is in uOhms | |
355 | * (equation 13 in datasheet). We hardcode a Current_LSB | |
356 | * of 1.0 x10-6. The only remaining parameter is RShunt. | |
357 | * There is no need to expose the CALIBRATION register | |
358 | * to the user for now. But we need to reset this register | |
359 | * if the user updates RShunt after driver init, e.g upon | |
360 | * reading an EEPROM/Probe-type value. | |
361 | */ | |
362 | static int ina2xx_set_calibration(struct ina2xx_chip_info *chip) | |
363 | { | |
364 | u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor, | |
365 | chip->shunt_resistor); | |
366 | ||
367 | return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval); | |
368 | } | |
369 | ||
b17dc401 MT |
370 | static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val) |
371 | { | |
372 | if (val <= 0 || val > chip->config->calibration_factor) | |
373 | return -EINVAL; | |
374 | ||
375 | chip->shunt_resistor = val; | |
7906dd52 | 376 | |
b17dc401 MT |
377 | return 0; |
378 | } | |
379 | ||
380 | static ssize_t ina2xx_shunt_resistor_show(struct device *dev, | |
381 | struct device_attribute *attr, | |
382 | char *buf) | |
383 | { | |
384 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); | |
385 | ||
386 | return sprintf(buf, "%d\n", chip->shunt_resistor); | |
387 | } | |
388 | ||
389 | static ssize_t ina2xx_shunt_resistor_store(struct device *dev, | |
390 | struct device_attribute *attr, | |
391 | const char *buf, size_t len) | |
392 | { | |
393 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); | |
394 | unsigned long val; | |
395 | int ret; | |
396 | ||
397 | ret = kstrtoul((const char *) buf, 10, &val); | |
398 | if (ret) | |
399 | return ret; | |
400 | ||
401 | ret = set_shunt_resistor(chip, val); | |
402 | if (ret) | |
403 | return ret; | |
404 | ||
d1ef4f2c MT |
405 | /* Update the Calibration register */ |
406 | ret = ina2xx_set_calibration(chip); | |
407 | if (ret) | |
408 | return ret; | |
409 | ||
b17dc401 MT |
410 | return len; |
411 | } | |
f9993c07 | 412 | |
c43a102e MT |
413 | #define INA2XX_CHAN(_type, _index, _address) { \ |
414 | .type = (_type), \ | |
415 | .address = (_address), \ | |
416 | .indexed = 1, \ | |
417 | .channel = (_index), \ | |
418 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ | |
419 | | BIT(IIO_CHAN_INFO_SCALE), \ | |
420 | .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ | |
421 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ | |
422 | .scan_index = (_index), \ | |
423 | .scan_type = { \ | |
424 | .sign = 'u', \ | |
425 | .realbits = 16, \ | |
426 | .storagebits = 16, \ | |
e8aab48b | 427 | .endianness = IIO_CPU, \ |
c43a102e MT |
428 | } \ |
429 | } | |
430 | ||
431 | /* | |
432 | * Sampling Freq is a consequence of the integration times of | |
433 | * the Voltage channels. | |
434 | */ | |
435 | #define INA2XX_CHAN_VOLTAGE(_index, _address) { \ | |
436 | .type = IIO_VOLTAGE, \ | |
437 | .address = (_address), \ | |
438 | .indexed = 1, \ | |
439 | .channel = (_index), \ | |
440 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ | |
441 | BIT(IIO_CHAN_INFO_SCALE) | \ | |
442 | BIT(IIO_CHAN_INFO_INT_TIME), \ | |
443 | .scan_index = (_index), \ | |
444 | .scan_type = { \ | |
445 | .sign = 'u', \ | |
446 | .realbits = 16, \ | |
447 | .storagebits = 16, \ | |
448 | .endianness = IIO_LE, \ | |
449 | } \ | |
450 | } | |
451 | ||
452 | static const struct iio_chan_spec ina2xx_channels[] = { | |
453 | INA2XX_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE), | |
454 | INA2XX_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE), | |
75e1a3a7 MT |
455 | INA2XX_CHAN(IIO_POWER, 2, INA2XX_POWER), |
456 | INA2XX_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT), | |
c43a102e MT |
457 | IIO_CHAN_SOFT_TIMESTAMP(4), |
458 | }; | |
459 | ||
460 | static int ina2xx_work_buffer(struct iio_dev *indio_dev) | |
461 | { | |
462 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
463 | unsigned short data[8]; | |
464 | int bit, ret, i = 0; | |
c43a102e MT |
465 | s64 time_a, time_b; |
466 | unsigned int alert; | |
467 | ||
468 | time_a = iio_get_time_ns(); | |
469 | ||
470 | /* | |
471 | * Because the timer thread and the chip conversion clock | |
472 | * are asynchronous, the period difference will eventually | |
473 | * result in reading V[k-1] again, or skip V[k] at time Tk. | |
474 | * In order to resync the timer with the conversion process | |
475 | * we check the ConVersionReadyFlag. | |
476 | * On hardware that supports using the ALERT pin to toggle a | |
477 | * GPIO a triggered buffer could be used instead. | |
478 | * For now, we pay for that extra read of the ALERT register | |
479 | */ | |
f9993c07 MT |
480 | if (!chip->allow_async_readout) |
481 | do { | |
482 | ret = regmap_read(chip->regmap, INA226_ALERT_MASK, | |
483 | &alert); | |
484 | if (ret < 0) | |
485 | return ret; | |
c43a102e | 486 | |
f9993c07 | 487 | alert &= INA266_CVRF; |
f9993c07 | 488 | } while (!alert); |
c43a102e MT |
489 | |
490 | /* | |
491 | * Single register reads: bulk_read will not work with ina226 | |
492 | * as there is no auto-increment of the address register for | |
493 | * data length longer than 16bits. | |
494 | */ | |
495 | for_each_set_bit(bit, indio_dev->active_scan_mask, | |
496 | indio_dev->masklength) { | |
497 | unsigned int val; | |
498 | ||
499 | ret = regmap_read(chip->regmap, | |
500 | INA2XX_SHUNT_VOLTAGE + bit, &val); | |
501 | if (ret < 0) | |
502 | return ret; | |
503 | ||
504 | data[i++] = val; | |
505 | } | |
506 | ||
507 | time_b = iio_get_time_ns(); | |
508 | ||
509 | iio_push_to_buffers_with_timestamp(indio_dev, | |
510 | (unsigned int *)data, time_a); | |
511 | ||
c43a102e MT |
512 | chip->prev_ns = time_a; |
513 | ||
1961bce7 | 514 | return (unsigned long)(time_b - time_a) / 1000; |
c43a102e MT |
515 | }; |
516 | ||
517 | static int ina2xx_capture_thread(void *data) | |
518 | { | |
7906dd52 | 519 | struct iio_dev *indio_dev = data; |
c43a102e MT |
520 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); |
521 | unsigned int sampling_us = SAMPLING_PERIOD(chip); | |
522 | int buffer_us; | |
523 | ||
524 | /* | |
525 | * Poll a bit faster than the chip internal Fs, in case | |
526 | * we wish to sync with the conversion ready flag. | |
527 | */ | |
f9993c07 MT |
528 | if (!chip->allow_async_readout) |
529 | sampling_us -= 200; | |
c43a102e MT |
530 | |
531 | do { | |
532 | buffer_us = ina2xx_work_buffer(indio_dev); | |
533 | if (buffer_us < 0) | |
534 | return buffer_us; | |
535 | ||
536 | if (sampling_us > buffer_us) | |
537 | udelay(sampling_us - buffer_us); | |
538 | ||
539 | } while (!kthread_should_stop()); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | static int ina2xx_buffer_enable(struct iio_dev *indio_dev) | |
545 | { | |
546 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
547 | unsigned int sampling_us = SAMPLING_PERIOD(chip); | |
548 | ||
1961bce7 AD |
549 | dev_dbg(&indio_dev->dev, "Enabling buffer w/ scan_mask %02x, freq = %d, avg =%u\n", |
550 | (unsigned int)(*indio_dev->active_scan_mask), | |
551 | 1000000 / sampling_us, chip->avg); | |
c43a102e | 552 | |
1961bce7 AD |
553 | dev_dbg(&indio_dev->dev, "Expected work period: %u us\n", sampling_us); |
554 | dev_dbg(&indio_dev->dev, "Async readout mode: %d\n", | |
555 | chip->allow_async_readout); | |
c43a102e MT |
556 | |
557 | chip->prev_ns = iio_get_time_ns(); | |
558 | ||
559 | chip->task = kthread_run(ina2xx_capture_thread, (void *)indio_dev, | |
46294cd9 MT |
560 | "%s:%d-%uus", indio_dev->name, indio_dev->id, |
561 | sampling_us); | |
c43a102e MT |
562 | |
563 | return PTR_ERR_OR_ZERO(chip->task); | |
564 | } | |
565 | ||
566 | static int ina2xx_buffer_disable(struct iio_dev *indio_dev) | |
567 | { | |
568 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
569 | ||
570 | if (chip->task) { | |
571 | kthread_stop(chip->task); | |
572 | chip->task = NULL; | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static const struct iio_buffer_setup_ops ina2xx_setup_ops = { | |
579 | .postenable = &ina2xx_buffer_enable, | |
580 | .predisable = &ina2xx_buffer_disable, | |
581 | }; | |
582 | ||
583 | static int ina2xx_debug_reg(struct iio_dev *indio_dev, | |
584 | unsigned reg, unsigned writeval, unsigned *readval) | |
585 | { | |
586 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
587 | ||
588 | if (!readval) | |
589 | return regmap_write(chip->regmap, reg, writeval); | |
590 | ||
591 | return regmap_read(chip->regmap, reg, readval); | |
592 | } | |
593 | ||
594 | /* Possible integration times for vshunt and vbus */ | |
7906dd52 | 595 | static IIO_CONST_ATTR_INT_TIME_AVAIL("0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244"); |
c43a102e | 596 | |
f9993c07 MT |
597 | static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR, |
598 | ina2xx_allow_async_readout_show, | |
599 | ina2xx_allow_async_readout_store, 0); | |
600 | ||
b17dc401 MT |
601 | static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR, |
602 | ina2xx_shunt_resistor_show, | |
603 | ina2xx_shunt_resistor_store, 0); | |
604 | ||
c43a102e | 605 | static struct attribute *ina2xx_attributes[] = { |
f9993c07 | 606 | &iio_dev_attr_in_allow_async_readout.dev_attr.attr, |
c43a102e | 607 | &iio_const_attr_integration_time_available.dev_attr.attr, |
b17dc401 | 608 | &iio_dev_attr_in_shunt_resistor.dev_attr.attr, |
c43a102e MT |
609 | NULL, |
610 | }; | |
611 | ||
612 | static const struct attribute_group ina2xx_attribute_group = { | |
613 | .attrs = ina2xx_attributes, | |
614 | }; | |
615 | ||
616 | static const struct iio_info ina2xx_info = { | |
c43a102e | 617 | .driver_module = THIS_MODULE, |
7906dd52 AD |
618 | .attrs = &ina2xx_attribute_group, |
619 | .read_raw = ina2xx_read_raw, | |
620 | .write_raw = ina2xx_write_raw, | |
621 | .debugfs_reg_access = ina2xx_debug_reg, | |
c43a102e MT |
622 | }; |
623 | ||
624 | /* Initialize the configuration and calibration registers. */ | |
625 | static int ina2xx_init(struct ina2xx_chip_info *chip, unsigned int config) | |
626 | { | |
d1ef4f2c | 627 | int ret = regmap_write(chip->regmap, INA2XX_CONFIG, config); |
7906dd52 | 628 | if (ret) |
c43a102e | 629 | return ret; |
7906dd52 | 630 | |
d1ef4f2c | 631 | return ina2xx_set_calibration(chip); |
c43a102e MT |
632 | } |
633 | ||
634 | static int ina2xx_probe(struct i2c_client *client, | |
635 | const struct i2c_device_id *id) | |
636 | { | |
637 | struct ina2xx_chip_info *chip; | |
638 | struct iio_dev *indio_dev; | |
639 | struct iio_buffer *buffer; | |
c43a102e | 640 | unsigned int val; |
7906dd52 | 641 | int ret; |
c43a102e MT |
642 | |
643 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); | |
644 | if (!indio_dev) | |
645 | return -ENOMEM; | |
646 | ||
647 | chip = iio_priv(indio_dev); | |
648 | ||
7906dd52 AD |
649 | /* This is only used for device removal purposes. */ |
650 | i2c_set_clientdata(client, indio_dev); | |
651 | ||
652 | chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config); | |
653 | if (IS_ERR(chip->regmap)) { | |
654 | dev_err(&client->dev, "failed to allocate register map\n"); | |
655 | return PTR_ERR(chip->regmap); | |
656 | } | |
657 | ||
c43a102e MT |
658 | chip->config = &ina2xx_config[id->driver_data]; |
659 | ||
7906dd52 AD |
660 | mutex_init(&chip->state_lock); |
661 | ||
c43a102e MT |
662 | if (of_property_read_u32(client->dev.of_node, |
663 | "shunt-resistor", &val) < 0) { | |
664 | struct ina2xx_platform_data *pdata = | |
665 | dev_get_platdata(&client->dev); | |
666 | ||
667 | if (pdata) | |
668 | val = pdata->shunt_uohms; | |
669 | else | |
670 | val = INA2XX_RSHUNT_DEFAULT; | |
671 | } | |
672 | ||
b17dc401 MT |
673 | ret = set_shunt_resistor(chip, val); |
674 | if (ret) | |
675 | return ret; | |
c43a102e | 676 | |
c43a102e MT |
677 | /* Patch the current config register with default. */ |
678 | val = chip->config->config_default; | |
679 | ||
680 | if (id->driver_data == ina226) { | |
681 | ina226_set_average(chip, INA226_DEFAULT_AVG, &val); | |
682 | ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val); | |
683 | ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val); | |
684 | } | |
685 | ||
686 | ret = ina2xx_init(chip, val); | |
7906dd52 AD |
687 | if (ret) { |
688 | dev_err(&client->dev, "error configuring the device\n"); | |
689 | return ret; | |
c43a102e MT |
690 | } |
691 | ||
7906dd52 AD |
692 | indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; |
693 | indio_dev->dev.parent = &client->dev; | |
694 | indio_dev->channels = ina2xx_channels; | |
695 | indio_dev->num_channels = ARRAY_SIZE(ina2xx_channels); | |
696 | indio_dev->name = id->name; | |
697 | indio_dev->info = &ina2xx_info; | |
698 | indio_dev->setup_ops = &ina2xx_setup_ops; | |
699 | ||
c43a102e MT |
700 | buffer = devm_iio_kfifo_allocate(&indio_dev->dev); |
701 | if (!buffer) | |
702 | return -ENOMEM; | |
703 | ||
c43a102e MT |
704 | iio_device_attach_buffer(indio_dev, buffer); |
705 | ||
706 | return iio_device_register(indio_dev); | |
707 | } | |
708 | ||
c43a102e MT |
709 | static int ina2xx_remove(struct i2c_client *client) |
710 | { | |
711 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | |
712 | struct ina2xx_chip_info *chip = iio_priv(indio_dev); | |
713 | ||
714 | iio_device_unregister(indio_dev); | |
715 | ||
716 | /* Powerdown */ | |
717 | return regmap_update_bits(chip->regmap, INA2XX_CONFIG, | |
718 | INA2XX_MODE_MASK, 0); | |
719 | } | |
720 | ||
c43a102e MT |
721 | static const struct i2c_device_id ina2xx_id[] = { |
722 | {"ina219", ina219}, | |
723 | {"ina220", ina219}, | |
724 | {"ina226", ina226}, | |
725 | {"ina230", ina226}, | |
726 | {"ina231", ina226}, | |
727 | {} | |
728 | }; | |
c43a102e MT |
729 | MODULE_DEVICE_TABLE(i2c, ina2xx_id); |
730 | ||
731 | static struct i2c_driver ina2xx_driver = { | |
732 | .driver = { | |
733 | .name = KBUILD_MODNAME, | |
734 | }, | |
735 | .probe = ina2xx_probe, | |
736 | .remove = ina2xx_remove, | |
737 | .id_table = ina2xx_id, | |
738 | }; | |
c43a102e MT |
739 | module_i2c_driver(ina2xx_driver); |
740 | ||
741 | MODULE_AUTHOR("Marc Titinger <marc.titinger@baylibre.com>"); | |
742 | MODULE_DESCRIPTION("Texas Instruments INA2XX ADC driver"); | |
743 | MODULE_LICENSE("GPL v2"); |