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igb: Add device support for flashless SKU of i210 device
[deliverable/linux.git] / drivers / iio / adc / max1363.c
CommitLineData
d1325cf4 1 /*
82020b0e
JC		 2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
82020b0e
JC		 21 * - Control of internal reference.
22 */
d1325cf4
JC		 23
24#include <linux/interrupt.h>
d1325cf4
JC		 25#include <linux/device.h>
26#include <linux/kernel.h>
27#include <linux/sysfs.h>
28#include <linux/list.h>
29#include <linux/i2c.h>
d1325cf4 30#include <linux/regulator/consumer.h>
5a0e3ad6 31#include <linux/slab.h>
c40ab874 32#include <linux/err.h>
99c97852 33#include <linux/module.h>
d1325cf4 34
06458e27
JC		 35#include <linux/iio/iio.h>
36#include <linux/iio/sysfs.h>
37#include <linux/iio/events.h>
38#include <linux/iio/buffer.h>
39#include <linux/iio/driver.h>
b3bcbfcf
JC		 40#include <linux/iio/kfifo_buf.h>
41#include <linux/iio/trigger_consumer.h>
4389fbec 42#include <linux/iio/triggered_buffer.h>
b3bcbfcf
JC		 43
44#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
45
46/* There is a fair bit more defined here than currently
47 * used, but the intention is to support everything these
48 * chips do in the long run */
49
50/* see data sheets */
51/* max1363 and max1236, max1237, max1238, max1239 */
52#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
53#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
54#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
55#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
56#define MAX1363_SETUP_POWER_UP_INT_REF 0x10
57#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
58
71d2c120 59/* think about including max11600 etc - more settings */
b3bcbfcf
JC		 60#define MAX1363_SETUP_EXT_CLOCK 0x08
61#define MAX1363_SETUP_INT_CLOCK 0x00
62#define MAX1363_SETUP_UNIPOLAR 0x00
63#define MAX1363_SETUP_BIPOLAR 0x04
64#define MAX1363_SETUP_RESET 0x00
65#define MAX1363_SETUP_NORESET 0x02
66/* max1363 only - though don't care on others.
67 * For now monitor modes are not implemented as the relevant
68 * line is not connected on my test board.
69 * The definitions are here as I intend to add this soon.
70 */
71#define MAX1363_SETUP_MONITOR_SETUP 0x01
72
73/* Specific to the max1363 */
74#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
75#define MAX1363_MON_INT_ENABLE 0x01
76
77/* defined for readability reasons */
78/* All chips */
79#define MAX1363_CONFIG_BYTE(a) ((a))
80
81#define MAX1363_CONFIG_SE 0x01
82#define MAX1363_CONFIG_DE 0x00
83#define MAX1363_CONFIG_SCAN_TO_CS 0x00
84#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
85#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
86#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
87/* max123{6-9} only */
88#define MAX1236_SCAN_MID_TO_CHANNEL 0x40
89
71d2c120 90/* max1363 only - merely part of channel selects or don't care for others */
b3bcbfcf
JC		 91#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
92
93#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
94
95/* max1363 strictly 0x06 - but doesn't matter */
96#define MAX1363_CHANNEL_SEL_MASK 0x1E
97#define MAX1363_SCAN_MASK 0x60
98#define MAX1363_SE_DE_MASK 0x01
99
100#define MAX1363_MAX_CHANNELS 25
101/**
102 * struct max1363_mode - scan mode information
103 * @conf: The corresponding value of the configuration register
104 * @modemask: Bit mask corresponding to channels enabled in this mode
105 */
106struct max1363_mode {
107 int8_t conf;
108 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
109};
cdf38709 110
b3bcbfcf
JC		 111/* This must be maintained along side the max1363_mode_table in max1363_core */
112enum max1363_modes {
113 /* Single read of a single channel */
114 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
115 /* Differential single read */
116 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
117 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
118 /* Scan to channel and mid to channel where overlapping */
119 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
120 s6to7, s0to7, s6to8, s0to8, s6to9,
121 s0to9, s6to10, s0to10, s6to11, s0to11,
122 /* Differential scan to channel and mid to channel where overlapping */
123 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
124 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
125 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
126 d7m6to11m10, d1m0to11m10,
127};
128
129/**
130 * struct max1363_chip_info - chip specifc information
b3bcbfcf 131 * @info: iio core function callbacks structure
2593b13a
JC		 132 * @channels: channel specification
133 * @num_channels: number of channels
b3bcbfcf 134 * @mode_list: array of available scan modes
b3bcbfcf 135 * @default_mode: the scan mode in which the chip starts up
2593b13a 136 * @int_vref_mv: the internal reference voltage
71d2c120 137 * @num_modes: number of modes
2593b13a 138 * @bits: accuracy of the adc in bits
b3bcbfcf
JC		 139 */
140struct max1363_chip_info {
141 const struct iio_info *info;
2593b13a
JC		 142 const struct iio_chan_spec *channels;
143 int num_channels;
b3bcbfcf
JC		 144 const enum max1363_modes *mode_list;
145 enum max1363_modes default_mode;
146 u16 int_vref_mv;
147 u8 num_modes;
148 u8 bits;
149};
150
151/**
152 * struct max1363_state - driver instance specific data
153 * @client: i2c_client
154 * @setupbyte: cache of current device setup byte
155 * @configbyte: cache of current device config byte
71d2c120 156 * @chip_info: chip model specific constants, available modes, etc.
b3bcbfcf
JC		 157 * @current_mode: the scan mode of this chip
158 * @requestedmask: a valid requested set of channels
159 * @reg: supply regulator
160 * @monitor_on: whether monitor mode is enabled
161 * @monitor_speed: parameter corresponding to device monitor speed setting
162 * @mask_high: bitmask for enabled high thresholds
163 * @mask_low: bitmask for enabled low thresholds
164 * @thresh_high: high threshold values
165 * @thresh_low: low threshold values
a405b00e
GR		 166 * @vref: Reference voltage regulator
167 * @vref_uv: Actual (external or internal) reference voltage
b3bcbfcf
JC		 168 */
169struct max1363_state {
170 struct i2c_client *client;
171 u8 setupbyte;
172 u8 configbyte;
173 const struct max1363_chip_info *chip_info;
174 const struct max1363_mode *current_mode;
175 u32 requestedmask;
176 struct regulator *reg;
177
178 /* Using monitor modes and buffer at the same time is
179 currently not supported */
180 bool monitor_on;
181 unsigned int monitor_speed:3;
182 u8 mask_high;
183 u8 mask_low;
184 /* 4x unipolar first then the fours bipolar ones */
185 s16 thresh_high[8];
186 s16 thresh_low[8];
a405b00e
GR		 187 struct regulator *vref;
188 u32 vref_uv;
b3bcbfcf 189};
d1325cf4 190
58f0a255
JC		 191#define MAX1363_MODE_SINGLE(_num, _mask) { \
192 .conf = MAX1363_CHANNEL_SEL(_num) \
193 | MAX1363_CONFIG_SCAN_SINGLE_1 \
194 | MAX1363_CONFIG_SE, \
32b5eeca 195 .modemask[0] = _mask, \
58f0a255
JC		 196 }
197
198#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
199 .conf = MAX1363_CHANNEL_SEL(_num) \
200 | MAX1363_CONFIG_SCAN_TO_CS \
201 | MAX1363_CONFIG_SE, \
32b5eeca 202 .modemask[0] = _mask, \
58f0a255
JC		 203 }
204
205/* note not available for max1363 hence naming */
206#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
207 .conf = MAX1363_CHANNEL_SEL(_num) \
208 | MAX1236_SCAN_MID_TO_CHANNEL \
209 | MAX1363_CONFIG_SE, \
32b5eeca 210 .modemask[0] = _mask \
58f0a255
JC		 211}
212
213#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
214 .conf = MAX1363_CHANNEL_SEL(_nump) \
215 | MAX1363_CONFIG_SCAN_SINGLE_1 \
216 | MAX1363_CONFIG_DE, \
32b5eeca 217 .modemask[0] = _mask \
58f0a255
JC		 218 }
219
220/* Can't think how to automate naming so specify for now */
221#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
222 .conf = MAX1363_CHANNEL_SEL(_num) \
223 | MAX1363_CONFIG_SCAN_TO_CS \
224 | MAX1363_CONFIG_DE, \
32b5eeca 225 .modemask[0] = _mask \
58f0a255
JC		 226 }
227
228/* note only available for max1363 hence naming */
229#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
230 .conf = MAX1363_CHANNEL_SEL(_num) \
231 | MAX1236_SCAN_MID_TO_CHANNEL \
232 | MAX1363_CONFIG_SE, \
32b5eeca 233 .modemask[0] = _mask \
58f0a255 234}
82020b0e 235
82020b0e
JC		 236static const struct max1363_mode max1363_mode_table[] = {
237 /* All of the single channel options first */
238 MAX1363_MODE_SINGLE(0, 1 << 0),
239 MAX1363_MODE_SINGLE(1, 1 << 1),
240 MAX1363_MODE_SINGLE(2, 1 << 2),
241 MAX1363_MODE_SINGLE(3, 1 << 3),
242 MAX1363_MODE_SINGLE(4, 1 << 4),
243 MAX1363_MODE_SINGLE(5, 1 << 5),
244 MAX1363_MODE_SINGLE(6, 1 << 6),
245 MAX1363_MODE_SINGLE(7, 1 << 7),
246 MAX1363_MODE_SINGLE(8, 1 << 8),
247 MAX1363_MODE_SINGLE(9, 1 << 9),
248 MAX1363_MODE_SINGLE(10, 1 << 10),
249 MAX1363_MODE_SINGLE(11, 1 << 11),
250
251 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
252 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
253 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
254 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
255 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
256 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
257 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
258 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
259 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
260 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
261 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
262 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
263
264 /* The multichannel scans next */
265 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
266 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
268 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
282
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
d1325cf4
JC		 297};
298
b3bcbfcf 299static const struct max1363_mode
c52cfb63 300*max1363_match_mode(const unsigned long *mask,
71d2c120 301 const struct max1363_chip_info *ci)
1b183e4b 302{
82020b0e
JC		 303 int i;
304 if (mask)
305 for (i = 0; i < ci->num_modes; i++)
32b5eeca
JC		 306 if (bitmap_subset(mask,
307 max1363_mode_table[ci->mode_list[i]].
308 modemask,
309 MAX1363_MAX_CHANNELS))
1b183e4b
GKH		 310 return &max1363_mode_table[ci->mode_list[i]];
311 return NULL;
c608cb01 312}
82020b0e 313
82020b0e
JC		 314static int max1363_write_basic_config(struct i2c_client *client,
315 unsigned char d1,
316 unsigned char d2)
317{
58f0a255 318 u8 tx_buf[2] = {d1, d2};
82020b0e 319
58f0a255 320 return i2c_master_send(client, tx_buf, 2);
82020b0e
JC		 321}
322
b3bcbfcf 323static int max1363_set_scan_mode(struct max1363_state *st)
82020b0e
JC		 324{
325 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
326 | MAX1363_SCAN_MASK
327 | MAX1363_SE_DE_MASK);
328 st->configbyte |= st->current_mode->conf;
329
330 return max1363_write_basic_config(st->client,
331 st->setupbyte,
332 st->configbyte);
333}
334
298cd976
JC		 335static int max1363_read_single_chan(struct iio_dev *indio_dev,
336 struct iio_chan_spec const *chan,
337 int *val,
338 long m)
82020b0e 339{
298cd976
JC		 340 int ret = 0;
341 s32 data;
482bb4e6 342 u8 rxbuf[2];
298cd976
JC		 343 struct max1363_state *st = iio_priv(indio_dev);
344 struct i2c_client *client = st->client;
82020b0e 345
b6b7068c 346 mutex_lock(&indio_dev->mlock);
440a5200
JC		 347 /*
348 * If monitor mode is enabled, the method for reading a single
349 * channel will have to be rather different and has not yet
350 * been implemented.
3ca34cc4
JC		 351 *
352 * Also, cannot read directly if buffered capture enabled.
440a5200 353 */
3ca34cc4 354 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
440a5200
JC		 355 ret = -EBUSY;
356 goto error_ret;
357 }
358
3ca34cc4
JC		 359 /* Check to see if current scan mode is correct */
360 if (st->current_mode != &max1363_mode_table[chan->address]) {
361 /* Update scan mode if needed */
362 st->current_mode = &max1363_mode_table[chan->address];
363 ret = max1363_set_scan_mode(st);
364 if (ret < 0)
365 goto error_ret;
366 }
367 if (st->chip_info->bits != 8) {
368 /* Get reading */
369 data = i2c_master_recv(client, rxbuf, 2);
82020b0e
JC		 370 if (data < 0) {
371 ret = data;
372 goto error_ret;
373 }
482bb4e6
GR		 374 data = (rxbuf[1] | rxbuf[0] << 8) &
375 ((1 << st->chip_info->bits) - 1);
82020b0e 376 } else {
3ca34cc4
JC		 377 /* Get reading */
378 data = i2c_master_recv(client, rxbuf, 1);
379 if (data < 0) {
380 ret = data;
381 goto error_ret;
82020b0e 382 }
3ca34cc4 383 data = rxbuf[0];
82020b0e 384 }
298cd976 385 *val = data;
82020b0e 386error_ret:
b6b7068c 387 mutex_unlock(&indio_dev->mlock);
298cd976
JC		 388 return ret;
389
82020b0e
JC		 390}
391
298cd976
JC		 392static int max1363_read_raw(struct iio_dev *indio_dev,
393 struct iio_chan_spec const *chan,
394 int *val,
395 int *val2,
396 long m)
82020b0e 397{
298cd976
JC		 398 struct max1363_state *st = iio_priv(indio_dev);
399 int ret;
a405b00e
GR		 400 unsigned long scale_uv;
401
298cd976 402 switch (m) {
b11f98ff 403 case IIO_CHAN_INFO_RAW:
298cd976 404 ret = max1363_read_single_chan(indio_dev, chan, val, m);
cd038019 405 if (ret < 0)
298cd976
JC		 406 return ret;
407 return IIO_VAL_INT;
c8a9f805 408 case IIO_CHAN_INFO_SCALE:
a405b00e
GR		 409 scale_uv = st->vref_uv >> st->chip_info->bits;
410 *val = scale_uv / 1000;
411 *val2 = (scale_uv % 1000) * 1000;
412 return IIO_VAL_INT_PLUS_MICRO;
298cd976
JC		 413 default:
414 return -EINVAL;
415 }
416 return 0;
82020b0e
JC		 417}
418
d1325cf4
JC		 419/* Applies to max1363 */
420static const enum max1363_modes max1363_mode_list[] = {
421 _s0, _s1, _s2, _s3,
d1325cf4
JC		 422 s0to1, s0to2, s0to3,
423 d0m1, d2m3, d1m0, d3m2,
d1325cf4
JC		 424 d0m1to2m3, d1m0to3m2,
425};
426
298cd976
JC		 427#define MAX1363_EV_M \
428 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
429 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
f6e52e59 430
ade7ef7b
JC		 431#define MAX1363_CHAN_U(num, addr, si, bits, evmask) \
432 { \
433 .type = IIO_VOLTAGE, \
434 .indexed = 1, \
435 .channel = num, \
436 .address = addr, \
f6e52e59
JC		 437 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
438 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
bc234e72 439 .datasheet_name = "AIN"#num, \
18cffbed
JC		 440 .scan_type = { \
441 .sign = 'u', \
442 .realbits = bits, \
443 .storagebits = (bits > 8) ? 16 : 8, \
444 .endianness = IIO_BE, \
445 }, \
ade7ef7b
JC		 446 .scan_index = si, \
447 .event_mask = evmask, \
448 }
298cd976 449
298cd976 450/* bipolar channel */
ade7ef7b
JC		 451#define MAX1363_CHAN_B(num, num2, addr, si, bits, evmask) \
452 { \
453 .type = IIO_VOLTAGE, \
454 .differential = 1, \
455 .indexed = 1, \
456 .channel = num, \
457 .channel2 = num2, \
458 .address = addr, \
f6e52e59
JC		 459 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
460 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
bc234e72 461 .datasheet_name = "AIN"#num"-AIN"#num2, \
18cffbed
JC		 462 .scan_type = { \
463 .sign = 's', \
464 .realbits = bits, \
465 .storagebits = (bits > 8) ? 16 : 8, \
466 .endianness = IIO_BE, \
467 }, \
ade7ef7b
JC		 468 .scan_index = si, \
469 .event_mask = evmask, \
298cd976
JC		 470 }
471
ade7ef7b
JC		 472#define MAX1363_4X_CHANS(bits, em) { \
473 MAX1363_CHAN_U(0, _s0, 0, bits, em), \
474 MAX1363_CHAN_U(1, _s1, 1, bits, em), \
475 MAX1363_CHAN_U(2, _s2, 2, bits, em), \
476 MAX1363_CHAN_U(3, _s3, 3, bits, em), \
477 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, em), \
478 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, em), \
479 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, em), \
480 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, em), \
481 IIO_CHAN_SOFT_TIMESTAMP(8) \
482 }
483
f4e4b955
LPC		 484static const struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
485static const struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
486static const struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
487static const struct iio_chan_spec max1361_channels[] =
ade7ef7b 488 MAX1363_4X_CHANS(10, MAX1363_EV_M);
f4e4b955 489static const struct iio_chan_spec max1363_channels[] =
ade7ef7b 490 MAX1363_4X_CHANS(12, MAX1363_EV_M);
298cd976 491
4abf6f8b 492/* Applies to max1236, max1237 */
d1325cf4
JC		 493static const enum max1363_modes max1236_mode_list[] = {
494 _s0, _s1, _s2, _s3,
d1325cf4
JC		 495 s0to1, s0to2, s0to3,
496 d0m1, d2m3, d1m0, d3m2,
d1325cf4
JC		 497 d0m1to2m3, d1m0to3m2,
498 s2to3,
499};
500
501/* Applies to max1238, max1239 */
502static const enum max1363_modes max1238_mode_list[] = {
503 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
d1325cf4
JC		 504 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
505 s0to7, s0to8, s0to9, s0to10, s0to11,
506 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
507 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
d1325cf4
JC		 508 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
509 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
510 s6to7, s6to8, s6to9, s6to10, s6to11,
82020b0e 511 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
d1325cf4
JC		 512};
513
298cd976 514#define MAX1363_12X_CHANS(bits) { \
ade7ef7b
JC		 515 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
516 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
517 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
518 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
519 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
520 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
521 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
522 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
523 MAX1363_CHAN_U(8, _s8, 8, bits, 0), \
524 MAX1363_CHAN_U(9, _s9, 9, bits, 0), \
525 MAX1363_CHAN_U(10, _s10, 10, bits, 0), \
526 MAX1363_CHAN_U(11, _s11, 11, bits, 0), \
527 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, 0), \
528 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, 0), \
529 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, 0), \
530 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, 0), \
531 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, 0), \
532 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, 0), \
533 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, 0), \
534 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, 0), \
535 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, 0), \
536 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, 0), \
537 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, 0), \
538 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, 0), \
298cd976
JC		 539 IIO_CHAN_SOFT_TIMESTAMP(24) \
540 }
f4e4b955
LPC		 541static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
542static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
543static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
d1325cf4 544
c3fa0fdd
JC		 545static const enum max1363_modes max11607_mode_list[] = {
546 _s0, _s1, _s2, _s3,
547 s0to1, s0to2, s0to3,
548 s2to3,
549 d0m1, d2m3, d1m0, d3m2,
550 d0m1to2m3, d1m0to3m2,
551};
552
553static const enum max1363_modes max11608_mode_list[] = {
554 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
555 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
556 s6to7,
557 d0m1, d2m3, d4m5, d6m7,
558 d1m0, d3m2, d5m4, d7m6,
559 d0m1to2m3, d0m1to4m5, d0m1to6m7,
560 d1m0to3m2, d1m0to5m4, d1m0to7m6,
561};
562
ade7ef7b
JC		 563#define MAX1363_8X_CHANS(bits) { \
564 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
565 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
566 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
567 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
568 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
569 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
570 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
571 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
572 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, 0), \
573 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, 0), \
574 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, 0), \
575 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, 0), \
576 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, 0), \
577 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, 0), \
578 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, 0), \
579 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, 0), \
580 IIO_CHAN_SOFT_TIMESTAMP(16) \
581}
f4e4b955
LPC		 582static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
583static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
584static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
c3fa0fdd 585
586d1525
JC		 586static const enum max1363_modes max11644_mode_list[] = {
587 _s0, _s1, s0to1, d0m1, d1m0,
588};
589
590#define MAX1363_2X_CHANS(bits) { \
ade7ef7b
JC		 591 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
592 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
593 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, 0), \
594 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, 0), \
586d1525
JC		 595 IIO_CHAN_SOFT_TIMESTAMP(4) \
596 }
597
f4e4b955
LPC		 598static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
599static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
586d1525 600
d1325cf4
JC		 601enum { max1361,
602 max1362,
603 max1363,
604 max1364,
3bf877c1
JC		 605 max1036,
606 max1037,
607 max1038,
608 max1039,
d1325cf4
JC		 609 max1136,
610 max1137,
611 max1138,
612 max1139,
613 max1236,
614 max1237,
615 max1238,
616 max1239,
3bf877c1
JC		 617 max11600,
618 max11601,
619 max11602,
620 max11603,
621 max11604,
622 max11605,
c3fa0fdd
JC		 623 max11606,
624 max11607,
625 max11608,
626 max11609,
627 max11610,
628 max11611,
629 max11612,
630 max11613,
631 max11614,
632 max11615,
633 max11616,
634 max11617,
586d1525
JC		 635 max11644,
636 max11645,
637 max11646,
638 max11647
d1325cf4
JC		 639};
640
440a5200
JC		 641static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
642 8300, 4200, 2000, 1000 };
643
644static ssize_t max1363_monitor_show_freq(struct device *dev,
645 struct device_attribute *attr,
646 char *buf)
647{
62c51839 648 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
440a5200
JC		 649 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
650}
651
652static ssize_t max1363_monitor_store_freq(struct device *dev,
653 struct device_attribute *attr,
654 const char *buf,
655 size_t len)
656{
62c51839 657 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
3dba81ba 658 struct max1363_state *st = iio_priv(indio_dev);
440a5200
JC		 659 int i, ret;
660 unsigned long val;
661 bool found = false;
662
ddeb64f3 663 ret = kstrtoul(buf, 10, &val);
440a5200
JC		 664 if (ret)
665 return -EINVAL;
666 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
667 if (val == max1363_monitor_speeds[i]) {
668 found = true;
669 break;
670 }
671 if (!found)
672 return -EINVAL;
673
b6b7068c 674 mutex_lock(&indio_dev->mlock);
440a5200 675 st->monitor_speed = i;
b6b7068c 676 mutex_unlock(&indio_dev->mlock);
440a5200
JC		 677
678 return 0;
679}
680
681static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
682 max1363_monitor_show_freq,
683 max1363_monitor_store_freq);
684
685static IIO_CONST_ATTR(sampling_frequency_available,
686 "133000 665000 33300 16600 8300 4200 2000 1000");
687
298cd976 688static int max1363_read_thresh(struct iio_dev *indio_dev,
330c6c57 689 u64 event_code,
298cd976 690 int *val)
440a5200 691{
3dba81ba 692 struct max1363_state *st = iio_priv(indio_dev);
298cd976 693 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
da367160 694 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
440a5200 695 else
da367160 696 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
298cd976 697 return 0;
440a5200
JC		 698}
699
298cd976 700static int max1363_write_thresh(struct iio_dev *indio_dev,
330c6c57 701 u64 event_code,
298cd976 702 int val)
440a5200 703{
298cd976
JC		 704 struct max1363_state *st = iio_priv(indio_dev);
705 /* make it handle signed correctly as well */
440a5200
JC		 706 switch (st->chip_info->bits) {
707 case 10:
708 if (val > 0x3FF)
709 return -EINVAL;
710 break;
711 case 12:
712 if (val > 0xFFF)
713 return -EINVAL;
714 break;
715 }
716
298cd976
JC		 717 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
718 case IIO_EV_DIR_FALLING:
da367160 719 st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
440a5200 720 break;
298cd976 721 case IIO_EV_DIR_RISING:
da367160 722 st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
440a5200
JC		 723 break;
724 }
725
440a5200
JC		 726 return 0;
727}
728
330c6c57 729static const u64 max1363_event_codes[] = {
6835cb6b
JC		 730 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
731 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
732 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
733 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
734 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
735 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
736 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
737 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
738 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
739 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
740 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
741 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
742 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
743 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
744 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
745 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
58f0a255
JC		 746};
747
aaf370db 748static irqreturn_t max1363_event_handler(int irq, void *private)
440a5200 749{
aaf370db
JC		 750 struct iio_dev *indio_dev = private;
751 struct max1363_state *st = iio_priv(indio_dev);
752 s64 timestamp = iio_get_time_ns();
58f0a255 753 unsigned long mask, loc;
440a5200
JC		 754 u8 rx;
755 u8 tx[2] = { st->setupbyte,
756 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
757
758 i2c_master_recv(st->client, &rx, 1);
58f0a255
JC		 759 mask = rx;
760 for_each_set_bit(loc, &mask, 8)
5aa96188 761 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
440a5200 762 i2c_master_send(st->client, tx, 2);
aaf370db
JC		 763
764 return IRQ_HANDLED;
440a5200
JC		 765}
766
298cd976 767static int max1363_read_event_config(struct iio_dev *indio_dev,
330c6c57 768 u64 event_code)
440a5200 769{
3dba81ba 770 struct max1363_state *st = iio_priv(indio_dev);
298cd976 771 int val;
da367160 772 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
0d9fa2ce 773
b6b7068c 774 mutex_lock(&indio_dev->mlock);
298cd976
JC		 775 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
776 val = (1 << number) & st->mask_low;
440a5200 777 else
298cd976 778 val = (1 << number) & st->mask_high;
b6b7068c 779 mutex_unlock(&indio_dev->mlock);
440a5200 780
298cd976 781 return val;
440a5200
JC		 782}
783
784static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
785{
786 u8 *tx_buf;
787 int ret, i = 3, j;
788 unsigned long numelements;
789 int len;
32b5eeca 790 const long *modemask;
440a5200
JC		 791
792 if (!enabled) {
ec443728 793 /* transition to buffered capture is not currently supported */
440a5200
JC		 794 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
795 st->configbyte &= ~MAX1363_SCAN_MASK;
796 st->monitor_on = false;
797 return max1363_write_basic_config(st->client,
798 st->setupbyte,
799 st->configbyte);
800 }
801
802 /* Ensure we are in the relevant mode */
803 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
804 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
805 | MAX1363_SCAN_MASK
806 | MAX1363_SE_DE_MASK);
807 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
808 if ((st->mask_low | st->mask_high) & 0x0F) {
809 st->configbyte |= max1363_mode_table[s0to3].conf;
810 modemask = max1363_mode_table[s0to3].modemask;
811 } else if ((st->mask_low | st->mask_high) & 0x30) {
812 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
813 modemask = max1363_mode_table[d0m1to2m3].modemask;
814 } else {
815 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
816 modemask = max1363_mode_table[d1m0to3m2].modemask;
817 }
32b5eeca 818 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
440a5200
JC		 819 len = 3 * numelements + 3;
820 tx_buf = kmalloc(len, GFP_KERNEL);
821 if (!tx_buf) {
822 ret = -ENOMEM;
823 goto error_ret;
824 }
825 tx_buf[0] = st->configbyte;
826 tx_buf[1] = st->setupbyte;
827 tx_buf[2] = (st->monitor_speed << 1);
828
829 /*
830 * So we need to do yet another bit of nefarious scan mode
831 * setup to match what we need.
832 */
833 for (j = 0; j < 8; j++)
32b5eeca 834 if (test_bit(j, modemask)) {
440a5200
JC		 835 /* Establish the mode is in the scan */
836 if (st->mask_low & (1 << j)) {
837 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
838 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
839 } else if (j < 4) {
840 tx_buf[i] = 0;
841 tx_buf[i + 1] = 0;
842 } else {
843 tx_buf[i] = 0x80;
844 tx_buf[i + 1] = 0;
845 }
846 if (st->mask_high & (1 << j)) {
847 tx_buf[i + 1] |=
848 (st->thresh_high[j] >> 8) & 0x0F;
849 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
850 } else if (j < 4) {
851 tx_buf[i + 1] |= 0x0F;
852 tx_buf[i + 2] = 0xFF;
853 } else {
854 tx_buf[i + 1] |= 0x07;
855 tx_buf[i + 2] = 0xFF;
856 }
857 i += 3;
858 }
859
860
861 ret = i2c_master_send(st->client, tx_buf, len);
862 if (ret < 0)
863 goto error_ret;
864 if (ret != len) {
865 ret = -EIO;
866 goto error_ret;
867 }
868
869 /*
870 * Now that we hopefully have sensible thresholds in place it is
871 * time to turn the interrupts on.
872 * It is unclear from the data sheet if this should be necessary
873 * (i.e. whether monitor mode setup is atomic) but it appears to
874 * be in practice.
875 */
876 tx_buf[0] = st->setupbyte;
877 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
878 ret = i2c_master_send(st->client, tx_buf, 2);
879 if (ret < 0)
880 goto error_ret;
881 if (ret != 2) {
882 ret = -EIO;
883 goto error_ret;
884 }
885 ret = 0;
886 st->monitor_on = true;
887error_ret:
888
889 kfree(tx_buf);
890
891 return ret;
892}
893
894/*
25985edc 895 * To keep this manageable we always use one of 3 scan modes.
440a5200
JC		 896 * Scan 0...3, 0-1,2-3 and 1-0,3-2
897 */
298cd976 898
440a5200
JC		 899static inline int __max1363_check_event_mask(int thismask, int checkmask)
900{
901 int ret = 0;
902 /* Is it unipolar */
903 if (thismask < 4) {
904 if (checkmask & ~0x0F) {
905 ret = -EBUSY;
906 goto error_ret;
907 }
908 } else if (thismask < 6) {
909 if (checkmask & ~0x30) {
910 ret = -EBUSY;
911 goto error_ret;
912 }
913 } else if (checkmask & ~0xC0)
914 ret = -EBUSY;
915error_ret:
916 return ret;
917}
918
298cd976 919static int max1363_write_event_config(struct iio_dev *indio_dev,
330c6c57 920 u64 event_code,
298cd976 921 int state)
440a5200 922{
298cd976 923 int ret = 0;
3dba81ba 924 struct max1363_state *st = iio_priv(indio_dev);
440a5200 925 u16 unifiedmask;
da367160 926 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
298cd976 927
3dba81ba 928 mutex_lock(&indio_dev->mlock);
440a5200 929 unifiedmask = st->mask_low | st->mask_high;
298cd976
JC		 930 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
931
932 if (state == 0)
933 st->mask_low &= ~(1 << number);
440a5200 934 else {
298cd976
JC		 935 ret = __max1363_check_event_mask((1 << number),
936 unifiedmask);
440a5200
JC		 937 if (ret)
938 goto error_ret;
298cd976 939 st->mask_low |= (1 << number);
440a5200
JC		 940 }
941 } else {
298cd976
JC		 942 if (state == 0)
943 st->mask_high &= ~(1 << number);
440a5200 944 else {
298cd976
JC		 945 ret = __max1363_check_event_mask((1 << number),
946 unifiedmask);
440a5200
JC		 947 if (ret)
948 goto error_ret;
298cd976 949 st->mask_high |= (1 << number);
440a5200
JC		 950 }
951 }
440a5200
JC		 952
953 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
954error_ret:
3dba81ba 955 mutex_unlock(&indio_dev->mlock);
440a5200 956
298cd976 957 return ret;
440a5200
JC		 958}
959
440a5200
JC		 960/*
961 * As with scan_elements, only certain sets of these can
962 * be combined.
963 */
964static struct attribute *max1363_event_attributes[] = {
440a5200
JC		 965 &iio_dev_attr_sampling_frequency.dev_attr.attr,
966 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
440a5200
JC		 967 NULL,
968};
969
6fe8135f
JC		 970static struct attribute_group max1363_event_attribute_group = {
971 .attrs = max1363_event_attributes,
8e7d9672 972 .name = "events",
6fe8135f
JC		 973};
974
b3bcbfcf
JC		 975static int max1363_update_scan_mode(struct iio_dev *indio_dev,
976 const unsigned long *scan_mask)
977{
978 struct max1363_state *st = iio_priv(indio_dev);
979
980 /*
981 * Need to figure out the current mode based upon the requested
982 * scan mask in iio_dev
983 */
984 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
985 if (!st->current_mode)
986 return -EINVAL;
987 max1363_set_scan_mode(st);
988 return 0;
989}
6fe8135f
JC		 990
991static const struct iio_info max1238_info = {
992 .read_raw = &max1363_read_raw,
993 .driver_module = THIS_MODULE,
a9ea1b17 994 .update_scan_mode = &max1363_update_scan_mode,
6fe8135f
JC		 995};
996
997static const struct iio_info max1363_info = {
998 .read_event_value = &max1363_read_thresh,
999 .write_event_value = &max1363_write_thresh,
1000 .read_event_config = &max1363_read_event_config,
1001 .write_event_config = &max1363_write_event_config,
1002 .read_raw = &max1363_read_raw,
c52cfb63 1003 .update_scan_mode = &max1363_update_scan_mode,
6fe8135f 1004 .driver_module = THIS_MODULE,
6fe8135f
JC		 1005 .event_attrs = &max1363_event_attribute_group,
1006};
1007
1008/* max1363 and max1368 tested - rest from data sheet */
1009static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1010 [max1361] = {
1011 .bits = 10,
1012 .int_vref_mv = 2048,
1013 .mode_list = max1363_mode_list,
1014 .num_modes = ARRAY_SIZE(max1363_mode_list),
1015 .default_mode = s0to3,
1016 .channels = max1361_channels,
1017 .num_channels = ARRAY_SIZE(max1361_channels),
1018 .info = &max1363_info,
1019 },
1020 [max1362] = {
1021 .bits = 10,
1022 .int_vref_mv = 4096,
1023 .mode_list = max1363_mode_list,
1024 .num_modes = ARRAY_SIZE(max1363_mode_list),
1025 .default_mode = s0to3,
1026 .channels = max1361_channels,
1027 .num_channels = ARRAY_SIZE(max1361_channels),
1028 .info = &max1363_info,
1029 },
1030 [max1363] = {
1031 .bits = 12,
1032 .int_vref_mv = 2048,
1033 .mode_list = max1363_mode_list,
1034 .num_modes = ARRAY_SIZE(max1363_mode_list),
1035 .default_mode = s0to3,
1036 .channels = max1363_channels,
1037 .num_channels = ARRAY_SIZE(max1363_channels),
1038 .info = &max1363_info,
1039 },
1040 [max1364] = {
1041 .bits = 12,
1042 .int_vref_mv = 4096,
1043 .mode_list = max1363_mode_list,
1044 .num_modes = ARRAY_SIZE(max1363_mode_list),
1045 .default_mode = s0to3,
1046 .channels = max1363_channels,
1047 .num_channels = ARRAY_SIZE(max1363_channels),
1048 .info = &max1363_info,
1049 },
1050 [max1036] = {
1051 .bits = 8,
1052 .int_vref_mv = 4096,
1053 .mode_list = max1236_mode_list,
1054 .num_modes = ARRAY_SIZE(max1236_mode_list),
1055 .default_mode = s0to3,
1056 .info = &max1238_info,
1057 .channels = max1036_channels,
1058 .num_channels = ARRAY_SIZE(max1036_channels),
1059 },
1060 [max1037] = {
1061 .bits = 8,
1062 .int_vref_mv = 2048,
1063 .mode_list = max1236_mode_list,
1064 .num_modes = ARRAY_SIZE(max1236_mode_list),
1065 .default_mode = s0to3,
1066 .info = &max1238_info,
1067 .channels = max1036_channels,
1068 .num_channels = ARRAY_SIZE(max1036_channels),
1069 },
1070 [max1038] = {
1071 .bits = 8,
1072 .int_vref_mv = 4096,
1073 .mode_list = max1238_mode_list,
1074 .num_modes = ARRAY_SIZE(max1238_mode_list),
1075 .default_mode = s0to11,
1076 .info = &max1238_info,
1077 .channels = max1038_channels,
1078 .num_channels = ARRAY_SIZE(max1038_channels),
1079 },
1080 [max1039] = {
1081 .bits = 8,
1082 .int_vref_mv = 2048,
1083 .mode_list = max1238_mode_list,
1084 .num_modes = ARRAY_SIZE(max1238_mode_list),
1085 .default_mode = s0to11,
1086 .info = &max1238_info,
1087 .channels = max1038_channels,
1088 .num_channels = ARRAY_SIZE(max1038_channels),
1089 },
1090 [max1136] = {
1091 .bits = 10,
1092 .int_vref_mv = 4096,
1093 .mode_list = max1236_mode_list,
1094 .num_modes = ARRAY_SIZE(max1236_mode_list),
1095 .default_mode = s0to3,
1096 .info = &max1238_info,
1097 .channels = max1136_channels,
1098 .num_channels = ARRAY_SIZE(max1136_channels),
1099 },
1100 [max1137] = {
1101 .bits = 10,
1102 .int_vref_mv = 2048,
1103 .mode_list = max1236_mode_list,
1104 .num_modes = ARRAY_SIZE(max1236_mode_list),
1105 .default_mode = s0to3,
1106 .info = &max1238_info,
1107 .channels = max1136_channels,
1108 .num_channels = ARRAY_SIZE(max1136_channels),
1109 },
1110 [max1138] = {
1111 .bits = 10,
1112 .int_vref_mv = 4096,
1113 .mode_list = max1238_mode_list,
1114 .num_modes = ARRAY_SIZE(max1238_mode_list),
1115 .default_mode = s0to11,
1116 .info = &max1238_info,
1117 .channels = max1138_channels,
1118 .num_channels = ARRAY_SIZE(max1138_channels),
1119 },
1120 [max1139] = {
1121 .bits = 10,
1122 .int_vref_mv = 2048,
1123 .mode_list = max1238_mode_list,
1124 .num_modes = ARRAY_SIZE(max1238_mode_list),
1125 .default_mode = s0to11,
1126 .info = &max1238_info,
1127 .channels = max1138_channels,
1128 .num_channels = ARRAY_SIZE(max1138_channels),
1129 },
1130 [max1236] = {
1131 .bits = 12,
1132 .int_vref_mv = 4096,
1133 .mode_list = max1236_mode_list,
1134 .num_modes = ARRAY_SIZE(max1236_mode_list),
1135 .default_mode = s0to3,
1136 .info = &max1238_info,
1137 .channels = max1236_channels,
1138 .num_channels = ARRAY_SIZE(max1236_channels),
1139 },
1140 [max1237] = {
1141 .bits = 12,
1142 .int_vref_mv = 2048,
1143 .mode_list = max1236_mode_list,
1144 .num_modes = ARRAY_SIZE(max1236_mode_list),
1145 .default_mode = s0to3,
1146 .info = &max1238_info,
1147 .channels = max1236_channels,
1148 .num_channels = ARRAY_SIZE(max1236_channels),
1149 },
1150 [max1238] = {
1151 .bits = 12,
1152 .int_vref_mv = 4096,
1153 .mode_list = max1238_mode_list,
1154 .num_modes = ARRAY_SIZE(max1238_mode_list),
1155 .default_mode = s0to11,
1156 .info = &max1238_info,
1157 .channels = max1238_channels,
1158 .num_channels = ARRAY_SIZE(max1238_channels),
1159 },
1160 [max1239] = {
1161 .bits = 12,
1162 .int_vref_mv = 2048,
1163 .mode_list = max1238_mode_list,
1164 .num_modes = ARRAY_SIZE(max1238_mode_list),
1165 .default_mode = s0to11,
1166 .info = &max1238_info,
1167 .channels = max1238_channels,
1168 .num_channels = ARRAY_SIZE(max1238_channels),
1169 },
1170 [max11600] = {
1171 .bits = 8,
1172 .int_vref_mv = 4096,
1173 .mode_list = max11607_mode_list,
1174 .num_modes = ARRAY_SIZE(max11607_mode_list),
1175 .default_mode = s0to3,
1176 .info = &max1238_info,
1177 .channels = max1036_channels,
1178 .num_channels = ARRAY_SIZE(max1036_channels),
1179 },
1180 [max11601] = {
1181 .bits = 8,
1182 .int_vref_mv = 2048,
1183 .mode_list = max11607_mode_list,
1184 .num_modes = ARRAY_SIZE(max11607_mode_list),
1185 .default_mode = s0to3,
1186 .info = &max1238_info,
1187 .channels = max1036_channels,
1188 .num_channels = ARRAY_SIZE(max1036_channels),
1189 },
1190 [max11602] = {
1191 .bits = 8,
1192 .int_vref_mv = 4096,
1193 .mode_list = max11608_mode_list,
1194 .num_modes = ARRAY_SIZE(max11608_mode_list),
1195 .default_mode = s0to7,
1196 .info = &max1238_info,
1197 .channels = max11602_channels,
1198 .num_channels = ARRAY_SIZE(max11602_channels),
1199 },
1200 [max11603] = {
1201 .bits = 8,
1202 .int_vref_mv = 2048,
1203 .mode_list = max11608_mode_list,
1204 .num_modes = ARRAY_SIZE(max11608_mode_list),
1205 .default_mode = s0to7,
1206 .info = &max1238_info,
1207 .channels = max11602_channels,
1208 .num_channels = ARRAY_SIZE(max11602_channels),
1209 },
1210 [max11604] = {
1211 .bits = 8,
1212 .int_vref_mv = 4098,
1213 .mode_list = max1238_mode_list,
1214 .num_modes = ARRAY_SIZE(max1238_mode_list),
1215 .default_mode = s0to11,
1216 .info = &max1238_info,
1217 .channels = max1238_channels,
1218 .num_channels = ARRAY_SIZE(max1238_channels),
1219 },
1220 [max11605] = {
1221 .bits = 8,
1222 .int_vref_mv = 2048,
1223 .mode_list = max1238_mode_list,
1224 .num_modes = ARRAY_SIZE(max1238_mode_list),
1225 .default_mode = s0to11,
1226 .info = &max1238_info,
1227 .channels = max1238_channels,
1228 .num_channels = ARRAY_SIZE(max1238_channels),
1229 },
1230 [max11606] = {
1231 .bits = 10,
1232 .int_vref_mv = 4096,
1233 .mode_list = max11607_mode_list,
1234 .num_modes = ARRAY_SIZE(max11607_mode_list),
1235 .default_mode = s0to3,
1236 .info = &max1238_info,
1237 .channels = max1136_channels,
1238 .num_channels = ARRAY_SIZE(max1136_channels),
1239 },
1240 [max11607] = {
1241 .bits = 10,
1242 .int_vref_mv = 2048,
1243 .mode_list = max11607_mode_list,
1244 .num_modes = ARRAY_SIZE(max11607_mode_list),
1245 .default_mode = s0to3,
1246 .info = &max1238_info,
1247 .channels = max1136_channels,
1248 .num_channels = ARRAY_SIZE(max1136_channels),
1249 },
1250 [max11608] = {
1251 .bits = 10,
1252 .int_vref_mv = 4096,
1253 .mode_list = max11608_mode_list,
1254 .num_modes = ARRAY_SIZE(max11608_mode_list),
1255 .default_mode = s0to7,
1256 .info = &max1238_info,
1257 .channels = max11608_channels,
1258 .num_channels = ARRAY_SIZE(max11608_channels),
1259 },
1260 [max11609] = {
1261 .bits = 10,
1262 .int_vref_mv = 2048,
1263 .mode_list = max11608_mode_list,
1264 .num_modes = ARRAY_SIZE(max11608_mode_list),
1265 .default_mode = s0to7,
1266 .info = &max1238_info,
1267 .channels = max11608_channels,
1268 .num_channels = ARRAY_SIZE(max11608_channels),
1269 },
1270 [max11610] = {
1271 .bits = 10,
1272 .int_vref_mv = 4098,
1273 .mode_list = max1238_mode_list,
1274 .num_modes = ARRAY_SIZE(max1238_mode_list),
1275 .default_mode = s0to11,
1276 .info = &max1238_info,
1277 .channels = max1238_channels,
1278 .num_channels = ARRAY_SIZE(max1238_channels),
1279 },
1280 [max11611] = {
1281 .bits = 10,
1282 .int_vref_mv = 2048,
1283 .mode_list = max1238_mode_list,
1284 .num_modes = ARRAY_SIZE(max1238_mode_list),
1285 .default_mode = s0to11,
1286 .info = &max1238_info,
1287 .channels = max1238_channels,
1288 .num_channels = ARRAY_SIZE(max1238_channels),
1289 },
1290 [max11612] = {
1291 .bits = 12,
1292 .int_vref_mv = 4096,
1293 .mode_list = max11607_mode_list,
1294 .num_modes = ARRAY_SIZE(max11607_mode_list),
1295 .default_mode = s0to3,
1296 .info = &max1238_info,
1297 .channels = max1363_channels,
1298 .num_channels = ARRAY_SIZE(max1363_channels),
1299 },
1300 [max11613] = {
1301 .bits = 12,
1302 .int_vref_mv = 2048,
1303 .mode_list = max11607_mode_list,
1304 .num_modes = ARRAY_SIZE(max11607_mode_list),
1305 .default_mode = s0to3,
1306 .info = &max1238_info,
1307 .channels = max1363_channels,
1308 .num_channels = ARRAY_SIZE(max1363_channels),
1309 },
1310 [max11614] = {
1311 .bits = 12,
1312 .int_vref_mv = 4096,
1313 .mode_list = max11608_mode_list,
1314 .num_modes = ARRAY_SIZE(max11608_mode_list),
1315 .default_mode = s0to7,
1316 .info = &max1238_info,
1317 .channels = max11614_channels,
1318 .num_channels = ARRAY_SIZE(max11614_channels),
1319 },
1320 [max11615] = {
1321 .bits = 12,
1322 .int_vref_mv = 2048,
1323 .mode_list = max11608_mode_list,
1324 .num_modes = ARRAY_SIZE(max11608_mode_list),
1325 .default_mode = s0to7,
1326 .info = &max1238_info,
1327 .channels = max11614_channels,
1328 .num_channels = ARRAY_SIZE(max11614_channels),
1329 },
1330 [max11616] = {
1331 .bits = 12,
1332 .int_vref_mv = 4098,
1333 .mode_list = max1238_mode_list,
1334 .num_modes = ARRAY_SIZE(max1238_mode_list),
1335 .default_mode = s0to11,
1336 .info = &max1238_info,
1337 .channels = max1238_channels,
1338 .num_channels = ARRAY_SIZE(max1238_channels),
1339 },
1340 [max11617] = {
1341 .bits = 12,
1342 .int_vref_mv = 2048,
1343 .mode_list = max1238_mode_list,
1344 .num_modes = ARRAY_SIZE(max1238_mode_list),
1345 .default_mode = s0to11,
1346 .info = &max1238_info,
1347 .channels = max1238_channels,
1348 .num_channels = ARRAY_SIZE(max1238_channels),
1349 },
1350 [max11644] = {
1351 .bits = 12,
1352 .int_vref_mv = 2048,
1353 .mode_list = max11644_mode_list,
1354 .num_modes = ARRAY_SIZE(max11644_mode_list),
1355 .default_mode = s0to1,
1356 .info = &max1238_info,
1357 .channels = max11644_channels,
1358 .num_channels = ARRAY_SIZE(max11644_channels),
1359 },
1360 [max11645] = {
1361 .bits = 12,
1362 .int_vref_mv = 4096,
1363 .mode_list = max11644_mode_list,
1364 .num_modes = ARRAY_SIZE(max11644_mode_list),
1365 .default_mode = s0to1,
1366 .info = &max1238_info,
1367 .channels = max11644_channels,
1368 .num_channels = ARRAY_SIZE(max11644_channels),
1369 },
1370 [max11646] = {
1371 .bits = 10,
1372 .int_vref_mv = 2048,
1373 .mode_list = max11644_mode_list,
1374 .num_modes = ARRAY_SIZE(max11644_mode_list),
1375 .default_mode = s0to1,
1376 .info = &max1238_info,
1377 .channels = max11646_channels,
1378 .num_channels = ARRAY_SIZE(max11646_channels),
1379 },
1380 [max11647] = {
1381 .bits = 10,
1382 .int_vref_mv = 4096,
1383 .mode_list = max11644_mode_list,
1384 .num_modes = ARRAY_SIZE(max11644_mode_list),
1385 .default_mode = s0to1,
1386 .info = &max1238_info,
1387 .channels = max11646_channels,
1388 .num_channels = ARRAY_SIZE(max11646_channels),
1389 },
1390};
1391
d1325cf4
JC		 1392static int max1363_initial_setup(struct max1363_state *st)
1393{
a405b00e 1394 st->setupbyte = MAX1363_SETUP_INT_CLOCK
d1325cf4
JC		 1395 | MAX1363_SETUP_UNIPOLAR
1396 | MAX1363_SETUP_NORESET;
1397
a405b00e
GR		 1398 if (st->vref)
1399 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1400 else
1401 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1402 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1403
71d2c120 1404 /* Set scan mode writes the config anyway so wait until then */
d1325cf4
JC		 1405 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1406 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1407 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1408
1409 return max1363_set_scan_mode(st);
1410}
1411
fc52692c 1412static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
cd4361c7
MH		 1413{
1414 struct max1363_state *st = iio_priv(indio_dev);
1415 unsigned long *masks;
1416 int i;
1417
7c3e8675
GR		 1418 masks = devm_kzalloc(&indio_dev->dev,
1419 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) *
1420 (st->chip_info->num_modes + 1), GFP_KERNEL);
cd4361c7
MH		 1421 if (!masks)
1422 return -ENOMEM;
1423
1424 for (i = 0; i < st->chip_info->num_modes; i++)
1425 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1426 max1363_mode_table[st->chip_info->mode_list[i]]
1427 .modemask, MAX1363_MAX_CHANNELS);
1428
1429 indio_dev->available_scan_masks = masks;
1430
1431 return 0;
1432}
1433
b3bcbfcf
JC		 1434static irqreturn_t max1363_trigger_handler(int irq, void *p)
1435{
1436 struct iio_poll_func *pf = p;
1437 struct iio_dev *indio_dev = pf->indio_dev;
1438 struct max1363_state *st = iio_priv(indio_dev);
1439 s64 time_ns;
1440 __u8 *rxbuf;
1441 int b_sent;
1442 size_t d_size;
1443 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1444 MAX1363_MAX_CHANNELS);
1445
1446 /* Ensure the timestamp is 8 byte aligned */
1447 if (st->chip_info->bits != 8)
1448 d_size = numvals*2;
1449 else
1450 d_size = numvals;
1451 if (indio_dev->scan_timestamp) {
1452 d_size += sizeof(s64);
1453 if (d_size % sizeof(s64))
1454 d_size += sizeof(s64) - (d_size % sizeof(s64));
1455 }
1456 /* Monitor mode prevents reading. Whilst not currently implemented
1457 * might as well have this test in here in the meantime as it does
1458 * no harm.
1459 */
1460 if (numvals == 0)
1461 goto done;
1462
1463 rxbuf = kmalloc(d_size, GFP_KERNEL);
1464 if (rxbuf == NULL)
1465 goto done;
1466 if (st->chip_info->bits != 8)
1467 b_sent = i2c_master_recv(st->client, rxbuf, numvals*2);
1468 else
1469 b_sent = i2c_master_recv(st->client, rxbuf, numvals);
1470 if (b_sent < 0)
1471 goto done_free;
1472
1473 time_ns = iio_get_time_ns();
1474
1475 if (indio_dev->scan_timestamp)
1476 memcpy(rxbuf + d_size - sizeof(s64), &time_ns, sizeof(time_ns));
1477 iio_push_to_buffers(indio_dev, rxbuf);
1478
1479done_free:
1480 kfree(rxbuf);
1481done:
1482 iio_trigger_notify_done(indio_dev->trig);
1483
1484 return IRQ_HANDLED;
1485}
1486
ec443728 1487static const struct iio_buffer_setup_ops max1363_buffered_setup_ops = {
b3bcbfcf
JC		 1488 .postenable = &iio_triggered_buffer_postenable,
1489 .preenable = &iio_sw_buffer_preenable,
1490 .predisable = &iio_triggered_buffer_predisable,
1491};
1492
fc52692c
GKH		 1493static int max1363_probe(struct i2c_client *client,
1494 const struct i2c_device_id *id)
d1325cf4 1495{
cd4361c7 1496 int ret;
3dba81ba
JC		 1497 struct max1363_state *st;
1498 struct iio_dev *indio_dev;
a405b00e 1499 struct regulator *vref;
f88af7e7 1500
7cbb7537 1501 indio_dev = iio_device_alloc(sizeof(struct max1363_state));
3dba81ba 1502 if (indio_dev == NULL) {
d1325cf4 1503 ret = -ENOMEM;
b77b8f8c 1504 goto error_out;
d1325cf4 1505 }
b77b8f8c 1506
315ce4b8 1507 indio_dev->dev.of_node = client->dev.of_node;
0b27d678
JC		 1508 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1509 if (ret < 0)
1510 goto error_free_device;
b77b8f8c 1511
3dba81ba 1512 st = iio_priv(indio_dev);
b77b8f8c 1513
7c3e8675 1514 st->reg = devm_regulator_get(&client->dev, "vcc");
b77b8f8c
JC		 1515 if (IS_ERR(st->reg)) {
1516 ret = PTR_ERR(st->reg);
1517 goto error_unregister_map;
1518 }
1519
1520 ret = regulator_enable(st->reg);
1521 if (ret)
7c3e8675 1522 goto error_unregister_map;
b77b8f8c 1523
3dba81ba
JC		 1524 /* this is only used for device removal purposes */
1525 i2c_set_clientdata(client, indio_dev);
1526
3dba81ba
JC		 1527 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1528 st->client = client;
d1325cf4 1529
a405b00e
GR		 1530 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1531 vref = devm_regulator_get(&client->dev, "vref");
1532 if (!IS_ERR(vref)) {
1533 int vref_uv;
1534
1535 ret = regulator_enable(vref);
1536 if (ret)
1537 goto error_disable_reg;
1538 st->vref = vref;
1539 vref_uv = regulator_get_voltage(vref);
1540 if (vref_uv <= 0) {
1541 ret = -EINVAL;
1542 goto error_disable_reg;
1543 }
1544 st->vref_uv = vref_uv;
1545 }
1546
cd4361c7
MH		 1547 ret = max1363_alloc_scan_masks(indio_dev);
1548 if (ret)
b77b8f8c 1549 goto error_disable_reg;
82020b0e 1550
71d2c120 1551 /* Establish that the iio_dev is a child of the i2c device */
3dba81ba 1552 indio_dev->dev.parent = &client->dev;
845bd12a 1553 indio_dev->name = id->name;
8e7d9672
JC		 1554 indio_dev->channels = st->chip_info->channels;
1555 indio_dev->num_channels = st->chip_info->num_channels;
6fe8135f
JC		 1556 indio_dev->info = st->chip_info->info;
1557 indio_dev->modes = INDIO_DIRECT_MODE;
d1325cf4 1558 ret = max1363_initial_setup(st);
58f0a255 1559 if (ret < 0)
7c3e8675 1560 goto error_disable_reg;
d1325cf4 1561
4389fbec
PM		 1562 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1563 &max1363_trigger_handler, &max1363_buffered_setup_ops);
d1325cf4 1564 if (ret)
7c3e8675 1565 goto error_disable_reg;
d1325cf4 1566
6fe8135f 1567 if (client->irq) {
7c3e8675 1568 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
aaf370db
JC		 1569 NULL,
1570 &max1363_event_handler,
1571 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1572 "max1363_event",
1573 indio_dev);
298cd976 1574
440a5200 1575 if (ret)
ec443728 1576 goto error_uninit_buffer;
440a5200
JC		 1577 }
1578
26d25ae3
JC		 1579 ret = iio_device_register(indio_dev);
1580 if (ret < 0)
7c3e8675 1581 goto error_uninit_buffer;
f88af7e7 1582
26d25ae3 1583 return 0;
7c3e8675 1584
ec443728 1585error_uninit_buffer:
4389fbec 1586 iio_triggered_buffer_cleanup(indio_dev);
d1325cf4 1587error_disable_reg:
a405b00e
GR		 1588 if (st->vref)
1589 regulator_disable(st->vref);
b77b8f8c 1590 regulator_disable(st->reg);
678fb42e 1591error_unregister_map:
6cb2afd7 1592 iio_map_array_unregister(indio_dev);
b77b8f8c
JC		 1593error_free_device:
1594 iio_device_free(indio_dev);
f88af7e7 1595error_out:
d1325cf4
JC		 1596 return ret;
1597}
1598
fc52692c 1599static int max1363_remove(struct i2c_client *client)
d1325cf4 1600{
3dba81ba
JC		 1601 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1602 struct max1363_state *st = iio_priv(indio_dev);
440a5200 1603
d2fffd6c 1604 iio_device_unregister(indio_dev);
4389fbec 1605 iio_triggered_buffer_cleanup(indio_dev);
a405b00e
GR		 1606 if (st->vref)
1607 regulator_disable(st->vref);
678fb42e 1608 regulator_disable(st->reg);
6cb2afd7 1609 iio_map_array_unregister(indio_dev);
7cbb7537 1610 iio_device_free(indio_dev);
d1325cf4
JC		 1611
1612 return 0;
1613}
1614
1615static const struct i2c_device_id max1363_id[] = {
1616 { "max1361", max1361 },
1617 { "max1362", max1362 },
1618 { "max1363", max1363 },
1619 { "max1364", max1364 },
3bf877c1
JC		 1620 { "max1036", max1036 },
1621 { "max1037", max1037 },
1622 { "max1038", max1038 },
1623 { "max1039", max1039 },
d1325cf4
JC		 1624 { "max1136", max1136 },
1625 { "max1137", max1137 },
1626 { "max1138", max1138 },
1627 { "max1139", max1139 },
1628 { "max1236", max1236 },
1629 { "max1237", max1237 },
1630 { "max1238", max1238 },
1631 { "max1239", max1239 },
3bf877c1
JC		 1632 { "max11600", max11600 },
1633 { "max11601", max11601 },
1634 { "max11602", max11602 },
1635 { "max11603", max11603 },
1636 { "max11604", max11604 },
1637 { "max11605", max11605 },
c3fa0fdd
JC		 1638 { "max11606", max11606 },
1639 { "max11607", max11607 },
1640 { "max11608", max11608 },
1641 { "max11609", max11609 },
1642 { "max11610", max11610 },
1643 { "max11611", max11611 },
1644 { "max11612", max11612 },
1645 { "max11613", max11613 },
1646 { "max11614", max11614 },
1647 { "max11615", max11615 },
1648 { "max11616", max11616 },
1649 { "max11617", max11617 },
d1325cf4
JC		 1650 {}
1651};
1652
1653MODULE_DEVICE_TABLE(i2c, max1363_id);
1654
1655static struct i2c_driver max1363_driver = {
1656 .driver = {
1657 .name = "max1363",
1658 },
1659 .probe = max1363_probe,
fc52692c 1660 .remove = max1363_remove,
d1325cf4
JC		 1661 .id_table = max1363_id,
1662};
6e5af184 1663module_i2c_driver(max1363_driver);
d1325cf4 1664
0f8c9620 1665MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
d1325cf4
JC		 1666MODULE_DESCRIPTION("Maxim 1363 ADC");
1667MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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