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RDMA/cxgb4: Disable interrupts in c4iw_ev_dispatch()
[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / device.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/debugfs.h>
35
36#include <rdma/ib_verbs.h>
37
38#include "iw_cxgb4.h"
39
40#define DRV_VERSION "0.1"
41
42MODULE_AUTHOR("Steve Wise");
43MODULE_DESCRIPTION("Chelsio T4 RDMA Driver");
44MODULE_LICENSE("Dual BSD/GPL");
45MODULE_VERSION(DRV_VERSION);
46
2c974781
VP		 47struct uld_ctx {
48 struct list_head entry;
49 struct cxgb4_lld_info lldi;
50 struct c4iw_dev *dev;
51};
52
2f25e9a5 53static LIST_HEAD(uld_ctx_list);
cfdda9d7
SW		 54static DEFINE_MUTEX(dev_mutex);
55
56static struct dentry *c4iw_debugfs_root;
57
9e8d1fa3 58struct c4iw_debugfs_data {
cfdda9d7
SW		 59 struct c4iw_dev *devp;
60 char *buf;
61 int bufsize;
62 int pos;
63};
64
9e8d1fa3 65static int count_idrs(int id, void *p, void *data)
cfdda9d7 66{
cfdda9d7
SW		 67 int *countp = data;
68
cfdda9d7
SW		 69 *countp = *countp + 1;
70 return 0;
71}
72
9e8d1fa3
SW		 73static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
74 loff_t *ppos)
75{
76 struct c4iw_debugfs_data *d = file->private_data;
9e8d1fa3 77
3160977a 78 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
9e8d1fa3
SW		 79}
80
81static int dump_qp(int id, void *p, void *data)
cfdda9d7
SW		 82{
83 struct c4iw_qp *qp = p;
9e8d1fa3 84 struct c4iw_debugfs_data *qpd = data;
cfdda9d7
SW		 85 int space;
86 int cc;
87
88 if (id != qp->wq.sq.qid)
89 return 0;
90
91 space = qpd->bufsize - qpd->pos - 1;
92 if (space == 0)
93 return 1;
94
95 if (qp->ep)
db5d040d
SW		 96 cc = snprintf(qpd->buf + qpd->pos, space,
97 "qp sq id %u rq id %u state %u onchip %u "
cfdda9d7 98 "ep tid %u state %u %pI4:%u->%pI4:%u\n",
db5d040d
SW		 99 qp->wq.sq.qid, qp->wq.rq.qid, (int)qp->attr.state,
100 qp->wq.sq.flags & T4_SQ_ONCHIP,
cfdda9d7
SW		 101 qp->ep->hwtid, (int)qp->ep->com.state,
102 &qp->ep->com.local_addr.sin_addr.s_addr,
103 ntohs(qp->ep->com.local_addr.sin_port),
104 &qp->ep->com.remote_addr.sin_addr.s_addr,
105 ntohs(qp->ep->com.remote_addr.sin_port));
106 else
db5d040d
SW		 107 cc = snprintf(qpd->buf + qpd->pos, space,
108 "qp sq id %u rq id %u state %u onchip %u\n",
109 qp->wq.sq.qid, qp->wq.rq.qid,
110 (int)qp->attr.state,
111 qp->wq.sq.flags & T4_SQ_ONCHIP);
cfdda9d7
SW		 112 if (cc < space)
113 qpd->pos += cc;
114 return 0;
115}
116
117static int qp_release(struct inode *inode, struct file *file)
118{
9e8d1fa3 119 struct c4iw_debugfs_data *qpd = file->private_data;
cfdda9d7
SW		 120 if (!qpd) {
121 printk(KERN_INFO "%s null qpd?\n", __func__);
122 return 0;
123 }
124 kfree(qpd->buf);
125 kfree(qpd);
126 return 0;
127}
128
129static int qp_open(struct inode *inode, struct file *file)
130{
9e8d1fa3 131 struct c4iw_debugfs_data *qpd;
cfdda9d7
SW		 132 int ret = 0;
133 int count = 1;
134
135 qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
136 if (!qpd) {
137 ret = -ENOMEM;
138 goto out;
139 }
140 qpd->devp = inode->i_private;
141 qpd->pos = 0;
142
143 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 144 idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
cfdda9d7
SW		 145 spin_unlock_irq(&qpd->devp->lock);
146
147 qpd->bufsize = count * 128;
148 qpd->buf = kmalloc(qpd->bufsize, GFP_KERNEL);
149 if (!qpd->buf) {
150 ret = -ENOMEM;
151 goto err1;
152 }
153
154 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 155 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
cfdda9d7
SW		 156 spin_unlock_irq(&qpd->devp->lock);
157
158 qpd->buf[qpd->pos++] = 0;
159 file->private_data = qpd;
160 goto out;
161err1:
162 kfree(qpd);
163out:
164 return ret;
165}
166
9e8d1fa3
SW		 167static const struct file_operations qp_debugfs_fops = {
168 .owner = THIS_MODULE,
169 .open = qp_open,
170 .release = qp_release,
171 .read = debugfs_read,
8bbac892 172 .llseek = default_llseek,
9e8d1fa3
SW		 173};
174
175static int dump_stag(int id, void *p, void *data)
cfdda9d7 176{
9e8d1fa3
SW		 177 struct c4iw_debugfs_data *stagd = data;
178 int space;
179 int cc;
cfdda9d7 180
9e8d1fa3
SW		 181 space = stagd->bufsize - stagd->pos - 1;
182 if (space == 0)
183 return 1;
184
185 cc = snprintf(stagd->buf + stagd->pos, space, "0x%x\n", id<<8);
186 if (cc < space)
187 stagd->pos += cc;
188 return 0;
189}
190
191static int stag_release(struct inode *inode, struct file *file)
192{
193 struct c4iw_debugfs_data *stagd = file->private_data;
194 if (!stagd) {
195 printk(KERN_INFO "%s null stagd?\n", __func__);
cfdda9d7 196 return 0;
9e8d1fa3
SW		 197 }
198 kfree(stagd->buf);
199 kfree(stagd);
200 return 0;
201}
cfdda9d7 202
9e8d1fa3
SW		 203static int stag_open(struct inode *inode, struct file *file)
204{
205 struct c4iw_debugfs_data *stagd;
206 int ret = 0;
207 int count = 1;
cfdda9d7 208
9e8d1fa3
SW		 209 stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
210 if (!stagd) {
211 ret = -ENOMEM;
212 goto out;
213 }
214 stagd->devp = inode->i_private;
215 stagd->pos = 0;
cfdda9d7 216
9e8d1fa3
SW		 217 spin_lock_irq(&stagd->devp->lock);
218 idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
219 spin_unlock_irq(&stagd->devp->lock);
220
221 stagd->bufsize = count * sizeof("0x12345678\n");
222 stagd->buf = kmalloc(stagd->bufsize, GFP_KERNEL);
223 if (!stagd->buf) {
224 ret = -ENOMEM;
225 goto err1;
cfdda9d7 226 }
9e8d1fa3
SW		 227
228 spin_lock_irq(&stagd->devp->lock);
229 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
230 spin_unlock_irq(&stagd->devp->lock);
231
232 stagd->buf[stagd->pos++] = 0;
233 file->private_data = stagd;
234 goto out;
235err1:
236 kfree(stagd);
237out:
238 return ret;
cfdda9d7
SW		 239}
240
9e8d1fa3 241static const struct file_operations stag_debugfs_fops = {
cfdda9d7 242 .owner = THIS_MODULE,
9e8d1fa3
SW		 243 .open = stag_open,
244 .release = stag_release,
245 .read = debugfs_read,
8bbac892 246 .llseek = default_llseek,
cfdda9d7
SW		 247};
248
8d81ef34
VP		 249static int stats_show(struct seq_file *seq, void *v)
250{
251 struct c4iw_dev *dev = seq->private;
252
253 seq_printf(seq, " Object: %10s %10s %10s\n", "Total", "Current", "Max");
254 seq_printf(seq, " PDID: %10llu %10llu %10llu\n",
255 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
256 dev->rdev.stats.pd.max);
257 seq_printf(seq, " QID: %10llu %10llu %10llu\n",
258 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
259 dev->rdev.stats.qid.max);
260 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu\n",
261 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
262 dev->rdev.stats.stag.max);
263 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu\n",
264 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
265 dev->rdev.stats.pbl.max);
266 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu\n",
267 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
268 dev->rdev.stats.rqt.max);
269 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu\n",
270 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
271 dev->rdev.stats.ocqp.max);
2c974781
VP		 272 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
273 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
274 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
8d81ef34
VP		 275 return 0;
276}
277
278static int stats_open(struct inode *inode, struct file *file)
279{
280 return single_open(file, stats_show, inode->i_private);
281}
282
283static ssize_t stats_clear(struct file *file, const char __user *buf,
284 size_t count, loff_t *pos)
285{
286 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
287
288 mutex_lock(&dev->rdev.stats.lock);
289 dev->rdev.stats.pd.max = 0;
290 dev->rdev.stats.qid.max = 0;
291 dev->rdev.stats.stag.max = 0;
292 dev->rdev.stats.pbl.max = 0;
293 dev->rdev.stats.rqt.max = 0;
294 dev->rdev.stats.ocqp.max = 0;
2c974781
VP		 295 dev->rdev.stats.db_full = 0;
296 dev->rdev.stats.db_empty = 0;
297 dev->rdev.stats.db_drop = 0;
8d81ef34
VP		 298 mutex_unlock(&dev->rdev.stats.lock);
299 return count;
300}
301
302static const struct file_operations stats_debugfs_fops = {
303 .owner = THIS_MODULE,
304 .open = stats_open,
305 .release = single_release,
306 .read = seq_read,
307 .llseek = seq_lseek,
308 .write = stats_clear,
309};
310
cfdda9d7
SW		 311static int setup_debugfs(struct c4iw_dev *devp)
312{
313 struct dentry *de;
314
315 if (!devp->debugfs_root)
316 return -1;
317
318 de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
319 (void *)devp, &qp_debugfs_fops);
320 if (de && de->d_inode)
321 de->d_inode->i_size = 4096;
9e8d1fa3
SW		 322
323 de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
324 (void *)devp, &stag_debugfs_fops);
325 if (de && de->d_inode)
326 de->d_inode->i_size = 4096;
8d81ef34
VP		 327
328 de = debugfs_create_file("stats", S_IWUSR, devp->debugfs_root,
329 (void *)devp, &stats_debugfs_fops);
330 if (de && de->d_inode)
331 de->d_inode->i_size = 4096;
332
cfdda9d7
SW		 333 return 0;
334}
335
336void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
337 struct c4iw_dev_ucontext *uctx)
338{
339 struct list_head *pos, *nxt;
340 struct c4iw_qid_list *entry;
341
342 mutex_lock(&uctx->lock);
343 list_for_each_safe(pos, nxt, &uctx->qpids) {
344 entry = list_entry(pos, struct c4iw_qid_list, entry);
345 list_del_init(&entry->entry);
8d81ef34 346 if (!(entry->qid & rdev->qpmask)) {
cfdda9d7 347 c4iw_put_resource(&rdev->resource.qid_fifo, entry->qid,
8d81ef34
VP		 348 &rdev->resource.qid_fifo_lock);
349 mutex_lock(&rdev->stats.lock);
350 rdev->stats.qid.cur -= rdev->qpmask + 1;
351 mutex_unlock(&rdev->stats.lock);
352 }
cfdda9d7
SW		 353 kfree(entry);
354 }
355
356 list_for_each_safe(pos, nxt, &uctx->qpids) {
357 entry = list_entry(pos, struct c4iw_qid_list, entry);
358 list_del_init(&entry->entry);
359 kfree(entry);
360 }
361 mutex_unlock(&uctx->lock);
362}
363
364void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
365 struct c4iw_dev_ucontext *uctx)
366{
367 INIT_LIST_HEAD(&uctx->qpids);
368 INIT_LIST_HEAD(&uctx->cqids);
369 mutex_init(&uctx->lock);
370}
371
372/* Caller takes care of locking if needed */
373static int c4iw_rdev_open(struct c4iw_rdev *rdev)
374{
375 int err;
376
377 c4iw_init_dev_ucontext(rdev, &rdev->uctx);
378
379 /*
380 * qpshift is the number of bits to shift the qpid left in order
381 * to get the correct address of the doorbell for that qp.
382 */
383 rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
384 rdev->qpmask = rdev->lldi.udb_density - 1;
385 rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
386 rdev->cqmask = rdev->lldi.ucq_density - 1;
387 PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
93fb72e4
SW		 388 "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
389 "qp qid start %u size %u cq qid start %u size %u\n",
cfdda9d7
SW		 390 __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
391 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
392 rdev->lldi.vr->pbl.start,
393 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
93fb72e4
SW		 394 rdev->lldi.vr->rq.size,
395 rdev->lldi.vr->qp.start,
396 rdev->lldi.vr->qp.size,
397 rdev->lldi.vr->cq.start,
398 rdev->lldi.vr->cq.size);
cfdda9d7
SW		 399 PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
400 "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
401 (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
402 (void *)pci_resource_start(rdev->lldi.pdev, 2),
403 rdev->lldi.db_reg,
404 rdev->lldi.gts_reg,
405 rdev->qpshift, rdev->qpmask,
406 rdev->cqshift, rdev->cqmask);
407
408 if (c4iw_num_stags(rdev) == 0) {
409 err = -EINVAL;
410 goto err1;
411 }
412
8d81ef34
VP		 413 rdev->stats.pd.total = T4_MAX_NUM_PD;
414 rdev->stats.stag.total = rdev->lldi.vr->stag.size;
415 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
416 rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
417 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
418 rdev->stats.qid.total = rdev->lldi.vr->qp.size;
419
cfdda9d7
SW		 420 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
421 if (err) {
422 printk(KERN_ERR MOD "error %d initializing resources\n", err);
423 goto err1;
424 }
425 err = c4iw_pblpool_create(rdev);
426 if (err) {
427 printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
428 goto err2;
429 }
430 err = c4iw_rqtpool_create(rdev);
431 if (err) {
432 printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
433 goto err3;
434 }
c6d7b267
SW		 435 err = c4iw_ocqp_pool_create(rdev);
436 if (err) {
437 printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
438 goto err4;
439 }
cfdda9d7 440 return 0;
c6d7b267
SW		 441err4:
442 c4iw_rqtpool_destroy(rdev);
cfdda9d7
SW		 443err3:
444 c4iw_pblpool_destroy(rdev);
445err2:
446 c4iw_destroy_resource(&rdev->resource);
447err1:
448 return err;
449}
450
451static void c4iw_rdev_close(struct c4iw_rdev *rdev)
452{
453 c4iw_pblpool_destroy(rdev);
454 c4iw_rqtpool_destroy(rdev);
455 c4iw_destroy_resource(&rdev->resource);
456}
457
9efe10a1 458static void c4iw_dealloc(struct uld_ctx *ctx)
cfdda9d7 459{
2f25e9a5
SW		 460 c4iw_rdev_close(&ctx->dev->rdev);
461 idr_destroy(&ctx->dev->cqidr);
462 idr_destroy(&ctx->dev->qpidr);
463 idr_destroy(&ctx->dev->mmidr);
464 iounmap(ctx->dev->rdev.oc_mw_kva);
465 ib_dealloc_device(&ctx->dev->ibdev);
466 ctx->dev = NULL;
cfdda9d7
SW		 467}
468
9efe10a1
SW		 469static void c4iw_remove(struct uld_ctx *ctx)
470{
471 PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
472 c4iw_unregister_device(ctx->dev);
473 c4iw_dealloc(ctx);
474}
475
476static int rdma_supported(const struct cxgb4_lld_info *infop)
477{
478 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
479 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
480 infop->vr->cq.size > 0 && infop->vr->ocq.size > 0;
481}
482
cfdda9d7
SW		 483static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
484{
485 struct c4iw_dev *devp;
486 int ret;
487
9efe10a1
SW		 488 if (!rdma_supported(infop)) {
489 printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
490 pci_name(infop->pdev));
491 return ERR_PTR(-ENOSYS);
492 }
cfdda9d7
SW		 493 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
494 if (!devp) {
495 printk(KERN_ERR MOD "Cannot allocate ib device\n");
bbe9a0a2 496 return ERR_PTR(-ENOMEM);
cfdda9d7
SW		 497 }
498 devp->rdev.lldi = *infop;
499
c6d7b267
SW		 500 devp->rdev.oc_mw_pa = pci_resource_start(devp->rdev.lldi.pdev, 2) +
501 (pci_resource_len(devp->rdev.lldi.pdev, 2) -
502 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size));
503 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
504 devp->rdev.lldi.vr->ocq.size);
505
2f25e9a5 506 PDBG(KERN_INFO MOD "ocq memory: "
c6d7b267
SW		 507 "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
508 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
509 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
510
cfdda9d7
SW		 511 ret = c4iw_rdev_open(&devp->rdev);
512 if (ret) {
cfdda9d7
SW		 513 printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
514 ib_dealloc_device(&devp->ibdev);
bbe9a0a2 515 return ERR_PTR(ret);
cfdda9d7
SW		 516 }
517
518 idr_init(&devp->cqidr);
519 idr_init(&devp->qpidr);
520 idr_init(&devp->mmidr);
521 spin_lock_init(&devp->lock);
8d81ef34 522 mutex_init(&devp->rdev.stats.lock);
2c974781 523 mutex_init(&devp->db_mutex);
cfdda9d7 524
cfdda9d7
SW		 525 if (c4iw_debugfs_root) {
526 devp->debugfs_root = debugfs_create_dir(
527 pci_name(devp->rdev.lldi.pdev),
528 c4iw_debugfs_root);
529 setup_debugfs(devp);
530 }
531 return devp;
532}
533
534static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
535{
2f25e9a5 536 struct uld_ctx *ctx;
cfdda9d7
SW		 537 static int vers_printed;
538 int i;
539
540 if (!vers_printed++)
541 printk(KERN_INFO MOD "Chelsio T4 RDMA Driver - version %s\n",
542 DRV_VERSION);
543
2f25e9a5
SW		 544 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
545 if (!ctx) {
546 ctx = ERR_PTR(-ENOMEM);
cfdda9d7 547 goto out;
2f25e9a5
SW		 548 }
549 ctx->lldi = *infop;
cfdda9d7
SW		 550
551 PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
2f25e9a5
SW		 552 __func__, pci_name(ctx->lldi.pdev),
553 ctx->lldi.nchan, ctx->lldi.nrxq,
554 ctx->lldi.ntxq, ctx->lldi.nports);
555
556 mutex_lock(&dev_mutex);
557 list_add_tail(&ctx->entry, &uld_ctx_list);
558 mutex_unlock(&dev_mutex);
cfdda9d7 559
2f25e9a5
SW		 560 for (i = 0; i < ctx->lldi.nrxq; i++)
561 PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
cfdda9d7 562out:
2f25e9a5 563 return ctx;
cfdda9d7
SW		 564}
565
cfdda9d7
SW		 566static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
567 const struct pkt_gl *gl)
568{
2f25e9a5
SW		 569 struct uld_ctx *ctx = handle;
570 struct c4iw_dev *dev = ctx->dev;
cfdda9d7
SW		 571 struct sk_buff *skb;
572 const struct cpl_act_establish *rpl;
573 unsigned int opcode;
574
575 if (gl == NULL) {
576 /* omit RSS and rsp_ctrl at end of descriptor */
577 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
578
579 skb = alloc_skb(256, GFP_ATOMIC);
580 if (!skb)
581 goto nomem;
582 __skb_put(skb, len);
583 skb_copy_to_linear_data(skb, &rsp[1], len);
584 } else if (gl == CXGB4_MSG_AN) {
585 const struct rsp_ctrl *rc = (void *)rsp;
586
587 u32 qid = be32_to_cpu(rc->pldbuflen_qid);
588 c4iw_ev_handler(dev, qid);
589 return 0;
590 } else {
da411ba1 591 skb = cxgb4_pktgl_to_skb(gl, 128, 128);
cfdda9d7
SW		 592 if (unlikely(!skb))
593 goto nomem;
594 }
595
596 rpl = cplhdr(skb);
597 opcode = rpl->ot.opcode;
598
599 if (c4iw_handlers[opcode])
600 c4iw_handlers[opcode](dev, skb);
601 else
602 printk(KERN_INFO "%s no handler opcode 0x%x...\n", __func__,
603 opcode);
604
605 return 0;
606nomem:
607 return -1;
608}
609
610static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
611{
2f25e9a5 612 struct uld_ctx *ctx = handle;
1c01c538 613
cfdda9d7 614 PDBG("%s new_state %u\n", __func__, new_state);
1c01c538
SW		 615 switch (new_state) {
616 case CXGB4_STATE_UP:
2f25e9a5
SW		 617 printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
618 if (!ctx->dev) {
9efe10a1 619 int ret;
2f25e9a5
SW		 620
621 ctx->dev = c4iw_alloc(&ctx->lldi);
9efe10a1
SW		 622 if (IS_ERR(ctx->dev)) {
623 printk(KERN_ERR MOD
624 "%s: initialization failed: %ld\n",
625 pci_name(ctx->lldi.pdev),
626 PTR_ERR(ctx->dev));
627 ctx->dev = NULL;
628 break;
629 }
630 ret = c4iw_register_device(ctx->dev);
631 if (ret) {
1c01c538
SW		 632 printk(KERN_ERR MOD
633 "%s: RDMA registration failed: %d\n",
2f25e9a5 634 pci_name(ctx->lldi.pdev), ret);
9efe10a1
SW		 635 c4iw_dealloc(ctx);
636 }
1c01c538
SW		 637 }
638 break;
639 case CXGB4_STATE_DOWN:
640 printk(KERN_INFO MOD "%s: Down\n",
2f25e9a5
SW		 641 pci_name(ctx->lldi.pdev));
642 if (ctx->dev)
643 c4iw_remove(ctx);
1c01c538
SW		 644 break;
645 case CXGB4_STATE_START_RECOVERY:
646 printk(KERN_INFO MOD "%s: Fatal Error\n",
2f25e9a5
SW		 647 pci_name(ctx->lldi.pdev));
648 if (ctx->dev) {
767fbe81
SW		 649 struct ib_event event;
650
2f25e9a5 651 ctx->dev->rdev.flags |= T4_FATAL_ERROR;
767fbe81
SW		 652 memset(&event, 0, sizeof event);
653 event.event = IB_EVENT_DEVICE_FATAL;
2f25e9a5 654 event.device = &ctx->dev->ibdev;
767fbe81 655 ib_dispatch_event(&event);
2f25e9a5 656 c4iw_remove(ctx);
767fbe81 657 }
1c01c538
SW		 658 break;
659 case CXGB4_STATE_DETACH:
660 printk(KERN_INFO MOD "%s: Detach\n",
2f25e9a5
SW		 661 pci_name(ctx->lldi.pdev));
662 if (ctx->dev)
663 c4iw_remove(ctx);
1c01c538
SW		 664 break;
665 }
cfdda9d7
SW		 666 return 0;
667}
668
2c974781
VP		 669static int disable_qp_db(int id, void *p, void *data)
670{
671 struct c4iw_qp *qp = p;
672
673 t4_disable_wq_db(&qp->wq);
674 return 0;
675}
676
677static void stop_queues(struct uld_ctx *ctx)
678{
679 spin_lock_irq(&ctx->dev->lock);
680 ctx->dev->db_state = FLOW_CONTROL;
681 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
682 spin_unlock_irq(&ctx->dev->lock);
683}
684
685static int enable_qp_db(int id, void *p, void *data)
686{
687 struct c4iw_qp *qp = p;
688
689 t4_enable_wq_db(&qp->wq);
690 return 0;
691}
692
693static void resume_queues(struct uld_ctx *ctx)
694{
695 spin_lock_irq(&ctx->dev->lock);
696 ctx->dev->db_state = NORMAL;
697 idr_for_each(&ctx->dev->qpidr, enable_qp_db, NULL);
698 spin_unlock_irq(&ctx->dev->lock);
699}
700
701static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
702{
703 struct uld_ctx *ctx = handle;
704
705 switch (control) {
706 case CXGB4_CONTROL_DB_FULL:
707 stop_queues(ctx);
708 mutex_lock(&ctx->dev->rdev.stats.lock);
709 ctx->dev->rdev.stats.db_full++;
710 mutex_unlock(&ctx->dev->rdev.stats.lock);
711 break;
712 case CXGB4_CONTROL_DB_EMPTY:
713 resume_queues(ctx);
714 mutex_lock(&ctx->dev->rdev.stats.lock);
715 ctx->dev->rdev.stats.db_empty++;
716 mutex_unlock(&ctx->dev->rdev.stats.lock);
717 break;
718 case CXGB4_CONTROL_DB_DROP:
719 printk(KERN_WARNING MOD "%s: Fatal DB DROP\n",
720 pci_name(ctx->lldi.pdev));
721 mutex_lock(&ctx->dev->rdev.stats.lock);
722 ctx->dev->rdev.stats.db_drop++;
723 mutex_unlock(&ctx->dev->rdev.stats.lock);
724 break;
725 default:
726 printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
727 pci_name(ctx->lldi.pdev), control);
728 break;
729 }
730 return 0;
731}
732
cfdda9d7
SW		 733static struct cxgb4_uld_info c4iw_uld_info = {
734 .name = DRV_NAME,
735 .add = c4iw_uld_add,
736 .rx_handler = c4iw_uld_rx_handler,
737 .state_change = c4iw_uld_state_change,
2c974781 738 .control = c4iw_uld_control,
cfdda9d7
SW		 739};
740
741static int __init c4iw_init_module(void)
742{
743 int err;
744
745 err = c4iw_cm_init();
746 if (err)
747 return err;
748
749 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
750 if (!c4iw_debugfs_root)
751 printk(KERN_WARNING MOD
752 "could not create debugfs entry, continuing\n");
753
754 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
755
756 return 0;
757}
758
759static void __exit c4iw_exit_module(void)
760{
2f25e9a5 761 struct uld_ctx *ctx, *tmp;
cfdda9d7 762
cfdda9d7 763 mutex_lock(&dev_mutex);
2f25e9a5
SW		 764 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
765 if (ctx->dev)
766 c4iw_remove(ctx);
767 kfree(ctx);
cfdda9d7
SW		 768 }
769 mutex_unlock(&dev_mutex);
fd388ce6 770 cxgb4_unregister_uld(CXGB4_ULD_RDMA);
cfdda9d7
SW		 771 c4iw_cm_term();
772 debugfs_remove_recursive(c4iw_debugfs_root);
773}
774
775module_init(c4iw_init_module);
776module_exit(c4iw_exit_module);
Linux kernel - Deliverables
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