Linux 3.1-rc9
[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / device.c
CommitLineData
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1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/debugfs.h>
35
36#include <rdma/ib_verbs.h>
37
38#include "iw_cxgb4.h"
39
40#define DRV_VERSION "0.1"
41
42MODULE_AUTHOR("Steve Wise");
43MODULE_DESCRIPTION("Chelsio T4 RDMA Driver");
44MODULE_LICENSE("Dual BSD/GPL");
45MODULE_VERSION(DRV_VERSION);
46
2f25e9a5 47static LIST_HEAD(uld_ctx_list);
cfdda9d7
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48static DEFINE_MUTEX(dev_mutex);
49
50static struct dentry *c4iw_debugfs_root;
51
9e8d1fa3 52struct c4iw_debugfs_data {
cfdda9d7
SW
53 struct c4iw_dev *devp;
54 char *buf;
55 int bufsize;
56 int pos;
57};
58
9e8d1fa3 59static int count_idrs(int id, void *p, void *data)
cfdda9d7 60{
cfdda9d7
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61 int *countp = data;
62
cfdda9d7
SW
63 *countp = *countp + 1;
64 return 0;
65}
66
9e8d1fa3
SW
67static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
68 loff_t *ppos)
69{
70 struct c4iw_debugfs_data *d = file->private_data;
9e8d1fa3 71
3160977a 72 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
9e8d1fa3
SW
73}
74
75static int dump_qp(int id, void *p, void *data)
cfdda9d7
SW
76{
77 struct c4iw_qp *qp = p;
9e8d1fa3 78 struct c4iw_debugfs_data *qpd = data;
cfdda9d7
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79 int space;
80 int cc;
81
82 if (id != qp->wq.sq.qid)
83 return 0;
84
85 space = qpd->bufsize - qpd->pos - 1;
86 if (space == 0)
87 return 1;
88
89 if (qp->ep)
db5d040d
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90 cc = snprintf(qpd->buf + qpd->pos, space,
91 "qp sq id %u rq id %u state %u onchip %u "
cfdda9d7 92 "ep tid %u state %u %pI4:%u->%pI4:%u\n",
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93 qp->wq.sq.qid, qp->wq.rq.qid, (int)qp->attr.state,
94 qp->wq.sq.flags & T4_SQ_ONCHIP,
cfdda9d7
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95 qp->ep->hwtid, (int)qp->ep->com.state,
96 &qp->ep->com.local_addr.sin_addr.s_addr,
97 ntohs(qp->ep->com.local_addr.sin_port),
98 &qp->ep->com.remote_addr.sin_addr.s_addr,
99 ntohs(qp->ep->com.remote_addr.sin_port));
100 else
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101 cc = snprintf(qpd->buf + qpd->pos, space,
102 "qp sq id %u rq id %u state %u onchip %u\n",
103 qp->wq.sq.qid, qp->wq.rq.qid,
104 (int)qp->attr.state,
105 qp->wq.sq.flags & T4_SQ_ONCHIP);
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106 if (cc < space)
107 qpd->pos += cc;
108 return 0;
109}
110
111static int qp_release(struct inode *inode, struct file *file)
112{
9e8d1fa3 113 struct c4iw_debugfs_data *qpd = file->private_data;
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114 if (!qpd) {
115 printk(KERN_INFO "%s null qpd?\n", __func__);
116 return 0;
117 }
118 kfree(qpd->buf);
119 kfree(qpd);
120 return 0;
121}
122
123static int qp_open(struct inode *inode, struct file *file)
124{
9e8d1fa3 125 struct c4iw_debugfs_data *qpd;
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126 int ret = 0;
127 int count = 1;
128
129 qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
130 if (!qpd) {
131 ret = -ENOMEM;
132 goto out;
133 }
134 qpd->devp = inode->i_private;
135 qpd->pos = 0;
136
137 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 138 idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
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139 spin_unlock_irq(&qpd->devp->lock);
140
141 qpd->bufsize = count * 128;
142 qpd->buf = kmalloc(qpd->bufsize, GFP_KERNEL);
143 if (!qpd->buf) {
144 ret = -ENOMEM;
145 goto err1;
146 }
147
148 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 149 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
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150 spin_unlock_irq(&qpd->devp->lock);
151
152 qpd->buf[qpd->pos++] = 0;
153 file->private_data = qpd;
154 goto out;
155err1:
156 kfree(qpd);
157out:
158 return ret;
159}
160
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161static const struct file_operations qp_debugfs_fops = {
162 .owner = THIS_MODULE,
163 .open = qp_open,
164 .release = qp_release,
165 .read = debugfs_read,
8bbac892 166 .llseek = default_llseek,
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167};
168
169static int dump_stag(int id, void *p, void *data)
cfdda9d7 170{
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171 struct c4iw_debugfs_data *stagd = data;
172 int space;
173 int cc;
cfdda9d7 174
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175 space = stagd->bufsize - stagd->pos - 1;
176 if (space == 0)
177 return 1;
178
179 cc = snprintf(stagd->buf + stagd->pos, space, "0x%x\n", id<<8);
180 if (cc < space)
181 stagd->pos += cc;
182 return 0;
183}
184
185static int stag_release(struct inode *inode, struct file *file)
186{
187 struct c4iw_debugfs_data *stagd = file->private_data;
188 if (!stagd) {
189 printk(KERN_INFO "%s null stagd?\n", __func__);
cfdda9d7 190 return 0;
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191 }
192 kfree(stagd->buf);
193 kfree(stagd);
194 return 0;
195}
cfdda9d7 196
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197static int stag_open(struct inode *inode, struct file *file)
198{
199 struct c4iw_debugfs_data *stagd;
200 int ret = 0;
201 int count = 1;
cfdda9d7 202
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203 stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
204 if (!stagd) {
205 ret = -ENOMEM;
206 goto out;
207 }
208 stagd->devp = inode->i_private;
209 stagd->pos = 0;
cfdda9d7 210
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211 spin_lock_irq(&stagd->devp->lock);
212 idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
213 spin_unlock_irq(&stagd->devp->lock);
214
215 stagd->bufsize = count * sizeof("0x12345678\n");
216 stagd->buf = kmalloc(stagd->bufsize, GFP_KERNEL);
217 if (!stagd->buf) {
218 ret = -ENOMEM;
219 goto err1;
cfdda9d7 220 }
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221
222 spin_lock_irq(&stagd->devp->lock);
223 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
224 spin_unlock_irq(&stagd->devp->lock);
225
226 stagd->buf[stagd->pos++] = 0;
227 file->private_data = stagd;
228 goto out;
229err1:
230 kfree(stagd);
231out:
232 return ret;
cfdda9d7
SW
233}
234
9e8d1fa3 235static const struct file_operations stag_debugfs_fops = {
cfdda9d7 236 .owner = THIS_MODULE,
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237 .open = stag_open,
238 .release = stag_release,
239 .read = debugfs_read,
8bbac892 240 .llseek = default_llseek,
cfdda9d7
SW
241};
242
243static int setup_debugfs(struct c4iw_dev *devp)
244{
245 struct dentry *de;
246
247 if (!devp->debugfs_root)
248 return -1;
249
250 de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
251 (void *)devp, &qp_debugfs_fops);
252 if (de && de->d_inode)
253 de->d_inode->i_size = 4096;
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254
255 de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
256 (void *)devp, &stag_debugfs_fops);
257 if (de && de->d_inode)
258 de->d_inode->i_size = 4096;
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259 return 0;
260}
261
262void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
263 struct c4iw_dev_ucontext *uctx)
264{
265 struct list_head *pos, *nxt;
266 struct c4iw_qid_list *entry;
267
268 mutex_lock(&uctx->lock);
269 list_for_each_safe(pos, nxt, &uctx->qpids) {
270 entry = list_entry(pos, struct c4iw_qid_list, entry);
271 list_del_init(&entry->entry);
272 if (!(entry->qid & rdev->qpmask))
273 c4iw_put_resource(&rdev->resource.qid_fifo, entry->qid,
274 &rdev->resource.qid_fifo_lock);
275 kfree(entry);
276 }
277
278 list_for_each_safe(pos, nxt, &uctx->qpids) {
279 entry = list_entry(pos, struct c4iw_qid_list, entry);
280 list_del_init(&entry->entry);
281 kfree(entry);
282 }
283 mutex_unlock(&uctx->lock);
284}
285
286void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
287 struct c4iw_dev_ucontext *uctx)
288{
289 INIT_LIST_HEAD(&uctx->qpids);
290 INIT_LIST_HEAD(&uctx->cqids);
291 mutex_init(&uctx->lock);
292}
293
294/* Caller takes care of locking if needed */
295static int c4iw_rdev_open(struct c4iw_rdev *rdev)
296{
297 int err;
298
299 c4iw_init_dev_ucontext(rdev, &rdev->uctx);
300
301 /*
302 * qpshift is the number of bits to shift the qpid left in order
303 * to get the correct address of the doorbell for that qp.
304 */
305 rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
306 rdev->qpmask = rdev->lldi.udb_density - 1;
307 rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
308 rdev->cqmask = rdev->lldi.ucq_density - 1;
309 PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
93fb72e4
SW
310 "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
311 "qp qid start %u size %u cq qid start %u size %u\n",
cfdda9d7
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312 __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
313 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
314 rdev->lldi.vr->pbl.start,
315 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
93fb72e4
SW
316 rdev->lldi.vr->rq.size,
317 rdev->lldi.vr->qp.start,
318 rdev->lldi.vr->qp.size,
319 rdev->lldi.vr->cq.start,
320 rdev->lldi.vr->cq.size);
cfdda9d7
SW
321 PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
322 "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
323 (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
324 (void *)pci_resource_start(rdev->lldi.pdev, 2),
325 rdev->lldi.db_reg,
326 rdev->lldi.gts_reg,
327 rdev->qpshift, rdev->qpmask,
328 rdev->cqshift, rdev->cqmask);
329
330 if (c4iw_num_stags(rdev) == 0) {
331 err = -EINVAL;
332 goto err1;
333 }
334
335 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
336 if (err) {
337 printk(KERN_ERR MOD "error %d initializing resources\n", err);
338 goto err1;
339 }
340 err = c4iw_pblpool_create(rdev);
341 if (err) {
342 printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
343 goto err2;
344 }
345 err = c4iw_rqtpool_create(rdev);
346 if (err) {
347 printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
348 goto err3;
349 }
c6d7b267
SW
350 err = c4iw_ocqp_pool_create(rdev);
351 if (err) {
352 printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
353 goto err4;
354 }
cfdda9d7 355 return 0;
c6d7b267
SW
356err4:
357 c4iw_rqtpool_destroy(rdev);
cfdda9d7
SW
358err3:
359 c4iw_pblpool_destroy(rdev);
360err2:
361 c4iw_destroy_resource(&rdev->resource);
362err1:
363 return err;
364}
365
366static void c4iw_rdev_close(struct c4iw_rdev *rdev)
367{
368 c4iw_pblpool_destroy(rdev);
369 c4iw_rqtpool_destroy(rdev);
370 c4iw_destroy_resource(&rdev->resource);
371}
372
2f25e9a5
SW
373struct uld_ctx {
374 struct list_head entry;
375 struct cxgb4_lld_info lldi;
376 struct c4iw_dev *dev;
377};
378
379static void c4iw_remove(struct uld_ctx *ctx)
cfdda9d7 380{
2f25e9a5
SW
381 PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
382 c4iw_unregister_device(ctx->dev);
383 c4iw_rdev_close(&ctx->dev->rdev);
384 idr_destroy(&ctx->dev->cqidr);
385 idr_destroy(&ctx->dev->qpidr);
386 idr_destroy(&ctx->dev->mmidr);
387 iounmap(ctx->dev->rdev.oc_mw_kva);
388 ib_dealloc_device(&ctx->dev->ibdev);
389 ctx->dev = NULL;
cfdda9d7
SW
390}
391
392static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
393{
394 struct c4iw_dev *devp;
395 int ret;
396
397 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
398 if (!devp) {
399 printk(KERN_ERR MOD "Cannot allocate ib device\n");
bbe9a0a2 400 return ERR_PTR(-ENOMEM);
cfdda9d7
SW
401 }
402 devp->rdev.lldi = *infop;
403
c6d7b267
SW
404 devp->rdev.oc_mw_pa = pci_resource_start(devp->rdev.lldi.pdev, 2) +
405 (pci_resource_len(devp->rdev.lldi.pdev, 2) -
406 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size));
407 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
408 devp->rdev.lldi.vr->ocq.size);
409
2f25e9a5 410 PDBG(KERN_INFO MOD "ocq memory: "
c6d7b267
SW
411 "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
412 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
413 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
414
cfdda9d7
SW
415 ret = c4iw_rdev_open(&devp->rdev);
416 if (ret) {
417 mutex_unlock(&dev_mutex);
418 printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
419 ib_dealloc_device(&devp->ibdev);
bbe9a0a2 420 return ERR_PTR(ret);
cfdda9d7
SW
421 }
422
423 idr_init(&devp->cqidr);
424 idr_init(&devp->qpidr);
425 idr_init(&devp->mmidr);
426 spin_lock_init(&devp->lock);
cfdda9d7 427
cfdda9d7
SW
428 if (c4iw_debugfs_root) {
429 devp->debugfs_root = debugfs_create_dir(
430 pci_name(devp->rdev.lldi.pdev),
431 c4iw_debugfs_root);
432 setup_debugfs(devp);
433 }
434 return devp;
435}
436
437static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
438{
2f25e9a5 439 struct uld_ctx *ctx;
cfdda9d7
SW
440 static int vers_printed;
441 int i;
442
443 if (!vers_printed++)
444 printk(KERN_INFO MOD "Chelsio T4 RDMA Driver - version %s\n",
445 DRV_VERSION);
446
2f25e9a5
SW
447 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
448 if (!ctx) {
449 ctx = ERR_PTR(-ENOMEM);
cfdda9d7 450 goto out;
2f25e9a5
SW
451 }
452 ctx->lldi = *infop;
cfdda9d7
SW
453
454 PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
2f25e9a5
SW
455 __func__, pci_name(ctx->lldi.pdev),
456 ctx->lldi.nchan, ctx->lldi.nrxq,
457 ctx->lldi.ntxq, ctx->lldi.nports);
458
459 mutex_lock(&dev_mutex);
460 list_add_tail(&ctx->entry, &uld_ctx_list);
461 mutex_unlock(&dev_mutex);
cfdda9d7 462
2f25e9a5
SW
463 for (i = 0; i < ctx->lldi.nrxq; i++)
464 PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
cfdda9d7 465out:
2f25e9a5 466 return ctx;
cfdda9d7
SW
467}
468
cfdda9d7
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469static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
470 const struct pkt_gl *gl)
471{
2f25e9a5
SW
472 struct uld_ctx *ctx = handle;
473 struct c4iw_dev *dev = ctx->dev;
cfdda9d7
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474 struct sk_buff *skb;
475 const struct cpl_act_establish *rpl;
476 unsigned int opcode;
477
478 if (gl == NULL) {
479 /* omit RSS and rsp_ctrl at end of descriptor */
480 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
481
482 skb = alloc_skb(256, GFP_ATOMIC);
483 if (!skb)
484 goto nomem;
485 __skb_put(skb, len);
486 skb_copy_to_linear_data(skb, &rsp[1], len);
487 } else if (gl == CXGB4_MSG_AN) {
488 const struct rsp_ctrl *rc = (void *)rsp;
489
490 u32 qid = be32_to_cpu(rc->pldbuflen_qid);
491 c4iw_ev_handler(dev, qid);
492 return 0;
493 } else {
da411ba1 494 skb = cxgb4_pktgl_to_skb(gl, 128, 128);
cfdda9d7
SW
495 if (unlikely(!skb))
496 goto nomem;
497 }
498
499 rpl = cplhdr(skb);
500 opcode = rpl->ot.opcode;
501
502 if (c4iw_handlers[opcode])
503 c4iw_handlers[opcode](dev, skb);
504 else
505 printk(KERN_INFO "%s no handler opcode 0x%x...\n", __func__,
506 opcode);
507
508 return 0;
509nomem:
510 return -1;
511}
512
513static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
514{
2f25e9a5 515 struct uld_ctx *ctx = handle;
1c01c538 516
cfdda9d7 517 PDBG("%s new_state %u\n", __func__, new_state);
1c01c538
SW
518 switch (new_state) {
519 case CXGB4_STATE_UP:
2f25e9a5
SW
520 printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
521 if (!ctx->dev) {
522 int ret = 0;
523
524 ctx->dev = c4iw_alloc(&ctx->lldi);
525 if (!IS_ERR(ctx->dev))
526 ret = c4iw_register_device(ctx->dev);
527 if (IS_ERR(ctx->dev) || ret)
1c01c538
SW
528 printk(KERN_ERR MOD
529 "%s: RDMA registration failed: %d\n",
2f25e9a5 530 pci_name(ctx->lldi.pdev), ret);
1c01c538
SW
531 }
532 break;
533 case CXGB4_STATE_DOWN:
534 printk(KERN_INFO MOD "%s: Down\n",
2f25e9a5
SW
535 pci_name(ctx->lldi.pdev));
536 if (ctx->dev)
537 c4iw_remove(ctx);
1c01c538
SW
538 break;
539 case CXGB4_STATE_START_RECOVERY:
540 printk(KERN_INFO MOD "%s: Fatal Error\n",
2f25e9a5
SW
541 pci_name(ctx->lldi.pdev));
542 if (ctx->dev) {
767fbe81
SW
543 struct ib_event event;
544
2f25e9a5 545 ctx->dev->rdev.flags |= T4_FATAL_ERROR;
767fbe81
SW
546 memset(&event, 0, sizeof event);
547 event.event = IB_EVENT_DEVICE_FATAL;
2f25e9a5 548 event.device = &ctx->dev->ibdev;
767fbe81 549 ib_dispatch_event(&event);
2f25e9a5 550 c4iw_remove(ctx);
767fbe81 551 }
1c01c538
SW
552 break;
553 case CXGB4_STATE_DETACH:
554 printk(KERN_INFO MOD "%s: Detach\n",
2f25e9a5
SW
555 pci_name(ctx->lldi.pdev));
556 if (ctx->dev)
557 c4iw_remove(ctx);
1c01c538
SW
558 break;
559 }
cfdda9d7
SW
560 return 0;
561}
562
563static struct cxgb4_uld_info c4iw_uld_info = {
564 .name = DRV_NAME,
565 .add = c4iw_uld_add,
566 .rx_handler = c4iw_uld_rx_handler,
567 .state_change = c4iw_uld_state_change,
568};
569
570static int __init c4iw_init_module(void)
571{
572 int err;
573
574 err = c4iw_cm_init();
575 if (err)
576 return err;
577
578 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
579 if (!c4iw_debugfs_root)
580 printk(KERN_WARNING MOD
581 "could not create debugfs entry, continuing\n");
582
583 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
584
585 return 0;
586}
587
588static void __exit c4iw_exit_module(void)
589{
2f25e9a5 590 struct uld_ctx *ctx, *tmp;
cfdda9d7 591
cfdda9d7 592 mutex_lock(&dev_mutex);
2f25e9a5
SW
593 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
594 if (ctx->dev)
595 c4iw_remove(ctx);
596 kfree(ctx);
cfdda9d7
SW
597 }
598 mutex_unlock(&dev_mutex);
fd388ce6 599 cxgb4_unregister_uld(CXGB4_ULD_RDMA);
cfdda9d7
SW
600 c4iw_cm_term();
601 debugfs_remove_recursive(c4iw_debugfs_root);
602}
603
604module_init(c4iw_init_module);
605module_exit(c4iw_exit_module);
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