[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h

/*
 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *      - Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __IW_CXGB4_H__
#define __IW_CXGB4_H__

#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/idr.h>
#include <linux/workqueue.h>
#include <linux/netdevice.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/inet.h>
#include <linux/wait.h>
#include <linux/kref.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/kfifo.h>

#include <asm/byteorder.h>

#include <net/net_namespace.h>

#include <rdma/ib_verbs.h>
#include <rdma/iw_cm.h>

#include "cxgb4.h"
#include "cxgb4_uld.h"
#include "l2t.h"
#include "user.h"

#define DRV_NAME "iw_cxgb4"
#define MOD DRV_NAME ":"

extern int c4iw_debug;
#define PDBG(fmt, args...) \
do { \
	if (c4iw_debug) \
		printk(MOD fmt, ## args); \
} while (0)

#include "t4.h"

#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)

static inline void *cplhdr(struct sk_buff *skb)
{
	return skb->data;
}

#define C4IW_WR_TO (10*HZ)

struct c4iw_wr_wait {
	wait_queue_head_t wait;
	int done;
	int ret;
};

static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
{
	wr_waitp->ret = 0;
	wr_waitp->done = 0;
	init_waitqueue_head(&wr_waitp->wait);
}

struct c4iw_resource {
	struct kfifo tpt_fifo;
	spinlock_t tpt_fifo_lock;
	struct kfifo qid_fifo;
	spinlock_t qid_fifo_lock;
	struct kfifo pdid_fifo;
	spinlock_t pdid_fifo_lock;
};

struct c4iw_qid_list {
	struct list_head entry;
	u32 qid;
};

struct c4iw_dev_ucontext {
	struct list_head qpids;
	struct list_head cqids;
	struct mutex lock;
};

enum c4iw_rdev_flags {
	T4_FATAL_ERROR = (1<<0),
};

struct c4iw_rdev {
	struct c4iw_resource resource;
	unsigned long qpshift;
	u32 qpmask;
	unsigned long cqshift;
	u32 cqmask;
	struct c4iw_dev_ucontext uctx;
	struct gen_pool *pbl_pool;
	struct gen_pool *rqt_pool;
	u32 flags;
	struct cxgb4_lld_info lldi;
};

static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
{
	return rdev->flags & T4_FATAL_ERROR;
}

static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
{
	return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
}

struct c4iw_dev {
	struct ib_device ibdev;
	struct c4iw_rdev rdev;
	u32 device_cap_flags;
	struct idr cqidr;
	struct idr qpidr;
	struct idr mmidr;
	spinlock_t lock;
	struct list_head entry;
	struct delayed_work db_drop_task;
	struct dentry *debugfs_root;
};

static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
{
	return container_of(ibdev, struct c4iw_dev, ibdev);
}

static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
{
	return container_of(rdev, struct c4iw_dev, rdev);
}

static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
{
	return idr_find(&rhp->cqidr, cqid);
}

static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
{
	return idr_find(&rhp->qpidr, qpid);
}

static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
{
	return idr_find(&rhp->mmidr, mmid);
}

static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
				void *handle, u32 id)
{
	int ret;
	int newid;

	do {
		if (!idr_pre_get(idr, GFP_KERNEL))
			return -ENOMEM;
		spin_lock_irq(&rhp->lock);
		ret = idr_get_new_above(idr, handle, id, &newid);
		BUG_ON(newid != id);
		spin_unlock_irq(&rhp->lock);
	} while (ret == -EAGAIN);

	return ret;
}

static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
{
	spin_lock_irq(&rhp->lock);
	idr_remove(idr, id);
	spin_unlock_irq(&rhp->lock);
}

struct c4iw_pd {
	struct ib_pd ibpd;
	u32 pdid;
	struct c4iw_dev *rhp;
};

static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct c4iw_pd, ibpd);
}

struct tpt_attributes {
	u64 len;
	u64 va_fbo;
	enum fw_ri_mem_perms perms;
	u32 stag;
	u32 pdid;
	u32 qpid;
	u32 pbl_addr;
	u32 pbl_size;
	u32 state:1;
	u32 type:2;
	u32 rsvd:1;
	u32 remote_invaliate_disable:1;
	u32 zbva:1;
	u32 mw_bind_enable:1;
	u32 page_size:5;
};

struct c4iw_mr {
	struct ib_mr ibmr;
	struct ib_umem *umem;
	struct c4iw_dev *rhp;
	u64 kva;
	struct tpt_attributes attr;
};

static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct c4iw_mr, ibmr);
}

struct c4iw_mw {
	struct ib_mw ibmw;
	struct c4iw_dev *rhp;
	u64 kva;
	struct tpt_attributes attr;
};

static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
{
	return container_of(ibmw, struct c4iw_mw, ibmw);
}

struct c4iw_fr_page_list {
	struct ib_fast_reg_page_list ibpl;
	DECLARE_PCI_UNMAP_ADDR(mapping);
	dma_addr_t dma_addr;
	struct c4iw_dev *dev;
	int size;
};

static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
					struct ib_fast_reg_page_list *ibpl)
{
	return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
}

struct c4iw_cq {
	struct ib_cq ibcq;
	struct c4iw_dev *rhp;
	struct t4_cq cq;
	spinlock_t lock;
	atomic_t refcnt;
	wait_queue_head_t wait;
};

static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
{
	return container_of(ibcq, struct c4iw_cq, ibcq);
}

struct c4iw_mpa_attributes {
	u8 initiator;
	u8 recv_marker_enabled;
	u8 xmit_marker_enabled;
	u8 crc_enabled;
	u8 version;
	u8 p2p_type;
};

struct c4iw_qp_attributes {
	u32 scq;
	u32 rcq;
	u32 sq_num_entries;
	u32 rq_num_entries;
	u32 sq_max_sges;
	u32 sq_max_sges_rdma_write;
	u32 rq_max_sges;
	u32 state;
	u8 enable_rdma_read;
	u8 enable_rdma_write;
	u8 enable_bind;
	u8 enable_mmid0_fastreg;
	u32 max_ord;
	u32 max_ird;
	u32 pd;
	u32 next_state;
	char terminate_buffer[52];
	u32 terminate_msg_len;
	u8 is_terminate_local;
	struct c4iw_mpa_attributes mpa_attr;
	struct c4iw_ep *llp_stream_handle;
};

struct c4iw_qp {
	struct ib_qp ibqp;
	struct c4iw_dev *rhp;
	struct c4iw_ep *ep;
	struct c4iw_qp_attributes attr;
	struct t4_wq wq;
	spinlock_t lock;
	atomic_t refcnt;
	wait_queue_head_t wait;
	struct timer_list timer;
};

static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct c4iw_qp, ibqp);
}

struct c4iw_ucontext {
	struct ib_ucontext ibucontext;
	struct c4iw_dev_ucontext uctx;
	u32 key;
	spinlock_t mmap_lock;
	struct list_head mmaps;
};

static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
{
	return container_of(c, struct c4iw_ucontext, ibucontext);
}

struct c4iw_mm_entry {
	struct list_head entry;
	u64 addr;
	u32 key;
	unsigned len;
};

static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
						u32 key, unsigned len)
{
	struct list_head *pos, *nxt;
	struct c4iw_mm_entry *mm;

	spin_lock(&ucontext->mmap_lock);
	list_for_each_safe(pos, nxt, &ucontext->mmaps) {

		mm = list_entry(pos, struct c4iw_mm_entry, entry);
		if (mm->key == key && mm->len == len) {
			list_del_init(&mm->entry);
			spin_unlock(&ucontext->mmap_lock);
			PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
			     key, (unsigned long long) mm->addr, mm->len);
			return mm;
		}
	}
	spin_unlock(&ucontext->mmap_lock);
	return NULL;
}

static inline void insert_mmap(struct c4iw_ucontext *ucontext,
			       struct c4iw_mm_entry *mm)
{
	spin_lock(&ucontext->mmap_lock);
	PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
	     mm->key, (unsigned long long) mm->addr, mm->len);
	list_add_tail(&mm->entry, &ucontext->mmaps);
	spin_unlock(&ucontext->mmap_lock);
}

enum c4iw_qp_attr_mask {
	C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
	C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
	C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
	C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
	C4IW_QP_ATTR_MAX_ORD = 1 << 11,
	C4IW_QP_ATTR_MAX_IRD = 1 << 12,
	C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
	C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
	C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
	C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
				     C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
				     C4IW_QP_ATTR_MAX_ORD |
				     C4IW_QP_ATTR_MAX_IRD |
				     C4IW_QP_ATTR_LLP_STREAM_HANDLE |
				     C4IW_QP_ATTR_STREAM_MSG_BUFFER |
				     C4IW_QP_ATTR_MPA_ATTR |
				     C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
};

int c4iw_modify_qp(struct c4iw_dev *rhp,
				struct c4iw_qp *qhp,
				enum c4iw_qp_attr_mask mask,
				struct c4iw_qp_attributes *attrs,
				int internal);

enum c4iw_qp_state {
	C4IW_QP_STATE_IDLE,
	C4IW_QP_STATE_RTS,
	C4IW_QP_STATE_ERROR,
	C4IW_QP_STATE_TERMINATE,
	C4IW_QP_STATE_CLOSING,
	C4IW_QP_STATE_TOT
};

static inline int c4iw_convert_state(enum ib_qp_state ib_state)
{
	switch (ib_state) {
	case IB_QPS_RESET:
	case IB_QPS_INIT:
		return C4IW_QP_STATE_IDLE;
	case IB_QPS_RTS:
		return C4IW_QP_STATE_RTS;
	case IB_QPS_SQD:
		return C4IW_QP_STATE_CLOSING;
	case IB_QPS_SQE:
		return C4IW_QP_STATE_TERMINATE;
	case IB_QPS_ERR:
		return C4IW_QP_STATE_ERROR;
	default:
		return -1;
	}
}

static inline u32 c4iw_ib_to_tpt_access(int a)
{
	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
	       (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
	       (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
	       FW_RI_MEM_ACCESS_LOCAL_READ;
}

static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
{
	return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
	       (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
}

enum c4iw_mmid_state {
	C4IW_STAG_STATE_VALID,
	C4IW_STAG_STATE_INVALID
};

#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"

#define MPA_KEY_REQ "MPA ID Req Frame"
#define MPA_KEY_REP "MPA ID Rep Frame"

#define MPA_MAX_PRIVATE_DATA	256
#define MPA_REJECT		0x20
#define MPA_CRC			0x40
#define MPA_MARKERS		0x80
#define MPA_FLAGS_MASK		0xE0

#define c4iw_put_ep(ep) { \
	PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
	     ep, atomic_read(&((ep)->kref.refcount))); \
	WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
	kref_put(&((ep)->kref), _c4iw_free_ep); \
}

#define c4iw_get_ep(ep) { \
	PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
	     ep, atomic_read(&((ep)->kref.refcount))); \
	kref_get(&((ep)->kref));  \
}
void _c4iw_free_ep(struct kref *kref);

struct mpa_message {
	u8 key[16];
	u8 flags;
	u8 revision;
	__be16 private_data_size;
	u8 private_data[0];
};

struct terminate_message {
	u8 layer_etype;
	u8 ecode;
	__be16 hdrct_rsvd;
	u8 len_hdrs[0];
};

#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)

enum c4iw_layers_types {
	LAYER_RDMAP		= 0x00,
	LAYER_DDP		= 0x10,
	LAYER_MPA		= 0x20,
	RDMAP_LOCAL_CATA	= 0x00,
	RDMAP_REMOTE_PROT	= 0x01,
	RDMAP_REMOTE_OP		= 0x02,
	DDP_LOCAL_CATA		= 0x00,
	DDP_TAGGED_ERR		= 0x01,
	DDP_UNTAGGED_ERR	= 0x02,
	DDP_LLP			= 0x03
};

enum c4iw_rdma_ecodes {
	RDMAP_INV_STAG		= 0x00,
	RDMAP_BASE_BOUNDS	= 0x01,
	RDMAP_ACC_VIOL		= 0x02,
	RDMAP_STAG_NOT_ASSOC	= 0x03,
	RDMAP_TO_WRAP		= 0x04,
	RDMAP_INV_VERS		= 0x05,
	RDMAP_INV_OPCODE	= 0x06,
	RDMAP_STREAM_CATA	= 0x07,
	RDMAP_GLOBAL_CATA	= 0x08,
	RDMAP_CANT_INV_STAG	= 0x09,
	RDMAP_UNSPECIFIED	= 0xff
};

enum c4iw_ddp_ecodes {
	DDPT_INV_STAG		= 0x00,
	DDPT_BASE_BOUNDS	= 0x01,
	DDPT_STAG_NOT_ASSOC	= 0x02,
	DDPT_TO_WRAP		= 0x03,
	DDPT_INV_VERS		= 0x04,
	DDPU_INV_QN		= 0x01,
	DDPU_INV_MSN_NOBUF	= 0x02,
	DDPU_INV_MSN_RANGE	= 0x03,
	DDPU_INV_MO		= 0x04,
	DDPU_MSG_TOOBIG		= 0x05,
	DDPU_INV_VERS		= 0x06
};

enum c4iw_mpa_ecodes {
	MPA_CRC_ERR		= 0x02,
	MPA_MARKER_ERR		= 0x03
};

enum c4iw_ep_state {
	IDLE = 0,
	LISTEN,
	CONNECTING,
	MPA_REQ_WAIT,
	MPA_REQ_SENT,
	MPA_REQ_RCVD,
	MPA_REP_SENT,
	FPDU_MODE,
	ABORTING,
	CLOSING,
	MORIBUND,
	DEAD,
};

enum c4iw_ep_flags {
	PEER_ABORT_IN_PROGRESS	= 0,
	ABORT_REQ_IN_PROGRESS	= 1,
	RELEASE_RESOURCES	= 2,
	CLOSE_SENT		= 3,
};

struct c4iw_ep_common {
	struct iw_cm_id *cm_id;
	struct c4iw_qp *qp;
	struct c4iw_dev *dev;
	enum c4iw_ep_state state;
	struct kref kref;
	spinlock_t lock;
	struct sockaddr_in local_addr;
	struct sockaddr_in remote_addr;
	wait_queue_head_t waitq;
	int rpl_done;
	int rpl_err;
	unsigned long flags;
};

struct c4iw_listen_ep {
	struct c4iw_ep_common com;
	unsigned int stid;
	int backlog;
};

struct c4iw_ep {
	struct c4iw_ep_common com;
	struct c4iw_ep *parent_ep;
	struct timer_list timer;
	struct list_head entry;
	unsigned int atid;
	u32 hwtid;
	u32 snd_seq;
	u32 rcv_seq;
	struct l2t_entry *l2t;
	struct dst_entry *dst;
	struct sk_buff *mpa_skb;
	struct c4iw_mpa_attributes mpa_attr;
	u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
	unsigned int mpa_pkt_len;
	u32 ird;
	u32 ord;
	u32 smac_idx;
	u32 tx_chan;
	u32 mtu;
	u16 mss;
	u16 emss;
	u16 plen;
	u16 rss_qid;
	u16 txq_idx;
	u8 tos;
};

static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
{
	return cm_id->provider_data;
}

static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
{
	return cm_id->provider_data;
}

static inline int compute_wscale(int win)
{
	int wscale = 0;

	while (wscale < 14 && (65535<<wscale) < win)
		wscale++;
	return wscale;
}

typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);

int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
		     struct l2t_entry *l2t);
void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
		   struct c4iw_dev_ucontext *uctx);
u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
int c4iw_pblpool_create(struct c4iw_rdev *rdev);
int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
void c4iw_destroy_resource(struct c4iw_resource *rscp);
int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
int c4iw_register_device(struct c4iw_dev *dev);
void c4iw_unregister_device(struct c4iw_dev *dev);
int __init c4iw_cm_init(void);
void __exit c4iw_cm_term(void);
void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
			       struct c4iw_dev_ucontext *uctx);
void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
			    struct c4iw_dev_ucontext *uctx);
int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
		      struct ib_send_wr **bad_wr);
int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
		      struct ib_recv_wr **bad_wr);
int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
		 struct ib_mw_bind *mw_bind);
int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
int c4iw_destroy_listen(struct iw_cm_id *cm_id);
int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
void c4iw_qp_add_ref(struct ib_qp *qp);
void c4iw_qp_rem_ref(struct ib_qp *qp);
void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
					struct ib_device *device,
					int page_list_len);
struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
int c4iw_dealloc_mw(struct ib_mw *mw);
struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
					   u64 length, u64 virt, int acc,
					   struct ib_udata *udata);
struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
					struct ib_phys_buf *buffer_list,
					int num_phys_buf,
					int acc,
					u64 *iova_start);
int c4iw_reregister_phys_mem(struct ib_mr *mr,
				     int mr_rereg_mask,
				     struct ib_pd *pd,
				     struct ib_phys_buf *buffer_list,
				     int num_phys_buf,
				     int acc, u64 *iova_start);
int c4iw_dereg_mr(struct ib_mr *ib_mr);
int c4iw_destroy_cq(struct ib_cq *ib_cq);
struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
					int vector,
					struct ib_ucontext *ib_context,
					struct ib_udata *udata);
int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
int c4iw_destroy_qp(struct ib_qp *ib_qp);
struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
			     struct ib_qp_init_attr *attrs,
			     struct ib_udata *udata);
int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
				 int attr_mask, struct ib_udata *udata);
struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
void c4iw_flush_hw_cq(struct t4_cq *cq);
void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
int c4iw_post_zb_read(struct c4iw_qp *qhp);
int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
		struct c4iw_dev_ucontext *uctx);
u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
		struct c4iw_dev_ucontext *uctx);
void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);

extern struct cxgb4_client t4c_client;
extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
extern int c4iw_max_read_depth;

#endif
Commit	Line	Data
cfdda9d7 SW	1	/*
	2	* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	* - Redistributions in binary form must reproduce the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer in the documentation and/or other materials
	20	* provided with the distribution.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	23	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	24	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	25	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	26	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	27	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	28	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	29	* SOFTWARE.
	30	*/
	31	#ifndef __IW_CXGB4_H__
	32	#define __IW_CXGB4_H__
	33
	34	#include <linux/mutex.h>
	35	#include <linux/list.h>
	36	#include <linux/spinlock.h>
	37	#include <linux/idr.h>
	38	#include <linux/workqueue.h>
	39	#include <linux/netdevice.h>
	40	#include <linux/sched.h>
	41	#include <linux/pci.h>
	42	#include <linux/dma-mapping.h>
	43	#include <linux/inet.h>
	44	#include <linux/wait.h>
	45	#include <linux/kref.h>
	46	#include <linux/timer.h>
	47	#include <linux/io.h>
	48	#include <linux/kfifo.h>
	49
	50	#include <asm/byteorder.h>
	51
	52	#include <net/net_namespace.h>
	53
	54	#include <rdma/ib_verbs.h>
	55	#include <rdma/iw_cm.h>
	56
	57	#include "cxgb4.h"
	58	#include "cxgb4_uld.h"
	59	#include "l2t.h"
	60	#include "user.h"
	61
	62	#define DRV_NAME "iw_cxgb4"
	63	#define MOD DRV_NAME ":"
	64
65	extern int c4iw_debug;
66	#define PDBG(fmt, args...) \
67	do { \
68	if (c4iw_debug) \
69	printk(MOD fmt, ## args); \
70	} while (0)
71
72	#include "t4.h"
73
74	#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
75	#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
76
77	static inline void cplhdr(struct sk_buff skb)
78	{
79	return skb->data;
80	}
81
82	#define C4IW_WR_TO (10*HZ)
83
84	struct c4iw_wr_wait {
85	wait_queue_head_t wait;
86	int done;
87	int ret;
88	};
89
90	static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
91	{
92	wr_waitp->ret = 0;
93	wr_waitp->done = 0;
94	init_waitqueue_head(&wr_waitp->wait);
95	}
96
97	struct c4iw_resource {
98	struct kfifo tpt_fifo;
99	spinlock_t tpt_fifo_lock;
100	struct kfifo qid_fifo;
101	spinlock_t qid_fifo_lock;
102	struct kfifo pdid_fifo;
103	spinlock_t pdid_fifo_lock;
104	};
105
106	struct c4iw_qid_list {
107	struct list_head entry;
108	u32 qid;
109	};
110
111	struct c4iw_dev_ucontext {
112	struct list_head qpids;
113	struct list_head cqids;
114	struct mutex lock;
115	};
116
117	enum c4iw_rdev_flags {
118	T4_FATAL_ERROR = (1<<0),
119	};
120
121	struct c4iw_rdev {
122	struct c4iw_resource resource;
123	unsigned long qpshift;
124	u32 qpmask;
125	unsigned long cqshift;
126	u32 cqmask;
127	struct c4iw_dev_ucontext uctx;
128	struct gen_pool *pbl_pool;
129	struct gen_pool *rqt_pool;
130	u32 flags;
131	struct cxgb4_lld_info lldi;
132	};
133
134	static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
135	{
136	return rdev->flags & T4_FATAL_ERROR;
137	}
138
139	static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
140	{
141	return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
142	}
143
144	struct c4iw_dev {
145	struct ib_device ibdev;
146	struct c4iw_rdev rdev;
147	u32 device_cap_flags;
148	struct idr cqidr;
149	struct idr qpidr;
150	struct idr mmidr;
151	spinlock_t lock;
152	struct list_head entry;
153	struct delayed_work db_drop_task;
154	struct dentry *debugfs_root;
155	};
156
157	static inline struct c4iw_dev to_c4iw_dev(struct ib_device ibdev)
158	{
159	return container_of(ibdev, struct c4iw_dev, ibdev);
160	}
161
162	static inline struct c4iw_dev rdev_to_c4iw_dev(struct c4iw_rdev rdev)
163	{
164	return container_of(rdev, struct c4iw_dev, rdev);
165	}
166
167	static inline struct c4iw_cq get_chp(struct c4iw_dev rhp, u32 cqid)
168	{
169	return idr_find(&rhp->cqidr, cqid);
170	}
171
172	static inline struct c4iw_qp get_qhp(struct c4iw_dev rhp, u32 qpid)
173	{
174	return idr_find(&rhp->qpidr, qpid);
175	}
176
177	static inline struct c4iw_mr get_mhp(struct c4iw_dev rhp, u32 mmid)
178	{
179	return idr_find(&rhp->mmidr, mmid);
180	}
181
182	static inline int insert_handle(struct c4iw_dev rhp, struct idr idr,
183	void *handle, u32 id)
184	{
185	int ret;
186	int newid;
187
188	do {
189	if (!idr_pre_get(idr, GFP_KERNEL))
190	return -ENOMEM;
191	spin_lock_irq(&rhp->lock);
192	ret = idr_get_new_above(idr, handle, id, &newid);
193	BUG_ON(newid != id);
194	spin_unlock_irq(&rhp->lock);
195	} while (ret == -EAGAIN);
196
197	return ret;
198	}
199
200	static inline void remove_handle(struct c4iw_dev rhp, struct idr idr, u32 id)
201	{
202	spin_lock_irq(&rhp->lock);
203	idr_remove(idr, id);
204	spin_unlock_irq(&rhp->lock);
205	}
206
207	struct c4iw_pd {
208	struct ib_pd ibpd;
209	u32 pdid;
210	struct c4iw_dev *rhp;
211	};
212
213	static inline struct c4iw_pd to_c4iw_pd(struct ib_pd ibpd)
214	{
215	return container_of(ibpd, struct c4iw_pd, ibpd);
216	}
217
218	struct tpt_attributes {
219	u64 len;
220	u64 va_fbo;
221	enum fw_ri_mem_perms perms;
222	u32 stag;
223	u32 pdid;
224	u32 qpid;
225	u32 pbl_addr;
226	u32 pbl_size;
227	u32 state:1;
228	u32 type:2;
229	u32 rsvd:1;
230	u32 remote_invaliate_disable:1;
231	u32 zbva:1;
232	u32 mw_bind_enable:1;
233	u32 page_size:5;
234	};
235
236	struct c4iw_mr {
237	struct ib_mr ibmr;
238	struct ib_umem *umem;
239	struct c4iw_dev *rhp;
240	u64 kva;
241	struct tpt_attributes attr;
242	};
243
244	static inline struct c4iw_mr to_c4iw_mr(struct ib_mr ibmr)
245	{
246	return container_of(ibmr, struct c4iw_mr, ibmr);
247	}
248
249	struct c4iw_mw {
250	struct ib_mw ibmw;
251	struct c4iw_dev *rhp;
252	u64 kva;
253	struct tpt_attributes attr;
254	};
255
256	static inline struct c4iw_mw to_c4iw_mw(struct ib_mw ibmw)
257	{
258	return container_of(ibmw, struct c4iw_mw, ibmw);
259	}
260
261	struct c4iw_fr_page_list {
262	struct ib_fast_reg_page_list ibpl;
263	DECLARE_PCI_UNMAP_ADDR(mapping);
264	dma_addr_t dma_addr;
265	struct c4iw_dev *dev;
266	int size;
267	};
268
269	static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
270	struct ib_fast_reg_page_list *ibpl)
271	{
272	return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
273	}
274
275	struct c4iw_cq {
276	struct ib_cq ibcq;
277	struct c4iw_dev *rhp;
278	struct t4_cq cq;
279	spinlock_t lock;
280	atomic_t refcnt;
281	wait_queue_head_t wait;
282	};
283
284	static inline struct c4iw_cq to_c4iw_cq(struct ib_cq ibcq)
285	{
286	return container_of(ibcq, struct c4iw_cq, ibcq);
287	}
288
289	struct c4iw_mpa_attributes {
290	u8 initiator;
291	u8 recv_marker_enabled;
292	u8 xmit_marker_enabled;
293	u8 crc_enabled;
294	u8 version;
295	u8 p2p_type;
296	};
297
298	struct c4iw_qp_attributes {
299	u32 scq;
300	u32 rcq;
301	u32 sq_num_entries;
302	u32 rq_num_entries;
303	u32 sq_max_sges;
304	u32 sq_max_sges_rdma_write;
305	u32 rq_max_sges;
306	u32 state;
307	u8 enable_rdma_read;
308	u8 enable_rdma_write;
309	u8 enable_bind;
310	u8 enable_mmid0_fastreg;
311	u32 max_ord;
312	u32 max_ird;
313	u32 pd;
314	u32 next_state;
315	char terminate_buffer[52];
316	u32 terminate_msg_len;
317	u8 is_terminate_local;
318	struct c4iw_mpa_attributes mpa_attr;
319	struct c4iw_ep *llp_stream_handle;
320	};
321
322	struct c4iw_qp {
323	struct ib_qp ibqp;
324	struct c4iw_dev *rhp;
325	struct c4iw_ep *ep;
326	struct c4iw_qp_attributes attr;
327	struct t4_wq wq;
328	spinlock_t lock;
329	atomic_t refcnt;
330	wait_queue_head_t wait;
331	struct timer_list timer;
332	};
333
334	static inline struct c4iw_qp to_c4iw_qp(struct ib_qp ibqp)
335	{
336	return container_of(ibqp, struct c4iw_qp, ibqp);
337	}
338
339	struct c4iw_ucontext {
340	struct ib_ucontext ibucontext;
341	struct c4iw_dev_ucontext uctx;
342	u32 key;
343	spinlock_t mmap_lock;
344	struct list_head mmaps;
345	};
346
347	static inline struct c4iw_ucontext to_c4iw_ucontext(struct ib_ucontext c)
348	{
349	return container_of(c, struct c4iw_ucontext, ibucontext);
350	}
351
352	struct c4iw_mm_entry {
353	struct list_head entry;
354	u64 addr;
355	u32 key;
356	unsigned len;
357	};
358
359	static inline struct c4iw_mm_entry remove_mmap(struct c4iw_ucontext ucontext,
360	u32 key, unsigned len)
361	{
362	struct list_head pos, nxt;
363	struct c4iw_mm_entry *mm;
364
365	spin_lock(&ucontext->mmap_lock);
366	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
367
368	mm = list_entry(pos, struct c4iw_mm_entry, entry);
369	if (mm->key == key && mm->len == len) {
370	list_del_init(&mm->entry);
371	spin_unlock(&ucontext->mmap_lock);
372	PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
373	key, (unsigned long long) mm->addr, mm->len);
374	return mm;
375	}
376	}
377	spin_unlock(&ucontext->mmap_lock);
378	return NULL;
379	}
380
381	static inline void insert_mmap(struct c4iw_ucontext *ucontext,
382	struct c4iw_mm_entry *mm)
383	{
384	spin_lock(&ucontext->mmap_lock);
385	PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
386	mm->key, (unsigned long long) mm->addr, mm->len);
387	list_add_tail(&mm->entry, &ucontext->mmaps);
388	spin_unlock(&ucontext->mmap_lock);
389	}
390
391	enum c4iw_qp_attr_mask {
392	C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
393	C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
394	C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
395	C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
396	C4IW_QP_ATTR_MAX_ORD = 1 << 11,
397	C4IW_QP_ATTR_MAX_IRD = 1 << 12,
398	C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
399	C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
400	C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
401	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
402	C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ \|
403	C4IW_QP_ATTR_ENABLE_RDMA_WRITE \|
404	C4IW_QP_ATTR_MAX_ORD \|
405	C4IW_QP_ATTR_MAX_IRD \|
406	C4IW_QP_ATTR_LLP_STREAM_HANDLE \|
407	C4IW_QP_ATTR_STREAM_MSG_BUFFER \|
408	C4IW_QP_ATTR_MPA_ATTR \|
409	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
410	};
411
412	int c4iw_modify_qp(struct c4iw_dev *rhp,
413	struct c4iw_qp *qhp,
414	enum c4iw_qp_attr_mask mask,
415	struct c4iw_qp_attributes *attrs,
416	int internal);
417
418	enum c4iw_qp_state {
419	C4IW_QP_STATE_IDLE,
420	C4IW_QP_STATE_RTS,
421	C4IW_QP_STATE_ERROR,
422	C4IW_QP_STATE_TERMINATE,
423	C4IW_QP_STATE_CLOSING,
424	C4IW_QP_STATE_TOT
425	};
426
427	static inline int c4iw_convert_state(enum ib_qp_state ib_state)
428	{
429	switch (ib_state) {
430	case IB_QPS_RESET:
431	case IB_QPS_INIT:
432	return C4IW_QP_STATE_IDLE;
433	case IB_QPS_RTS:
434	return C4IW_QP_STATE_RTS;
435	case IB_QPS_SQD:
436	return C4IW_QP_STATE_CLOSING;
437	case IB_QPS_SQE:
438	return C4IW_QP_STATE_TERMINATE;
439	case IB_QPS_ERR:
440	return C4IW_QP_STATE_ERROR;
441	default:
442	return -1;
443	}
444	}
445
446	static inline u32 c4iw_ib_to_tpt_access(int a)
447	{
448	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) \|
449	(a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) \|
450	(a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) \|
451	FW_RI_MEM_ACCESS_LOCAL_READ;
452	}
453
454	static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
455	{
456	return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) \|
457	(acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
458	}
459
460	enum c4iw_mmid_state {
461	C4IW_STAG_STATE_VALID,
462	C4IW_STAG_STATE_INVALID
463	};
464
465	#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
466
467	#define MPA_KEY_REQ "MPA ID Req Frame"
468	#define MPA_KEY_REP "MPA ID Rep Frame"
469
470	#define MPA_MAX_PRIVATE_DATA 256
471	#define MPA_REJECT 0x20
472	#define MPA_CRC 0x40
473	#define MPA_MARKERS 0x80
474	#define MPA_FLAGS_MASK 0xE0
475
476	#define c4iw_put_ep(ep) { \
477	PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
478	ep, atomic_read(&((ep)->kref.refcount))); \
479	WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
480	kref_put(&((ep)->kref), _c4iw_free_ep); \
481	}
482
483	#define c4iw_get_ep(ep) { \
484	PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
485	ep, atomic_read(&((ep)->kref.refcount))); \
486	kref_get(&((ep)->kref)); \
487	}
488	void _c4iw_free_ep(struct kref *kref);
489
490	struct mpa_message {
491	u8 key[16];
492	u8 flags;
493	u8 revision;
494	__be16 private_data_size;
495	u8 private_data[0];
496	};
497
498	struct terminate_message {
499	u8 layer_etype;
500	u8 ecode;
501	__be16 hdrct_rsvd;
502	u8 len_hdrs[0];
503	};
504
505	#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
506
507	enum c4iw_layers_types {
508	LAYER_RDMAP = 0x00,
509	LAYER_DDP = 0x10,
510	LAYER_MPA = 0x20,
511	RDMAP_LOCAL_CATA = 0x00,
512	RDMAP_REMOTE_PROT = 0x01,
513	RDMAP_REMOTE_OP = 0x02,
514	DDP_LOCAL_CATA = 0x00,
515	DDP_TAGGED_ERR = 0x01,
516	DDP_UNTAGGED_ERR = 0x02,
517	DDP_LLP = 0x03
518	};
519
520	enum c4iw_rdma_ecodes {
521	RDMAP_INV_STAG = 0x00,
522	RDMAP_BASE_BOUNDS = 0x01,
523	RDMAP_ACC_VIOL = 0x02,
524	RDMAP_STAG_NOT_ASSOC = 0x03,
525	RDMAP_TO_WRAP = 0x04,
526	RDMAP_INV_VERS = 0x05,
527	RDMAP_INV_OPCODE = 0x06,
528	RDMAP_STREAM_CATA = 0x07,
529	RDMAP_GLOBAL_CATA = 0x08,
530	RDMAP_CANT_INV_STAG = 0x09,
531	RDMAP_UNSPECIFIED = 0xff
532	};
533
534	enum c4iw_ddp_ecodes {
535	DDPT_INV_STAG = 0x00,
536	DDPT_BASE_BOUNDS = 0x01,
537	DDPT_STAG_NOT_ASSOC = 0x02,
538	DDPT_TO_WRAP = 0x03,
539	DDPT_INV_VERS = 0x04,
540	DDPU_INV_QN = 0x01,
541	DDPU_INV_MSN_NOBUF = 0x02,
542	DDPU_INV_MSN_RANGE = 0x03,
543	DDPU_INV_MO = 0x04,
544	DDPU_MSG_TOOBIG = 0x05,
545	DDPU_INV_VERS = 0x06
546	};
547
548	enum c4iw_mpa_ecodes {
549	MPA_CRC_ERR = 0x02,
550	MPA_MARKER_ERR = 0x03
551	};
552
553	enum c4iw_ep_state {
554	IDLE = 0,
555	LISTEN,
556	CONNECTING,
557	MPA_REQ_WAIT,
558	MPA_REQ_SENT,
559	MPA_REQ_RCVD,
560	MPA_REP_SENT,
561	FPDU_MODE,
562	ABORTING,
563	CLOSING,
564	MORIBUND,
565	DEAD,
566	};
567
568	enum c4iw_ep_flags {
569	PEER_ABORT_IN_PROGRESS = 0,
570	ABORT_REQ_IN_PROGRESS = 1,
571	RELEASE_RESOURCES = 2,
572	CLOSE_SENT = 3,
573	};
574
575	struct c4iw_ep_common {
576	struct iw_cm_id *cm_id;
577	struct c4iw_qp *qp;
578	struct c4iw_dev *dev;
579	enum c4iw_ep_state state;
580	struct kref kref;
581	spinlock_t lock;
582	struct sockaddr_in local_addr;
583	struct sockaddr_in remote_addr;
584	wait_queue_head_t waitq;
585	int rpl_done;
586	int rpl_err;
587	unsigned long flags;
588	};
589
590	struct c4iw_listen_ep {
591	struct c4iw_ep_common com;
592	unsigned int stid;
593	int backlog;
594	};
595
596	struct c4iw_ep {
597	struct c4iw_ep_common com;
598	struct c4iw_ep *parent_ep;
599	struct timer_list timer;
be4c9bad	600	struct list_head entry;
cfdda9d7 SW	601	unsigned int atid;
	602	u32 hwtid;
	603	u32 snd_seq;
	604	u32 rcv_seq;
	605	struct l2t_entry *l2t;
	606	struct dst_entry *dst;
	607	struct sk_buff *mpa_skb;
	608	struct c4iw_mpa_attributes mpa_attr;
	609	u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
	610	unsigned int mpa_pkt_len;
	611	u32 ird;
	612	u32 ord;
	613	u32 smac_idx;
	614	u32 tx_chan;
	615	u32 mtu;
	616	u16 mss;
	617	u16 emss;
	618	u16 plen;
	619	u16 rss_qid;
	620	u16 txq_idx;
	621	u8 tos;
	622	};
	623
	624	static inline struct c4iw_ep to_ep(struct iw_cm_id cm_id)
	625	{
	626	return cm_id->provider_data;
	627	}
	628
	629	static inline struct c4iw_listen_ep to_listen_ep(struct iw_cm_id cm_id)
	630	{
	631	return cm_id->provider_data;
	632	}
	633
	634	static inline int compute_wscale(int win)
	635	{
	636	int wscale = 0;
	637
	638	while (wscale < 14 && (65535<<wscale) < win)
	639	wscale++;
	640	return wscale;
	641	}
	642
	643	typedef int (c4iw_handler_func)(struct c4iw_dev dev, struct sk_buff *skb);
	644
	645	int c4iw_ep_redirect(void ctx, struct dst_entry old, struct dst_entry *new,
	646	struct l2t_entry *l2t);
	647	void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
	648	struct c4iw_dev_ucontext *uctx);
	649	u32 c4iw_get_resource(struct kfifo fifo, spinlock_t lock);
	650	void c4iw_put_resource(struct kfifo fifo, u32 entry, spinlock_t lock);
	651	int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
	652	int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
	653	int c4iw_pblpool_create(struct c4iw_rdev *rdev);
	654	int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
	655	void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
	656	void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
	657	void c4iw_destroy_resource(struct c4iw_resource *rscp);
	658	int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
	659	int c4iw_register_device(struct c4iw_dev *dev);
	660	void c4iw_unregister_device(struct c4iw_dev *dev);
	661	int __init c4iw_cm_init(void);
	662	void __exit c4iw_cm_term(void);
	663	void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
	664	struct c4iw_dev_ucontext *uctx);
665	void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
666	struct c4iw_dev_ucontext *uctx);
667	int c4iw_poll_cq(struct ib_cq ibcq, int num_entries, struct ib_wc wc);
668	int c4iw_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
669	struct ib_send_wr **bad_wr);
670	int c4iw_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
671	struct ib_recv_wr **bad_wr);
672	int c4iw_bind_mw(struct ib_qp qp, struct ib_mw mw,
673	struct ib_mw_bind *mw_bind);
674	int c4iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param);
675	int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
676	int c4iw_destroy_listen(struct iw_cm_id *cm_id);
677	int c4iw_accept_cr(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param);
678	int c4iw_reject_cr(struct iw_cm_id cm_id, const void pdata, u8 pdata_len);
679	void c4iw_qp_add_ref(struct ib_qp *qp);
680	void c4iw_qp_rem_ref(struct ib_qp *qp);
681	void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
682	struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
683	struct ib_device *device,
684	int page_list_len);
685	struct ib_mr c4iw_alloc_fast_reg_mr(struct ib_pd pd, int pbl_depth);
686	int c4iw_dealloc_mw(struct ib_mw *mw);
687	struct ib_mw c4iw_alloc_mw(struct ib_pd pd);
688	struct ib_mr c4iw_reg_user_mr(struct ib_pd pd, u64 start,
689	u64 length, u64 virt, int acc,
690	struct ib_udata *udata);
691	struct ib_mr c4iw_get_dma_mr(struct ib_pd pd, int acc);
692	struct ib_mr c4iw_register_phys_mem(struct ib_pd pd,
693	struct ib_phys_buf *buffer_list,
694	int num_phys_buf,
695	int acc,
696	u64 *iova_start);
697	int c4iw_reregister_phys_mem(struct ib_mr *mr,
698	int mr_rereg_mask,
699	struct ib_pd *pd,
700	struct ib_phys_buf *buffer_list,
701	int num_phys_buf,
702	int acc, u64 *iova_start);
703	int c4iw_dereg_mr(struct ib_mr *ib_mr);
704	int c4iw_destroy_cq(struct ib_cq *ib_cq);
705	struct ib_cq c4iw_create_cq(struct ib_device ibdev, int entries,
706	int vector,
707	struct ib_ucontext *ib_context,
708	struct ib_udata *udata);
709	int c4iw_resize_cq(struct ib_cq cq, int cqe, struct ib_udata udata);
710	int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
711	int c4iw_destroy_qp(struct ib_qp *ib_qp);
712	struct ib_qp c4iw_create_qp(struct ib_pd pd,
713	struct ib_qp_init_attr *attrs,
714	struct ib_udata *udata);
715	int c4iw_ib_modify_qp(struct ib_qp ibqp, struct ib_qp_attr attr,
716	int attr_mask, struct ib_udata *udata);
717	struct ib_qp c4iw_get_qp(struct ib_device dev, int qpn);
718	u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
719	void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
720	u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
721	void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
722	int c4iw_ofld_send(struct c4iw_rdev rdev, struct sk_buff skb);
723	void c4iw_flush_hw_cq(struct t4_cq *cq);
724	void c4iw_count_rcqes(struct t4_cq cq, struct t4_wq wq, int *count);
725	void c4iw_count_scqes(struct t4_cq cq, struct t4_wq wq, int *count);
726	int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
727	int c4iw_flush_rq(struct t4_wq wq, struct t4_cq cq, int count);
728	int c4iw_flush_sq(struct t4_wq wq, struct t4_cq cq, int count);
729	int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
730	u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
731	int c4iw_post_zb_read(struct c4iw_qp *qhp);
732	int c4iw_post_terminate(struct c4iw_qp qhp, struct t4_cqe err_cqe);
733	u32 c4iw_get_cqid(struct c4iw_rdev rdev, struct c4iw_dev_ucontext uctx);
734	void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
735	struct c4iw_dev_ucontext *uctx);
736	u32 c4iw_get_qpid(struct c4iw_rdev rdev, struct c4iw_dev_ucontext uctx);
737	void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
738	struct c4iw_dev_ucontext *uctx);
739	void c4iw_ev_dispatch(struct c4iw_dev dev, struct t4_cqe err_cqe);
740
741	extern struct cxgb4_client t4c_client;
742	extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
be4c9bad	743	extern int c4iw_max_read_depth;
cfdda9d7 SW	744
cfdda9d7 SW	745	#endif