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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
3cbdb928 45int db_fc_threshold = 1000;
422eea0a 46module_param(db_fc_threshold, int, 0644);
3cbdb928
VP		 47MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51int db_coalescing_threshold;
52module_param(db_coalescing_threshold, int, 0644);
53MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
422eea0a 56
42b6a949
VP		 57static int max_fr_immd = T4_MAX_FR_IMMD;
58module_param(max_fr_immd, int, 0644);
59MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
2f5b48c3
SW		 61static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
62{
63 unsigned long flag;
64 spin_lock_irqsave(&qhp->lock, flag);
65 qhp->attr.state = state;
66 spin_unlock_irqrestore(&qhp->lock, flag);
67}
68
c6d7b267
SW		 69static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
70{
71 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
72}
73
74static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
75{
76 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
77 pci_unmap_addr(sq, mapping));
78}
79
80static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 if (t4_sq_onchip(sq))
83 dealloc_oc_sq(rdev, sq);
84 else
85 dealloc_host_sq(rdev, sq);
86}
87
88static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
89{
f079af7a 90 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
c6d7b267
SW		 91 return -ENOSYS;
92 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
93 if (!sq->dma_addr)
94 return -ENOMEM;
95 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
96 rdev->lldi.vr->ocq.start;
97 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
98 rdev->lldi.vr->ocq.start);
99 sq->flags |= T4_SQ_ONCHIP;
100 return 0;
101}
102
103static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
104{
105 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
106 &(sq->dma_addr), GFP_KERNEL);
107 if (!sq->queue)
108 return -ENOMEM;
109 sq->phys_addr = virt_to_phys(sq->queue);
110 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
111 return 0;
112}
113
5b0c2759
TLSC		 114static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
115{
116 int ret = -ENOSYS;
117 if (user)
118 ret = alloc_oc_sq(rdev, sq);
119 if (ret)
120 ret = alloc_host_sq(rdev, sq);
121 return ret;
122}
123
cfdda9d7
SW		 124static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct c4iw_dev_ucontext *uctx)
126{
127 /*
128 * uP clears EQ contexts when the connection exits rdma mode,
129 * so no need to post a RESET WR for these EQs.
130 */
131 dma_free_coherent(&(rdev->lldi.pdev->dev),
132 wq->rq.memsize, wq->rq.queue,
f38926aa 133 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 134 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 135 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
136 kfree(wq->rq.sw_rq);
137 kfree(wq->sq.sw_sq);
138 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
139 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
140 return 0;
141}
142
143static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 struct t4_cq *rcq, struct t4_cq *scq,
145 struct c4iw_dev_ucontext *uctx)
146{
147 int user = (uctx != &rdev->uctx);
148 struct fw_ri_res_wr *res_wr;
149 struct fw_ri_res *res;
150 int wr_len;
151 struct c4iw_wr_wait wr_wait;
152 struct sk_buff *skb;
9919d5bd 153 int ret = 0;
cfdda9d7
SW		 154 int eqsize;
155
156 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
157 if (!wq->sq.qid)
158 return -ENOMEM;
159
160 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
c079c287
EG		 161 if (!wq->rq.qid) {
162 ret = -ENOMEM;
163 goto free_sq_qid;
164 }
cfdda9d7
SW		 165
166 if (!user) {
167 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
168 GFP_KERNEL);
c079c287
EG		 169 if (!wq->sq.sw_sq) {
170 ret = -ENOMEM;
171 goto free_rq_qid;
172 }
cfdda9d7
SW		 173
174 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
175 GFP_KERNEL);
c079c287
EG		 176 if (!wq->rq.sw_rq) {
177 ret = -ENOMEM;
178 goto free_sw_sq;
179 }
cfdda9d7
SW		 180 }
181
182 /*
183 * RQT must be a power of 2.
184 */
185 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
186 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
c079c287
EG		 187 if (!wq->rq.rqt_hwaddr) {
188 ret = -ENOMEM;
189 goto free_sw_rq;
190 }
cfdda9d7 191
5b0c2759
TLSC		 192 ret = alloc_sq(rdev, &wq->sq, user);
193 if (ret)
194 goto free_hwaddr;
cfdda9d7 195 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 196 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 197
198 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
199 wq->rq.memsize, &(wq->rq.dma_addr),
200 GFP_KERNEL);
55e57a78
WY		 201 if (!wq->rq.queue) {
202 ret = -ENOMEM;
c079c287 203 goto free_sq;
55e57a78 204 }
cfdda9d7
SW		 205 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
206 __func__, wq->sq.queue,
207 (unsigned long long)virt_to_phys(wq->sq.queue),
208 wq->rq.queue,
209 (unsigned long long)virt_to_phys(wq->rq.queue));
210 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 211 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 212
213 wq->db = rdev->lldi.db_reg;
214 wq->gts = rdev->lldi.gts_reg;
215 if (user) {
216 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
217 (wq->sq.qid << rdev->qpshift);
218 wq->sq.udb &= PAGE_MASK;
219 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
220 (wq->rq.qid << rdev->qpshift);
221 wq->rq.udb &= PAGE_MASK;
222 }
223 wq->rdev = rdev;
224 wq->rq.msn = 1;
225
226 /* build fw_ri_res_wr */
227 wr_len = sizeof *res_wr + 2 * sizeof *res;
228
d3c814e8 229 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 230 if (!skb) {
231 ret = -ENOMEM;
c079c287 232 goto free_dma;
cfdda9d7
SW		 233 }
234 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
235
236 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
237 memset(res_wr, 0, wr_len);
238 res_wr->op_nres = cpu_to_be32(
239 FW_WR_OP(FW_RI_RES_WR) |
240 V_FW_RI_RES_WR_NRES(2) |
241 FW_WR_COMPL(1));
242 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 243 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 244 res = res_wr->res;
245 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
246 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
247
248 /*
249 * eqsize is the number of 64B entries plus the status page size.
250 */
251 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
252
253 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
254 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
255 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
256 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 257 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 258 V_FW_RI_RES_WR_IQID(scq->cqid));
259 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
260 V_FW_RI_RES_WR_DCAEN(0) |
261 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 262 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 263 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 264 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
265 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
266 V_FW_RI_RES_WR_EQSIZE(eqsize));
267 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
268 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
269 res++;
270 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
271 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
272
273 /*
274 * eqsize is the number of 64B entries plus the status page size.
275 */
276 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
277 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
278 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
279 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
280 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
281 V_FW_RI_RES_WR_IQID(rcq->cqid));
282 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
283 V_FW_RI_RES_WR_DCAEN(0) |
284 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 285 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 286 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 287 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
288 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
289 V_FW_RI_RES_WR_EQSIZE(eqsize));
290 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
291 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
292
293 c4iw_init_wr_wait(&wr_wait);
294
295 ret = c4iw_ofld_send(rdev, skb);
296 if (ret)
c079c287 297 goto free_dma;
aadc4df3 298 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7 299 if (ret)
c079c287 300 goto free_dma;
cfdda9d7
SW		 301
302 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
303 __func__, wq->sq.qid, wq->rq.qid, wq->db,
304 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
305
306 return 0;
c079c287 307free_dma:
cfdda9d7
SW		 308 dma_free_coherent(&(rdev->lldi.pdev->dev),
309 wq->rq.memsize, wq->rq.queue,
f38926aa 310 dma_unmap_addr(&wq->rq, mapping));
c079c287 311free_sq:
c6d7b267 312 dealloc_sq(rdev, &wq->sq);
c079c287 313free_hwaddr:
cfdda9d7 314 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
c079c287 315free_sw_rq:
cfdda9d7 316 kfree(wq->rq.sw_rq);
c079c287 317free_sw_sq:
cfdda9d7 318 kfree(wq->sq.sw_sq);
c079c287 319free_rq_qid:
cfdda9d7 320 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
c079c287 321free_sq_qid:
cfdda9d7 322 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
c079c287 323 return ret;
cfdda9d7
SW		 324}
325
d37ac31d
SW		 326static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
327 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 328{
d37ac31d
SW		 329 u8 *dstp, *srcp;
330 u32 plen = 0;
cfdda9d7 331 int i;
d37ac31d
SW		 332 int rem, len;
333
334 dstp = (u8 *)immdp->data;
335 for (i = 0; i < wr->num_sge; i++) {
336 if ((plen + wr->sg_list[i].length) > max)
337 return -EMSGSIZE;
338 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
339 plen += wr->sg_list[i].length;
340 rem = wr->sg_list[i].length;
341 while (rem) {
342 if (dstp == (u8 *)&sq->queue[sq->size])
343 dstp = (u8 *)sq->queue;
344 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
345 len = rem;
346 else
347 len = (u8 *)&sq->queue[sq->size] - dstp;
348 memcpy(dstp, srcp, len);
349 dstp += len;
350 srcp += len;
351 rem -= len;
352 }
353 }
13fecb83
SW		 354 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
355 if (len)
356 memset(dstp, 0, len);
d37ac31d
SW		 357 immdp->op = FW_RI_DATA_IMMD;
358 immdp->r1 = 0;
359 immdp->r2 = 0;
360 immdp->immdlen = cpu_to_be32(plen);
361 *plenp = plen;
362 return 0;
363}
364
365static int build_isgl(__be64 *queue_start, __be64 *queue_end,
366 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
367 int num_sge, u32 *plenp)
368
369{
370 int i;
371 u32 plen = 0;
372 __be64 *flitp = (__be64 *)isglp->sge;
373
374 for (i = 0; i < num_sge; i++) {
375 if ((plen + sg_list[i].length) < plen)
376 return -EMSGSIZE;
377 plen += sg_list[i].length;
378 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
379 sg_list[i].length);
380 if (++flitp == queue_end)
381 flitp = queue_start;
382 *flitp = cpu_to_be64(sg_list[i].addr);
383 if (++flitp == queue_end)
384 flitp = queue_start;
385 }
13fecb83 386 *flitp = (__force __be64)0;
d37ac31d
SW		 387 isglp->op = FW_RI_DATA_ISGL;
388 isglp->r1 = 0;
389 isglp->nsge = cpu_to_be16(num_sge);
390 isglp->r2 = 0;
391 if (plenp)
392 *plenp = plen;
393 return 0;
394}
395
396static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
397 struct ib_send_wr *wr, u8 *len16)
398{
cfdda9d7
SW		 399 u32 plen;
400 int size;
d37ac31d 401 int ret;
cfdda9d7
SW		 402
403 if (wr->num_sge > T4_MAX_SEND_SGE)
404 return -EINVAL;
405 switch (wr->opcode) {
406 case IB_WR_SEND:
407 if (wr->send_flags & IB_SEND_SOLICITED)
408 wqe->send.sendop_pkd = cpu_to_be32(
409 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
410 else
411 wqe->send.sendop_pkd = cpu_to_be32(
412 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
413 wqe->send.stag_inv = 0;
414 break;
415 case IB_WR_SEND_WITH_INV:
416 if (wr->send_flags & IB_SEND_SOLICITED)
417 wqe->send.sendop_pkd = cpu_to_be32(
418 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
419 else
420 wqe->send.sendop_pkd = cpu_to_be32(
421 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
422 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
423 break;
424
425 default:
426 return -EINVAL;
427 }
d37ac31d 428
cfdda9d7
SW		 429 plen = 0;
430 if (wr->num_sge) {
431 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 432 ret = build_immd(sq, wqe->send.u.immd_src, wr,
433 T4_MAX_SEND_INLINE, &plen);
434 if (ret)
435 return ret;
cfdda9d7
SW		 436 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
437 plen;
438 } else {
d37ac31d
SW		 439 ret = build_isgl((__be64 *)sq->queue,
440 (__be64 *)&sq->queue[sq->size],
441 wqe->send.u.isgl_src,
442 wr->sg_list, wr->num_sge, &plen);
443 if (ret)
444 return ret;
cfdda9d7
SW		 445 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
446 wr->num_sge * sizeof(struct fw_ri_sge);
447 }
448 } else {
449 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
450 wqe->send.u.immd_src[0].r1 = 0;
451 wqe->send.u.immd_src[0].r2 = 0;
452 wqe->send.u.immd_src[0].immdlen = 0;
453 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 454 plen = 0;
cfdda9d7
SW		 455 }
456 *len16 = DIV_ROUND_UP(size, 16);
457 wqe->send.plen = cpu_to_be32(plen);
458 return 0;
459}
460
d37ac31d
SW		 461static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
462 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 463{
cfdda9d7
SW		 464 u32 plen;
465 int size;
d37ac31d 466 int ret;
cfdda9d7 467
d37ac31d 468 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 469 return -EINVAL;
470 wqe->write.r2 = 0;
471 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
472 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 473 if (wr->num_sge) {
474 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 475 ret = build_immd(sq, wqe->write.u.immd_src, wr,
476 T4_MAX_WRITE_INLINE, &plen);
477 if (ret)
478 return ret;
cfdda9d7
SW		 479 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
480 plen;
481 } else {
d37ac31d
SW		 482 ret = build_isgl((__be64 *)sq->queue,
483 (__be64 *)&sq->queue[sq->size],
484 wqe->write.u.isgl_src,
485 wr->sg_list, wr->num_sge, &plen);
486 if (ret)
487 return ret;
cfdda9d7
SW		 488 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
489 wr->num_sge * sizeof(struct fw_ri_sge);
490 }
491 } else {
492 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
493 wqe->write.u.immd_src[0].r1 = 0;
494 wqe->write.u.immd_src[0].r2 = 0;
495 wqe->write.u.immd_src[0].immdlen = 0;
496 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 497 plen = 0;
cfdda9d7
SW		 498 }
499 *len16 = DIV_ROUND_UP(size, 16);
500 wqe->write.plen = cpu_to_be32(plen);
501 return 0;
502}
503
504static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
505{
506 if (wr->num_sge > 1)
507 return -EINVAL;
508 if (wr->num_sge) {
509 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
510 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
511 >> 32));
512 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
513 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
514 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
515 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
516 >> 32));
517 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
518 } else {
519 wqe->read.stag_src = cpu_to_be32(2);
520 wqe->read.to_src_hi = 0;
521 wqe->read.to_src_lo = 0;
522 wqe->read.stag_sink = cpu_to_be32(2);
523 wqe->read.plen = 0;
524 wqe->read.to_sink_hi = 0;
525 wqe->read.to_sink_lo = 0;
526 }
527 wqe->read.r2 = 0;
528 wqe->read.r5 = 0;
529 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
530 return 0;
531}
532
533static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
534 struct ib_recv_wr *wr, u8 *len16)
535{
d37ac31d 536 int ret;
cfdda9d7 537
d37ac31d
SW		 538 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
539 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
540 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
541 if (ret)
542 return ret;
cfdda9d7
SW		 543 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
544 wr->num_sge * sizeof(struct fw_ri_sge), 16);
545 return 0;
546}
547
40dbf6ee 548static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
42b6a949 549 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
cfdda9d7
SW		 550{
551
552 struct fw_ri_immd *imdp;
553 __be64 *p;
554 int i;
555 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 556 int rem;
cfdda9d7
SW		 557
558 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
559 return -EINVAL;
560
561 wqe->fr.qpbinde_to_dcacpu = 0;
562 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
563 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
564 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
565 wqe->fr.len_hi = 0;
566 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
567 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
568 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
569 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
570 0xffffffff);
42b6a949
VP		 571
572 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
573 struct c4iw_fr_page_list *c4pl =
574 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
575 struct fw_ri_dsgl *sglp;
576
577 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
578 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
579 cpu_to_be64((u64)
580 wr->wr.fast_reg.page_list->page_list[i]);
581 }
582
583 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
584 sglp->op = FW_RI_DATA_DSGL;
585 sglp->r1 = 0;
586 sglp->nsge = cpu_to_be16(1);
587 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
588 sglp->len0 = cpu_to_be32(pbllen);
589
590 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
591 } else {
592 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
593 imdp->op = FW_RI_DATA_IMMD;
594 imdp->r1 = 0;
595 imdp->r2 = 0;
596 imdp->immdlen = cpu_to_be32(pbllen);
597 p = (__be64 *)(imdp + 1);
598 rem = pbllen;
599 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
600 *p = cpu_to_be64(
601 (u64)wr->wr.fast_reg.page_list->page_list[i]);
602 rem -= sizeof(*p);
603 if (++p == (__be64 *)&sq->queue[sq->size])
604 p = (__be64 *)sq->queue;
605 }
606 BUG_ON(rem < 0);
607 while (rem) {
608 *p = 0;
609 rem -= sizeof(*p);
610 if (++p == (__be64 *)&sq->queue[sq->size])
611 p = (__be64 *)sq->queue;
612 }
613 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
614 + pbllen, 16);
cfdda9d7
SW		 615 }
616 return 0;
617}
618
619static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
620 u8 *len16)
621{
622 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
623 wqe->inv.r2 = 0;
624 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
625 return 0;
626}
627
628void c4iw_qp_add_ref(struct ib_qp *qp)
629{
630 PDBG("%s ib_qp %p\n", __func__, qp);
631 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
632}
633
634void c4iw_qp_rem_ref(struct ib_qp *qp)
635{
636 PDBG("%s ib_qp %p\n", __func__, qp);
637 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
638 wake_up(&(to_c4iw_qp(qp)->wait));
639}
640
05eb2389
SW		 641static void add_to_fc_list(struct list_head *head, struct list_head *entry)
642{
643 if (list_empty(entry))
644 list_add_tail(entry, head);
645}
646
647static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
648{
649 unsigned long flags;
650
651 spin_lock_irqsave(&qhp->rhp->lock, flags);
652 spin_lock(&qhp->lock);
653 if (qhp->rhp->db_state == NORMAL) {
654 t4_ring_sq_db(&qhp->wq, inc);
655 } else {
656 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
657 qhp->wq.sq.wq_pidx_inc += inc;
658 }
659 spin_unlock(&qhp->lock);
660 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
661 return 0;
662}
663
664static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
665{
666 unsigned long flags;
667
668 spin_lock_irqsave(&qhp->rhp->lock, flags);
669 spin_lock(&qhp->lock);
670 if (qhp->rhp->db_state == NORMAL) {
671 t4_ring_rq_db(&qhp->wq, inc);
672 } else {
673 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
674 qhp->wq.rq.wq_pidx_inc += inc;
675 }
676 spin_unlock(&qhp->lock);
677 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
678 return 0;
679}
680
cfdda9d7
SW		 681int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
682 struct ib_send_wr **bad_wr)
683{
684 int err = 0;
685 u8 len16 = 0;
686 enum fw_wr_opcodes fw_opcode = 0;
687 enum fw_ri_wr_flags fw_flags;
688 struct c4iw_qp *qhp;
689 union t4_wr *wqe;
690 u32 num_wrs;
691 struct t4_swsqe *swsqe;
692 unsigned long flag;
693 u16 idx = 0;
694
695 qhp = to_c4iw_qp(ibqp);
696 spin_lock_irqsave(&qhp->lock, flag);
697 if (t4_wq_in_error(&qhp->wq)) {
698 spin_unlock_irqrestore(&qhp->lock, flag);
699 return -EINVAL;
700 }
701 num_wrs = t4_sq_avail(&qhp->wq);
702 if (num_wrs == 0) {
703 spin_unlock_irqrestore(&qhp->lock, flag);
704 return -ENOMEM;
705 }
706 while (wr) {
707 if (num_wrs == 0) {
708 err = -ENOMEM;
709 *bad_wr = wr;
710 break;
711 }
d37ac31d
SW		 712 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
713 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
714
cfdda9d7
SW		 715 fw_flags = 0;
716 if (wr->send_flags & IB_SEND_SOLICITED)
717 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
718 if (wr->send_flags & IB_SEND_SIGNALED)
719 fw_flags |= FW_RI_COMPLETION_FLAG;
720 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
721 switch (wr->opcode) {
722 case IB_WR_SEND_WITH_INV:
723 case IB_WR_SEND:
724 if (wr->send_flags & IB_SEND_FENCE)
725 fw_flags |= FW_RI_READ_FENCE_FLAG;
726 fw_opcode = FW_RI_SEND_WR;
727 if (wr->opcode == IB_WR_SEND)
728 swsqe->opcode = FW_RI_SEND;
729 else
730 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 731 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 732 break;
733 case IB_WR_RDMA_WRITE:
734 fw_opcode = FW_RI_RDMA_WRITE_WR;
735 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 736 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 737 break;
738 case IB_WR_RDMA_READ:
2f1fb507 739 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 740 fw_opcode = FW_RI_RDMA_READ_WR;
741 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 742 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 743 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 744 else
745 fw_flags = 0;
cfdda9d7
SW		 746 err = build_rdma_read(wqe, wr, &len16);
747 if (err)
748 break;
749 swsqe->read_len = wr->sg_list[0].length;
750 if (!qhp->wq.sq.oldest_read)
751 qhp->wq.sq.oldest_read = swsqe;
752 break;
753 case IB_WR_FAST_REG_MR:
754 fw_opcode = FW_RI_FR_NSMR_WR;
755 swsqe->opcode = FW_RI_FAST_REGISTER;
42b6a949
VP		 756 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
757 is_t5(
758 qhp->rhp->rdev.lldi.adapter_type) ?
759 1 : 0);
cfdda9d7
SW		 760 break;
761 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 762 if (wr->send_flags & IB_SEND_FENCE)
763 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 764 fw_opcode = FW_RI_INV_LSTAG_WR;
765 swsqe->opcode = FW_RI_LOCAL_INV;
766 err = build_inv_stag(wqe, wr, &len16);
767 break;
768 default:
769 PDBG("%s post of type=%d TBD!\n", __func__,
770 wr->opcode);
771 err = -EINVAL;
772 }
773 if (err) {
774 *bad_wr = wr;
775 break;
776 }
777 swsqe->idx = qhp->wq.sq.pidx;
778 swsqe->complete = 0;
779 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
1cf24dce 780 swsqe->flushed = 0;
cfdda9d7
SW		 781 swsqe->wr_id = wr->wr_id;
782
783 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
784
785 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
786 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
787 swsqe->opcode, swsqe->read_len);
788 wr = wr->next;
789 num_wrs--;
d37ac31d
SW		 790 t4_sq_produce(&qhp->wq, len16);
791 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7 792 }
05eb2389 793 if (!qhp->rhp->rdev.status_page->db_off) {
cfdda9d7 794 t4_ring_sq_db(&qhp->wq, idx);
05eb2389
SW		 795 spin_unlock_irqrestore(&qhp->lock, flag);
796 } else {
797 spin_unlock_irqrestore(&qhp->lock, flag);
798 ring_kernel_sq_db(qhp, idx);
799 }
cfdda9d7
SW		 800 return err;
801}
802
803int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
804 struct ib_recv_wr **bad_wr)
805{
806 int err = 0;
807 struct c4iw_qp *qhp;
808 union t4_recv_wr *wqe;
809 u32 num_wrs;
810 u8 len16 = 0;
811 unsigned long flag;
812 u16 idx = 0;
813
814 qhp = to_c4iw_qp(ibqp);
815 spin_lock_irqsave(&qhp->lock, flag);
816 if (t4_wq_in_error(&qhp->wq)) {
817 spin_unlock_irqrestore(&qhp->lock, flag);
818 return -EINVAL;
819 }
820 num_wrs = t4_rq_avail(&qhp->wq);
821 if (num_wrs == 0) {
822 spin_unlock_irqrestore(&qhp->lock, flag);
823 return -ENOMEM;
824 }
825 while (wr) {
826 if (wr->num_sge > T4_MAX_RECV_SGE) {
827 err = -EINVAL;
828 *bad_wr = wr;
829 break;
830 }
d37ac31d
SW		 831 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
832 qhp->wq.rq.wq_pidx *
833 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 834 if (num_wrs)
835 err = build_rdma_recv(qhp, wqe, wr, &len16);
836 else
837 err = -ENOMEM;
838 if (err) {
839 *bad_wr = wr;
840 break;
841 }
842
843 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
844
845 wqe->recv.opcode = FW_RI_RECV_WR;
846 wqe->recv.r1 = 0;
847 wqe->recv.wrid = qhp->wq.rq.pidx;
848 wqe->recv.r2[0] = 0;
849 wqe->recv.r2[1] = 0;
850 wqe->recv.r2[2] = 0;
851 wqe->recv.len16 = len16;
cfdda9d7
SW		 852 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
853 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 854 t4_rq_produce(&qhp->wq, len16);
855 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 856 wr = wr->next;
857 num_wrs--;
cfdda9d7 858 }
05eb2389 859 if (!qhp->rhp->rdev.status_page->db_off) {
cfdda9d7 860 t4_ring_rq_db(&qhp->wq, idx);
05eb2389
SW		 861 spin_unlock_irqrestore(&qhp->lock, flag);
862 } else {
863 spin_unlock_irqrestore(&qhp->lock, flag);
864 ring_kernel_rq_db(qhp, idx);
865 }
cfdda9d7
SW		 866 return err;
867}
868
869int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
870{
871 return -ENOSYS;
872}
873
874static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
875 u8 *ecode)
876{
877 int status;
878 int tagged;
879 int opcode;
880 int rqtype;
881 int send_inv;
882
883 if (!err_cqe) {
884 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
885 *ecode = 0;
886 return;
887 }
888
889 status = CQE_STATUS(err_cqe);
890 opcode = CQE_OPCODE(err_cqe);
891 rqtype = RQ_TYPE(err_cqe);
892 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
893 (opcode == FW_RI_SEND_WITH_SE_INV);
894 tagged = (opcode == FW_RI_RDMA_WRITE) ||
895 (rqtype && (opcode == FW_RI_READ_RESP));
896
897 switch (status) {
898 case T4_ERR_STAG:
899 if (send_inv) {
900 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
901 *ecode = RDMAP_CANT_INV_STAG;
902 } else {
903 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
904 *ecode = RDMAP_INV_STAG;
905 }
906 break;
907 case T4_ERR_PDID:
908 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
909 if ((opcode == FW_RI_SEND_WITH_INV) ||
910 (opcode == FW_RI_SEND_WITH_SE_INV))
911 *ecode = RDMAP_CANT_INV_STAG;
912 else
913 *ecode = RDMAP_STAG_NOT_ASSOC;
914 break;
915 case T4_ERR_QPID:
916 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
917 *ecode = RDMAP_STAG_NOT_ASSOC;
918 break;
919 case T4_ERR_ACCESS:
920 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
921 *ecode = RDMAP_ACC_VIOL;
922 break;
923 case T4_ERR_WRAP:
924 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
925 *ecode = RDMAP_TO_WRAP;
926 break;
927 case T4_ERR_BOUND:
928 if (tagged) {
929 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
930 *ecode = DDPT_BASE_BOUNDS;
931 } else {
932 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
933 *ecode = RDMAP_BASE_BOUNDS;
934 }
935 break;
936 case T4_ERR_INVALIDATE_SHARED_MR:
937 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
938 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
939 *ecode = RDMAP_CANT_INV_STAG;
940 break;
941 case T4_ERR_ECC:
942 case T4_ERR_ECC_PSTAG:
943 case T4_ERR_INTERNAL_ERR:
944 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
945 *ecode = 0;
946 break;
947 case T4_ERR_OUT_OF_RQE:
948 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
949 *ecode = DDPU_INV_MSN_NOBUF;
950 break;
951 case T4_ERR_PBL_ADDR_BOUND:
952 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
953 *ecode = DDPT_BASE_BOUNDS;
954 break;
955 case T4_ERR_CRC:
956 *layer_type = LAYER_MPA|DDP_LLP;
957 *ecode = MPA_CRC_ERR;
958 break;
959 case T4_ERR_MARKER:
960 *layer_type = LAYER_MPA|DDP_LLP;
961 *ecode = MPA_MARKER_ERR;
962 break;
963 case T4_ERR_PDU_LEN_ERR:
964 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
965 *ecode = DDPU_MSG_TOOBIG;
966 break;
967 case T4_ERR_DDP_VERSION:
968 if (tagged) {
969 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
970 *ecode = DDPT_INV_VERS;
971 } else {
972 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
973 *ecode = DDPU_INV_VERS;
974 }
975 break;
976 case T4_ERR_RDMA_VERSION:
977 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
978 *ecode = RDMAP_INV_VERS;
979 break;
980 case T4_ERR_OPCODE:
981 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
982 *ecode = RDMAP_INV_OPCODE;
983 break;
984 case T4_ERR_DDP_QUEUE_NUM:
985 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
986 *ecode = DDPU_INV_QN;
987 break;
988 case T4_ERR_MSN:
989 case T4_ERR_MSN_GAP:
990 case T4_ERR_MSN_RANGE:
991 case T4_ERR_IRD_OVERFLOW:
992 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
993 *ecode = DDPU_INV_MSN_RANGE;
994 break;
995 case T4_ERR_TBIT:
996 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
997 *ecode = 0;
998 break;
999 case T4_ERR_MO:
1000 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1001 *ecode = DDPU_INV_MO;
1002 break;
1003 default:
1004 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1005 *ecode = 0;
1006 break;
1007 }
1008}
1009
be4c9bad
RD		 1010static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1011 gfp_t gfp)
cfdda9d7
SW		 1012{
1013 struct fw_ri_wr *wqe;
1014 struct sk_buff *skb;
1015 struct terminate_message *term;
1016
1017 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1018 qhp->ep->hwtid);
1019
be4c9bad 1020 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 1021 if (!skb)
be4c9bad 1022 return;
cfdda9d7
SW		 1023 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1024
1025 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1026 memset(wqe, 0, sizeof *wqe);
1027 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1028 wqe->flowid_len16 = cpu_to_be32(
1029 FW_WR_FLOWID(qhp->ep->hwtid) |
1030 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1031
1032 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1033 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1034 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 1035 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1036 term->layer_etype = qhp->attr.layer_etype;
1037 term->ecode = qhp->attr.ecode;
1038 } else
1039 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 1040 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 1041}
1042
1043/*
1044 * Assumes qhp lock is held.
1045 */
1046static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 1047 struct c4iw_cq *schp)
cfdda9d7
SW		 1048{
1049 int count;
1050 int flushed;
2f5b48c3 1051 unsigned long flag;
cfdda9d7
SW		 1052
1053 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 1054
732bee7a 1055 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1056 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7 1057 spin_lock(&qhp->lock);
1cf24dce
SW		 1058
1059 if (qhp->wq.flushed) {
1060 spin_unlock(&qhp->lock);
1061 spin_unlock_irqrestore(&rchp->lock, flag);
1062 return;
1063 }
1064 qhp->wq.flushed = 1;
1065
1066 c4iw_flush_hw_cq(rchp);
cfdda9d7
SW		 1067 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1068 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1069 spin_unlock(&qhp->lock);
2f5b48c3 1070 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 1071 if (flushed) {
1072 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 1073 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 1074 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1075 }
cfdda9d7 1076
732bee7a 1077 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1078 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7 1079 spin_lock(&qhp->lock);
1cf24dce
SW		 1080 if (schp != rchp)
1081 c4iw_flush_hw_cq(schp);
1082 flushed = c4iw_flush_sq(qhp);
cfdda9d7 1083 spin_unlock(&qhp->lock);
2f5b48c3 1084 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 1085 if (flushed) {
1086 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 1087 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 1088 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1089 }
cfdda9d7
SW		 1090}
1091
2f5b48c3 1092static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 1093{
1094 struct c4iw_cq *rchp, *schp;
581bbe2c 1095 unsigned long flag;
cfdda9d7 1096
1cf24dce
SW		 1097 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1098 schp = to_c4iw_cq(qhp->ibqp.send_cq);
cfdda9d7 1099
1cf24dce 1100 t4_set_wq_in_error(&qhp->wq);
cfdda9d7 1101 if (qhp->ibqp.uobject) {
cfdda9d7 1102 t4_set_cq_in_error(&rchp->cq);
581bbe2c 1103 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 1104 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 1105 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 1106 if (schp != rchp) {
cfdda9d7 1107 t4_set_cq_in_error(&schp->cq);
581bbe2c 1108 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 1109 (*schp->ibcq.comp_handler)(&schp->ibcq,
1110 schp->ibcq.cq_context);
581bbe2c 1111 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 1112 }
cfdda9d7
SW		 1113 return;
1114 }
2f5b48c3 1115 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1116}
1117
73d6fcad
SW		 1118static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1119 struct c4iw_ep *ep)
cfdda9d7
SW		 1120{
1121 struct fw_ri_wr *wqe;
1122 int ret;
cfdda9d7
SW		 1123 struct sk_buff *skb;
1124
1125 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1126 ep->hwtid);
cfdda9d7 1127
d3c814e8 1128 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1129 if (!skb)
1130 return -ENOMEM;
73d6fcad 1131 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1132
1133 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1134 memset(wqe, 0, sizeof *wqe);
1135 wqe->op_compl = cpu_to_be32(
1136 FW_WR_OP(FW_RI_INIT_WR) |
1137 FW_WR_COMPL(1));
1138 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1139 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1140 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1141 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1142
1143 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1144 ret = c4iw_ofld_send(&rhp->rdev, skb);
1145 if (ret)
1146 goto out;
1147
2f5b48c3 1148 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1149 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1150out:
1151 PDBG("%s ret %d\n", __func__, ret);
1152 return ret;
1153}
1154
1155static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1156{
d2fe99e8 1157 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1158 memset(&init->u, 0, sizeof init->u);
1159 switch (p2p_type) {
1160 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1161 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1162 init->u.write.stag_sink = cpu_to_be32(1);
1163 init->u.write.to_sink = cpu_to_be64(1);
1164 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1165 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1166 sizeof(struct fw_ri_immd),
1167 16);
1168 break;
1169 case FW_RI_INIT_P2PTYPE_READ_REQ:
1170 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1171 init->u.read.stag_src = cpu_to_be32(1);
1172 init->u.read.to_src_lo = cpu_to_be32(1);
1173 init->u.read.stag_sink = cpu_to_be32(1);
1174 init->u.read.to_sink_lo = cpu_to_be32(1);
1175 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1176 break;
1177 }
1178}
1179
1180static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1181{
1182 struct fw_ri_wr *wqe;
1183 int ret;
cfdda9d7
SW		 1184 struct sk_buff *skb;
1185
1186 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1187 qhp->ep->hwtid);
1188
d3c814e8 1189 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1190 if (!skb)
1191 return -ENOMEM;
1192 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1193
1194 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1195 memset(wqe, 0, sizeof *wqe);
1196 wqe->op_compl = cpu_to_be32(
1197 FW_WR_OP(FW_RI_INIT_WR) |
1198 FW_WR_COMPL(1));
1199 wqe->flowid_len16 = cpu_to_be32(
1200 FW_WR_FLOWID(qhp->ep->hwtid) |
1201 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1202
2f5b48c3 1203 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1204
1205 wqe->u.init.type = FW_RI_TYPE_INIT;
1206 wqe->u.init.mpareqbit_p2ptype =
1207 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1208 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1209 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1210 if (qhp->attr.mpa_attr.recv_marker_enabled)
1211 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1212 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1213 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1214 if (qhp->attr.mpa_attr.crc_enabled)
1215 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1216
1217 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1218 FW_RI_QP_RDMA_WRITE_ENABLE |
1219 FW_RI_QP_BIND_ENABLE;
1220 if (!qhp->ibqp.uobject)
1221 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1222 FW_RI_QP_STAG0_ENABLE;
1223 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1224 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1225 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1226 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1227 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1228 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1229 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1230 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1231 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1232 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1233 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1234 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1235 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1236 rhp->rdev.lldi.vr->rq.start);
1237 if (qhp->attr.mpa_attr.initiator)
1238 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1239
cfdda9d7
SW		 1240 ret = c4iw_ofld_send(&rhp->rdev, skb);
1241 if (ret)
1242 goto out;
1243
2f5b48c3
SW		 1244 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1245 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1246out:
1247 PDBG("%s ret %d\n", __func__, ret);
1248 return ret;
1249}
1250
1251int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1252 enum c4iw_qp_attr_mask mask,
1253 struct c4iw_qp_attributes *attrs,
1254 int internal)
1255{
1256 int ret = 0;
1257 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1258 int disconnect = 0;
1259 int terminate = 0;
1260 int abort = 0;
1261 int free = 0;
1262 struct c4iw_ep *ep = NULL;
1263
1264 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1265 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1266 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1267
2f5b48c3 1268 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1269
1270 /* Process attr changes if in IDLE */
1271 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1272 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1273 ret = -EIO;
1274 goto out;
1275 }
1276 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1277 newattr.enable_rdma_read = attrs->enable_rdma_read;
1278 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1279 newattr.enable_rdma_write = attrs->enable_rdma_write;
1280 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1281 newattr.enable_bind = attrs->enable_bind;
1282 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1283 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1284 ret = -EINVAL;
1285 goto out;
1286 }
1287 newattr.max_ord = attrs->max_ord;
1288 }
1289 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1290 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1291 ret = -EINVAL;
1292 goto out;
1293 }
1294 newattr.max_ird = attrs->max_ird;
1295 }
1296 qhp->attr = newattr;
1297 }
1298
2c974781 1299 if (mask & C4IW_QP_ATTR_SQ_DB) {
05eb2389 1300 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
2c974781
VP		 1301 goto out;
1302 }
1303 if (mask & C4IW_QP_ATTR_RQ_DB) {
05eb2389 1304 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
2c974781
VP		 1305 goto out;
1306 }
1307
cfdda9d7
SW		 1308 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1309 goto out;
1310 if (qhp->attr.state == attrs->next_state)
1311 goto out;
1312
1313 switch (qhp->attr.state) {
1314 case C4IW_QP_STATE_IDLE:
1315 switch (attrs->next_state) {
1316 case C4IW_QP_STATE_RTS:
1317 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1318 ret = -EINVAL;
1319 goto out;
1320 }
1321 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1322 ret = -EINVAL;
1323 goto out;
1324 }
1325 qhp->attr.mpa_attr = attrs->mpa_attr;
1326 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1327 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1328 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1329
1330 /*
1331 * Ref the endpoint here and deref when we
1332 * disassociate the endpoint from the QP. This
1333 * happens in CLOSING->IDLE transition or *->ERROR
1334 * transition.
1335 */
1336 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1337 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1338 if (ret)
1339 goto err;
1340 break;
1341 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1342 set_state(qhp, C4IW_QP_STATE_ERROR);
1343 flush_qp(qhp);
cfdda9d7
SW		 1344 break;
1345 default:
1346 ret = -EINVAL;
1347 goto out;
1348 }
1349 break;
1350 case C4IW_QP_STATE_RTS:
1351 switch (attrs->next_state) {
1352 case C4IW_QP_STATE_CLOSING:
1353 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
2f5b48c3 1354 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1355 ep = qhp->ep;
cfdda9d7
SW		 1356 if (!internal) {
1357 abort = 0;
1358 disconnect = 1;
2f5b48c3 1359 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1360 }
1cf24dce 1361 t4_set_wq_in_error(&qhp->wq);
73d6fcad 1362 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1363 if (ret)
cfdda9d7 1364 goto err;
cfdda9d7
SW		 1365 break;
1366 case C4IW_QP_STATE_TERMINATE:
2f5b48c3 1367 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1368 qhp->attr.layer_etype = attrs->layer_etype;
1369 qhp->attr.ecode = attrs->ecode;
1cf24dce 1370 t4_set_wq_in_error(&qhp->wq);
be4c9bad 1371 ep = qhp->ep;
09992579 1372 disconnect = 1;
0e42c1f4
SW		 1373 if (!internal)
1374 terminate = 1;
09992579
SW		 1375 else {
1376 ret = rdma_fini(rhp, qhp, ep);
1377 if (ret)
1378 goto err;
1379 }
2f5b48c3 1380 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1381 break;
1382 case C4IW_QP_STATE_ERROR:
2f5b48c3 1383 set_state(qhp, C4IW_QP_STATE_ERROR);
1cf24dce 1384 t4_set_wq_in_error(&qhp->wq);
cfdda9d7
SW		 1385 if (!internal) {
1386 abort = 1;
1387 disconnect = 1;
1388 ep = qhp->ep;
2f5b48c3 1389 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1390 }
1391 goto err;
1392 break;
1393 default:
1394 ret = -EINVAL;
1395 goto out;
1396 }
1397 break;
1398 case C4IW_QP_STATE_CLOSING:
1399 if (!internal) {
1400 ret = -EINVAL;
1401 goto out;
1402 }
1403 switch (attrs->next_state) {
1404 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1405 flush_qp(qhp);
1406 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1407 qhp->attr.llp_stream_handle = NULL;
1408 c4iw_put_ep(&qhp->ep->com);
1409 qhp->ep = NULL;
1410 wake_up(&qhp->wait);
1411 break;
1412 case C4IW_QP_STATE_ERROR:
1413 goto err;
1414 default:
1415 ret = -EINVAL;
1416 goto err;
1417 }
1418 break;
1419 case C4IW_QP_STATE_ERROR:
1420 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1421 ret = -EINVAL;
1422 goto out;
1423 }
1424 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1425 ret = -EINVAL;
1426 goto out;
1427 }
2f5b48c3 1428 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1429 break;
1430 case C4IW_QP_STATE_TERMINATE:
1431 if (!internal) {
1432 ret = -EINVAL;
1433 goto out;
1434 }
1435 goto err;
1436 break;
1437 default:
1438 printk(KERN_ERR "%s in a bad state %d\n",
1439 __func__, qhp->attr.state);
1440 ret = -EINVAL;
1441 goto err;
1442 break;
1443 }
1444 goto out;
1445err:
1446 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1447 qhp->wq.sq.qid);
1448
1449 /* disassociate the LLP connection */
1450 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1451 if (!ep)
1452 ep = qhp->ep;
cfdda9d7 1453 qhp->ep = NULL;
2f5b48c3 1454 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7 1455 free = 1;
91e9c071 1456 abort = 1;
cfdda9d7
SW		 1457 wake_up(&qhp->wait);
1458 BUG_ON(!ep);
2f5b48c3 1459 flush_qp(qhp);
cfdda9d7 1460out:
2f5b48c3 1461 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1462
1463 if (terminate)
be4c9bad 1464 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1465
1466 /*
1467 * If disconnect is 1, then we need to initiate a disconnect
1468 * on the EP. This can be a normal close (RTS->CLOSING) or
1469 * an abnormal close (RTS/CLOSING->ERROR).
1470 */
1471 if (disconnect) {
be4c9bad
RD		 1472 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1473 GFP_KERNEL);
cfdda9d7
SW		 1474 c4iw_put_ep(&ep->com);
1475 }
1476
1477 /*
1478 * If free is 1, then we've disassociated the EP from the QP
1479 * and we need to dereference the EP.
1480 */
1481 if (free)
1482 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1483 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1484 return ret;
1485}
1486
1487int c4iw_destroy_qp(struct ib_qp *ib_qp)
1488{
1489 struct c4iw_dev *rhp;
1490 struct c4iw_qp *qhp;
1491 struct c4iw_qp_attributes attrs;
1492 struct c4iw_ucontext *ucontext;
1493
1494 qhp = to_c4iw_qp(ib_qp);
1495 rhp = qhp->rhp;
1496
1497 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1498 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1499 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1500 else
1501 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1502 wait_event(qhp->wait, !qhp->ep);
1503
05eb2389 1504 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1505 atomic_dec(&qhp->refcnt);
1506 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1507
05eb2389
SW		 1508 spin_lock_irq(&rhp->lock);
1509 if (!list_empty(&qhp->db_fc_entry))
1510 list_del_init(&qhp->db_fc_entry);
1511 spin_unlock_irq(&rhp->lock);
1512
cfdda9d7
SW		 1513 ucontext = ib_qp->uobject ?
1514 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1515 destroy_qp(&rhp->rdev, &qhp->wq,
1516 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1517
1518 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1519 kfree(qhp);
1520 return 0;
1521}
1522
1523struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1524 struct ib_udata *udata)
1525{
1526 struct c4iw_dev *rhp;
1527 struct c4iw_qp *qhp;
1528 struct c4iw_pd *php;
1529 struct c4iw_cq *schp;
1530 struct c4iw_cq *rchp;
1531 struct c4iw_create_qp_resp uresp;
1532 int sqsize, rqsize;
1533 struct c4iw_ucontext *ucontext;
1534 int ret;
c6d7b267 1535 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1536
1537 PDBG("%s ib_pd %p\n", __func__, pd);
1538
1539 if (attrs->qp_type != IB_QPT_RC)
1540 return ERR_PTR(-EINVAL);
1541
1542 php = to_c4iw_pd(pd);
1543 rhp = php->rhp;
1544 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1545 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1546 if (!schp || !rchp)
1547 return ERR_PTR(-EINVAL);
1548
1549 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1550 return ERR_PTR(-EINVAL);
1551
1552 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1553 if (rqsize > T4_MAX_RQ_SIZE)
1554 return ERR_PTR(-E2BIG);
1555
1556 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1557 if (sqsize > T4_MAX_SQ_SIZE)
1558 return ERR_PTR(-E2BIG);
1559
1560 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1561
cfdda9d7
SW		 1562 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1563 if (!qhp)
1564 return ERR_PTR(-ENOMEM);
1565 qhp->wq.sq.size = sqsize;
1566 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1cf24dce 1567 qhp->wq.sq.flush_cidx = -1;
cfdda9d7
SW		 1568 qhp->wq.rq.size = rqsize;
1569 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1570
1571 if (ucontext) {
1572 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1573 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1574 }
1575
1576 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1577 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1578
1579 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1580 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1581 if (ret)
1582 goto err1;
1583
1584 attrs->cap.max_recv_wr = rqsize - 1;
1585 attrs->cap.max_send_wr = sqsize - 1;
1586 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1587
1588 qhp->rhp = rhp;
1589 qhp->attr.pd = php->pdid;
1590 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1591 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1592 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1593 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1594 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1595 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1596 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1597 qhp->attr.state = C4IW_QP_STATE_IDLE;
1598 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1599 qhp->attr.enable_rdma_read = 1;
1600 qhp->attr.enable_rdma_write = 1;
1601 qhp->attr.enable_bind = 1;
1602 qhp->attr.max_ord = 1;
1603 qhp->attr.max_ird = 1;
1604 spin_lock_init(&qhp->lock);
2f5b48c3 1605 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1606 init_waitqueue_head(&qhp->wait);
1607 atomic_set(&qhp->refcnt, 1);
1608
05eb2389 1609 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
cfdda9d7
SW		 1610 if (ret)
1611 goto err2;
1612
cfdda9d7
SW		 1613 if (udata) {
1614 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1615 if (!mm1) {
1616 ret = -ENOMEM;
30a6a62f 1617 goto err3;
cfdda9d7
SW		 1618 }
1619 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1620 if (!mm2) {
1621 ret = -ENOMEM;
30a6a62f 1622 goto err4;
cfdda9d7
SW		 1623 }
1624 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1625 if (!mm3) {
1626 ret = -ENOMEM;
30a6a62f 1627 goto err5;
cfdda9d7
SW		 1628 }
1629 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1630 if (!mm4) {
1631 ret = -ENOMEM;
30a6a62f 1632 goto err6;
cfdda9d7 1633 }
c6d7b267
SW		 1634 if (t4_sq_onchip(&qhp->wq.sq)) {
1635 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1636 if (!mm5) {
1637 ret = -ENOMEM;
1638 goto err7;
1639 }
1640 uresp.flags = C4IW_QPF_ONCHIP;
1641 } else
1642 uresp.flags = 0;
cfdda9d7
SW		 1643 uresp.qid_mask = rhp->rdev.qpmask;
1644 uresp.sqid = qhp->wq.sq.qid;
1645 uresp.sq_size = qhp->wq.sq.size;
1646 uresp.sq_memsize = qhp->wq.sq.memsize;
1647 uresp.rqid = qhp->wq.rq.qid;
1648 uresp.rq_size = qhp->wq.rq.size;
1649 uresp.rq_memsize = qhp->wq.rq.memsize;
1650 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1651 if (mm5) {
1652 uresp.ma_sync_key = ucontext->key;
1653 ucontext->key += PAGE_SIZE;
ae1fe07f
DC		 1654 } else {
1655 uresp.ma_sync_key = 0;
c6d7b267 1656 }
cfdda9d7
SW		 1657 uresp.sq_key = ucontext->key;
1658 ucontext->key += PAGE_SIZE;
1659 uresp.rq_key = ucontext->key;
1660 ucontext->key += PAGE_SIZE;
1661 uresp.sq_db_gts_key = ucontext->key;
1662 ucontext->key += PAGE_SIZE;
1663 uresp.rq_db_gts_key = ucontext->key;
1664 ucontext->key += PAGE_SIZE;
1665 spin_unlock(&ucontext->mmap_lock);
1666 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1667 if (ret)
c6d7b267 1668 goto err8;
cfdda9d7 1669 mm1->key = uresp.sq_key;
c6d7b267 1670 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1671 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1672 insert_mmap(ucontext, mm1);
1673 mm2->key = uresp.rq_key;
1674 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1675 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1676 insert_mmap(ucontext, mm2);
1677 mm3->key = uresp.sq_db_gts_key;
1678 mm3->addr = qhp->wq.sq.udb;
1679 mm3->len = PAGE_SIZE;
1680 insert_mmap(ucontext, mm3);
1681 mm4->key = uresp.rq_db_gts_key;
1682 mm4->addr = qhp->wq.rq.udb;
1683 mm4->len = PAGE_SIZE;
1684 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1685 if (mm5) {
1686 mm5->key = uresp.ma_sync_key;
1687 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1688 + A_PCIE_MA_SYNC) & PAGE_MASK;
1689 mm5->len = PAGE_SIZE;
1690 insert_mmap(ucontext, mm5);
1691 }
cfdda9d7
SW		 1692 }
1693 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1694 init_timer(&(qhp->timer));
05eb2389 1695 INIT_LIST_HEAD(&qhp->db_fc_entry);
cfdda9d7
SW		 1696 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1697 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1698 qhp->wq.sq.qid);
1699 return &qhp->ibqp;
c6d7b267
SW		 1700err8:
1701 kfree(mm5);
cfdda9d7 1702err7:
30a6a62f 1703 kfree(mm4);
cfdda9d7 1704err6:
30a6a62f 1705 kfree(mm3);
cfdda9d7 1706err5:
30a6a62f 1707 kfree(mm2);
cfdda9d7 1708err4:
30a6a62f 1709 kfree(mm1);
cfdda9d7
SW		 1710err3:
1711 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1712err2:
1713 destroy_qp(&rhp->rdev, &qhp->wq,
1714 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1715err1:
1716 kfree(qhp);
1717 return ERR_PTR(ret);
1718}
1719
1720int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1721 int attr_mask, struct ib_udata *udata)
1722{
1723 struct c4iw_dev *rhp;
1724 struct c4iw_qp *qhp;
1725 enum c4iw_qp_attr_mask mask = 0;
1726 struct c4iw_qp_attributes attrs;
1727
1728 PDBG("%s ib_qp %p\n", __func__, ibqp);
1729
1730 /* iwarp does not support the RTR state */
1731 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1732 attr_mask &= ~IB_QP_STATE;
1733
1734 /* Make sure we still have something left to do */
1735 if (!attr_mask)
1736 return 0;
1737
1738 memset(&attrs, 0, sizeof attrs);
1739 qhp = to_c4iw_qp(ibqp);
1740 rhp = qhp->rhp;
1741
1742 attrs.next_state = c4iw_convert_state(attr->qp_state);
1743 attrs.enable_rdma_read = (attr->qp_access_flags &
1744 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1745 attrs.enable_rdma_write = (attr->qp_access_flags &
1746 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1747 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1748
1749
1750 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1751 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1752 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1753 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1754 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1755
2c974781
VP		 1756 /*
1757 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1758 * ringing the queue db when we're in DB_FULL mode.
1759 */
1760 attrs.sq_db_inc = attr->sq_psn;
1761 attrs.rq_db_inc = attr->rq_psn;
1762 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1763 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1764
cfdda9d7
SW		 1765 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1766}
1767
1768struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1769{
1770 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1771 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1772}
67bbc055
VP		 1773
1774int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1775 int attr_mask, struct ib_qp_init_attr *init_attr)
1776{
1777 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1778
1779 memset(attr, 0, sizeof *attr);
1780 memset(init_attr, 0, sizeof *init_attr);
1781 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1782 return 0;
1783}
Linux kernel - Deliverables
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