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RDMA/cxgb4: Don't set completion flag for read requests
[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include "iw_cxgb4.h"
33
c6d7b267
SW		 34static int ocqp_support;
35module_param(ocqp_support, int, 0644);
36MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=0)");
37
2f5b48c3
SW		 38static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
39{
40 unsigned long flag;
41 spin_lock_irqsave(&qhp->lock, flag);
42 qhp->attr.state = state;
43 spin_unlock_irqrestore(&qhp->lock, flag);
44}
45
c6d7b267
SW		 46static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
47{
48 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
49}
50
51static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
52{
53 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
54 pci_unmap_addr(sq, mapping));
55}
56
57static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
58{
59 if (t4_sq_onchip(sq))
60 dealloc_oc_sq(rdev, sq);
61 else
62 dealloc_host_sq(rdev, sq);
63}
64
65static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
66{
67 if (!ocqp_support || !t4_ocqp_supported())
68 return -ENOSYS;
69 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
70 if (!sq->dma_addr)
71 return -ENOMEM;
72 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
73 rdev->lldi.vr->ocq.start;
74 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
75 rdev->lldi.vr->ocq.start);
76 sq->flags |= T4_SQ_ONCHIP;
77 return 0;
78}
79
80static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
83 &(sq->dma_addr), GFP_KERNEL);
84 if (!sq->queue)
85 return -ENOMEM;
86 sq->phys_addr = virt_to_phys(sq->queue);
87 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
88 return 0;
89}
90
cfdda9d7
SW		 91static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
92 struct c4iw_dev_ucontext *uctx)
93{
94 /*
95 * uP clears EQ contexts when the connection exits rdma mode,
96 * so no need to post a RESET WR for these EQs.
97 */
98 dma_free_coherent(&(rdev->lldi.pdev->dev),
99 wq->rq.memsize, wq->rq.queue,
f38926aa 100 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 101 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 102 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
103 kfree(wq->rq.sw_rq);
104 kfree(wq->sq.sw_sq);
105 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
106 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
107 return 0;
108}
109
110static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
111 struct t4_cq *rcq, struct t4_cq *scq,
112 struct c4iw_dev_ucontext *uctx)
113{
114 int user = (uctx != &rdev->uctx);
115 struct fw_ri_res_wr *res_wr;
116 struct fw_ri_res *res;
117 int wr_len;
118 struct c4iw_wr_wait wr_wait;
119 struct sk_buff *skb;
120 int ret;
121 int eqsize;
122
123 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
124 if (!wq->sq.qid)
125 return -ENOMEM;
126
127 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
128 if (!wq->rq.qid)
129 goto err1;
130
131 if (!user) {
132 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
133 GFP_KERNEL);
134 if (!wq->sq.sw_sq)
135 goto err2;
136
137 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
138 GFP_KERNEL);
139 if (!wq->rq.sw_rq)
140 goto err3;
141 }
142
143 /*
144 * RQT must be a power of 2.
145 */
146 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
147 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
148 if (!wq->rq.rqt_hwaddr)
149 goto err4;
150
c6d7b267
SW		 151 if (user) {
152 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
153 goto err5;
154 } else
155 if (alloc_host_sq(rdev, &wq->sq))
156 goto err5;
cfdda9d7 157 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 158 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 159
160 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
161 wq->rq.memsize, &(wq->rq.dma_addr),
162 GFP_KERNEL);
163 if (!wq->rq.queue)
164 goto err6;
165 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
166 __func__, wq->sq.queue,
167 (unsigned long long)virt_to_phys(wq->sq.queue),
168 wq->rq.queue,
169 (unsigned long long)virt_to_phys(wq->rq.queue));
170 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 171 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 172
173 wq->db = rdev->lldi.db_reg;
174 wq->gts = rdev->lldi.gts_reg;
175 if (user) {
176 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
177 (wq->sq.qid << rdev->qpshift);
178 wq->sq.udb &= PAGE_MASK;
179 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
180 (wq->rq.qid << rdev->qpshift);
181 wq->rq.udb &= PAGE_MASK;
182 }
183 wq->rdev = rdev;
184 wq->rq.msn = 1;
185
186 /* build fw_ri_res_wr */
187 wr_len = sizeof *res_wr + 2 * sizeof *res;
188
d3c814e8 189 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 190 if (!skb) {
191 ret = -ENOMEM;
192 goto err7;
193 }
194 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
195
196 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
197 memset(res_wr, 0, wr_len);
198 res_wr->op_nres = cpu_to_be32(
199 FW_WR_OP(FW_RI_RES_WR) |
200 V_FW_RI_RES_WR_NRES(2) |
201 FW_WR_COMPL(1));
202 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 203 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 204 res = res_wr->res;
205 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
206 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
207
208 /*
209 * eqsize is the number of 64B entries plus the status page size.
210 */
211 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
212
213 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
214 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
215 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
216 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
c6d7b267 217 t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0 |
cfdda9d7
SW		 218 V_FW_RI_RES_WR_IQID(scq->cqid));
219 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
220 V_FW_RI_RES_WR_DCAEN(0) |
221 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 222 V_FW_RI_RES_WR_FBMIN(2) |
cfdda9d7
SW		 223 V_FW_RI_RES_WR_FBMAX(3) |
224 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
225 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
226 V_FW_RI_RES_WR_EQSIZE(eqsize));
227 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
228 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
229 res++;
230 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
231 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
232
233 /*
234 * eqsize is the number of 64B entries plus the status page size.
235 */
236 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
237 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
238 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
239 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
240 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
241 V_FW_RI_RES_WR_IQID(rcq->cqid));
242 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
243 V_FW_RI_RES_WR_DCAEN(0) |
244 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 245 V_FW_RI_RES_WR_FBMIN(2) |
cfdda9d7
SW		 246 V_FW_RI_RES_WR_FBMAX(3) |
247 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
248 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
249 V_FW_RI_RES_WR_EQSIZE(eqsize));
250 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
251 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
252
253 c4iw_init_wr_wait(&wr_wait);
254
255 ret = c4iw_ofld_send(rdev, skb);
256 if (ret)
257 goto err7;
aadc4df3 258 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7
SW		 259 if (ret)
260 goto err7;
261
262 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
263 __func__, wq->sq.qid, wq->rq.qid, wq->db,
264 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
265
266 return 0;
267err7:
268 dma_free_coherent(&(rdev->lldi.pdev->dev),
269 wq->rq.memsize, wq->rq.queue,
f38926aa 270 dma_unmap_addr(&wq->rq, mapping));
cfdda9d7 271err6:
c6d7b267 272 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 273err5:
274 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
275err4:
276 kfree(wq->rq.sw_rq);
277err3:
278 kfree(wq->sq.sw_sq);
279err2:
280 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
281err1:
282 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
283 return -ENOMEM;
284}
285
d37ac31d
SW		 286static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
287 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 288{
d37ac31d
SW		 289 u8 *dstp, *srcp;
290 u32 plen = 0;
cfdda9d7 291 int i;
d37ac31d
SW		 292 int rem, len;
293
294 dstp = (u8 *)immdp->data;
295 for (i = 0; i < wr->num_sge; i++) {
296 if ((plen + wr->sg_list[i].length) > max)
297 return -EMSGSIZE;
298 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
299 plen += wr->sg_list[i].length;
300 rem = wr->sg_list[i].length;
301 while (rem) {
302 if (dstp == (u8 *)&sq->queue[sq->size])
303 dstp = (u8 *)sq->queue;
304 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
305 len = rem;
306 else
307 len = (u8 *)&sq->queue[sq->size] - dstp;
308 memcpy(dstp, srcp, len);
309 dstp += len;
310 srcp += len;
311 rem -= len;
312 }
313 }
13fecb83
SW		 314 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
315 if (len)
316 memset(dstp, 0, len);
d37ac31d
SW		 317 immdp->op = FW_RI_DATA_IMMD;
318 immdp->r1 = 0;
319 immdp->r2 = 0;
320 immdp->immdlen = cpu_to_be32(plen);
321 *plenp = plen;
322 return 0;
323}
324
325static int build_isgl(__be64 *queue_start, __be64 *queue_end,
326 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
327 int num_sge, u32 *plenp)
328
329{
330 int i;
331 u32 plen = 0;
332 __be64 *flitp = (__be64 *)isglp->sge;
333
334 for (i = 0; i < num_sge; i++) {
335 if ((plen + sg_list[i].length) < plen)
336 return -EMSGSIZE;
337 plen += sg_list[i].length;
338 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
339 sg_list[i].length);
340 if (++flitp == queue_end)
341 flitp = queue_start;
342 *flitp = cpu_to_be64(sg_list[i].addr);
343 if (++flitp == queue_end)
344 flitp = queue_start;
345 }
13fecb83 346 *flitp = (__force __be64)0;
d37ac31d
SW		 347 isglp->op = FW_RI_DATA_ISGL;
348 isglp->r1 = 0;
349 isglp->nsge = cpu_to_be16(num_sge);
350 isglp->r2 = 0;
351 if (plenp)
352 *plenp = plen;
353 return 0;
354}
355
356static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
357 struct ib_send_wr *wr, u8 *len16)
358{
cfdda9d7
SW		 359 u32 plen;
360 int size;
d37ac31d 361 int ret;
cfdda9d7
SW		 362
363 if (wr->num_sge > T4_MAX_SEND_SGE)
364 return -EINVAL;
365 switch (wr->opcode) {
366 case IB_WR_SEND:
367 if (wr->send_flags & IB_SEND_SOLICITED)
368 wqe->send.sendop_pkd = cpu_to_be32(
369 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
370 else
371 wqe->send.sendop_pkd = cpu_to_be32(
372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
373 wqe->send.stag_inv = 0;
374 break;
375 case IB_WR_SEND_WITH_INV:
376 if (wr->send_flags & IB_SEND_SOLICITED)
377 wqe->send.sendop_pkd = cpu_to_be32(
378 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
379 else
380 wqe->send.sendop_pkd = cpu_to_be32(
381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
382 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
383 break;
384
385 default:
386 return -EINVAL;
387 }
d37ac31d 388
cfdda9d7
SW		 389 plen = 0;
390 if (wr->num_sge) {
391 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 392 ret = build_immd(sq, wqe->send.u.immd_src, wr,
393 T4_MAX_SEND_INLINE, &plen);
394 if (ret)
395 return ret;
cfdda9d7
SW		 396 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
397 plen;
398 } else {
d37ac31d
SW		 399 ret = build_isgl((__be64 *)sq->queue,
400 (__be64 *)&sq->queue[sq->size],
401 wqe->send.u.isgl_src,
402 wr->sg_list, wr->num_sge, &plen);
403 if (ret)
404 return ret;
cfdda9d7
SW		 405 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
406 wr->num_sge * sizeof(struct fw_ri_sge);
407 }
408 } else {
409 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
410 wqe->send.u.immd_src[0].r1 = 0;
411 wqe->send.u.immd_src[0].r2 = 0;
412 wqe->send.u.immd_src[0].immdlen = 0;
413 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 414 plen = 0;
cfdda9d7
SW		 415 }
416 *len16 = DIV_ROUND_UP(size, 16);
417 wqe->send.plen = cpu_to_be32(plen);
418 return 0;
419}
420
d37ac31d
SW		 421static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
422 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 423{
cfdda9d7
SW		 424 u32 plen;
425 int size;
d37ac31d 426 int ret;
cfdda9d7 427
d37ac31d 428 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 429 return -EINVAL;
430 wqe->write.r2 = 0;
431 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
432 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 433 if (wr->num_sge) {
434 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 435 ret = build_immd(sq, wqe->write.u.immd_src, wr,
436 T4_MAX_WRITE_INLINE, &plen);
437 if (ret)
438 return ret;
cfdda9d7
SW		 439 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
440 plen;
441 } else {
d37ac31d
SW		 442 ret = build_isgl((__be64 *)sq->queue,
443 (__be64 *)&sq->queue[sq->size],
444 wqe->write.u.isgl_src,
445 wr->sg_list, wr->num_sge, &plen);
446 if (ret)
447 return ret;
cfdda9d7
SW		 448 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
449 wr->num_sge * sizeof(struct fw_ri_sge);
450 }
451 } else {
452 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
453 wqe->write.u.immd_src[0].r1 = 0;
454 wqe->write.u.immd_src[0].r2 = 0;
455 wqe->write.u.immd_src[0].immdlen = 0;
456 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 457 plen = 0;
cfdda9d7
SW		 458 }
459 *len16 = DIV_ROUND_UP(size, 16);
460 wqe->write.plen = cpu_to_be32(plen);
461 return 0;
462}
463
464static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
465{
466 if (wr->num_sge > 1)
467 return -EINVAL;
468 if (wr->num_sge) {
469 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
470 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
471 >> 32));
472 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
473 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
474 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
475 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
476 >> 32));
477 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
478 } else {
479 wqe->read.stag_src = cpu_to_be32(2);
480 wqe->read.to_src_hi = 0;
481 wqe->read.to_src_lo = 0;
482 wqe->read.stag_sink = cpu_to_be32(2);
483 wqe->read.plen = 0;
484 wqe->read.to_sink_hi = 0;
485 wqe->read.to_sink_lo = 0;
486 }
487 wqe->read.r2 = 0;
488 wqe->read.r5 = 0;
489 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
490 return 0;
491}
492
493static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
494 struct ib_recv_wr *wr, u8 *len16)
495{
d37ac31d 496 int ret;
cfdda9d7 497
d37ac31d
SW		 498 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
499 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
500 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
501 if (ret)
502 return ret;
cfdda9d7
SW		 503 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
504 wr->num_sge * sizeof(struct fw_ri_sge), 16);
505 return 0;
506}
507
508static int build_fastreg(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
509{
510
511 struct fw_ri_immd *imdp;
512 __be64 *p;
513 int i;
514 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
515
516 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
517 return -EINVAL;
518
519 wqe->fr.qpbinde_to_dcacpu = 0;
520 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
521 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
522 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
523 wqe->fr.len_hi = 0;
524 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
525 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
526 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
527 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
528 0xffffffff);
529 if (pbllen > T4_MAX_FR_IMMD) {
530 struct c4iw_fr_page_list *c4pl =
531 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
532 struct fw_ri_dsgl *sglp;
533
534 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
535 sglp->op = FW_RI_DATA_DSGL;
536 sglp->r1 = 0;
537 sglp->nsge = cpu_to_be16(1);
538 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
539 sglp->len0 = cpu_to_be32(pbllen);
540
541 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *sglp, 16);
542 } else {
543 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
544 imdp->op = FW_RI_DATA_IMMD;
545 imdp->r1 = 0;
546 imdp->r2 = 0;
547 imdp->immdlen = cpu_to_be32(pbllen);
548 p = (__be64 *)(imdp + 1);
549 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++)
550 *p = cpu_to_be64(
551 (u64)wr->wr.fast_reg.page_list->page_list[i]);
552 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen,
553 16);
554 }
555 return 0;
556}
557
558static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
559 u8 *len16)
560{
561 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
562 wqe->inv.r2 = 0;
563 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
564 return 0;
565}
566
567void c4iw_qp_add_ref(struct ib_qp *qp)
568{
569 PDBG("%s ib_qp %p\n", __func__, qp);
570 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
571}
572
573void c4iw_qp_rem_ref(struct ib_qp *qp)
574{
575 PDBG("%s ib_qp %p\n", __func__, qp);
576 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
577 wake_up(&(to_c4iw_qp(qp)->wait));
578}
579
580int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
581 struct ib_send_wr **bad_wr)
582{
583 int err = 0;
584 u8 len16 = 0;
585 enum fw_wr_opcodes fw_opcode = 0;
586 enum fw_ri_wr_flags fw_flags;
587 struct c4iw_qp *qhp;
588 union t4_wr *wqe;
589 u32 num_wrs;
590 struct t4_swsqe *swsqe;
591 unsigned long flag;
592 u16 idx = 0;
593
594 qhp = to_c4iw_qp(ibqp);
595 spin_lock_irqsave(&qhp->lock, flag);
596 if (t4_wq_in_error(&qhp->wq)) {
597 spin_unlock_irqrestore(&qhp->lock, flag);
598 return -EINVAL;
599 }
600 num_wrs = t4_sq_avail(&qhp->wq);
601 if (num_wrs == 0) {
602 spin_unlock_irqrestore(&qhp->lock, flag);
603 return -ENOMEM;
604 }
605 while (wr) {
606 if (num_wrs == 0) {
607 err = -ENOMEM;
608 *bad_wr = wr;
609 break;
610 }
d37ac31d
SW		 611 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
612 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
613
cfdda9d7
SW		 614 fw_flags = 0;
615 if (wr->send_flags & IB_SEND_SOLICITED)
616 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
617 if (wr->send_flags & IB_SEND_SIGNALED)
618 fw_flags |= FW_RI_COMPLETION_FLAG;
619 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
620 switch (wr->opcode) {
621 case IB_WR_SEND_WITH_INV:
622 case IB_WR_SEND:
623 if (wr->send_flags & IB_SEND_FENCE)
624 fw_flags |= FW_RI_READ_FENCE_FLAG;
625 fw_opcode = FW_RI_SEND_WR;
626 if (wr->opcode == IB_WR_SEND)
627 swsqe->opcode = FW_RI_SEND;
628 else
629 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 630 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 631 break;
632 case IB_WR_RDMA_WRITE:
633 fw_opcode = FW_RI_RDMA_WRITE_WR;
634 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 635 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 636 break;
637 case IB_WR_RDMA_READ:
2f1fb507 638 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 639 fw_opcode = FW_RI_RDMA_READ_WR;
640 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 641 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 642 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 643 else
644 fw_flags = 0;
cfdda9d7
SW		 645 err = build_rdma_read(wqe, wr, &len16);
646 if (err)
647 break;
648 swsqe->read_len = wr->sg_list[0].length;
649 if (!qhp->wq.sq.oldest_read)
650 qhp->wq.sq.oldest_read = swsqe;
651 break;
652 case IB_WR_FAST_REG_MR:
653 fw_opcode = FW_RI_FR_NSMR_WR;
654 swsqe->opcode = FW_RI_FAST_REGISTER;
655 err = build_fastreg(wqe, wr, &len16);
656 break;
657 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 658 if (wr->send_flags & IB_SEND_FENCE)
659 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 660 fw_opcode = FW_RI_INV_LSTAG_WR;
661 swsqe->opcode = FW_RI_LOCAL_INV;
662 err = build_inv_stag(wqe, wr, &len16);
663 break;
664 default:
665 PDBG("%s post of type=%d TBD!\n", __func__,
666 wr->opcode);
667 err = -EINVAL;
668 }
669 if (err) {
670 *bad_wr = wr;
671 break;
672 }
673 swsqe->idx = qhp->wq.sq.pidx;
674 swsqe->complete = 0;
675 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
676 swsqe->wr_id = wr->wr_id;
677
678 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
679
680 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
681 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
682 swsqe->opcode, swsqe->read_len);
683 wr = wr->next;
684 num_wrs--;
d37ac31d
SW		 685 t4_sq_produce(&qhp->wq, len16);
686 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 687 }
688 if (t4_wq_db_enabled(&qhp->wq))
689 t4_ring_sq_db(&qhp->wq, idx);
690 spin_unlock_irqrestore(&qhp->lock, flag);
691 return err;
692}
693
694int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
695 struct ib_recv_wr **bad_wr)
696{
697 int err = 0;
698 struct c4iw_qp *qhp;
699 union t4_recv_wr *wqe;
700 u32 num_wrs;
701 u8 len16 = 0;
702 unsigned long flag;
703 u16 idx = 0;
704
705 qhp = to_c4iw_qp(ibqp);
706 spin_lock_irqsave(&qhp->lock, flag);
707 if (t4_wq_in_error(&qhp->wq)) {
708 spin_unlock_irqrestore(&qhp->lock, flag);
709 return -EINVAL;
710 }
711 num_wrs = t4_rq_avail(&qhp->wq);
712 if (num_wrs == 0) {
713 spin_unlock_irqrestore(&qhp->lock, flag);
714 return -ENOMEM;
715 }
716 while (wr) {
717 if (wr->num_sge > T4_MAX_RECV_SGE) {
718 err = -EINVAL;
719 *bad_wr = wr;
720 break;
721 }
d37ac31d
SW		 722 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
723 qhp->wq.rq.wq_pidx *
724 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 725 if (num_wrs)
726 err = build_rdma_recv(qhp, wqe, wr, &len16);
727 else
728 err = -ENOMEM;
729 if (err) {
730 *bad_wr = wr;
731 break;
732 }
733
734 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
735
736 wqe->recv.opcode = FW_RI_RECV_WR;
737 wqe->recv.r1 = 0;
738 wqe->recv.wrid = qhp->wq.rq.pidx;
739 wqe->recv.r2[0] = 0;
740 wqe->recv.r2[1] = 0;
741 wqe->recv.r2[2] = 0;
742 wqe->recv.len16 = len16;
cfdda9d7
SW		 743 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
744 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 745 t4_rq_produce(&qhp->wq, len16);
746 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 747 wr = wr->next;
748 num_wrs--;
cfdda9d7
SW		 749 }
750 if (t4_wq_db_enabled(&qhp->wq))
751 t4_ring_rq_db(&qhp->wq, idx);
752 spin_unlock_irqrestore(&qhp->lock, flag);
753 return err;
754}
755
756int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
757{
758 return -ENOSYS;
759}
760
761static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
762 u8 *ecode)
763{
764 int status;
765 int tagged;
766 int opcode;
767 int rqtype;
768 int send_inv;
769
770 if (!err_cqe) {
771 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
772 *ecode = 0;
773 return;
774 }
775
776 status = CQE_STATUS(err_cqe);
777 opcode = CQE_OPCODE(err_cqe);
778 rqtype = RQ_TYPE(err_cqe);
779 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
780 (opcode == FW_RI_SEND_WITH_SE_INV);
781 tagged = (opcode == FW_RI_RDMA_WRITE) ||
782 (rqtype && (opcode == FW_RI_READ_RESP));
783
784 switch (status) {
785 case T4_ERR_STAG:
786 if (send_inv) {
787 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
788 *ecode = RDMAP_CANT_INV_STAG;
789 } else {
790 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
791 *ecode = RDMAP_INV_STAG;
792 }
793 break;
794 case T4_ERR_PDID:
795 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
796 if ((opcode == FW_RI_SEND_WITH_INV) ||
797 (opcode == FW_RI_SEND_WITH_SE_INV))
798 *ecode = RDMAP_CANT_INV_STAG;
799 else
800 *ecode = RDMAP_STAG_NOT_ASSOC;
801 break;
802 case T4_ERR_QPID:
803 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
804 *ecode = RDMAP_STAG_NOT_ASSOC;
805 break;
806 case T4_ERR_ACCESS:
807 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
808 *ecode = RDMAP_ACC_VIOL;
809 break;
810 case T4_ERR_WRAP:
811 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
812 *ecode = RDMAP_TO_WRAP;
813 break;
814 case T4_ERR_BOUND:
815 if (tagged) {
816 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
817 *ecode = DDPT_BASE_BOUNDS;
818 } else {
819 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
820 *ecode = RDMAP_BASE_BOUNDS;
821 }
822 break;
823 case T4_ERR_INVALIDATE_SHARED_MR:
824 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
825 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
826 *ecode = RDMAP_CANT_INV_STAG;
827 break;
828 case T4_ERR_ECC:
829 case T4_ERR_ECC_PSTAG:
830 case T4_ERR_INTERNAL_ERR:
831 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
832 *ecode = 0;
833 break;
834 case T4_ERR_OUT_OF_RQE:
835 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
836 *ecode = DDPU_INV_MSN_NOBUF;
837 break;
838 case T4_ERR_PBL_ADDR_BOUND:
839 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
840 *ecode = DDPT_BASE_BOUNDS;
841 break;
842 case T4_ERR_CRC:
843 *layer_type = LAYER_MPA|DDP_LLP;
844 *ecode = MPA_CRC_ERR;
845 break;
846 case T4_ERR_MARKER:
847 *layer_type = LAYER_MPA|DDP_LLP;
848 *ecode = MPA_MARKER_ERR;
849 break;
850 case T4_ERR_PDU_LEN_ERR:
851 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
852 *ecode = DDPU_MSG_TOOBIG;
853 break;
854 case T4_ERR_DDP_VERSION:
855 if (tagged) {
856 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
857 *ecode = DDPT_INV_VERS;
858 } else {
859 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
860 *ecode = DDPU_INV_VERS;
861 }
862 break;
863 case T4_ERR_RDMA_VERSION:
864 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
865 *ecode = RDMAP_INV_VERS;
866 break;
867 case T4_ERR_OPCODE:
868 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
869 *ecode = RDMAP_INV_OPCODE;
870 break;
871 case T4_ERR_DDP_QUEUE_NUM:
872 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
873 *ecode = DDPU_INV_QN;
874 break;
875 case T4_ERR_MSN:
876 case T4_ERR_MSN_GAP:
877 case T4_ERR_MSN_RANGE:
878 case T4_ERR_IRD_OVERFLOW:
879 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
880 *ecode = DDPU_INV_MSN_RANGE;
881 break;
882 case T4_ERR_TBIT:
883 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
884 *ecode = 0;
885 break;
886 case T4_ERR_MO:
887 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
888 *ecode = DDPU_INV_MO;
889 break;
890 default:
891 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
892 *ecode = 0;
893 break;
894 }
895}
896
897int c4iw_post_zb_read(struct c4iw_qp *qhp)
898{
899 union t4_wr *wqe;
900 struct sk_buff *skb;
901 u8 len16;
902
903 PDBG("%s enter\n", __func__);
904 skb = alloc_skb(40, GFP_KERNEL);
905 if (!skb) {
906 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
907 return -ENOMEM;
908 }
909 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
910
911 wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read);
912 memset(wqe, 0, sizeof wqe->read);
913 wqe->read.r2 = cpu_to_be64(0);
914 wqe->read.stag_sink = cpu_to_be32(1);
915 wqe->read.to_sink_hi = cpu_to_be32(0);
916 wqe->read.to_sink_lo = cpu_to_be32(1);
917 wqe->read.stag_src = cpu_to_be32(1);
918 wqe->read.plen = cpu_to_be32(0);
919 wqe->read.to_src_hi = cpu_to_be32(0);
920 wqe->read.to_src_lo = cpu_to_be32(1);
921 len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
922 init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16);
923
924 return c4iw_ofld_send(&qhp->rhp->rdev, skb);
925}
926
be4c9bad
RD		 927static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
928 gfp_t gfp)
cfdda9d7
SW		 929{
930 struct fw_ri_wr *wqe;
931 struct sk_buff *skb;
932 struct terminate_message *term;
933
934 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
935 qhp->ep->hwtid);
936
be4c9bad 937 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 938 if (!skb)
be4c9bad 939 return;
cfdda9d7
SW		 940 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
941
942 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
943 memset(wqe, 0, sizeof *wqe);
944 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
945 wqe->flowid_len16 = cpu_to_be32(
946 FW_WR_FLOWID(qhp->ep->hwtid) |
947 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
948
949 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
950 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
951 term = (struct terminate_message *)wqe->u.terminate.termmsg;
952 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 953 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 954}
955
956/*
957 * Assumes qhp lock is held.
958 */
959static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 960 struct c4iw_cq *schp)
cfdda9d7
SW		 961{
962 int count;
963 int flushed;
2f5b48c3 964 unsigned long flag;
cfdda9d7
SW		 965
966 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 967
732bee7a 968 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 969 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7
SW		 970 spin_lock(&qhp->lock);
971 c4iw_flush_hw_cq(&rchp->cq);
972 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
973 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
974 spin_unlock(&qhp->lock);
2f5b48c3 975 spin_unlock_irqrestore(&rchp->lock, flag);
cfdda9d7
SW		 976 if (flushed)
977 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
978
732bee7a 979 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 980 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7
SW		 981 spin_lock(&qhp->lock);
982 c4iw_flush_hw_cq(&schp->cq);
983 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
984 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
985 spin_unlock(&qhp->lock);
2f5b48c3 986 spin_unlock_irqrestore(&schp->lock, flag);
cfdda9d7
SW		 987 if (flushed)
988 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
cfdda9d7
SW		 989}
990
2f5b48c3 991static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 992{
993 struct c4iw_cq *rchp, *schp;
994
995 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
996 schp = get_chp(qhp->rhp, qhp->attr.scq);
997
998 if (qhp->ibqp.uobject) {
999 t4_set_wq_in_error(&qhp->wq);
1000 t4_set_cq_in_error(&rchp->cq);
1001 if (schp != rchp)
1002 t4_set_cq_in_error(&schp->cq);
1003 return;
1004 }
2f5b48c3 1005 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1006}
1007
73d6fcad
SW		 1008static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1009 struct c4iw_ep *ep)
cfdda9d7
SW		 1010{
1011 struct fw_ri_wr *wqe;
1012 int ret;
cfdda9d7
SW		 1013 struct sk_buff *skb;
1014
1015 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1016 ep->hwtid);
cfdda9d7 1017
d3c814e8 1018 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1019 if (!skb)
1020 return -ENOMEM;
73d6fcad 1021 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1022
1023 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1024 memset(wqe, 0, sizeof *wqe);
1025 wqe->op_compl = cpu_to_be32(
1026 FW_WR_OP(FW_RI_INIT_WR) |
1027 FW_WR_COMPL(1));
1028 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1029 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1030 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1031 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1032
1033 wqe->u.fini.type = FW_RI_TYPE_FINI;
2f5b48c3 1034 c4iw_init_wr_wait(&ep->com.wr_wait);
cfdda9d7
SW		 1035 ret = c4iw_ofld_send(&rhp->rdev, skb);
1036 if (ret)
1037 goto out;
1038
2f5b48c3 1039 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1040 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1041out:
1042 PDBG("%s ret %d\n", __func__, ret);
1043 return ret;
1044}
1045
1046static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1047{
1048 memset(&init->u, 0, sizeof init->u);
1049 switch (p2p_type) {
1050 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1051 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1052 init->u.write.stag_sink = cpu_to_be32(1);
1053 init->u.write.to_sink = cpu_to_be64(1);
1054 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1055 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1056 sizeof(struct fw_ri_immd),
1057 16);
1058 break;
1059 case FW_RI_INIT_P2PTYPE_READ_REQ:
1060 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1061 init->u.read.stag_src = cpu_to_be32(1);
1062 init->u.read.to_src_lo = cpu_to_be32(1);
1063 init->u.read.stag_sink = cpu_to_be32(1);
1064 init->u.read.to_sink_lo = cpu_to_be32(1);
1065 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1066 break;
1067 }
1068}
1069
1070static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1071{
1072 struct fw_ri_wr *wqe;
1073 int ret;
cfdda9d7
SW		 1074 struct sk_buff *skb;
1075
1076 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1077 qhp->ep->hwtid);
1078
d3c814e8 1079 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1080 if (!skb)
1081 return -ENOMEM;
1082 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1083
1084 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1085 memset(wqe, 0, sizeof *wqe);
1086 wqe->op_compl = cpu_to_be32(
1087 FW_WR_OP(FW_RI_INIT_WR) |
1088 FW_WR_COMPL(1));
1089 wqe->flowid_len16 = cpu_to_be32(
1090 FW_WR_FLOWID(qhp->ep->hwtid) |
1091 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1092
2f5b48c3 1093 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1094
1095 wqe->u.init.type = FW_RI_TYPE_INIT;
1096 wqe->u.init.mpareqbit_p2ptype =
1097 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1098 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1099 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1100 if (qhp->attr.mpa_attr.recv_marker_enabled)
1101 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1102 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1103 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1104 if (qhp->attr.mpa_attr.crc_enabled)
1105 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1106
1107 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1108 FW_RI_QP_RDMA_WRITE_ENABLE |
1109 FW_RI_QP_BIND_ENABLE;
1110 if (!qhp->ibqp.uobject)
1111 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1112 FW_RI_QP_STAG0_ENABLE;
1113 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1114 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1115 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1116 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1117 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1118 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1119 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1120 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1121 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1122 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1123 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1124 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1125 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1126 rhp->rdev.lldi.vr->rq.start);
1127 if (qhp->attr.mpa_attr.initiator)
1128 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1129
2f5b48c3 1130 c4iw_init_wr_wait(&qhp->ep->com.wr_wait);
cfdda9d7
SW		 1131 ret = c4iw_ofld_send(&rhp->rdev, skb);
1132 if (ret)
1133 goto out;
1134
2f5b48c3
SW		 1135 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1136 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1137out:
1138 PDBG("%s ret %d\n", __func__, ret);
1139 return ret;
1140}
1141
1142int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1143 enum c4iw_qp_attr_mask mask,
1144 struct c4iw_qp_attributes *attrs,
1145 int internal)
1146{
1147 int ret = 0;
1148 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1149 int disconnect = 0;
1150 int terminate = 0;
1151 int abort = 0;
1152 int free = 0;
1153 struct c4iw_ep *ep = NULL;
1154
1155 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1156 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1157 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1158
2f5b48c3 1159 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1160
1161 /* Process attr changes if in IDLE */
1162 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1163 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1164 ret = -EIO;
1165 goto out;
1166 }
1167 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1168 newattr.enable_rdma_read = attrs->enable_rdma_read;
1169 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1170 newattr.enable_rdma_write = attrs->enable_rdma_write;
1171 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1172 newattr.enable_bind = attrs->enable_bind;
1173 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1174 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1175 ret = -EINVAL;
1176 goto out;
1177 }
1178 newattr.max_ord = attrs->max_ord;
1179 }
1180 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1181 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1182 ret = -EINVAL;
1183 goto out;
1184 }
1185 newattr.max_ird = attrs->max_ird;
1186 }
1187 qhp->attr = newattr;
1188 }
1189
1190 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1191 goto out;
1192 if (qhp->attr.state == attrs->next_state)
1193 goto out;
1194
1195 switch (qhp->attr.state) {
1196 case C4IW_QP_STATE_IDLE:
1197 switch (attrs->next_state) {
1198 case C4IW_QP_STATE_RTS:
1199 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1200 ret = -EINVAL;
1201 goto out;
1202 }
1203 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1204 ret = -EINVAL;
1205 goto out;
1206 }
1207 qhp->attr.mpa_attr = attrs->mpa_attr;
1208 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1209 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1210 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1211
1212 /*
1213 * Ref the endpoint here and deref when we
1214 * disassociate the endpoint from the QP. This
1215 * happens in CLOSING->IDLE transition or *->ERROR
1216 * transition.
1217 */
1218 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1219 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1220 if (ret)
1221 goto err;
1222 break;
1223 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1224 set_state(qhp, C4IW_QP_STATE_ERROR);
1225 flush_qp(qhp);
cfdda9d7
SW		 1226 break;
1227 default:
1228 ret = -EINVAL;
1229 goto out;
1230 }
1231 break;
1232 case C4IW_QP_STATE_RTS:
1233 switch (attrs->next_state) {
1234 case C4IW_QP_STATE_CLOSING:
1235 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
2f5b48c3 1236 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1237 ep = qhp->ep;
cfdda9d7
SW		 1238 if (!internal) {
1239 abort = 0;
1240 disconnect = 1;
2f5b48c3 1241 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1242 }
73d6fcad 1243 ret = rdma_fini(rhp, qhp, ep);
cfdda9d7 1244 if (ret) {
2f5b48c3
SW		 1245 if (internal)
1246 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1247 disconnect = abort = 1;
1248 goto err;
1249 }
1250 break;
1251 case C4IW_QP_STATE_TERMINATE:
2f5b48c3 1252 set_state(qhp, C4IW_QP_STATE_TERMINATE);
cfdda9d7
SW		 1253 if (qhp->ibqp.uobject)
1254 t4_set_wq_in_error(&qhp->wq);
be4c9bad 1255 ep = qhp->ep;
0e42c1f4
SW		 1256 if (!internal)
1257 terminate = 1;
be4c9bad 1258 disconnect = 1;
2f5b48c3 1259 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1260 break;
1261 case C4IW_QP_STATE_ERROR:
2f5b48c3 1262 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1263 if (!internal) {
1264 abort = 1;
1265 disconnect = 1;
1266 ep = qhp->ep;
2f5b48c3 1267 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1268 }
1269 goto err;
1270 break;
1271 default:
1272 ret = -EINVAL;
1273 goto out;
1274 }
1275 break;
1276 case C4IW_QP_STATE_CLOSING:
1277 if (!internal) {
1278 ret = -EINVAL;
1279 goto out;
1280 }
1281 switch (attrs->next_state) {
1282 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1283 flush_qp(qhp);
1284 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1285 qhp->attr.llp_stream_handle = NULL;
1286 c4iw_put_ep(&qhp->ep->com);
1287 qhp->ep = NULL;
1288 wake_up(&qhp->wait);
1289 break;
1290 case C4IW_QP_STATE_ERROR:
1291 goto err;
1292 default:
1293 ret = -EINVAL;
1294 goto err;
1295 }
1296 break;
1297 case C4IW_QP_STATE_ERROR:
1298 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1299 ret = -EINVAL;
1300 goto out;
1301 }
1302 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1303 ret = -EINVAL;
1304 goto out;
1305 }
2f5b48c3 1306 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1307 break;
1308 case C4IW_QP_STATE_TERMINATE:
1309 if (!internal) {
1310 ret = -EINVAL;
1311 goto out;
1312 }
1313 goto err;
1314 break;
1315 default:
1316 printk(KERN_ERR "%s in a bad state %d\n",
1317 __func__, qhp->attr.state);
1318 ret = -EINVAL;
1319 goto err;
1320 break;
1321 }
1322 goto out;
1323err:
1324 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1325 qhp->wq.sq.qid);
1326
1327 /* disassociate the LLP connection */
1328 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1329 if (!ep)
1330 ep = qhp->ep;
cfdda9d7 1331 qhp->ep = NULL;
2f5b48c3 1332 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1333 free = 1;
1334 wake_up(&qhp->wait);
1335 BUG_ON(!ep);
2f5b48c3 1336 flush_qp(qhp);
cfdda9d7 1337out:
2f5b48c3 1338 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1339
1340 if (terminate)
be4c9bad 1341 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1342
1343 /*
1344 * If disconnect is 1, then we need to initiate a disconnect
1345 * on the EP. This can be a normal close (RTS->CLOSING) or
1346 * an abnormal close (RTS/CLOSING->ERROR).
1347 */
1348 if (disconnect) {
be4c9bad
RD		 1349 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1350 GFP_KERNEL);
cfdda9d7
SW		 1351 c4iw_put_ep(&ep->com);
1352 }
1353
1354 /*
1355 * If free is 1, then we've disassociated the EP from the QP
1356 * and we need to dereference the EP.
1357 */
1358 if (free)
1359 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1360 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1361 return ret;
1362}
1363
1364int c4iw_destroy_qp(struct ib_qp *ib_qp)
1365{
1366 struct c4iw_dev *rhp;
1367 struct c4iw_qp *qhp;
1368 struct c4iw_qp_attributes attrs;
1369 struct c4iw_ucontext *ucontext;
1370
1371 qhp = to_c4iw_qp(ib_qp);
1372 rhp = qhp->rhp;
1373
1374 attrs.next_state = C4IW_QP_STATE_ERROR;
1375 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1376 wait_event(qhp->wait, !qhp->ep);
1377
1378 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1379 atomic_dec(&qhp->refcnt);
1380 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1381
1382 ucontext = ib_qp->uobject ?
1383 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1384 destroy_qp(&rhp->rdev, &qhp->wq,
1385 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1386
1387 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1388 kfree(qhp);
1389 return 0;
1390}
1391
1392struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1393 struct ib_udata *udata)
1394{
1395 struct c4iw_dev *rhp;
1396 struct c4iw_qp *qhp;
1397 struct c4iw_pd *php;
1398 struct c4iw_cq *schp;
1399 struct c4iw_cq *rchp;
1400 struct c4iw_create_qp_resp uresp;
1401 int sqsize, rqsize;
1402 struct c4iw_ucontext *ucontext;
1403 int ret;
c6d7b267 1404 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1405
1406 PDBG("%s ib_pd %p\n", __func__, pd);
1407
1408 if (attrs->qp_type != IB_QPT_RC)
1409 return ERR_PTR(-EINVAL);
1410
1411 php = to_c4iw_pd(pd);
1412 rhp = php->rhp;
1413 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1414 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1415 if (!schp || !rchp)
1416 return ERR_PTR(-EINVAL);
1417
1418 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1419 return ERR_PTR(-EINVAL);
1420
1421 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1422 if (rqsize > T4_MAX_RQ_SIZE)
1423 return ERR_PTR(-E2BIG);
1424
1425 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1426 if (sqsize > T4_MAX_SQ_SIZE)
1427 return ERR_PTR(-E2BIG);
1428
1429 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1430
1431
1432 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1433 if (!qhp)
1434 return ERR_PTR(-ENOMEM);
1435 qhp->wq.sq.size = sqsize;
1436 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1437 qhp->wq.rq.size = rqsize;
1438 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1439
1440 if (ucontext) {
1441 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1442 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1443 }
1444
1445 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1446 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1447
1448 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1449 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1450 if (ret)
1451 goto err1;
1452
1453 attrs->cap.max_recv_wr = rqsize - 1;
1454 attrs->cap.max_send_wr = sqsize - 1;
1455 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1456
1457 qhp->rhp = rhp;
1458 qhp->attr.pd = php->pdid;
1459 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1460 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1461 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1462 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1463 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1464 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1465 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1466 qhp->attr.state = C4IW_QP_STATE_IDLE;
1467 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1468 qhp->attr.enable_rdma_read = 1;
1469 qhp->attr.enable_rdma_write = 1;
1470 qhp->attr.enable_bind = 1;
1471 qhp->attr.max_ord = 1;
1472 qhp->attr.max_ird = 1;
1473 spin_lock_init(&qhp->lock);
2f5b48c3 1474 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1475 init_waitqueue_head(&qhp->wait);
1476 atomic_set(&qhp->refcnt, 1);
1477
1478 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1479 if (ret)
1480 goto err2;
1481
cfdda9d7
SW		 1482 if (udata) {
1483 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1484 if (!mm1) {
1485 ret = -ENOMEM;
30a6a62f 1486 goto err3;
cfdda9d7
SW		 1487 }
1488 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1489 if (!mm2) {
1490 ret = -ENOMEM;
30a6a62f 1491 goto err4;
cfdda9d7
SW		 1492 }
1493 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1494 if (!mm3) {
1495 ret = -ENOMEM;
30a6a62f 1496 goto err5;
cfdda9d7
SW		 1497 }
1498 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1499 if (!mm4) {
1500 ret = -ENOMEM;
30a6a62f 1501 goto err6;
cfdda9d7 1502 }
c6d7b267
SW		 1503 if (t4_sq_onchip(&qhp->wq.sq)) {
1504 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1505 if (!mm5) {
1506 ret = -ENOMEM;
1507 goto err7;
1508 }
1509 uresp.flags = C4IW_QPF_ONCHIP;
1510 } else
1511 uresp.flags = 0;
cfdda9d7
SW		 1512 uresp.qid_mask = rhp->rdev.qpmask;
1513 uresp.sqid = qhp->wq.sq.qid;
1514 uresp.sq_size = qhp->wq.sq.size;
1515 uresp.sq_memsize = qhp->wq.sq.memsize;
1516 uresp.rqid = qhp->wq.rq.qid;
1517 uresp.rq_size = qhp->wq.rq.size;
1518 uresp.rq_memsize = qhp->wq.rq.memsize;
1519 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1520 if (mm5) {
1521 uresp.ma_sync_key = ucontext->key;
1522 ucontext->key += PAGE_SIZE;
1523 }
cfdda9d7
SW		 1524 uresp.sq_key = ucontext->key;
1525 ucontext->key += PAGE_SIZE;
1526 uresp.rq_key = ucontext->key;
1527 ucontext->key += PAGE_SIZE;
1528 uresp.sq_db_gts_key = ucontext->key;
1529 ucontext->key += PAGE_SIZE;
1530 uresp.rq_db_gts_key = ucontext->key;
1531 ucontext->key += PAGE_SIZE;
1532 spin_unlock(&ucontext->mmap_lock);
1533 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1534 if (ret)
c6d7b267 1535 goto err8;
cfdda9d7 1536 mm1->key = uresp.sq_key;
c6d7b267 1537 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1538 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1539 insert_mmap(ucontext, mm1);
1540 mm2->key = uresp.rq_key;
1541 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1542 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1543 insert_mmap(ucontext, mm2);
1544 mm3->key = uresp.sq_db_gts_key;
1545 mm3->addr = qhp->wq.sq.udb;
1546 mm3->len = PAGE_SIZE;
1547 insert_mmap(ucontext, mm3);
1548 mm4->key = uresp.rq_db_gts_key;
1549 mm4->addr = qhp->wq.rq.udb;
1550 mm4->len = PAGE_SIZE;
1551 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1552 if (mm5) {
1553 mm5->key = uresp.ma_sync_key;
1554 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1555 + A_PCIE_MA_SYNC) & PAGE_MASK;
1556 mm5->len = PAGE_SIZE;
1557 insert_mmap(ucontext, mm5);
1558 }
cfdda9d7
SW		 1559 }
1560 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1561 init_timer(&(qhp->timer));
1562 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1563 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1564 qhp->wq.sq.qid);
1565 return &qhp->ibqp;
c6d7b267
SW		 1566err8:
1567 kfree(mm5);
cfdda9d7 1568err7:
30a6a62f 1569 kfree(mm4);
cfdda9d7 1570err6:
30a6a62f 1571 kfree(mm3);
cfdda9d7 1572err5:
30a6a62f 1573 kfree(mm2);
cfdda9d7 1574err4:
30a6a62f 1575 kfree(mm1);
cfdda9d7
SW		 1576err3:
1577 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1578err2:
1579 destroy_qp(&rhp->rdev, &qhp->wq,
1580 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1581err1:
1582 kfree(qhp);
1583 return ERR_PTR(ret);
1584}
1585
1586int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1587 int attr_mask, struct ib_udata *udata)
1588{
1589 struct c4iw_dev *rhp;
1590 struct c4iw_qp *qhp;
1591 enum c4iw_qp_attr_mask mask = 0;
1592 struct c4iw_qp_attributes attrs;
1593
1594 PDBG("%s ib_qp %p\n", __func__, ibqp);
1595
1596 /* iwarp does not support the RTR state */
1597 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1598 attr_mask &= ~IB_QP_STATE;
1599
1600 /* Make sure we still have something left to do */
1601 if (!attr_mask)
1602 return 0;
1603
1604 memset(&attrs, 0, sizeof attrs);
1605 qhp = to_c4iw_qp(ibqp);
1606 rhp = qhp->rhp;
1607
1608 attrs.next_state = c4iw_convert_state(attr->qp_state);
1609 attrs.enable_rdma_read = (attr->qp_access_flags &
1610 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1611 attrs.enable_rdma_write = (attr->qp_access_flags &
1612 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1613 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1614
1615
1616 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1617 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1618 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1619 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1620 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1621
1622 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1623}
1624
1625struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1626{
1627 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1628 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1629}
Linux kernel - Deliverables
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