[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / t4.h

/*
 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __T4_H__
#define __T4_H__

#include "t4_hw.h"
#include "t4_regs.h"
#include "t4_msg.h"
#include "t4fw_ri_api.h"

#define T4_MAX_NUM_QP 65536
#define T4_MAX_NUM_CQ 65536
#define T4_MAX_NUM_PD 65536
#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
#define T4_MAX_IQ_SIZE (65520 - 1)
#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
#define T4_MAX_NUM_STAG (1<<15)
#define T4_MAX_MR_SIZE (~0ULL)
#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
#define T4_STAG_UNSET 0xffffffff
#define T4_FW_MAJ 0
#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
#define A_PCIE_MA_SYNC 0x30b4

struct t4_status_page {
	__be32 rsvd1;	/* flit 0 - hw owns */
	__be16 rsvd2;
	__be16 qid;
	__be16 cidx;
	__be16 pidx;
	u8 qp_err;	/* flit 1 - sw owns */
	u8 db_off;
	u8 pad;
	u16 host_wq_pidx;
	u16 host_cidx;
	u16 host_pidx;
};

#define T4_EQ_ENTRY_SIZE 64

#define T4_SQ_NUM_SLOTS 5
#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
			sizeof(struct fw_ri_immd)) & ~31UL)
#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
#define T4_MAX_FR_DSGL 1024
#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))

static inline int t4_max_fr_depth(int use_dsgl)
{
	return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
}

#define T4_RQ_NUM_SLOTS 2
#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
#define T4_MAX_RECV_SGE 4

union t4_wr {
	struct fw_ri_res_wr res;
	struct fw_ri_wr ri;
	struct fw_ri_rdma_write_wr write;
	struct fw_ri_send_wr send;
	struct fw_ri_rdma_read_wr read;
	struct fw_ri_bind_mw_wr bind;
	struct fw_ri_fr_nsmr_wr fr;
	struct fw_ri_inv_lstag_wr inv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
};

union t4_recv_wr {
	struct fw_ri_recv_wr recv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
};

static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
{
	wqe->send.opcode = (u8)opcode;
	wqe->send.flags = flags;
	wqe->send.wrid = wrid;
	wqe->send.r1[0] = 0;
	wqe->send.r1[1] = 0;
	wqe->send.r1[2] = 0;
	wqe->send.len16 = len16;
}

/* CQE/AE status codes */
#define T4_ERR_SUCCESS                     0x0
#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
						/* STAG is offlimt, being 0, */
						/* or STAG_key mismatch */
#define T4_ERR_PDID                        0x2	/* PDID mismatch */
#define T4_ERR_QPID                        0x3	/* QPID mismatch */
#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
#define T4_ERR_WRAP                        0x5	/* Wrap error */
#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_ECC                         0x9	/* ECC error detected */
#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
						/* reading PSTAG for a MW  */
						/* Invalidate */
#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
						/* software error */
#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
#define T4_ERR_CRC                         0x10 /* CRC error */
#define T4_ERR_MARKER                      0x11 /* Marker error */
#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
#define T4_ERR_MSN                         0x18 /* MSN error */
#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
						/* or READ_REQ */
#define T4_ERR_MSN_GAP                     0x1B
#define T4_ERR_MSN_RANGE                   0x1C
#define T4_ERR_IRD_OVERFLOW                0x1D
#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
						/* software error */
#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
						/* mismatch) */
/*
 * CQE defs
 */
struct t4_cqe {
	__be32 header;
	__be32 len;
	union {
		struct {
			__be32 stag;
			__be32 msn;
		} rcqe;
		struct {
			u32 nada1;
			u16 nada2;
			u16 cidx;
		} scqe;
		struct {
			__be32 wrid_hi;
			__be32 wrid_low;
		} gen;
	} u;
	__be64 reserved;
	__be64 bits_type_ts;
};

/* macros for flit 0 of the cqe */

#define S_CQE_QPID        12
#define M_CQE_QPID        0xFFFFF
#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)

#define S_CQE_SWCQE       11
#define M_CQE_SWCQE       0x1
#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)

#define S_CQE_STATUS      5
#define M_CQE_STATUS      0x1F
#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)

#define S_CQE_TYPE        4
#define M_CQE_TYPE        0x1
#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)

#define S_CQE_OPCODE      0
#define M_CQE_OPCODE      0xF
#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)

#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
#define SQ_TYPE(x)	  (CQE_TYPE((x)))
#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))

#define CQE_SEND_OPCODE(x)( \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))

#define CQE_LEN(x)        (be32_to_cpu((x)->len))

/* used for RQ completion processing */
#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))

/* used for SQ completion processing */
#define CQE_WRID_SQ_IDX(x)	((x)->u.scqe.cidx)

/* generic accessor macros */
#define CQE_WRID_HI(x)		((x)->u.gen.wrid_hi)
#define CQE_WRID_LOW(x)		((x)->u.gen.wrid_low)

/* macros for flit 3 of the cqe */
#define S_CQE_GENBIT	63
#define M_CQE_GENBIT	0x1
#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)

#define S_CQE_OVFBIT	62
#define M_CQE_OVFBIT	0x1
#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)

#define S_CQE_IQTYPE	60
#define M_CQE_IQTYPE	0x3
#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)

#define M_CQE_TS	0x0fffffffffffffffULL
#define G_CQE_TS(x)	((x) & M_CQE_TS)

#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))

struct t4_swsqe {
	u64			wr_id;
	struct t4_cqe		cqe;
	int			read_len;
	int			opcode;
	int			complete;
	int			signaled;
	u16			idx;
	int                     flushed;
};

static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
{
#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
	return pgprot_writecombine(prot);
#else
	return pgprot_noncached(prot);
#endif
}

enum {
	T4_SQ_ONCHIP = (1<<0),
};

struct t4_sq {
	union t4_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	unsigned long phys_addr;
	struct t4_swsqe *sw_sq;
	struct t4_swsqe *oldest_read;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
	u16 flags;
	short flush_cidx;
};

struct t4_swrqe {
	u64 wr_id;
};

struct t4_rq {
	union  t4_recv_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_swrqe *sw_rq;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u32 msn;
	u32 rqt_hwaddr;
	u16 rqt_size;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
};

struct t4_wq {
	struct t4_sq sq;
	struct t4_rq rq;
	void __iomem *db;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	int flushed;
};

static inline int t4_rqes_posted(struct t4_wq *wq)
{
	return wq->rq.in_use;
}

static inline int t4_rq_empty(struct t4_wq *wq)
{
	return wq->rq.in_use == 0;
}

static inline int t4_rq_full(struct t4_wq *wq)
{
	return wq->rq.in_use == (wq->rq.size - 1);
}

static inline u32 t4_rq_avail(struct t4_wq *wq)
{
	return wq->rq.size - 1 - wq->rq.in_use;
}

static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
{
	wq->rq.in_use++;
	if (++wq->rq.pidx == wq->rq.size)
		wq->rq.pidx = 0;
	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline void t4_rq_consume(struct t4_wq *wq)
{
	wq->rq.in_use--;
	wq->rq.msn++;
	if (++wq->rq.cidx == wq->rq.size)
		wq->rq.cidx = 0;
}

static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
}

static inline u16 t4_rq_wq_size(struct t4_wq *wq)
{
		return wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline int t4_sq_onchip(struct t4_sq *sq)
{
	return sq->flags & T4_SQ_ONCHIP;
}

static inline int t4_sq_empty(struct t4_wq *wq)
{
	return wq->sq.in_use == 0;
}

static inline int t4_sq_full(struct t4_wq *wq)
{
	return wq->sq.in_use == (wq->sq.size - 1);
}

static inline u32 t4_sq_avail(struct t4_wq *wq)
{
	return wq->sq.size - 1 - wq->sq.in_use;
}

static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
{
	wq->sq.in_use++;
	if (++wq->sq.pidx == wq->sq.size)
		wq->sq.pidx = 0;
	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
}

static inline void t4_sq_consume(struct t4_wq *wq)
{
	BUG_ON(wq->sq.in_use < 1);
	if (wq->sq.cidx == wq->sq.flush_cidx)
		wq->sq.flush_cidx = -1;
	wq->sq.in_use--;
	if (++wq->sq.cidx == wq->sq.size)
		wq->sq.cidx = 0;
}

static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
}

static inline u16 t4_sq_wq_size(struct t4_wq *wq)
{
		return wq->sq.size * T4_SQ_NUM_SLOTS;
}

/* This function copies 64 byte coalesced work request to memory
 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
 * from the FIFO instead of from Host.
 */
static inline void pio_copy(u64 __iomem *dst, u64 *src)
{
	int count = 8;

	while (count) {
		writeq(*src, dst);
		src++;
		dst++;
		count--;
	}
}

static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			pio_copy(wq->sq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			writel(PIDX_T5(inc), wq->sq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
}

static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_recv_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			pio_copy(wq->rq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			writel(PIDX_T5(inc), wq->rq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
}

static inline int t4_wq_in_error(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.qp_err;
}

static inline void t4_set_wq_in_error(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.qp_err = 1;
}

static inline void t4_disable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 1;
}

static inline void t4_enable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 0;
}

static inline int t4_wq_db_enabled(struct t4_wq *wq)
{
	return !wq->rq.queue[wq->rq.size].status.db_off;
}

struct t4_cq {
	struct t4_cqe *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_cqe *sw_queue;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	u64 ugts;
	size_t memsize;
	__be64 bits_type_ts;
	u32 cqid;
	u16 size; /* including status page */
	u16 cidx;
	u16 sw_pidx;
	u16 sw_cidx;
	u16 sw_in_use;
	u16 cidx_inc;
	u8 gen;
	u8 error;
};

static inline int t4_arm_cq(struct t4_cq *cq, int se)
{
	u32 val;

	while (cq->cidx_inc > CIDXINC_MASK) {
		val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
		      INGRESSQID(cq->cqid);
		writel(val, cq->gts);
		cq->cidx_inc -= CIDXINC_MASK;
	}
	val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
	      INGRESSQID(cq->cqid);
	writel(val, cq->gts);
	cq->cidx_inc = 0;
	return 0;
}

static inline void t4_swcq_produce(struct t4_cq *cq)
{
	cq->sw_in_use++;
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
	}
	if (++cq->sw_pidx == cq->size)
		cq->sw_pidx = 0;
}

static inline void t4_swcq_consume(struct t4_cq *cq)
{
	BUG_ON(cq->sw_in_use < 1);
	cq->sw_in_use--;
	if (++cq->sw_cidx == cq->size)
		cq->sw_cidx = 0;
}

static inline void t4_hwcq_consume(struct t4_cq *cq)
{
	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) {
		u32 val;

		val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
		      INGRESSQID(cq->cqid);
		writel(val, cq->gts);
		cq->cidx_inc = 0;
	}
	if (++cq->cidx == cq->size) {
		cq->cidx = 0;
		cq->gen ^= 1;
	}
}

static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
{
	return (CQE_GENBIT(cqe) == cq->gen);
}

static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret;
	u16 prev_cidx;

	if (cq->cidx == 0)
		prev_cidx = cq->size - 1;
	else
		prev_cidx = cq->cidx - 1;

	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
		ret = -EOVERFLOW;
		cq->error = 1;
		printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
		BUG_ON(1);
	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {

		/* Ensure CQE is flushed to memory */
		rmb();
		*cqe = &cq->queue[cq->cidx];
		ret = 0;
	} else
		ret = -ENODATA;
	return ret;
}

static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
{
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
		return NULL;
	}
	if (cq->sw_in_use)
		return &cq->sw_queue[cq->sw_cidx];
	return NULL;
}

static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret = 0;

	if (cq->error)
		ret = -ENODATA;
	else if (cq->sw_in_use)
		*cqe = &cq->sw_queue[cq->sw_cidx];
	else
		ret = t4_next_hw_cqe(cq, cqe);
	return ret;
}

static inline int t4_cq_in_error(struct t4_cq *cq)
{
	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
}

static inline void t4_set_cq_in_error(struct t4_cq *cq)
{
	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
}
#endif

struct t4_dev_status_page {
	u8 db_off;
};
Commit	Line	Data
cfdda9d7 SW	1	/*
	2	* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	* - Redistributions in binary form must reproduce the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer in the documentation and/or other materials
	20	* provided with the distribution.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	23	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	24	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	25	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	26	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	27	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	28	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	29	* SOFTWARE.
	30	*/
	31	#ifndef __T4_H__
	32	#define __T4_H__
	33
	34	#include "t4_hw.h"
	35	#include "t4_regs.h"
	36	#include "t4_msg.h"
	37	#include "t4fw_ri_api.h"
	38
1cf24dce SW	39	#define T4_MAX_NUM_QP 65536
	40	#define T4_MAX_NUM_CQ 65536
	41	#define T4_MAX_NUM_PD 65536
f64b8843 SW	42	#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
	43	#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
	44	#define T4_MAX_IQ_SIZE (65520 - 1)
	45	#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
	46	#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
	47	#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
	48	#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
cfdda9d7	49	#define T4_MAX_NUM_STAG (1<<15)
a2de1499	50	#define T4_MAX_MR_SIZE (~0ULL)
cfdda9d7 SW	51	#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
	52	#define T4_STAG_UNSET 0xffffffff
	53	#define T4_FW_MAJ 0
	54	#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
c6d7b267	55	#define A_PCIE_MA_SYNC 0x30b4
cfdda9d7 SW	56
	57	struct t4_status_page {
	58	__be32 rsvd1; /* flit 0 - hw owns */
	59	__be16 rsvd2;
	60	__be16 qid;
	61	__be16 cidx;
	62	__be16 pidx;
	63	u8 qp_err; /* flit 1 - sw owns */
	64	u8 db_off;
422eea0a VP	65	u8 pad;
	66	u16 host_wq_pidx;
	67	u16 host_cidx;
	68	u16 host_pidx;
cfdda9d7 SW	69	};
cfdda9d7 SW	70
d37ac31d	71	#define T4_EQ_ENTRY_SIZE 64
cfdda9d7	72
40dbf6ee	73	#define T4_SQ_NUM_SLOTS 5
d37ac31d	74	#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
cfdda9d7 SW	75	#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	76	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	77	#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	78	sizeof(struct fw_ri_immd)))
	79	#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
	80	sizeof(struct fw_ri_rdma_write_wr) - \
	81	sizeof(struct fw_ri_immd)))
	82	#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
	83	sizeof(struct fw_ri_rdma_write_wr) - \
	84	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	85	#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
40dbf6ee	86	sizeof(struct fw_ri_immd)) & ~31UL)
a03d9f94 SW	87	#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
	88	#define T4_MAX_FR_DSGL 1024
	89	#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
	90
	91	static inline int t4_max_fr_depth(int use_dsgl)
	92	{
	93	return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
	94	}
cfdda9d7 SW	95
cfdda9d7 SW	96	#define T4_RQ_NUM_SLOTS 2
d37ac31d	97	#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
f64b8843	98	#define T4_MAX_RECV_SGE 4
cfdda9d7 SW	99
	100	union t4_wr {
	101	struct fw_ri_res_wr res;
	102	struct fw_ri_wr ri;
	103	struct fw_ri_rdma_write_wr write;
	104	struct fw_ri_send_wr send;
	105	struct fw_ri_rdma_read_wr read;
	106	struct fw_ri_bind_mw_wr bind;
	107	struct fw_ri_fr_nsmr_wr fr;
	108	struct fw_ri_inv_lstag_wr inv;
	109	struct t4_status_page status;
d37ac31d	110	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
cfdda9d7 SW	111	};
	112
	113	union t4_recv_wr {
	114	struct fw_ri_recv_wr recv;
	115	struct t4_status_page status;
d37ac31d	116	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
cfdda9d7 SW	117	};
	118
	119	static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
	120	enum fw_wr_opcodes opcode, u8 flags, u8 len16)
	121	{
cfdda9d7 SW	122	wqe->send.opcode = (u8)opcode;
	123	wqe->send.flags = flags;
	124	wqe->send.wrid = wrid;
	125	wqe->send.r1[0] = 0;
	126	wqe->send.r1[1] = 0;
	127	wqe->send.r1[2] = 0;
	128	wqe->send.len16 = len16;
cfdda9d7 SW	129	}
	130
	131	/* CQE/AE status codes */
	132	#define T4_ERR_SUCCESS 0x0
	133	#define T4_ERR_STAG 0x1 /* STAG invalid: either the */
	134	/* STAG is offlimt, being 0, */
	135	/* or STAG_key mismatch */
	136	#define T4_ERR_PDID 0x2 /* PDID mismatch */
	137	#define T4_ERR_QPID 0x3 /* QPID mismatch */
	138	#define T4_ERR_ACCESS 0x4 /* Invalid access right */
	139	#define T4_ERR_WRAP 0x5 /* Wrap error */
	140	#define T4_ERR_BOUND 0x6 /* base and bounds voilation */
	141	#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
	142	/* shared memory region */
	143	#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
	144	/* shared memory region */
	145	#define T4_ERR_ECC 0x9 /* ECC error detected */
	146	#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
	147	/* reading PSTAG for a MW */
	148	/* Invalidate */
	149	#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
	150	/* software error */
	151	#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
	152	#define T4_ERR_CRC 0x10 /* CRC error */
	153	#define T4_ERR_MARKER 0x11 /* Marker error */
	154	#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
	155	#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
	156	#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
	157	#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
	158	#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
	159	#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
	160	#define T4_ERR_MSN 0x18 /* MSN error */
	161	#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
	162	#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
	163	/* or READ_REQ */
	164	#define T4_ERR_MSN_GAP 0x1B
	165	#define T4_ERR_MSN_RANGE 0x1C
	166	#define T4_ERR_IRD_OVERFLOW 0x1D
	167	#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
	168	/* software error */
	169	#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
	170	/* mismatch) */
	171	/*
	172	* CQE defs
	173	*/
	174	struct t4_cqe {
	175	__be32 header;
	176	__be32 len;
	177	union {
	178	struct {
	179	__be32 stag;
	180	__be32 msn;
	181	} rcqe;
	182	struct {
	183	u32 nada1;
	184	u16 nada2;
	185	u16 cidx;
	186	} scqe;
	187	struct {
	188	__be32 wrid_hi;
	189	__be32 wrid_low;
	190	} gen;
	191	} u;
	192	__be64 reserved;
193	__be64 bits_type_ts;
194	};
195
196	/* macros for flit 0 of the cqe */
197
198	#define S_CQE_QPID 12
199	#define M_CQE_QPID 0xFFFFF
200	#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
201	#define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
202
203	#define S_CQE_SWCQE 11
204	#define M_CQE_SWCQE 0x1
205	#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
206	#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
207
208	#define S_CQE_STATUS 5
209	#define M_CQE_STATUS 0x1F
210	#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
211	#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
212
213	#define S_CQE_TYPE 4
214	#define M_CQE_TYPE 0x1
215	#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
216	#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
217
218	#define S_CQE_OPCODE 0
219	#define M_CQE_OPCODE 0xF
220	#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
221	#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
222
223	#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
224	#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
225	#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
226	#define SQ_TYPE(x) (CQE_TYPE((x)))
227	#define RQ_TYPE(x) (!CQE_TYPE((x)))
228	#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
229	#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
230
231	#define CQE_SEND_OPCODE(x)( \
232	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) \|\| \
233	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) \|\| \
234	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) \|\| \
235	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
236
237	#define CQE_LEN(x) (be32_to_cpu((x)->len))
238
239	/* used for RQ completion processing */
240	#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
241	#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
242
243	/* used for SQ completion processing */
244	#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
245
246	/* generic accessor macros */
247	#define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
248	#define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
249
250	/* macros for flit 3 of the cqe */
251	#define S_CQE_GENBIT 63
252	#define M_CQE_GENBIT 0x1
253	#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
254	#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
255
256	#define S_CQE_OVFBIT 62
257	#define M_CQE_OVFBIT 0x1
258	#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
259
260	#define S_CQE_IQTYPE 60
261	#define M_CQE_IQTYPE 0x3
262	#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
263
264	#define M_CQE_TS 0x0fffffffffffffffULL
265	#define G_CQE_TS(x) ((x) & M_CQE_TS)
266
267	#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
268	#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
269	#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
270
271	struct t4_swsqe {
272	u64 wr_id;
273	struct t4_cqe cqe;
274	int read_len;
275	int opcode;
276	int complete;
277	int signaled;
278	u16 idx;
1cf24dce	279	int flushed;
cfdda9d7 SW	280	};
cfdda9d7 SW	281
c6d7b267 SW	282	static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
c6d7b267 SW	283	{
e297d9dd	284	#if defined(__i386__) \|\| defined(__x86_64__) \|\| defined(CONFIG_PPC64)
c6d7b267	285	return pgprot_writecombine(prot);
c6d7b267 SW	286	#else
	287	return pgprot_noncached(prot);
	288	#endif
	289	}
	290
c6d7b267 SW	291	enum {
	292	T4_SQ_ONCHIP = (1<<0),
	293	};
	294
cfdda9d7 SW	295	struct t4_sq {
	296	union t4_wr *queue;
	297	dma_addr_t dma_addr;
f38926aa	298	DEFINE_DMA_UNMAP_ADDR(mapping);
c6d7b267	299	unsigned long phys_addr;
cfdda9d7 SW	300	struct t4_swsqe *sw_sq;
cfdda9d7 SW	301	struct t4_swsqe *oldest_read;
fa658a98	302	u64 __iomem *udb;
cfdda9d7 SW	303	size_t memsize;
	304	u32 qid;
	305	u16 in_use;
	306	u16 size;
	307	u16 cidx;
	308	u16 pidx;
d37ac31d	309	u16 wq_pidx;
05eb2389	310	u16 wq_pidx_inc;
c6d7b267	311	u16 flags;
1cf24dce	312	short flush_cidx;
cfdda9d7 SW	313	};
	314
	315	struct t4_swrqe {
	316	u64 wr_id;
	317	};
	318
	319	struct t4_rq {
	320	union t4_recv_wr *queue;
	321	dma_addr_t dma_addr;
f38926aa	322	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7	323	struct t4_swrqe *sw_rq;
fa658a98	324	u64 __iomem *udb;
cfdda9d7 SW	325	size_t memsize;
	326	u32 qid;
	327	u32 msn;
	328	u32 rqt_hwaddr;
	329	u16 rqt_size;
	330	u16 in_use;
	331	u16 size;
	332	u16 cidx;
	333	u16 pidx;
d37ac31d	334	u16 wq_pidx;
05eb2389	335	u16 wq_pidx_inc;
cfdda9d7 SW	336	};
	337
	338	struct t4_wq {
	339	struct t4_sq sq;
	340	struct t4_rq rq;
	341	void __iomem *db;
	342	void __iomem *gts;
	343	struct c4iw_rdev *rdev;
1cf24dce	344	int flushed;
cfdda9d7 SW	345	};
	346
	347	static inline int t4_rqes_posted(struct t4_wq *wq)
	348	{
	349	return wq->rq.in_use;
	350	}
	351
	352	static inline int t4_rq_empty(struct t4_wq *wq)
	353	{
	354	return wq->rq.in_use == 0;
	355	}
	356
	357	static inline int t4_rq_full(struct t4_wq *wq)
	358	{
	359	return wq->rq.in_use == (wq->rq.size - 1);
	360	}
	361
	362	static inline u32 t4_rq_avail(struct t4_wq *wq)
	363	{
	364	return wq->rq.size - 1 - wq->rq.in_use;
	365	}
	366
d37ac31d	367	static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	368	{
	369	wq->rq.in_use++;
	370	if (++wq->rq.pidx == wq->rq.size)
	371	wq->rq.pidx = 0;
d37ac31d SW	372	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	373	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
	374	wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
cfdda9d7 SW	375	}
	376
	377	static inline void t4_rq_consume(struct t4_wq *wq)
	378	{
	379	wq->rq.in_use--;
	380	wq->rq.msn++;
	381	if (++wq->rq.cidx == wq->rq.size)
	382	wq->rq.cidx = 0;
	383	}
	384
422eea0a VP	385	static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
	386	{
	387	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
	388	}
	389
	390	static inline u16 t4_rq_wq_size(struct t4_wq *wq)
	391	{
	392	return wq->rq.size * T4_RQ_NUM_SLOTS;
	393	}
	394
c6d7b267 SW	395	static inline int t4_sq_onchip(struct t4_sq *sq)
	396	{
	397	return sq->flags & T4_SQ_ONCHIP;
	398	}
	399
cfdda9d7 SW	400	static inline int t4_sq_empty(struct t4_wq *wq)
	401	{
	402	return wq->sq.in_use == 0;
	403	}
	404
	405	static inline int t4_sq_full(struct t4_wq *wq)
	406	{
	407	return wq->sq.in_use == (wq->sq.size - 1);
	408	}
	409
	410	static inline u32 t4_sq_avail(struct t4_wq *wq)
	411	{
	412	return wq->sq.size - 1 - wq->sq.in_use;
	413	}
	414
d37ac31d	415	static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	416	{
	417	wq->sq.in_use++;
	418	if (++wq->sq.pidx == wq->sq.size)
	419	wq->sq.pidx = 0;
d37ac31d SW	420	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	421	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
	422	wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
cfdda9d7 SW	423	}
	424
	425	static inline void t4_sq_consume(struct t4_wq *wq)
	426	{
1cf24dce SW	427	BUG_ON(wq->sq.in_use < 1);
	428	if (wq->sq.cidx == wq->sq.flush_cidx)
	429	wq->sq.flush_cidx = -1;
cfdda9d7 SW	430	wq->sq.in_use--;
	431	if (++wq->sq.cidx == wq->sq.size)
	432	wq->sq.cidx = 0;
	433	}
	434
422eea0a VP	435	static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
	436	{
	437	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
	438	}
	439
	440	static inline u16 t4_sq_wq_size(struct t4_wq *wq)
	441	{
	442	return wq->sq.size * T4_SQ_NUM_SLOTS;
	443	}
	444
fa658a98 SW	445	/* This function copies 64 byte coalesced work request to memory
	446	* mapped BAR2 space. For coalesced WRs, the SGE fetches data
	447	* from the FIFO instead of from Host.
	448	*/
	449	static inline void pio_copy(u64 __iomem dst, u64 src)
	450	{
	451	int count = 8;
	452
	453	while (count) {
	454	writeq(*src, dst);
	455	src++;
	456	dst++;
	457	count--;
	458	}
	459	}
	460
	461	static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
	462	union t4_wr *wqe)
cfdda9d7	463	{
fa658a98 SW	464
fa658a98 SW	465	/* Flush host queue memory writes. */
cfdda9d7	466	wmb();
fa658a98 SW	467	if (t5) {
	468	if (inc == 1 && wqe) {
	469	PDBG("%s: WC wq->sq.pidx = %d\n",
	470	__func__, wq->sq.pidx);
	471	pio_copy(wq->sq.udb + 7, (void *)wqe);
	472	} else {
	473	PDBG("%s: DB wq->sq.pidx = %d\n",
	474	__func__, wq->sq.pidx);
	475	writel(PIDX_T5(inc), wq->sq.udb);
	476	}
	477
	478	/* Flush user doorbell area writes. */
	479	wmb();
	480	return;
	481	}
cfdda9d7 SW	482	writel(QID(wq->sq.qid) \| PIDX(inc), wq->db);
	483	}
	484
fa658a98 SW	485	static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
fa658a98 SW	486	union t4_recv_wr *wqe)
cfdda9d7	487	{
fa658a98 SW	488
fa658a98 SW	489	/* Flush host queue memory writes. */
cfdda9d7	490	wmb();
fa658a98 SW	491	if (t5) {
	492	if (inc == 1 && wqe) {
	493	PDBG("%s: WC wq->rq.pidx = %d\n",
	494	__func__, wq->rq.pidx);
	495	pio_copy(wq->rq.udb + 7, (void *)wqe);
	496	} else {
	497	PDBG("%s: DB wq->rq.pidx = %d\n",
	498	__func__, wq->rq.pidx);
	499	writel(PIDX_T5(inc), wq->rq.udb);
	500	}
	501
	502	/* Flush user doorbell area writes. */
	503	wmb();
	504	return;
	505	}
cfdda9d7 SW	506	writel(QID(wq->rq.qid) \| PIDX(inc), wq->db);
	507	}
	508
	509	static inline int t4_wq_in_error(struct t4_wq *wq)
	510	{
c6d7b267	511	return wq->rq.queue[wq->rq.size].status.qp_err;
cfdda9d7 SW	512	}
	513
	514	static inline void t4_set_wq_in_error(struct t4_wq *wq)
	515	{
cfdda9d7 SW	516	wq->rq.queue[wq->rq.size].status.qp_err = 1;
	517	}
	518
	519	static inline void t4_disable_wq_db(struct t4_wq *wq)
	520	{
cfdda9d7 SW	521	wq->rq.queue[wq->rq.size].status.db_off = 1;
	522	}
	523
	524	static inline void t4_enable_wq_db(struct t4_wq *wq)
	525	{
cfdda9d7 SW	526	wq->rq.queue[wq->rq.size].status.db_off = 0;
	527	}
	528
	529	static inline int t4_wq_db_enabled(struct t4_wq *wq)
	530	{
c6d7b267	531	return !wq->rq.queue[wq->rq.size].status.db_off;
cfdda9d7 SW	532	}
	533
	534	struct t4_cq {
	535	struct t4_cqe *queue;
	536	dma_addr_t dma_addr;
f38926aa	537	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7 SW	538	struct t4_cqe *sw_queue;
	539	void __iomem *gts;
	540	struct c4iw_rdev *rdev;
	541	u64 ugts;
	542	size_t memsize;
84172dee	543	__be64 bits_type_ts;
cfdda9d7 SW	544	u32 cqid;
	545	u16 size; /* including status page */
	546	u16 cidx;
	547	u16 sw_pidx;
	548	u16 sw_cidx;
	549	u16 sw_in_use;
	550	u16 cidx_inc;
	551	u8 gen;
	552	u8 error;
	553	};
	554
	555	static inline int t4_arm_cq(struct t4_cq *cq, int se)
	556	{
	557	u32 val;
7ec45b92 SW	558
	559	while (cq->cidx_inc > CIDXINC_MASK) {
	560	val = SEINTARM(0) \| CIDXINC(CIDXINC_MASK) \| TIMERREG(7) \|
	561	INGRESSQID(cq->cqid);
be4c9bad	562	writel(val, cq->gts);
7ec45b92 SW	563	cq->cidx_inc -= CIDXINC_MASK;
	564	}
	565	val = SEINTARM(se) \| CIDXINC(cq->cidx_inc) \| TIMERREG(6) \|
	566	INGRESSQID(cq->cqid);
	567	writel(val, cq->gts);
	568	cq->cidx_inc = 0;
cfdda9d7 SW	569	return 0;
	570	}
	571
	572	static inline void t4_swcq_produce(struct t4_cq *cq)
	573	{
	574	cq->sw_in_use++;
1cf24dce SW	575	if (cq->sw_in_use == cq->size) {
	576	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	577	cq->error = 1;
	578	BUG_ON(1);
	579	}
cfdda9d7 SW	580	if (++cq->sw_pidx == cq->size)
	581	cq->sw_pidx = 0;
	582	}
	583
	584	static inline void t4_swcq_consume(struct t4_cq *cq)
	585	{
1cf24dce	586	BUG_ON(cq->sw_in_use < 1);
cfdda9d7 SW	587	cq->sw_in_use--;
	588	if (++cq->sw_cidx == cq->size)
	589	cq->sw_cidx = 0;
	590	}
	591
	592	static inline void t4_hwcq_consume(struct t4_cq *cq)
	593	{
84172dee	594	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
b298881f	595	if (++cq->cidx_inc == (cq->size >> 4) \|\| cq->cidx_inc == CIDXINC_MASK) {
ffc3f748 SW	596	u32 val;
	597
	598	val = SEINTARM(0) \| CIDXINC(cq->cidx_inc) \| TIMERREG(7) \|
	599	INGRESSQID(cq->cqid);
	600	writel(val, cq->gts);
7ec45b92	601	cq->cidx_inc = 0;
ffc3f748	602	}
cfdda9d7 SW	603	if (++cq->cidx == cq->size) {
	604	cq->cidx = 0;
	605	cq->gen ^= 1;
	606	}
	607	}
	608
	609	static inline int t4_valid_cqe(struct t4_cq cq, struct t4_cqe cqe)
	610	{
	611	return (CQE_GENBIT(cqe) == cq->gen);
	612	}
	613
	614	static inline int t4_next_hw_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	615	{
84172dee SW	616	int ret;
84172dee SW	617	u16 prev_cidx;
cfdda9d7	618
84172dee SW	619	if (cq->cidx == 0)
84172dee SW	620	prev_cidx = cq->size - 1;
cfdda9d7	621	else
84172dee SW	622	prev_cidx = cq->cidx - 1;
	623
	624	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
	625	ret = -EOVERFLOW;
cfdda9d7	626	cq->error = 1;
84172dee	627	printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
1cf24dce	628	BUG_ON(1);
84172dee	629	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
def4771f SW	630
	631	/* Ensure CQE is flushed to memory */
	632	rmb();
84172dee SW	633	*cqe = &cq->queue[cq->cidx];
	634	ret = 0;
	635	} else
	636	ret = -ENODATA;
cfdda9d7 SW	637	return ret;
	638	}
	639
	640	static inline struct t4_cqe t4_next_sw_cqe(struct t4_cq cq)
	641	{
1cf24dce SW	642	if (cq->sw_in_use == cq->size) {
	643	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	644	cq->error = 1;
	645	BUG_ON(1);
	646	return NULL;
	647	}
cfdda9d7 SW	648	if (cq->sw_in_use)
	649	return &cq->sw_queue[cq->sw_cidx];
	650	return NULL;
	651	}
	652
	653	static inline int t4_next_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	654	{
	655	int ret = 0;
	656
	657	if (cq->error)
	658	ret = -ENODATA;
	659	else if (cq->sw_in_use)
	660	*cqe = &cq->sw_queue[cq->sw_cidx];
	661	else
	662	ret = t4_next_hw_cqe(cq, cqe);
	663	return ret;
	664	}
	665
	666	static inline int t4_cq_in_error(struct t4_cq *cq)
	667	{
	668	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
	669	}
	670
	671	static inline void t4_set_cq_in_error(struct t4_cq *cq)
	672	{
	673	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
	674	}
	675	#endif
05eb2389 SW	676
	677	struct t4_dev_status_page {
	678	u8 db_off;
	679	};