[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / t4.h

/*
 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __T4_H__
#define __T4_H__

#include "t4_hw.h"
#include "t4_regs.h"
#include "t4_msg.h"
#include "t4fw_ri_api.h"

#define T4_MAX_NUM_QP 65536
#define T4_MAX_NUM_CQ 65536
#define T4_MAX_NUM_PD 65536
#define T4_MAX_NUM_STAG (1<<15)
#define T4_MAX_MR_SIZE (~0ULL)
#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
#define T4_STAG_UNSET 0xffffffff
#define T4_FW_MAJ 0
#define A_PCIE_MA_SYNC 0x30b4

struct t4_status_page {
	__be32 rsvd1;	/* flit 0 - hw owns */
	__be16 rsvd2;
	__be16 qid;
	__be16 cidx;
	__be16 pidx;
	u8 qp_err;	/* flit 1 - sw owns */
	u8 db_off;
	u8 pad;
	u16 host_wq_pidx;
	u16 host_cidx;
	u16 host_pidx;
};

#define T4_EQ_ENTRY_SIZE 64

#define T4_SQ_NUM_SLOTS 5
#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
			sizeof(struct fw_ri_immd)) & ~31UL)
#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
#define T4_MAX_FR_DSGL 1024
#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))

static inline int t4_max_fr_depth(int use_dsgl)
{
	return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
}

#define T4_RQ_NUM_SLOTS 2
#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
#define T4_MAX_RECV_SGE 4

union t4_wr {
	struct fw_ri_res_wr res;
	struct fw_ri_wr ri;
	struct fw_ri_rdma_write_wr write;
	struct fw_ri_send_wr send;
	struct fw_ri_rdma_read_wr read;
	struct fw_ri_bind_mw_wr bind;
	struct fw_ri_fr_nsmr_wr fr;
	struct fw_ri_inv_lstag_wr inv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
};

union t4_recv_wr {
	struct fw_ri_recv_wr recv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
};

static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
{
	wqe->send.opcode = (u8)opcode;
	wqe->send.flags = flags;
	wqe->send.wrid = wrid;
	wqe->send.r1[0] = 0;
	wqe->send.r1[1] = 0;
	wqe->send.r1[2] = 0;
	wqe->send.len16 = len16;
}

/* CQE/AE status codes */
#define T4_ERR_SUCCESS                     0x0
#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
						/* STAG is offlimt, being 0, */
						/* or STAG_key mismatch */
#define T4_ERR_PDID                        0x2	/* PDID mismatch */
#define T4_ERR_QPID                        0x3	/* QPID mismatch */
#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
#define T4_ERR_WRAP                        0x5	/* Wrap error */
#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_ECC                         0x9	/* ECC error detected */
#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
						/* reading PSTAG for a MW  */
						/* Invalidate */
#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
						/* software error */
#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
#define T4_ERR_CRC                         0x10 /* CRC error */
#define T4_ERR_MARKER                      0x11 /* Marker error */
#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
#define T4_ERR_MSN                         0x18 /* MSN error */
#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
						/* or READ_REQ */
#define T4_ERR_MSN_GAP                     0x1B
#define T4_ERR_MSN_RANGE                   0x1C
#define T4_ERR_IRD_OVERFLOW                0x1D
#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
						/* software error */
#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
						/* mismatch) */
/*
 * CQE defs
 */
struct t4_cqe {
	__be32 header;
	__be32 len;
	union {
		struct {
			__be32 stag;
			__be32 msn;
		} rcqe;
		struct {
			u32 nada1;
			u16 nada2;
			u16 cidx;
		} scqe;
		struct {
			__be32 wrid_hi;
			__be32 wrid_low;
		} gen;
	} u;
	__be64 reserved;
	__be64 bits_type_ts;
};

/* macros for flit 0 of the cqe */

#define S_CQE_QPID        12
#define M_CQE_QPID        0xFFFFF
#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)

#define S_CQE_SWCQE       11
#define M_CQE_SWCQE       0x1
#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)

#define S_CQE_STATUS      5
#define M_CQE_STATUS      0x1F
#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)

#define S_CQE_TYPE        4
#define M_CQE_TYPE        0x1
#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)

#define S_CQE_OPCODE      0
#define M_CQE_OPCODE      0xF
#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)

#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
#define SQ_TYPE(x)	  (CQE_TYPE((x)))
#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))

#define CQE_SEND_OPCODE(x)( \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))

#define CQE_LEN(x)        (be32_to_cpu((x)->len))

/* used for RQ completion processing */
#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))

/* used for SQ completion processing */
#define CQE_WRID_SQ_IDX(x)	((x)->u.scqe.cidx)

/* generic accessor macros */
#define CQE_WRID_HI(x)		(be32_to_cpu((x)->u.gen.wrid_hi))
#define CQE_WRID_LOW(x)		(be32_to_cpu((x)->u.gen.wrid_low))

/* macros for flit 3 of the cqe */
#define S_CQE_GENBIT	63
#define M_CQE_GENBIT	0x1
#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)

#define S_CQE_OVFBIT	62
#define M_CQE_OVFBIT	0x1
#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)

#define S_CQE_IQTYPE	60
#define M_CQE_IQTYPE	0x3
#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)

#define M_CQE_TS	0x0fffffffffffffffULL
#define G_CQE_TS(x)	((x) & M_CQE_TS)

#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))

struct t4_swsqe {
	u64			wr_id;
	struct t4_cqe		cqe;
	int			read_len;
	int			opcode;
	int			complete;
	int			signaled;
	u16			idx;
	int                     flushed;
	struct timespec         host_ts;
	u64                     sge_ts;
};

static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
{
#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
	return pgprot_writecombine(prot);
#else
	return pgprot_noncached(prot);
#endif
}

enum {
	T4_SQ_ONCHIP = (1<<0),
};

struct t4_sq {
	union t4_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	unsigned long phys_addr;
	struct t4_swsqe *sw_sq;
	struct t4_swsqe *oldest_read;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
	u16 flags;
	short flush_cidx;
};

struct t4_swrqe {
	u64 wr_id;
	struct timespec host_ts;
	u64 sge_ts;
};

struct t4_rq {
	union  t4_recv_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_swrqe *sw_rq;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u32 msn;
	u32 rqt_hwaddr;
	u16 rqt_size;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
};

struct t4_wq {
	struct t4_sq sq;
	struct t4_rq rq;
	void __iomem *db;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	int flushed;
};

static inline int t4_rqes_posted(struct t4_wq *wq)
{
	return wq->rq.in_use;
}

static inline int t4_rq_empty(struct t4_wq *wq)
{
	return wq->rq.in_use == 0;
}

static inline int t4_rq_full(struct t4_wq *wq)
{
	return wq->rq.in_use == (wq->rq.size - 1);
}

static inline u32 t4_rq_avail(struct t4_wq *wq)
{
	return wq->rq.size - 1 - wq->rq.in_use;
}

static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
{
	wq->rq.in_use++;
	if (++wq->rq.pidx == wq->rq.size)
		wq->rq.pidx = 0;
	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline void t4_rq_consume(struct t4_wq *wq)
{
	wq->rq.in_use--;
	wq->rq.msn++;
	if (++wq->rq.cidx == wq->rq.size)
		wq->rq.cidx = 0;
}

static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
}

static inline u16 t4_rq_wq_size(struct t4_wq *wq)
{
		return wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline int t4_sq_onchip(struct t4_sq *sq)
{
	return sq->flags & T4_SQ_ONCHIP;
}

static inline int t4_sq_empty(struct t4_wq *wq)
{
	return wq->sq.in_use == 0;
}

static inline int t4_sq_full(struct t4_wq *wq)
{
	return wq->sq.in_use == (wq->sq.size - 1);
}

static inline u32 t4_sq_avail(struct t4_wq *wq)
{
	return wq->sq.size - 1 - wq->sq.in_use;
}

static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
{
	wq->sq.in_use++;
	if (++wq->sq.pidx == wq->sq.size)
		wq->sq.pidx = 0;
	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
}

static inline void t4_sq_consume(struct t4_wq *wq)
{
	BUG_ON(wq->sq.in_use < 1);
	if (wq->sq.cidx == wq->sq.flush_cidx)
		wq->sq.flush_cidx = -1;
	wq->sq.in_use--;
	if (++wq->sq.cidx == wq->sq.size)
		wq->sq.cidx = 0;
}

static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
}

static inline u16 t4_sq_wq_size(struct t4_wq *wq)
{
		return wq->sq.size * T4_SQ_NUM_SLOTS;
}

/* This function copies 64 byte coalesced work request to memory
 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
 * from the FIFO instead of from Host.
 */
static inline void pio_copy(u64 __iomem *dst, u64 *src)
{
	int count = 8;

	while (count) {
		writeq(*src, dst);
		src++;
		dst++;
		count--;
	}
}

static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			pio_copy(wq->sq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			writel(PIDX_T5(inc), wq->sq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
}

static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_recv_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			pio_copy(wq->rq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			writel(PIDX_T5(inc), wq->rq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
}

static inline int t4_wq_in_error(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.qp_err;
}

static inline void t4_set_wq_in_error(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.qp_err = 1;
}

static inline void t4_disable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 1;
}

static inline void t4_enable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 0;
}

static inline int t4_wq_db_enabled(struct t4_wq *wq)
{
	return !wq->rq.queue[wq->rq.size].status.db_off;
}

struct t4_cq {
	struct t4_cqe *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_cqe *sw_queue;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	u64 ugts;
	size_t memsize;
	__be64 bits_type_ts;
	u32 cqid;
	int vector;
	u16 size; /* including status page */
	u16 cidx;
	u16 sw_pidx;
	u16 sw_cidx;
	u16 sw_in_use;
	u16 cidx_inc;
	u8 gen;
	u8 error;
};

static inline int t4_arm_cq(struct t4_cq *cq, int se)
{
	u32 val;

	while (cq->cidx_inc > CIDXINC_MASK) {
		val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
		      INGRESSQID(cq->cqid);
		writel(val, cq->gts);
		cq->cidx_inc -= CIDXINC_MASK;
	}
	val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
	      INGRESSQID(cq->cqid);
	writel(val, cq->gts);
	cq->cidx_inc = 0;
	return 0;
}

static inline void t4_swcq_produce(struct t4_cq *cq)
{
	cq->sw_in_use++;
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
	}
	if (++cq->sw_pidx == cq->size)
		cq->sw_pidx = 0;
}

static inline void t4_swcq_consume(struct t4_cq *cq)
{
	BUG_ON(cq->sw_in_use < 1);
	cq->sw_in_use--;
	if (++cq->sw_cidx == cq->size)
		cq->sw_cidx = 0;
}

static inline void t4_hwcq_consume(struct t4_cq *cq)
{
	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) {
		u32 val;

		val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
		      INGRESSQID(cq->cqid);
		writel(val, cq->gts);
		cq->cidx_inc = 0;
	}
	if (++cq->cidx == cq->size) {
		cq->cidx = 0;
		cq->gen ^= 1;
	}
}

static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
{
	return (CQE_GENBIT(cqe) == cq->gen);
}

static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret;
	u16 prev_cidx;

	if (cq->cidx == 0)
		prev_cidx = cq->size - 1;
	else
		prev_cidx = cq->cidx - 1;

	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
		ret = -EOVERFLOW;
		cq->error = 1;
		printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
		BUG_ON(1);
	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {

		/* Ensure CQE is flushed to memory */
		rmb();
		*cqe = &cq->queue[cq->cidx];
		ret = 0;
	} else
		ret = -ENODATA;
	return ret;
}

static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
{
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
		return NULL;
	}
	if (cq->sw_in_use)
		return &cq->sw_queue[cq->sw_cidx];
	return NULL;
}

static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret = 0;

	if (cq->error)
		ret = -ENODATA;
	else if (cq->sw_in_use)
		*cqe = &cq->sw_queue[cq->sw_cidx];
	else
		ret = t4_next_hw_cqe(cq, cqe);
	return ret;
}

static inline int t4_cq_in_error(struct t4_cq *cq)
{
	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
}

static inline void t4_set_cq_in_error(struct t4_cq *cq)
{
	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
}
#endif

struct t4_dev_status_page {
	u8 db_off;
};
Commit	Line	Data
cfdda9d7 SW	1	/*
	2	* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	* - Redistributions in binary form must reproduce the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer in the documentation and/or other materials
	20	* provided with the distribution.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	23	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	24	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	25	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	26	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	27	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	28	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	29	* SOFTWARE.
	30	*/
	31	#ifndef __T4_H__
	32	#define __T4_H__
	33
	34	#include "t4_hw.h"
	35	#include "t4_regs.h"
	36	#include "t4_msg.h"
	37	#include "t4fw_ri_api.h"
	38
1cf24dce SW	39	#define T4_MAX_NUM_QP 65536
	40	#define T4_MAX_NUM_CQ 65536
	41	#define T4_MAX_NUM_PD 65536
cfdda9d7	42	#define T4_MAX_NUM_STAG (1<<15)
a2de1499	43	#define T4_MAX_MR_SIZE (~0ULL)
cfdda9d7 SW	44	#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
	45	#define T4_STAG_UNSET 0xffffffff
	46	#define T4_FW_MAJ 0
c6d7b267	47	#define A_PCIE_MA_SYNC 0x30b4
cfdda9d7 SW	48
	49	struct t4_status_page {
	50	__be32 rsvd1; /* flit 0 - hw owns */
	51	__be16 rsvd2;
	52	__be16 qid;
	53	__be16 cidx;
	54	__be16 pidx;
	55	u8 qp_err; /* flit 1 - sw owns */
	56	u8 db_off;
422eea0a VP	57	u8 pad;
	58	u16 host_wq_pidx;
	59	u16 host_cidx;
	60	u16 host_pidx;
cfdda9d7 SW	61	};
cfdda9d7 SW	62
d37ac31d	63	#define T4_EQ_ENTRY_SIZE 64
cfdda9d7	64
40dbf6ee	65	#define T4_SQ_NUM_SLOTS 5
d37ac31d	66	#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
cfdda9d7 SW	67	#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	68	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	69	#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	70	sizeof(struct fw_ri_immd)))
	71	#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
	72	sizeof(struct fw_ri_rdma_write_wr) - \
	73	sizeof(struct fw_ri_immd)))
	74	#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
	75	sizeof(struct fw_ri_rdma_write_wr) - \
	76	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	77	#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
40dbf6ee	78	sizeof(struct fw_ri_immd)) & ~31UL)
a03d9f94 SW	79	#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
	80	#define T4_MAX_FR_DSGL 1024
	81	#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
	82
	83	static inline int t4_max_fr_depth(int use_dsgl)
	84	{
	85	return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
	86	}
cfdda9d7 SW	87
cfdda9d7 SW	88	#define T4_RQ_NUM_SLOTS 2
d37ac31d	89	#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
f64b8843	90	#define T4_MAX_RECV_SGE 4
cfdda9d7 SW	91
	92	union t4_wr {
	93	struct fw_ri_res_wr res;
	94	struct fw_ri_wr ri;
	95	struct fw_ri_rdma_write_wr write;
	96	struct fw_ri_send_wr send;
	97	struct fw_ri_rdma_read_wr read;
	98	struct fw_ri_bind_mw_wr bind;
	99	struct fw_ri_fr_nsmr_wr fr;
	100	struct fw_ri_inv_lstag_wr inv;
	101	struct t4_status_page status;
d37ac31d	102	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
cfdda9d7 SW	103	};
	104
	105	union t4_recv_wr {
	106	struct fw_ri_recv_wr recv;
	107	struct t4_status_page status;
d37ac31d	108	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
cfdda9d7 SW	109	};
	110
	111	static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
	112	enum fw_wr_opcodes opcode, u8 flags, u8 len16)
	113	{
cfdda9d7 SW	114	wqe->send.opcode = (u8)opcode;
	115	wqe->send.flags = flags;
	116	wqe->send.wrid = wrid;
	117	wqe->send.r1[0] = 0;
	118	wqe->send.r1[1] = 0;
	119	wqe->send.r1[2] = 0;
	120	wqe->send.len16 = len16;
cfdda9d7 SW	121	}
	122
	123	/* CQE/AE status codes */
	124	#define T4_ERR_SUCCESS 0x0
	125	#define T4_ERR_STAG 0x1 /* STAG invalid: either the */
	126	/* STAG is offlimt, being 0, */
	127	/* or STAG_key mismatch */
	128	#define T4_ERR_PDID 0x2 /* PDID mismatch */
	129	#define T4_ERR_QPID 0x3 /* QPID mismatch */
	130	#define T4_ERR_ACCESS 0x4 /* Invalid access right */
	131	#define T4_ERR_WRAP 0x5 /* Wrap error */
	132	#define T4_ERR_BOUND 0x6 /* base and bounds voilation */
	133	#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
	134	/* shared memory region */
	135	#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
	136	/* shared memory region */
	137	#define T4_ERR_ECC 0x9 /* ECC error detected */
	138	#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
	139	/* reading PSTAG for a MW */
	140	/* Invalidate */
	141	#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
	142	/* software error */
	143	#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
	144	#define T4_ERR_CRC 0x10 /* CRC error */
	145	#define T4_ERR_MARKER 0x11 /* Marker error */
	146	#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
	147	#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
	148	#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
	149	#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
	150	#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
	151	#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
	152	#define T4_ERR_MSN 0x18 /* MSN error */
	153	#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
	154	#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
	155	/* or READ_REQ */
	156	#define T4_ERR_MSN_GAP 0x1B
	157	#define T4_ERR_MSN_RANGE 0x1C
	158	#define T4_ERR_IRD_OVERFLOW 0x1D
	159	#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
	160	/* software error */
	161	#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
	162	/* mismatch) */
	163	/*
	164	* CQE defs
	165	*/
	166	struct t4_cqe {
	167	__be32 header;
	168	__be32 len;
	169	union {
	170	struct {
	171	__be32 stag;
	172	__be32 msn;
	173	} rcqe;
	174	struct {
	175	u32 nada1;
	176	u16 nada2;
	177	u16 cidx;
	178	} scqe;
	179	struct {
	180	__be32 wrid_hi;
	181	__be32 wrid_low;
	182	} gen;
	183	} u;
	184	__be64 reserved;
185	__be64 bits_type_ts;
186	};
187
188	/* macros for flit 0 of the cqe */
189
190	#define S_CQE_QPID 12
191	#define M_CQE_QPID 0xFFFFF
192	#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
193	#define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
194
195	#define S_CQE_SWCQE 11
196	#define M_CQE_SWCQE 0x1
197	#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
198	#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
199
200	#define S_CQE_STATUS 5
201	#define M_CQE_STATUS 0x1F
202	#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
203	#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
204
205	#define S_CQE_TYPE 4
206	#define M_CQE_TYPE 0x1
207	#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
208	#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
209
210	#define S_CQE_OPCODE 0
211	#define M_CQE_OPCODE 0xF
212	#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
213	#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
214
215	#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
216	#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
217	#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
218	#define SQ_TYPE(x) (CQE_TYPE((x)))
219	#define RQ_TYPE(x) (!CQE_TYPE((x)))
220	#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
221	#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
222
223	#define CQE_SEND_OPCODE(x)( \
224	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) \|\| \
225	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) \|\| \
226	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) \|\| \
227	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
228
229	#define CQE_LEN(x) (be32_to_cpu((x)->len))
230
231	/* used for RQ completion processing */
232	#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
233	#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
234
235	/* used for SQ completion processing */
236	#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
237
238	/* generic accessor macros */
031cf476 HS	239	#define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
031cf476 HS	240	#define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
cfdda9d7 SW	241
	242	/* macros for flit 3 of the cqe */
	243	#define S_CQE_GENBIT 63
	244	#define M_CQE_GENBIT 0x1
	245	#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
	246	#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
	247
	248	#define S_CQE_OVFBIT 62
	249	#define M_CQE_OVFBIT 0x1
	250	#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
	251
	252	#define S_CQE_IQTYPE 60
	253	#define M_CQE_IQTYPE 0x3
	254	#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
	255
	256	#define M_CQE_TS 0x0fffffffffffffffULL
	257	#define G_CQE_TS(x) ((x) & M_CQE_TS)
	258
	259	#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
	260	#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
	261	#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
	262
	263	struct t4_swsqe {
	264	u64 wr_id;
	265	struct t4_cqe cqe;
	266	int read_len;
	267	int opcode;
	268	int complete;
	269	int signaled;
	270	u16 idx;
1cf24dce	271	int flushed;
7730b4c7 HS	272	struct timespec host_ts;
7730b4c7 HS	273	u64 sge_ts;
cfdda9d7 SW	274	};
cfdda9d7 SW	275
c6d7b267 SW	276	static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
c6d7b267 SW	277	{
e297d9dd	278	#if defined(__i386__) \|\| defined(__x86_64__) \|\| defined(CONFIG_PPC64)
c6d7b267	279	return pgprot_writecombine(prot);
c6d7b267 SW	280	#else
	281	return pgprot_noncached(prot);
	282	#endif
	283	}
	284
c6d7b267 SW	285	enum {
	286	T4_SQ_ONCHIP = (1<<0),
	287	};
	288
cfdda9d7 SW	289	struct t4_sq {
	290	union t4_wr *queue;
	291	dma_addr_t dma_addr;
f38926aa	292	DEFINE_DMA_UNMAP_ADDR(mapping);
c6d7b267	293	unsigned long phys_addr;
cfdda9d7 SW	294	struct t4_swsqe *sw_sq;
cfdda9d7 SW	295	struct t4_swsqe *oldest_read;
fa658a98	296	u64 __iomem *udb;
cfdda9d7 SW	297	size_t memsize;
	298	u32 qid;
	299	u16 in_use;
	300	u16 size;
	301	u16 cidx;
	302	u16 pidx;
d37ac31d	303	u16 wq_pidx;
05eb2389	304	u16 wq_pidx_inc;
c6d7b267	305	u16 flags;
1cf24dce	306	short flush_cidx;
cfdda9d7 SW	307	};
	308
	309	struct t4_swrqe {
	310	u64 wr_id;
7730b4c7 HS	311	struct timespec host_ts;
7730b4c7 HS	312	u64 sge_ts;
cfdda9d7 SW	313	};
	314
	315	struct t4_rq {
	316	union t4_recv_wr *queue;
	317	dma_addr_t dma_addr;
f38926aa	318	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7	319	struct t4_swrqe *sw_rq;
fa658a98	320	u64 __iomem *udb;
cfdda9d7 SW	321	size_t memsize;
	322	u32 qid;
	323	u32 msn;
	324	u32 rqt_hwaddr;
	325	u16 rqt_size;
	326	u16 in_use;
	327	u16 size;
	328	u16 cidx;
	329	u16 pidx;
d37ac31d	330	u16 wq_pidx;
05eb2389	331	u16 wq_pidx_inc;
cfdda9d7 SW	332	};
	333
	334	struct t4_wq {
	335	struct t4_sq sq;
	336	struct t4_rq rq;
	337	void __iomem *db;
	338	void __iomem *gts;
	339	struct c4iw_rdev *rdev;
1cf24dce	340	int flushed;
cfdda9d7 SW	341	};
	342
	343	static inline int t4_rqes_posted(struct t4_wq *wq)
	344	{
	345	return wq->rq.in_use;
	346	}
	347
	348	static inline int t4_rq_empty(struct t4_wq *wq)
	349	{
	350	return wq->rq.in_use == 0;
	351	}
	352
	353	static inline int t4_rq_full(struct t4_wq *wq)
	354	{
	355	return wq->rq.in_use == (wq->rq.size - 1);
	356	}
	357
	358	static inline u32 t4_rq_avail(struct t4_wq *wq)
	359	{
	360	return wq->rq.size - 1 - wq->rq.in_use;
	361	}
	362
d37ac31d	363	static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	364	{
	365	wq->rq.in_use++;
	366	if (++wq->rq.pidx == wq->rq.size)
	367	wq->rq.pidx = 0;
d37ac31d SW	368	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	369	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
	370	wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
cfdda9d7 SW	371	}
	372
	373	static inline void t4_rq_consume(struct t4_wq *wq)
	374	{
	375	wq->rq.in_use--;
	376	wq->rq.msn++;
	377	if (++wq->rq.cidx == wq->rq.size)
	378	wq->rq.cidx = 0;
	379	}
	380
422eea0a VP	381	static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
	382	{
	383	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
	384	}
	385
	386	static inline u16 t4_rq_wq_size(struct t4_wq *wq)
	387	{
	388	return wq->rq.size * T4_RQ_NUM_SLOTS;
	389	}
	390
c6d7b267 SW	391	static inline int t4_sq_onchip(struct t4_sq *sq)
	392	{
	393	return sq->flags & T4_SQ_ONCHIP;
	394	}
	395
cfdda9d7 SW	396	static inline int t4_sq_empty(struct t4_wq *wq)
	397	{
	398	return wq->sq.in_use == 0;
	399	}
	400
	401	static inline int t4_sq_full(struct t4_wq *wq)
	402	{
	403	return wq->sq.in_use == (wq->sq.size - 1);
	404	}
	405
	406	static inline u32 t4_sq_avail(struct t4_wq *wq)
	407	{
	408	return wq->sq.size - 1 - wq->sq.in_use;
	409	}
	410
d37ac31d	411	static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	412	{
	413	wq->sq.in_use++;
	414	if (++wq->sq.pidx == wq->sq.size)
	415	wq->sq.pidx = 0;
d37ac31d SW	416	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	417	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
	418	wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
cfdda9d7 SW	419	}
	420
	421	static inline void t4_sq_consume(struct t4_wq *wq)
	422	{
1cf24dce SW	423	BUG_ON(wq->sq.in_use < 1);
	424	if (wq->sq.cidx == wq->sq.flush_cidx)
	425	wq->sq.flush_cidx = -1;
cfdda9d7 SW	426	wq->sq.in_use--;
	427	if (++wq->sq.cidx == wq->sq.size)
	428	wq->sq.cidx = 0;
	429	}
	430
422eea0a VP	431	static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
	432	{
	433	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
	434	}
	435
	436	static inline u16 t4_sq_wq_size(struct t4_wq *wq)
	437	{
	438	return wq->sq.size * T4_SQ_NUM_SLOTS;
	439	}
	440
fa658a98 SW	441	/* This function copies 64 byte coalesced work request to memory
	442	* mapped BAR2 space. For coalesced WRs, the SGE fetches data
	443	* from the FIFO instead of from Host.
	444	*/
	445	static inline void pio_copy(u64 __iomem dst, u64 src)
	446	{
	447	int count = 8;
	448
	449	while (count) {
	450	writeq(*src, dst);
	451	src++;
	452	dst++;
	453	count--;
	454	}
	455	}
	456
	457	static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
	458	union t4_wr *wqe)
cfdda9d7	459	{
fa658a98 SW	460
fa658a98 SW	461	/* Flush host queue memory writes. */
cfdda9d7	462	wmb();
fa658a98 SW	463	if (t5) {
	464	if (inc == 1 && wqe) {
	465	PDBG("%s: WC wq->sq.pidx = %d\n",
	466	__func__, wq->sq.pidx);
	467	pio_copy(wq->sq.udb + 7, (void *)wqe);
	468	} else {
	469	PDBG("%s: DB wq->sq.pidx = %d\n",
	470	__func__, wq->sq.pidx);
	471	writel(PIDX_T5(inc), wq->sq.udb);
	472	}
	473
	474	/* Flush user doorbell area writes. */
	475	wmb();
	476	return;
	477	}
cfdda9d7 SW	478	writel(QID(wq->sq.qid) \| PIDX(inc), wq->db);
	479	}
	480
fa658a98 SW	481	static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
fa658a98 SW	482	union t4_recv_wr *wqe)
cfdda9d7	483	{
fa658a98 SW	484
fa658a98 SW	485	/* Flush host queue memory writes. */
cfdda9d7	486	wmb();
fa658a98 SW	487	if (t5) {
	488	if (inc == 1 && wqe) {
	489	PDBG("%s: WC wq->rq.pidx = %d\n",
	490	__func__, wq->rq.pidx);
	491	pio_copy(wq->rq.udb + 7, (void *)wqe);
	492	} else {
	493	PDBG("%s: DB wq->rq.pidx = %d\n",
	494	__func__, wq->rq.pidx);
	495	writel(PIDX_T5(inc), wq->rq.udb);
	496	}
	497
	498	/* Flush user doorbell area writes. */
	499	wmb();
	500	return;
	501	}
cfdda9d7 SW	502	writel(QID(wq->rq.qid) \| PIDX(inc), wq->db);
	503	}
	504
	505	static inline int t4_wq_in_error(struct t4_wq *wq)
	506	{
c6d7b267	507	return wq->rq.queue[wq->rq.size].status.qp_err;
cfdda9d7 SW	508	}
	509
	510	static inline void t4_set_wq_in_error(struct t4_wq *wq)
	511	{
cfdda9d7 SW	512	wq->rq.queue[wq->rq.size].status.qp_err = 1;
	513	}
	514
	515	static inline void t4_disable_wq_db(struct t4_wq *wq)
	516	{
cfdda9d7 SW	517	wq->rq.queue[wq->rq.size].status.db_off = 1;
	518	}
	519
	520	static inline void t4_enable_wq_db(struct t4_wq *wq)
	521	{
cfdda9d7 SW	522	wq->rq.queue[wq->rq.size].status.db_off = 0;
	523	}
	524
	525	static inline int t4_wq_db_enabled(struct t4_wq *wq)
	526	{
c6d7b267	527	return !wq->rq.queue[wq->rq.size].status.db_off;
cfdda9d7 SW	528	}
	529
	530	struct t4_cq {
	531	struct t4_cqe *queue;
	532	dma_addr_t dma_addr;
f38926aa	533	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7 SW	534	struct t4_cqe *sw_queue;
	535	void __iomem *gts;
	536	struct c4iw_rdev *rdev;
	537	u64 ugts;
	538	size_t memsize;
84172dee	539	__be64 bits_type_ts;
cfdda9d7	540	u32 cqid;
cf38be6d	541	int vector;
cfdda9d7 SW	542	u16 size; /* including status page */
	543	u16 cidx;
	544	u16 sw_pidx;
	545	u16 sw_cidx;
	546	u16 sw_in_use;
	547	u16 cidx_inc;
	548	u8 gen;
	549	u8 error;
	550	};
	551
	552	static inline int t4_arm_cq(struct t4_cq *cq, int se)
	553	{
	554	u32 val;
7ec45b92 SW	555
	556	while (cq->cidx_inc > CIDXINC_MASK) {
	557	val = SEINTARM(0) \| CIDXINC(CIDXINC_MASK) \| TIMERREG(7) \|
	558	INGRESSQID(cq->cqid);
be4c9bad	559	writel(val, cq->gts);
7ec45b92 SW	560	cq->cidx_inc -= CIDXINC_MASK;
	561	}
	562	val = SEINTARM(se) \| CIDXINC(cq->cidx_inc) \| TIMERREG(6) \|
	563	INGRESSQID(cq->cqid);
	564	writel(val, cq->gts);
	565	cq->cidx_inc = 0;
cfdda9d7 SW	566	return 0;
	567	}
	568
	569	static inline void t4_swcq_produce(struct t4_cq *cq)
	570	{
	571	cq->sw_in_use++;
1cf24dce SW	572	if (cq->sw_in_use == cq->size) {
	573	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	574	cq->error = 1;
	575	BUG_ON(1);
	576	}
cfdda9d7 SW	577	if (++cq->sw_pidx == cq->size)
	578	cq->sw_pidx = 0;
	579	}
	580
	581	static inline void t4_swcq_consume(struct t4_cq *cq)
	582	{
1cf24dce	583	BUG_ON(cq->sw_in_use < 1);
cfdda9d7 SW	584	cq->sw_in_use--;
	585	if (++cq->sw_cidx == cq->size)
	586	cq->sw_cidx = 0;
	587	}
	588
	589	static inline void t4_hwcq_consume(struct t4_cq *cq)
	590	{
84172dee	591	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
b298881f	592	if (++cq->cidx_inc == (cq->size >> 4) \|\| cq->cidx_inc == CIDXINC_MASK) {
ffc3f748 SW	593	u32 val;
	594
	595	val = SEINTARM(0) \| CIDXINC(cq->cidx_inc) \| TIMERREG(7) \|
	596	INGRESSQID(cq->cqid);
	597	writel(val, cq->gts);
7ec45b92	598	cq->cidx_inc = 0;
ffc3f748	599	}
cfdda9d7 SW	600	if (++cq->cidx == cq->size) {
	601	cq->cidx = 0;
	602	cq->gen ^= 1;
	603	}
	604	}
	605
	606	static inline int t4_valid_cqe(struct t4_cq cq, struct t4_cqe cqe)
	607	{
	608	return (CQE_GENBIT(cqe) == cq->gen);
	609	}
	610
	611	static inline int t4_next_hw_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	612	{
84172dee SW	613	int ret;
84172dee SW	614	u16 prev_cidx;
cfdda9d7	615
84172dee SW	616	if (cq->cidx == 0)
84172dee SW	617	prev_cidx = cq->size - 1;
cfdda9d7	618	else
84172dee SW	619	prev_cidx = cq->cidx - 1;
	620
	621	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
	622	ret = -EOVERFLOW;
cfdda9d7	623	cq->error = 1;
84172dee	624	printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
1cf24dce	625	BUG_ON(1);
84172dee	626	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
def4771f SW	627
	628	/* Ensure CQE is flushed to memory */
	629	rmb();
84172dee SW	630	*cqe = &cq->queue[cq->cidx];
	631	ret = 0;
	632	} else
	633	ret = -ENODATA;
cfdda9d7 SW	634	return ret;
	635	}
	636
	637	static inline struct t4_cqe t4_next_sw_cqe(struct t4_cq cq)
	638	{
1cf24dce SW	639	if (cq->sw_in_use == cq->size) {
	640	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	641	cq->error = 1;
	642	BUG_ON(1);
	643	return NULL;
	644	}
cfdda9d7 SW	645	if (cq->sw_in_use)
	646	return &cq->sw_queue[cq->sw_cidx];
	647	return NULL;
	648	}
	649
	650	static inline int t4_next_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	651	{
	652	int ret = 0;
	653
	654	if (cq->error)
	655	ret = -ENODATA;
	656	else if (cq->sw_in_use)
	657	*cqe = &cq->sw_queue[cq->sw_cidx];
	658	else
	659	ret = t4_next_hw_cqe(cq, cqe);
	660	return ret;
	661	}
	662
	663	static inline int t4_cq_in_error(struct t4_cq *cq)
	664	{
	665	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
	666	}
	667
	668	static inline void t4_set_cq_in_error(struct t4_cq *cq)
	669	{
	670	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
	671	}
	672	#endif
05eb2389 SW	673
	674	struct t4_dev_status_page {
	675	u8 db_off;
	676	};