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77241056 | 1 | /* |
05d6ac1d | 2 | * Copyright(c) 2015, 2016 Intel Corporation. |
77241056 MM |
3 | * |
4 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
5 | * redistributing this file, you may do so under either license. | |
6 | * | |
7 | * GPL LICENSE SUMMARY | |
8 | * | |
77241056 MM |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * BSD LICENSE | |
19 | * | |
77241056 MM |
20 | * Redistribution and use in source and binary forms, with or without |
21 | * modification, are permitted provided that the following conditions | |
22 | * are met: | |
23 | * | |
24 | * - Redistributions of source code must retain the above copyright | |
25 | * notice, this list of conditions and the following disclaimer. | |
26 | * - Redistributions in binary form must reproduce the above copyright | |
27 | * notice, this list of conditions and the following disclaimer in | |
28 | * the documentation and/or other materials provided with the | |
29 | * distribution. | |
30 | * - Neither the name of Intel Corporation nor the names of its | |
31 | * contributors may be used to endorse or promote products derived | |
32 | * from this software without specific prior written permission. | |
33 | * | |
34 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
35 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
37 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
38 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
39 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
40 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
41 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
42 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
43 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
44 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
45 | * | |
46 | */ | |
47 | ||
48 | #include <linux/err.h> | |
49 | #include <linux/vmalloc.h> | |
50 | #include <linux/hash.h> | |
51 | #include <linux/module.h> | |
77241056 | 52 | #include <linux/seq_file.h> |
ec4274f1 DD |
53 | #include <rdma/rdma_vt.h> |
54 | #include <rdma/rdmavt_qp.h> | |
1ac57c50 | 55 | #include <rdma/ib_verbs.h> |
77241056 MM |
56 | |
57 | #include "hfi.h" | |
58 | #include "qp.h" | |
59 | #include "trace.h" | |
45842abb | 60 | #include "verbs_txreq.h" |
77241056 | 61 | |
a2c2d608 | 62 | unsigned int hfi1_qp_table_size = 256; |
77241056 MM |
63 | module_param_named(qp_table_size, hfi1_qp_table_size, uint, S_IRUGO); |
64 | MODULE_PARM_DESC(qp_table_size, "QP table size"); | |
65 | ||
895420dd | 66 | static void flush_tx_list(struct rvt_qp *qp); |
77241056 MM |
67 | static int iowait_sleep( |
68 | struct sdma_engine *sde, | |
69 | struct iowait *wait, | |
70 | struct sdma_txreq *stx, | |
71 | unsigned seq); | |
72 | static void iowait_wakeup(struct iowait *wait, int reason); | |
a545f530 | 73 | static void iowait_sdma_drained(struct iowait *wait); |
91702b4a | 74 | static void qp_pio_drain(struct rvt_qp *qp); |
77241056 | 75 | |
1c4b7d97 DD |
76 | static inline unsigned mk_qpn(struct rvt_qpn_table *qpt, |
77 | struct rvt_qpn_map *map, unsigned off) | |
77241056 | 78 | { |
1c4b7d97 | 79 | return (map - qpt->map) * RVT_BITS_PER_PAGE + off; |
77241056 MM |
80 | } |
81 | ||
82 | /* | |
83 | * Convert the AETH credit code into the number of credits. | |
84 | */ | |
85 | static const u16 credit_table[31] = { | |
86 | 0, /* 0 */ | |
87 | 1, /* 1 */ | |
88 | 2, /* 2 */ | |
89 | 3, /* 3 */ | |
90 | 4, /* 4 */ | |
91 | 6, /* 5 */ | |
92 | 8, /* 6 */ | |
93 | 12, /* 7 */ | |
94 | 16, /* 8 */ | |
95 | 24, /* 9 */ | |
96 | 32, /* A */ | |
97 | 48, /* B */ | |
98 | 64, /* C */ | |
99 | 96, /* D */ | |
100 | 128, /* E */ | |
101 | 192, /* F */ | |
102 | 256, /* 10 */ | |
103 | 384, /* 11 */ | |
104 | 512, /* 12 */ | |
105 | 768, /* 13 */ | |
106 | 1024, /* 14 */ | |
107 | 1536, /* 15 */ | |
108 | 2048, /* 16 */ | |
109 | 3072, /* 17 */ | |
110 | 4096, /* 18 */ | |
111 | 6144, /* 19 */ | |
112 | 8192, /* 1A */ | |
113 | 12288, /* 1B */ | |
114 | 16384, /* 1C */ | |
115 | 24576, /* 1D */ | |
116 | 32768 /* 1E */ | |
117 | }; | |
118 | ||
1ac57c50 MM |
119 | const struct rvt_operation_params hfi1_post_parms[RVT_OPERATION_MAX] = { |
120 | [IB_WR_RDMA_WRITE] = { | |
121 | .length = sizeof(struct ib_rdma_wr), | |
122 | .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), | |
123 | }, | |
124 | ||
125 | [IB_WR_RDMA_READ] = { | |
126 | .length = sizeof(struct ib_rdma_wr), | |
127 | .qpt_support = BIT(IB_QPT_RC), | |
128 | .flags = RVT_OPERATION_ATOMIC, | |
129 | }, | |
130 | ||
131 | [IB_WR_ATOMIC_CMP_AND_SWP] = { | |
132 | .length = sizeof(struct ib_atomic_wr), | |
133 | .qpt_support = BIT(IB_QPT_RC), | |
134 | .flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE, | |
135 | }, | |
136 | ||
137 | [IB_WR_ATOMIC_FETCH_AND_ADD] = { | |
138 | .length = sizeof(struct ib_atomic_wr), | |
139 | .qpt_support = BIT(IB_QPT_RC), | |
140 | .flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE, | |
141 | }, | |
142 | ||
143 | [IB_WR_RDMA_WRITE_WITH_IMM] = { | |
144 | .length = sizeof(struct ib_rdma_wr), | |
145 | .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), | |
146 | }, | |
147 | ||
148 | [IB_WR_SEND] = { | |
149 | .length = sizeof(struct ib_send_wr), | |
150 | .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | | |
151 | BIT(IB_QPT_UC) | BIT(IB_QPT_RC), | |
152 | }, | |
153 | ||
154 | [IB_WR_SEND_WITH_IMM] = { | |
155 | .length = sizeof(struct ib_send_wr), | |
156 | .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | | |
157 | BIT(IB_QPT_UC) | BIT(IB_QPT_RC), | |
158 | }, | |
159 | ||
c72cfe3e JX |
160 | [IB_WR_REG_MR] = { |
161 | .length = sizeof(struct ib_reg_wr), | |
162 | .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), | |
163 | .flags = RVT_OPERATION_LOCAL, | |
164 | }, | |
165 | ||
166 | [IB_WR_LOCAL_INV] = { | |
167 | .length = sizeof(struct ib_send_wr), | |
168 | .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), | |
169 | .flags = RVT_OPERATION_LOCAL, | |
170 | }, | |
171 | ||
172 | [IB_WR_SEND_WITH_INV] = { | |
173 | .length = sizeof(struct ib_send_wr), | |
174 | .qpt_support = BIT(IB_QPT_RC), | |
175 | }, | |
176 | ||
1ac57c50 MM |
177 | }; |
178 | ||
895420dd | 179 | static void flush_tx_list(struct rvt_qp *qp) |
77241056 | 180 | { |
4c6829c5 DD |
181 | struct hfi1_qp_priv *priv = qp->priv; |
182 | ||
183 | while (!list_empty(&priv->s_iowait.tx_head)) { | |
77241056 MM |
184 | struct sdma_txreq *tx; |
185 | ||
186 | tx = list_first_entry( | |
4c6829c5 | 187 | &priv->s_iowait.tx_head, |
77241056 MM |
188 | struct sdma_txreq, |
189 | list); | |
190 | list_del_init(&tx->list); | |
191 | hfi1_put_txreq( | |
192 | container_of(tx, struct verbs_txreq, txreq)); | |
193 | } | |
194 | } | |
195 | ||
895420dd | 196 | static void flush_iowait(struct rvt_qp *qp) |
77241056 | 197 | { |
4c6829c5 | 198 | struct hfi1_qp_priv *priv = qp->priv; |
77241056 MM |
199 | struct hfi1_ibdev *dev = to_idev(qp->ibqp.device); |
200 | unsigned long flags; | |
201 | ||
202 | write_seqlock_irqsave(&dev->iowait_lock, flags); | |
4c6829c5 DD |
203 | if (!list_empty(&priv->s_iowait.list)) { |
204 | list_del_init(&priv->s_iowait.list); | |
77241056 MM |
205 | if (atomic_dec_and_test(&qp->refcount)) |
206 | wake_up(&qp->wait); | |
207 | } | |
208 | write_sequnlock_irqrestore(&dev->iowait_lock, flags); | |
209 | } | |
210 | ||
211 | static inline int opa_mtu_enum_to_int(int mtu) | |
212 | { | |
213 | switch (mtu) { | |
214 | case OPA_MTU_8192: return 8192; | |
215 | case OPA_MTU_10240: return 10240; | |
216 | default: return -1; | |
217 | } | |
218 | } | |
219 | ||
220 | /** | |
221 | * This function is what we would push to the core layer if we wanted to be a | |
222 | * "first class citizen". Instead we hide this here and rely on Verbs ULPs | |
223 | * to blindly pass the MTU enum value from the PathRecord to us. | |
77241056 MM |
224 | */ |
225 | static inline int verbs_mtu_enum_to_int(struct ib_device *dev, enum ib_mtu mtu) | |
226 | { | |
ef699e84 | 227 | int val; |
77241056 | 228 | |
ef699e84 SS |
229 | /* Constraining 10KB packets to 8KB packets */ |
230 | if (mtu == (enum ib_mtu)OPA_MTU_10240) | |
231 | mtu = OPA_MTU_8192; | |
232 | val = opa_mtu_enum_to_int((int)mtu); | |
77241056 MM |
233 | if (val > 0) |
234 | return val; | |
235 | return ib_mtu_enum_to_int(mtu); | |
236 | } | |
237 | ||
ec4274f1 DD |
238 | int hfi1_check_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr, |
239 | int attr_mask, struct ib_udata *udata) | |
77241056 | 240 | { |
ec4274f1 | 241 | struct ib_qp *ibqp = &qp->ibqp; |
77241056 | 242 | struct hfi1_ibdev *dev = to_idev(ibqp->device); |
d7b8ba51 | 243 | struct hfi1_devdata *dd = dd_from_dev(dev); |
ec4274f1 | 244 | u8 sc; |
77241056 MM |
245 | |
246 | if (attr_mask & IB_QP_AV) { | |
d7b8ba51 | 247 | sc = ah_to_sc(ibqp->device, &attr->ah_attr); |
31e7af1c IW |
248 | if (sc == 0xf) |
249 | return -EINVAL; | |
250 | ||
d7b8ba51 MM |
251 | if (!qp_to_sdma_engine(qp, sc) && |
252 | dd->flags & HFI1_HAS_SEND_DMA) | |
ec4274f1 | 253 | return -EINVAL; |
721d0427 JJ |
254 | |
255 | if (!qp_to_send_context(qp, sc)) | |
256 | return -EINVAL; | |
77241056 MM |
257 | } |
258 | ||
259 | if (attr_mask & IB_QP_ALT_PATH) { | |
d7b8ba51 | 260 | sc = ah_to_sc(ibqp->device, &attr->alt_ah_attr); |
31e7af1c IW |
261 | if (sc == 0xf) |
262 | return -EINVAL; | |
263 | ||
d7b8ba51 MM |
264 | if (!qp_to_sdma_engine(qp, sc) && |
265 | dd->flags & HFI1_HAS_SEND_DMA) | |
ec4274f1 | 266 | return -EINVAL; |
721d0427 JJ |
267 | |
268 | if (!qp_to_send_context(qp, sc)) | |
269 | return -EINVAL; | |
77241056 MM |
270 | } |
271 | ||
ec4274f1 DD |
272 | return 0; |
273 | } | |
77241056 | 274 | |
ec4274f1 DD |
275 | void hfi1_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr, |
276 | int attr_mask, struct ib_udata *udata) | |
277 | { | |
278 | struct ib_qp *ibqp = &qp->ibqp; | |
279 | struct hfi1_qp_priv *priv = qp->priv; | |
77241056 MM |
280 | |
281 | if (attr_mask & IB_QP_AV) { | |
4c6829c5 DD |
282 | priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr); |
283 | priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc); | |
cef504c5 | 284 | priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc); |
77241056 MM |
285 | } |
286 | ||
ec4274f1 DD |
287 | if (attr_mask & IB_QP_PATH_MIG_STATE && |
288 | attr->path_mig_state == IB_MIG_MIGRATED && | |
289 | qp->s_mig_state == IB_MIG_ARMED) { | |
290 | qp->s_flags |= RVT_S_AHG_CLEAR; | |
291 | priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr); | |
292 | priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc); | |
cef504c5 | 293 | priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc); |
77241056 | 294 | } |
77241056 MM |
295 | } |
296 | ||
46a80d62 MM |
297 | /** |
298 | * hfi1_check_send_wqe - validate wqe | |
299 | * @qp - The qp | |
300 | * @wqe - The built wqe | |
301 | * | |
302 | * validate wqe. This is called | |
303 | * prior to inserting the wqe into | |
304 | * the ring but after the wqe has been | |
305 | * setup. | |
306 | * | |
307 | * Returns 0 on success, -EINVAL on failure | |
308 | * | |
309 | */ | |
310 | int hfi1_check_send_wqe(struct rvt_qp *qp, | |
311 | struct rvt_swqe *wqe) | |
31e7af1c IW |
312 | { |
313 | struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num); | |
46a80d62 | 314 | struct rvt_ah *ah; |
31e7af1c | 315 | |
46a80d62 MM |
316 | switch (qp->ibqp.qp_type) { |
317 | case IB_QPT_RC: | |
318 | case IB_QPT_UC: | |
319 | if (wqe->length > 0x80000000U) | |
320 | return -EINVAL; | |
321 | break; | |
322 | case IB_QPT_SMI: | |
323 | ah = ibah_to_rvtah(wqe->ud_wr.ah); | |
324 | if (wqe->length > (1 << ah->log_pmtu)) | |
325 | return -EINVAL; | |
326 | break; | |
327 | case IB_QPT_GSI: | |
328 | case IB_QPT_UD: | |
329 | ah = ibah_to_rvtah(wqe->ud_wr.ah); | |
330 | if (wqe->length > (1 << ah->log_pmtu)) | |
331 | return -EINVAL; | |
332 | if (ibp->sl_to_sc[ah->attr.sl] == 0xf) | |
333 | return -EINVAL; | |
334 | default: | |
335 | break; | |
31e7af1c | 336 | } |
91702b4a | 337 | return wqe->length <= piothreshold; |
31e7af1c IW |
338 | } |
339 | ||
77241056 MM |
340 | /** |
341 | * hfi1_compute_aeth - compute the AETH (syndrome + MSN) | |
342 | * @qp: the queue pair to compute the AETH for | |
343 | * | |
344 | * Returns the AETH. | |
345 | */ | |
895420dd | 346 | __be32 hfi1_compute_aeth(struct rvt_qp *qp) |
77241056 MM |
347 | { |
348 | u32 aeth = qp->r_msn & HFI1_MSN_MASK; | |
349 | ||
350 | if (qp->ibqp.srq) { | |
351 | /* | |
352 | * Shared receive queues don't generate credits. | |
353 | * Set the credit field to the invalid value. | |
354 | */ | |
355 | aeth |= HFI1_AETH_CREDIT_INVAL << HFI1_AETH_CREDIT_SHIFT; | |
356 | } else { | |
357 | u32 min, max, x; | |
358 | u32 credits; | |
895420dd | 359 | struct rvt_rwq *wq = qp->r_rq.wq; |
77241056 MM |
360 | u32 head; |
361 | u32 tail; | |
362 | ||
363 | /* sanity check pointers before trusting them */ | |
364 | head = wq->head; | |
365 | if (head >= qp->r_rq.size) | |
366 | head = 0; | |
367 | tail = wq->tail; | |
368 | if (tail >= qp->r_rq.size) | |
369 | tail = 0; | |
370 | /* | |
371 | * Compute the number of credits available (RWQEs). | |
372 | * There is a small chance that the pair of reads are | |
373 | * not atomic, which is OK, since the fuzziness is | |
374 | * resolved as further ACKs go out. | |
375 | */ | |
376 | credits = head - tail; | |
377 | if ((int)credits < 0) | |
378 | credits += qp->r_rq.size; | |
379 | /* | |
380 | * Binary search the credit table to find the code to | |
381 | * use. | |
382 | */ | |
383 | min = 0; | |
384 | max = 31; | |
385 | for (;;) { | |
386 | x = (min + max) / 2; | |
387 | if (credit_table[x] == credits) | |
388 | break; | |
e490974e | 389 | if (credit_table[x] > credits) { |
77241056 | 390 | max = x; |
e490974e | 391 | } else { |
edddfca0 | 392 | if (min == x) |
e490974e | 393 | break; |
edddfca0 | 394 | min = x; |
e490974e | 395 | } |
77241056 MM |
396 | } |
397 | aeth |= x << HFI1_AETH_CREDIT_SHIFT; | |
398 | } | |
399 | return cpu_to_be32(aeth); | |
400 | } | |
401 | ||
46a80d62 MM |
402 | /** |
403 | * _hfi1_schedule_send - schedule progress | |
404 | * @qp: the QP | |
405 | * | |
406 | * This schedules qp progress w/o regard to the s_flags. | |
407 | * | |
408 | * It is only used in the post send, which doesn't hold | |
409 | * the s_lock. | |
410 | */ | |
411 | void _hfi1_schedule_send(struct rvt_qp *qp) | |
412 | { | |
413 | struct hfi1_qp_priv *priv = qp->priv; | |
414 | struct hfi1_ibport *ibp = | |
415 | to_iport(qp->ibqp.device, qp->port_num); | |
416 | struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); | |
417 | struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); | |
418 | ||
419 | iowait_schedule(&priv->s_iowait, ppd->hfi1_wq, | |
420 | priv->s_sde ? | |
421 | priv->s_sde->cpu : | |
422 | cpumask_first(cpumask_of_node(dd->node))); | |
423 | } | |
424 | ||
14553ca1 MM |
425 | static void qp_pio_drain(struct rvt_qp *qp) |
426 | { | |
427 | struct hfi1_ibdev *dev; | |
428 | struct hfi1_qp_priv *priv = qp->priv; | |
429 | ||
430 | if (!priv->s_sendcontext) | |
431 | return; | |
432 | dev = to_idev(qp->ibqp.device); | |
433 | while (iowait_pio_pending(&priv->s_iowait)) { | |
434 | write_seqlock_irq(&dev->iowait_lock); | |
435 | hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 1); | |
436 | write_sequnlock_irq(&dev->iowait_lock); | |
437 | iowait_pio_drain(&priv->s_iowait); | |
438 | write_seqlock_irq(&dev->iowait_lock); | |
439 | hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 0); | |
440 | write_sequnlock_irq(&dev->iowait_lock); | |
441 | } | |
442 | } | |
443 | ||
46a80d62 MM |
444 | /** |
445 | * hfi1_schedule_send - schedule progress | |
446 | * @qp: the QP | |
447 | * | |
448 | * This schedules qp progress and caller should hold | |
449 | * the s_lock. | |
450 | */ | |
451 | void hfi1_schedule_send(struct rvt_qp *qp) | |
452 | { | |
453 | if (hfi1_send_ok(qp)) | |
454 | _hfi1_schedule_send(qp); | |
455 | } | |
456 | ||
77241056 MM |
457 | /** |
458 | * hfi1_get_credit - flush the send work queue of a QP | |
459 | * @qp: the qp who's send work queue to flush | |
460 | * @aeth: the Acknowledge Extended Transport Header | |
461 | * | |
462 | * The QP s_lock should be held. | |
463 | */ | |
895420dd | 464 | void hfi1_get_credit(struct rvt_qp *qp, u32 aeth) |
77241056 MM |
465 | { |
466 | u32 credit = (aeth >> HFI1_AETH_CREDIT_SHIFT) & HFI1_AETH_CREDIT_MASK; | |
467 | ||
468 | /* | |
469 | * If the credit is invalid, we can send | |
470 | * as many packets as we like. Otherwise, we have to | |
471 | * honor the credit field. | |
472 | */ | |
473 | if (credit == HFI1_AETH_CREDIT_INVAL) { | |
54d10c1e DD |
474 | if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) { |
475 | qp->s_flags |= RVT_S_UNLIMITED_CREDIT; | |
476 | if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) { | |
477 | qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT; | |
77241056 MM |
478 | hfi1_schedule_send(qp); |
479 | } | |
480 | } | |
54d10c1e | 481 | } else if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) { |
77241056 MM |
482 | /* Compute new LSN (i.e., MSN + credit) */ |
483 | credit = (aeth + credit_table[credit]) & HFI1_MSN_MASK; | |
484 | if (cmp_msn(credit, qp->s_lsn) > 0) { | |
485 | qp->s_lsn = credit; | |
54d10c1e DD |
486 | if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) { |
487 | qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT; | |
77241056 MM |
488 | hfi1_schedule_send(qp); |
489 | } | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
895420dd | 494 | void hfi1_qp_wakeup(struct rvt_qp *qp, u32 flag) |
77241056 MM |
495 | { |
496 | unsigned long flags; | |
497 | ||
498 | spin_lock_irqsave(&qp->s_lock, flags); | |
499 | if (qp->s_flags & flag) { | |
500 | qp->s_flags &= ~flag; | |
501 | trace_hfi1_qpwakeup(qp, flag); | |
502 | hfi1_schedule_send(qp); | |
503 | } | |
504 | spin_unlock_irqrestore(&qp->s_lock, flags); | |
505 | /* Notify hfi1_destroy_qp() if it is waiting. */ | |
506 | if (atomic_dec_and_test(&qp->refcount)) | |
507 | wake_up(&qp->wait); | |
508 | } | |
509 | ||
510 | static int iowait_sleep( | |
511 | struct sdma_engine *sde, | |
512 | struct iowait *wait, | |
513 | struct sdma_txreq *stx, | |
514 | unsigned seq) | |
515 | { | |
516 | struct verbs_txreq *tx = container_of(stx, struct verbs_txreq, txreq); | |
895420dd | 517 | struct rvt_qp *qp; |
4c6829c5 | 518 | struct hfi1_qp_priv *priv; |
77241056 MM |
519 | unsigned long flags; |
520 | int ret = 0; | |
521 | struct hfi1_ibdev *dev; | |
522 | ||
523 | qp = tx->qp; | |
4c6829c5 | 524 | priv = qp->priv; |
77241056 MM |
525 | |
526 | spin_lock_irqsave(&qp->s_lock, flags); | |
83693bd1 | 527 | if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { |
77241056 MM |
528 | /* |
529 | * If we couldn't queue the DMA request, save the info | |
530 | * and try again later rather than destroying the | |
531 | * buffer and undoing the side effects of the copy. | |
532 | */ | |
533 | /* Make a common routine? */ | |
534 | dev = &sde->dd->verbs_dev; | |
535 | list_add_tail(&stx->list, &wait->tx_head); | |
536 | write_seqlock(&dev->iowait_lock); | |
537 | if (sdma_progress(sde, seq, stx)) | |
538 | goto eagain; | |
4c6829c5 | 539 | if (list_empty(&priv->s_iowait.list)) { |
77241056 MM |
540 | struct hfi1_ibport *ibp = |
541 | to_iport(qp->ibqp.device, qp->port_num); | |
542 | ||
4eb06882 | 543 | ibp->rvp.n_dmawait++; |
54d10c1e | 544 | qp->s_flags |= RVT_S_WAIT_DMA_DESC; |
4c6829c5 | 545 | list_add_tail(&priv->s_iowait.list, &sde->dmawait); |
54d10c1e | 546 | trace_hfi1_qpsleep(qp, RVT_S_WAIT_DMA_DESC); |
77241056 MM |
547 | atomic_inc(&qp->refcount); |
548 | } | |
549 | write_sequnlock(&dev->iowait_lock); | |
54d10c1e | 550 | qp->s_flags &= ~RVT_S_BUSY; |
77241056 MM |
551 | spin_unlock_irqrestore(&qp->s_lock, flags); |
552 | ret = -EBUSY; | |
553 | } else { | |
554 | spin_unlock_irqrestore(&qp->s_lock, flags); | |
555 | hfi1_put_txreq(tx); | |
556 | } | |
557 | return ret; | |
558 | eagain: | |
559 | write_sequnlock(&dev->iowait_lock); | |
560 | spin_unlock_irqrestore(&qp->s_lock, flags); | |
561 | list_del_init(&stx->list); | |
562 | return -EAGAIN; | |
563 | } | |
564 | ||
565 | static void iowait_wakeup(struct iowait *wait, int reason) | |
566 | { | |
895420dd | 567 | struct rvt_qp *qp = iowait_to_qp(wait); |
77241056 MM |
568 | |
569 | WARN_ON(reason != SDMA_AVAIL_REASON); | |
54d10c1e | 570 | hfi1_qp_wakeup(qp, RVT_S_WAIT_DMA_DESC); |
77241056 MM |
571 | } |
572 | ||
a545f530 MM |
573 | static void iowait_sdma_drained(struct iowait *wait) |
574 | { | |
575 | struct rvt_qp *qp = iowait_to_qp(wait); | |
7049de65 | 576 | unsigned long flags; |
a545f530 MM |
577 | |
578 | /* | |
579 | * This happens when the send engine notes | |
580 | * a QP in the error state and cannot | |
581 | * do the flush work until that QP's | |
582 | * sdma work has finished. | |
583 | */ | |
7049de65 | 584 | spin_lock_irqsave(&qp->s_lock, flags); |
a545f530 MM |
585 | if (qp->s_flags & RVT_S_WAIT_DMA) { |
586 | qp->s_flags &= ~RVT_S_WAIT_DMA; | |
587 | hfi1_schedule_send(qp); | |
588 | } | |
7049de65 | 589 | spin_unlock_irqrestore(&qp->s_lock, flags); |
a545f530 MM |
590 | } |
591 | ||
77241056 MM |
592 | /** |
593 | * | |
594 | * qp_to_sdma_engine - map a qp to a send engine | |
595 | * @qp: the QP | |
596 | * @sc5: the 5 bit sc | |
597 | * | |
598 | * Return: | |
599 | * A send engine for the qp or NULL for SMI type qp. | |
600 | */ | |
895420dd | 601 | struct sdma_engine *qp_to_sdma_engine(struct rvt_qp *qp, u8 sc5) |
77241056 MM |
602 | { |
603 | struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); | |
604 | struct sdma_engine *sde; | |
605 | ||
606 | if (!(dd->flags & HFI1_HAS_SEND_DMA)) | |
607 | return NULL; | |
608 | switch (qp->ibqp.qp_type) { | |
77241056 MM |
609 | case IB_QPT_SMI: |
610 | return NULL; | |
611 | default: | |
612 | break; | |
613 | } | |
614 | sde = sdma_select_engine_sc(dd, qp->ibqp.qp_num >> dd->qos_shift, sc5); | |
615 | return sde; | |
616 | } | |
617 | ||
35f6befc JJ |
618 | /* |
619 | * qp_to_send_context - map a qp to a send context | |
620 | * @qp: the QP | |
621 | * @sc5: the 5 bit sc | |
622 | * | |
623 | * Return: | |
624 | * A send context for the qp | |
625 | */ | |
626 | struct send_context *qp_to_send_context(struct rvt_qp *qp, u8 sc5) | |
627 | { | |
628 | struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); | |
629 | ||
630 | switch (qp->ibqp.qp_type) { | |
631 | case IB_QPT_SMI: | |
632 | /* SMA packets to VL15 */ | |
633 | return dd->vld[15].sc; | |
634 | default: | |
635 | break; | |
636 | } | |
637 | ||
638 | return pio_select_send_context_sc(dd, qp->ibqp.qp_num >> dd->qos_shift, | |
639 | sc5); | |
640 | } | |
641 | ||
77241056 MM |
642 | struct qp_iter { |
643 | struct hfi1_ibdev *dev; | |
895420dd | 644 | struct rvt_qp *qp; |
77241056 MM |
645 | int specials; |
646 | int n; | |
647 | }; | |
648 | ||
649 | struct qp_iter *qp_iter_init(struct hfi1_ibdev *dev) | |
650 | { | |
651 | struct qp_iter *iter; | |
652 | ||
653 | iter = kzalloc(sizeof(*iter), GFP_KERNEL); | |
654 | if (!iter) | |
655 | return NULL; | |
656 | ||
657 | iter->dev = dev; | |
ec3f2c12 | 658 | iter->specials = dev->rdi.ibdev.phys_port_cnt * 2; |
77241056 MM |
659 | |
660 | return iter; | |
661 | } | |
662 | ||
663 | int qp_iter_next(struct qp_iter *iter) | |
664 | { | |
665 | struct hfi1_ibdev *dev = iter->dev; | |
666 | int n = iter->n; | |
667 | int ret = 1; | |
895420dd DD |
668 | struct rvt_qp *pqp = iter->qp; |
669 | struct rvt_qp *qp; | |
77241056 MM |
670 | |
671 | /* | |
672 | * The approach is to consider the special qps | |
673 | * as an additional table entries before the | |
674 | * real hash table. Since the qp code sets | |
675 | * the qp->next hash link to NULL, this works just fine. | |
676 | * | |
677 | * iter->specials is 2 * # ports | |
678 | * | |
679 | * n = 0..iter->specials is the special qp indices | |
680 | * | |
1c4b7d97 | 681 | * n = iter->specials..dev->rdi.qp_dev->qp_table_size+iter->specials are |
77241056 MM |
682 | * the potential hash bucket entries |
683 | * | |
684 | */ | |
1c4b7d97 | 685 | for (; n < dev->rdi.qp_dev->qp_table_size + iter->specials; n++) { |
77241056 MM |
686 | if (pqp) { |
687 | qp = rcu_dereference(pqp->next); | |
688 | } else { | |
689 | if (n < iter->specials) { | |
690 | struct hfi1_pportdata *ppd; | |
691 | struct hfi1_ibport *ibp; | |
692 | int pidx; | |
693 | ||
ec3f2c12 | 694 | pidx = n % dev->rdi.ibdev.phys_port_cnt; |
77241056 MM |
695 | ppd = &dd_from_dev(dev)->pport[pidx]; |
696 | ibp = &ppd->ibport_data; | |
697 | ||
698 | if (!(n & 1)) | |
4eb06882 | 699 | qp = rcu_dereference(ibp->rvp.qp[0]); |
77241056 | 700 | else |
4eb06882 | 701 | qp = rcu_dereference(ibp->rvp.qp[1]); |
77241056 MM |
702 | } else { |
703 | qp = rcu_dereference( | |
1c4b7d97 | 704 | dev->rdi.qp_dev->qp_table[ |
77241056 MM |
705 | (n - iter->specials)]); |
706 | } | |
707 | } | |
708 | pqp = qp; | |
709 | if (qp) { | |
710 | iter->qp = qp; | |
711 | iter->n = n; | |
712 | return 0; | |
713 | } | |
714 | } | |
715 | return ret; | |
716 | } | |
717 | ||
718 | static const char * const qp_type_str[] = { | |
719 | "SMI", "GSI", "RC", "UC", "UD", | |
720 | }; | |
721 | ||
895420dd | 722 | static int qp_idle(struct rvt_qp *qp) |
77241056 MM |
723 | { |
724 | return | |
725 | qp->s_last == qp->s_acked && | |
726 | qp->s_acked == qp->s_cur && | |
727 | qp->s_cur == qp->s_tail && | |
728 | qp->s_tail == qp->s_head; | |
729 | } | |
730 | ||
731 | void qp_iter_print(struct seq_file *s, struct qp_iter *iter) | |
732 | { | |
895420dd DD |
733 | struct rvt_swqe *wqe; |
734 | struct rvt_qp *qp = iter->qp; | |
4c6829c5 | 735 | struct hfi1_qp_priv *priv = qp->priv; |
77241056 | 736 | struct sdma_engine *sde; |
721d0427 | 737 | struct send_context *send_context; |
77241056 | 738 | |
4c6829c5 | 739 | sde = qp_to_sdma_engine(qp, priv->s_sc); |
83693bd1 | 740 | wqe = rvt_get_swqe_ptr(qp, qp->s_last); |
721d0427 | 741 | send_context = qp_to_send_context(qp, priv->s_sc); |
77241056 | 742 | seq_printf(s, |
ef6d8c4e | 743 | "N %d %s QP %x R %u %s %u %u %u f=%x %u %u %u %u %u %u PSN %x %x %x %x %x (%u %u %u %u %u %u %u) RQP %x LID %x SL %u MTU %u %u %u %u SDE %p,%u SC %p,%u SCQ %u %u PID %d\n", |
77241056 MM |
744 | iter->n, |
745 | qp_idle(qp) ? "I" : "B", | |
746 | qp->ibqp.qp_num, | |
747 | atomic_read(&qp->refcount), | |
748 | qp_type_str[qp->ibqp.qp_type], | |
749 | qp->state, | |
750 | wqe ? wqe->wr.opcode : 0, | |
751 | qp->s_hdrwords, | |
752 | qp->s_flags, | |
14553ca1 MM |
753 | iowait_sdma_pending(&priv->s_iowait), |
754 | iowait_pio_pending(&priv->s_iowait), | |
4c6829c5 | 755 | !list_empty(&priv->s_iowait.list), |
77241056 MM |
756 | qp->timeout, |
757 | wqe ? wqe->ssn : 0, | |
758 | qp->s_lsn, | |
759 | qp->s_last_psn, | |
760 | qp->s_psn, qp->s_next_psn, | |
761 | qp->s_sending_psn, qp->s_sending_hpsn, | |
762 | qp->s_last, qp->s_acked, qp->s_cur, | |
763 | qp->s_tail, qp->s_head, qp->s_size, | |
3585254d | 764 | qp->s_avail, |
77241056 MM |
765 | qp->remote_qpn, |
766 | qp->remote_ah_attr.dlid, | |
767 | qp->remote_ah_attr.sl, | |
768 | qp->pmtu, | |
20658661 | 769 | qp->s_retry, |
77241056 | 770 | qp->s_retry_cnt, |
77241056 MM |
771 | qp->s_rnr_retry_cnt, |
772 | sde, | |
721d0427 | 773 | sde ? sde->this_idx : 0, |
77e7639f | 774 | send_context, |
0358a440 VM |
775 | send_context ? send_context->sw_index : 0, |
776 | ibcq_to_rvtcq(qp->ibqp.send_cq)->queue->head, | |
ef086c0d MM |
777 | ibcq_to_rvtcq(qp->ibqp.send_cq)->queue->tail, |
778 | qp->pid); | |
77241056 MM |
779 | } |
780 | ||
895420dd | 781 | void qp_comm_est(struct rvt_qp *qp) |
77241056 | 782 | { |
54d10c1e | 783 | qp->r_flags |= RVT_R_COMM_EST; |
77241056 MM |
784 | if (qp->ibqp.event_handler) { |
785 | struct ib_event ev; | |
786 | ||
787 | ev.device = qp->ibqp.device; | |
788 | ev.element.qp = &qp->ibqp; | |
789 | ev.event = IB_EVENT_COMM_EST; | |
790 | qp->ibqp.event_handler(&ev, qp->ibqp.qp_context); | |
791 | } | |
792 | } | |
c2f3ffb0 | 793 | |
a2c2d608 DD |
794 | void *qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp, |
795 | gfp_t gfp) | |
796 | { | |
797 | struct hfi1_qp_priv *priv; | |
798 | ||
377f111e | 799 | priv = kzalloc_node(sizeof(*priv), gfp, rdi->dparms.node); |
a2c2d608 DD |
800 | if (!priv) |
801 | return ERR_PTR(-ENOMEM); | |
802 | ||
803 | priv->owner = qp; | |
804 | ||
a9b6b3bc DC |
805 | priv->s_ahg = kzalloc_node(sizeof(*priv->s_ahg), gfp, |
806 | rdi->dparms.node); | |
807 | if (!priv->s_ahg) { | |
a2c2d608 DD |
808 | kfree(priv); |
809 | return ERR_PTR(-ENOMEM); | |
810 | } | |
3c9d149b | 811 | setup_timer(&priv->s_rnr_timer, hfi1_rc_rnr_retry, (unsigned long)qp); |
08279d5c | 812 | qp->s_timer.function = hfi1_rc_timeout; |
a2c2d608 DD |
813 | return priv; |
814 | } | |
815 | ||
816 | void qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp) | |
817 | { | |
818 | struct hfi1_qp_priv *priv = qp->priv; | |
819 | ||
a9b6b3bc | 820 | kfree(priv->s_ahg); |
a2c2d608 DD |
821 | kfree(priv); |
822 | } | |
823 | ||
824 | unsigned free_all_qps(struct rvt_dev_info *rdi) | |
825 | { | |
826 | struct hfi1_ibdev *verbs_dev = container_of(rdi, | |
827 | struct hfi1_ibdev, | |
828 | rdi); | |
829 | struct hfi1_devdata *dd = container_of(verbs_dev, | |
830 | struct hfi1_devdata, | |
831 | verbs_dev); | |
832 | int n; | |
833 | unsigned qp_inuse = 0; | |
834 | ||
835 | for (n = 0; n < dd->num_pports; n++) { | |
836 | struct hfi1_ibport *ibp = &dd->pport[n].ibport_data; | |
837 | ||
a2c2d608 DD |
838 | rcu_read_lock(); |
839 | if (rcu_dereference(ibp->rvp.qp[0])) | |
840 | qp_inuse++; | |
841 | if (rcu_dereference(ibp->rvp.qp[1])) | |
842 | qp_inuse++; | |
843 | rcu_read_unlock(); | |
844 | } | |
845 | ||
846 | return qp_inuse; | |
847 | } | |
848 | ||
ec4274f1 DD |
849 | void flush_qp_waiters(struct rvt_qp *qp) |
850 | { | |
851 | flush_iowait(qp); | |
08279d5c | 852 | hfi1_stop_rc_timers(qp); |
ec4274f1 DD |
853 | } |
854 | ||
855 | void stop_send_queue(struct rvt_qp *qp) | |
856 | { | |
857 | struct hfi1_qp_priv *priv = qp->priv; | |
858 | ||
859 | cancel_work_sync(&priv->s_iowait.iowork); | |
08279d5c | 860 | hfi1_del_timers_sync(qp); |
ec4274f1 DD |
861 | } |
862 | ||
863 | void quiesce_qp(struct rvt_qp *qp) | |
864 | { | |
865 | struct hfi1_qp_priv *priv = qp->priv; | |
866 | ||
867 | iowait_sdma_drain(&priv->s_iowait); | |
14553ca1 | 868 | qp_pio_drain(qp); |
ec4274f1 DD |
869 | flush_tx_list(qp); |
870 | } | |
871 | ||
a2c2d608 DD |
872 | void notify_qp_reset(struct rvt_qp *qp) |
873 | { | |
874 | struct hfi1_qp_priv *priv = qp->priv; | |
875 | ||
876 | iowait_init( | |
877 | &priv->s_iowait, | |
878 | 1, | |
83693bd1 | 879 | _hfi1_do_send, |
a2c2d608 | 880 | iowait_sleep, |
a545f530 MM |
881 | iowait_wakeup, |
882 | iowait_sdma_drained); | |
a2c2d608 DD |
883 | priv->r_adefered = 0; |
884 | clear_ahg(qp); | |
885 | } | |
886 | ||
c2f3ffb0 MM |
887 | /* |
888 | * Switch to alternate path. | |
889 | * The QP s_lock should be held and interrupts disabled. | |
890 | */ | |
895420dd | 891 | void hfi1_migrate_qp(struct rvt_qp *qp) |
c2f3ffb0 | 892 | { |
4c6829c5 | 893 | struct hfi1_qp_priv *priv = qp->priv; |
c2f3ffb0 MM |
894 | struct ib_event ev; |
895 | ||
896 | qp->s_mig_state = IB_MIG_MIGRATED; | |
897 | qp->remote_ah_attr = qp->alt_ah_attr; | |
898 | qp->port_num = qp->alt_ah_attr.port_num; | |
899 | qp->s_pkey_index = qp->s_alt_pkey_index; | |
54d10c1e | 900 | qp->s_flags |= RVT_S_AHG_CLEAR; |
4c6829c5 DD |
901 | priv->s_sc = ah_to_sc(qp->ibqp.device, &qp->remote_ah_attr); |
902 | priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc); | |
c2f3ffb0 MM |
903 | |
904 | ev.device = qp->ibqp.device; | |
905 | ev.element.qp = &qp->ibqp; | |
906 | ev.event = IB_EVENT_PATH_MIG; | |
907 | qp->ibqp.event_handler(&ev, qp->ibqp.qp_context); | |
908 | } | |
ec4274f1 DD |
909 | |
910 | int mtu_to_path_mtu(u32 mtu) | |
911 | { | |
912 | return mtu_to_enum(mtu, OPA_MTU_8192); | |
913 | } | |
914 | ||
915 | u32 mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu) | |
916 | { | |
917 | u32 mtu; | |
918 | struct hfi1_ibdev *verbs_dev = container_of(rdi, | |
919 | struct hfi1_ibdev, | |
920 | rdi); | |
921 | struct hfi1_devdata *dd = container_of(verbs_dev, | |
922 | struct hfi1_devdata, | |
923 | verbs_dev); | |
924 | struct hfi1_ibport *ibp; | |
925 | u8 sc, vl; | |
926 | ||
927 | ibp = &dd->pport[qp->port_num - 1].ibport_data; | |
928 | sc = ibp->sl_to_sc[qp->remote_ah_attr.sl]; | |
929 | vl = sc_to_vlt(dd, sc); | |
930 | ||
931 | mtu = verbs_mtu_enum_to_int(qp->ibqp.device, pmtu); | |
932 | if (vl < PER_VL_SEND_CONTEXTS) | |
933 | mtu = min_t(u32, mtu, dd->vld[vl].mtu); | |
934 | return mtu; | |
935 | } | |
936 | ||
937 | int get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp, | |
938 | struct ib_qp_attr *attr) | |
939 | { | |
940 | int mtu, pidx = qp->port_num - 1; | |
941 | struct hfi1_ibdev *verbs_dev = container_of(rdi, | |
942 | struct hfi1_ibdev, | |
943 | rdi); | |
944 | struct hfi1_devdata *dd = container_of(verbs_dev, | |
945 | struct hfi1_devdata, | |
946 | verbs_dev); | |
947 | mtu = verbs_mtu_enum_to_int(qp->ibqp.device, attr->path_mtu); | |
948 | if (mtu == -1) | |
949 | return -1; /* values less than 0 are error */ | |
950 | ||
951 | if (mtu > dd->pport[pidx].ibmtu) | |
952 | return mtu_to_enum(dd->pport[pidx].ibmtu, IB_MTU_2048); | |
953 | else | |
954 | return attr->path_mtu; | |
955 | } | |
956 | ||
957 | void notify_error_qp(struct rvt_qp *qp) | |
958 | { | |
959 | struct hfi1_ibdev *dev = to_idev(qp->ibqp.device); | |
960 | struct hfi1_qp_priv *priv = qp->priv; | |
961 | ||
962 | write_seqlock(&dev->iowait_lock); | |
963 | if (!list_empty(&priv->s_iowait.list) && !(qp->s_flags & RVT_S_BUSY)) { | |
964 | qp->s_flags &= ~RVT_S_ANY_WAIT_IO; | |
965 | list_del_init(&priv->s_iowait.list); | |
966 | if (atomic_dec_and_test(&qp->refcount)) | |
967 | wake_up(&qp->wait); | |
968 | } | |
969 | write_sequnlock(&dev->iowait_lock); | |
970 | ||
971 | if (!(qp->s_flags & RVT_S_BUSY)) { | |
972 | qp->s_hdrwords = 0; | |
973 | if (qp->s_rdma_mr) { | |
974 | rvt_put_mr(qp->s_rdma_mr); | |
975 | qp->s_rdma_mr = NULL; | |
976 | } | |
977 | flush_tx_list(qp); | |
978 | } | |
979 | } | |
980 | ||
0ec79e87 KW |
981 | /** |
982 | * hfi1_error_port_qps - put a port's RC/UC qps into error state | |
983 | * @ibp: the ibport. | |
984 | * @sl: the service level. | |
985 | * | |
986 | * This function places all RC/UC qps with a given service level into error | |
987 | * state. It is generally called to force upper lay apps to abandon stale qps | |
988 | * after an sl->sc mapping change. | |
989 | */ | |
990 | void hfi1_error_port_qps(struct hfi1_ibport *ibp, u8 sl) | |
991 | { | |
992 | struct rvt_qp *qp = NULL; | |
993 | struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); | |
994 | struct hfi1_ibdev *dev = &ppd->dd->verbs_dev; | |
995 | int n; | |
996 | int lastwqe; | |
997 | struct ib_event ev; | |
998 | ||
999 | rcu_read_lock(); | |
1000 | ||
1001 | /* Deal only with RC/UC qps that use the given SL. */ | |
1002 | for (n = 0; n < dev->rdi.qp_dev->qp_table_size; n++) { | |
1003 | for (qp = rcu_dereference(dev->rdi.qp_dev->qp_table[n]); qp; | |
1004 | qp = rcu_dereference(qp->next)) { | |
1005 | if (qp->port_num == ppd->port && | |
1006 | (qp->ibqp.qp_type == IB_QPT_UC || | |
1007 | qp->ibqp.qp_type == IB_QPT_RC) && | |
1008 | qp->remote_ah_attr.sl == sl && | |
1009 | (ib_rvt_state_ops[qp->state] & | |
1010 | RVT_POST_SEND_OK)) { | |
1011 | spin_lock_irq(&qp->r_lock); | |
1012 | spin_lock(&qp->s_hlock); | |
1013 | spin_lock(&qp->s_lock); | |
1014 | lastwqe = rvt_error_qp(qp, | |
1015 | IB_WC_WR_FLUSH_ERR); | |
1016 | spin_unlock(&qp->s_lock); | |
1017 | spin_unlock(&qp->s_hlock); | |
1018 | spin_unlock_irq(&qp->r_lock); | |
1019 | if (lastwqe) { | |
1020 | ev.device = qp->ibqp.device; | |
1021 | ev.element.qp = &qp->ibqp; | |
1022 | ev.event = | |
1023 | IB_EVENT_QP_LAST_WQE_REACHED; | |
1024 | qp->ibqp.event_handler(&ev, | |
1025 | qp->ibqp.qp_context); | |
1026 | } | |
1027 | } | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | rcu_read_unlock(); | |
1032 | } |