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1 | /******************************************************************************* |
2 | * | |
3 | * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenFabrics.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | * | |
33 | *******************************************************************************/ | |
34 | ||
35 | #ifndef I40IW_D_H | |
36 | #define I40IW_D_H | |
37 | ||
38 | #define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024) | |
39 | #define I40IW_VF_DB_ADDR_OFFSET (64 * 1024) | |
40 | ||
41 | #define I40IW_PUSH_OFFSET (4 * 1024 * 1024) | |
42 | #define I40IW_PF_FIRST_PUSH_PAGE_INDEX 16 | |
43 | #define I40IW_VF_PUSH_OFFSET ((8 + 64) * 1024) | |
44 | #define I40IW_VF_FIRST_PUSH_PAGE_INDEX 2 | |
45 | ||
46 | #define I40IW_PE_DB_SIZE_4M 1 | |
47 | #define I40IW_PE_DB_SIZE_8M 2 | |
48 | ||
49 | #define I40IW_DDP_VER 1 | |
50 | #define I40IW_RDMAP_VER 1 | |
51 | ||
52 | #define I40IW_RDMA_MODE_RDMAC 0 | |
53 | #define I40IW_RDMA_MODE_IETF 1 | |
54 | ||
55 | #define I40IW_QP_STATE_INVALID 0 | |
56 | #define I40IW_QP_STATE_IDLE 1 | |
57 | #define I40IW_QP_STATE_RTS 2 | |
58 | #define I40IW_QP_STATE_CLOSING 3 | |
59 | #define I40IW_QP_STATE_RESERVED 4 | |
60 | #define I40IW_QP_STATE_TERMINATE 5 | |
61 | #define I40IW_QP_STATE_ERROR 6 | |
62 | ||
63 | #define I40IW_STAG_STATE_INVALID 0 | |
64 | #define I40IW_STAG_STATE_VALID 1 | |
65 | ||
66 | #define I40IW_STAG_TYPE_SHARED 0 | |
67 | #define I40IW_STAG_TYPE_NONSHARED 1 | |
68 | ||
69 | #define I40IW_MAX_USER_PRIORITY 8 | |
70 | ||
71 | #define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits) | |
72 | #define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits) | |
73 | #define LS_32_1(val, bits) (u32)(val << bits) | |
74 | #define RS_32_1(val, bits) (u32)(val >> bits) | |
75 | #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) | |
76 | ||
77 | #define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK)) | |
78 | ||
79 | #define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT) | |
80 | #define LS_32(val, field) ((val << field ## _SHIFT) & (field ## _MASK)) | |
81 | #define RS_32(val, field) ((val & field ## _MASK) >> field ## _SHIFT) | |
82 | ||
83 | #define TERM_DDP_LEN_TAGGED 14 | |
84 | #define TERM_DDP_LEN_UNTAGGED 18 | |
85 | #define TERM_RDMA_LEN 28 | |
86 | #define RDMA_OPCODE_MASK 0x0f | |
87 | #define RDMA_READ_REQ_OPCODE 1 | |
88 | #define Q2_BAD_FRAME_OFFSET 72 | |
89 | #define CQE_MAJOR_DRV 0x8000 | |
90 | ||
91 | #define I40IW_TERM_SENT 0x01 | |
92 | #define I40IW_TERM_RCVD 0x02 | |
93 | #define I40IW_TERM_DONE 0x04 | |
94 | #define I40IW_MAC_HLEN 14 | |
95 | ||
96 | #define I40IW_INVALID_WQE_INDEX 0xffffffff | |
97 | ||
98 | #define I40IW_CQP_WAIT_POLL_REGS 1 | |
99 | #define I40IW_CQP_WAIT_POLL_CQ 2 | |
100 | #define I40IW_CQP_WAIT_EVENT 3 | |
101 | ||
102 | #define I40IW_CQP_INIT_WQE(wqe) memset(wqe, 0, 64) | |
103 | ||
104 | #define I40IW_GET_CURRENT_CQ_ELEMENT(_cq) \ | |
105 | ( \ | |
106 | &((_cq)->cq_base[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \ | |
107 | ) | |
108 | #define I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(_cq) \ | |
109 | ( \ | |
110 | &(((struct i40iw_extended_cqe *) \ | |
111 | ((_cq)->cq_base))[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \ | |
112 | ) | |
113 | ||
114 | #define I40IW_GET_CURRENT_AEQ_ELEMENT(_aeq) \ | |
115 | ( \ | |
116 | &_aeq->aeqe_base[I40IW_RING_GETCURRENT_TAIL(_aeq->aeq_ring)] \ | |
117 | ) | |
118 | ||
119 | #define I40IW_GET_CURRENT_CEQ_ELEMENT(_ceq) \ | |
120 | ( \ | |
121 | &_ceq->ceqe_base[I40IW_RING_GETCURRENT_TAIL(_ceq->ceq_ring)] \ | |
122 | ) | |
123 | ||
124 | #define I40IW_AE_SOURCE_RQ 0x1 | |
125 | #define I40IW_AE_SOURCE_RQ_0011 0x3 | |
126 | ||
127 | #define I40IW_AE_SOURCE_CQ 0x2 | |
128 | #define I40IW_AE_SOURCE_CQ_0110 0x6 | |
129 | #define I40IW_AE_SOURCE_CQ_1010 0xA | |
130 | #define I40IW_AE_SOURCE_CQ_1110 0xE | |
131 | ||
132 | #define I40IW_AE_SOURCE_SQ 0x5 | |
133 | #define I40IW_AE_SOURCE_SQ_0111 0x7 | |
134 | ||
135 | #define I40IW_AE_SOURCE_IN_RR_WR 0x9 | |
136 | #define I40IW_AE_SOURCE_IN_RR_WR_1011 0xB | |
137 | #define I40IW_AE_SOURCE_OUT_RR 0xD | |
138 | #define I40IW_AE_SOURCE_OUT_RR_1111 0xF | |
139 | ||
140 | #define I40IW_TCP_STATE_NON_EXISTENT 0 | |
141 | #define I40IW_TCP_STATE_CLOSED 1 | |
142 | #define I40IW_TCP_STATE_LISTEN 2 | |
143 | #define I40IW_STATE_SYN_SEND 3 | |
144 | #define I40IW_TCP_STATE_SYN_RECEIVED 4 | |
145 | #define I40IW_TCP_STATE_ESTABLISHED 5 | |
146 | #define I40IW_TCP_STATE_CLOSE_WAIT 6 | |
147 | #define I40IW_TCP_STATE_FIN_WAIT_1 7 | |
148 | #define I40IW_TCP_STATE_CLOSING 8 | |
149 | #define I40IW_TCP_STATE_LAST_ACK 9 | |
150 | #define I40IW_TCP_STATE_FIN_WAIT_2 10 | |
151 | #define I40IW_TCP_STATE_TIME_WAIT 11 | |
152 | #define I40IW_TCP_STATE_RESERVED_1 12 | |
153 | #define I40IW_TCP_STATE_RESERVED_2 13 | |
154 | #define I40IW_TCP_STATE_RESERVED_3 14 | |
155 | #define I40IW_TCP_STATE_RESERVED_4 15 | |
156 | ||
157 | /* ILQ CQP hash table fields */ | |
158 | #define I40IW_CQPSQ_QHASH_VLANID_SHIFT 32 | |
159 | #define I40IW_CQPSQ_QHASH_VLANID_MASK \ | |
160 | ((u64)0xfff << I40IW_CQPSQ_QHASH_VLANID_SHIFT) | |
161 | ||
162 | #define I40IW_CQPSQ_QHASH_QPN_SHIFT 32 | |
163 | #define I40IW_CQPSQ_QHASH_QPN_MASK \ | |
164 | ((u64)0x3ffff << I40IW_CQPSQ_QHASH_QPN_SHIFT) | |
165 | ||
166 | #define I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT 0 | |
167 | #define I40IW_CQPSQ_QHASH_QS_HANDLE_MASK ((u64)0x3ff << I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT) | |
168 | ||
169 | #define I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT 16 | |
170 | #define I40IW_CQPSQ_QHASH_SRC_PORT_MASK \ | |
171 | ((u64)0xffff << I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT) | |
172 | ||
173 | #define I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT 0 | |
174 | #define I40IW_CQPSQ_QHASH_DEST_PORT_MASK \ | |
175 | ((u64)0xffff << I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT) | |
176 | ||
177 | #define I40IW_CQPSQ_QHASH_ADDR0_SHIFT 32 | |
178 | #define I40IW_CQPSQ_QHASH_ADDR0_MASK \ | |
179 | ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR0_SHIFT) | |
180 | ||
181 | #define I40IW_CQPSQ_QHASH_ADDR1_SHIFT 0 | |
182 | #define I40IW_CQPSQ_QHASH_ADDR1_MASK \ | |
183 | ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR1_SHIFT) | |
184 | ||
185 | #define I40IW_CQPSQ_QHASH_ADDR2_SHIFT 32 | |
186 | #define I40IW_CQPSQ_QHASH_ADDR2_MASK \ | |
187 | ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR2_SHIFT) | |
188 | ||
189 | #define I40IW_CQPSQ_QHASH_ADDR3_SHIFT 0 | |
190 | #define I40IW_CQPSQ_QHASH_ADDR3_MASK \ | |
191 | ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR3_SHIFT) | |
192 | ||
193 | #define I40IW_CQPSQ_QHASH_WQEVALID_SHIFT 63 | |
194 | #define I40IW_CQPSQ_QHASH_WQEVALID_MASK \ | |
195 | ((u64)0x1 << I40IW_CQPSQ_QHASH_WQEVALID_SHIFT) | |
196 | #define I40IW_CQPSQ_QHASH_OPCODE_SHIFT 32 | |
197 | #define I40IW_CQPSQ_QHASH_OPCODE_MASK \ | |
198 | ((u64)0x3f << I40IW_CQPSQ_QHASH_OPCODE_SHIFT) | |
199 | ||
200 | #define I40IW_CQPSQ_QHASH_MANAGE_SHIFT 61 | |
201 | #define I40IW_CQPSQ_QHASH_MANAGE_MASK \ | |
202 | ((u64)0x3 << I40IW_CQPSQ_QHASH_MANAGE_SHIFT) | |
203 | ||
204 | #define I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT 60 | |
205 | #define I40IW_CQPSQ_QHASH_IPV4VALID_MASK \ | |
206 | ((u64)0x1 << I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT) | |
207 | ||
208 | #define I40IW_CQPSQ_QHASH_VLANVALID_SHIFT 59 | |
209 | #define I40IW_CQPSQ_QHASH_VLANVALID_MASK \ | |
210 | ((u64)0x1 << I40IW_CQPSQ_QHASH_VLANVALID_SHIFT) | |
211 | ||
212 | #define I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT 42 | |
213 | #define I40IW_CQPSQ_QHASH_ENTRYTYPE_MASK \ | |
214 | ((u64)0x7 << I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT) | |
215 | /* CQP Host Context */ | |
216 | #define I40IW_CQPHC_EN_DC_TCP_SHIFT 0 | |
217 | #define I40IW_CQPHC_EN_DC_TCP_MASK (1UL << I40IW_CQPHC_EN_DC_TCP_SHIFT) | |
218 | ||
219 | #define I40IW_CQPHC_SQSIZE_SHIFT 8 | |
220 | #define I40IW_CQPHC_SQSIZE_MASK (0xfUL << I40IW_CQPHC_SQSIZE_SHIFT) | |
221 | ||
222 | #define I40IW_CQPHC_DISABLE_PFPDUS_SHIFT 1 | |
223 | #define I40IW_CQPHC_DISABLE_PFPDUS_MASK (0x1UL << I40IW_CQPHC_DISABLE_PFPDUS_SHIFT) | |
224 | ||
225 | #define I40IW_CQPHC_ENABLED_VFS_SHIFT 32 | |
226 | #define I40IW_CQPHC_ENABLED_VFS_MASK (0x3fULL << I40IW_CQPHC_ENABLED_VFS_SHIFT) | |
227 | ||
228 | #define I40IW_CQPHC_HMC_PROFILE_SHIFT 0 | |
229 | #define I40IW_CQPHC_HMC_PROFILE_MASK (0x7ULL << I40IW_CQPHC_HMC_PROFILE_SHIFT) | |
230 | ||
231 | #define I40IW_CQPHC_SVER_SHIFT 24 | |
232 | #define I40IW_CQPHC_SVER_MASK (0xffUL << I40IW_CQPHC_SVER_SHIFT) | |
233 | ||
234 | #define I40IW_CQPHC_SQBASE_SHIFT 9 | |
235 | #define I40IW_CQPHC_SQBASE_MASK \ | |
236 | (0xfffffffffffffeULL << I40IW_CQPHC_SQBASE_SHIFT) | |
237 | ||
238 | #define I40IW_CQPHC_QPCTX_SHIFT 0 | |
239 | #define I40IW_CQPHC_QPCTX_MASK \ | |
240 | (0xffffffffffffffffULL << I40IW_CQPHC_QPCTX_SHIFT) | |
241 | #define I40IW_CQPHC_SVER 1 | |
242 | ||
243 | #define I40IW_CQP_SW_SQSIZE_4 4 | |
244 | #define I40IW_CQP_SW_SQSIZE_2048 2048 | |
245 | ||
246 | /* iWARP QP Doorbell shadow area */ | |
247 | #define I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT 0 | |
248 | #define I40IW_QP_DBSA_HW_SQ_TAIL_MASK \ | |
249 | (0x3fffUL << I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT) | |
250 | ||
251 | /* Completion Queue Doorbell shadow area */ | |
252 | #define I40IW_CQ_DBSA_CQEIDX_SHIFT 0 | |
253 | #define I40IW_CQ_DBSA_CQEIDX_MASK (0xfffffUL << I40IW_CQ_DBSA_CQEIDX_SHIFT) | |
254 | ||
255 | #define I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT 0 | |
256 | #define I40IW_CQ_DBSA_SW_CQ_SELECT_MASK \ | |
257 | (0x3fffUL << I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT) | |
258 | ||
259 | #define I40IW_CQ_DBSA_ARM_NEXT_SHIFT 14 | |
260 | #define I40IW_CQ_DBSA_ARM_NEXT_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SHIFT) | |
261 | ||
262 | #define I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT 15 | |
263 | #define I40IW_CQ_DBSA_ARM_NEXT_SE_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT) | |
264 | ||
265 | #define I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT 16 | |
266 | #define I40IW_CQ_DBSA_ARM_SEQ_NUM_MASK \ | |
267 | (0x3UL << I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT) | |
268 | ||
269 | /* CQP and iWARP Completion Queue */ | |
270 | #define I40IW_CQ_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
271 | #define I40IW_CQ_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK | |
272 | ||
273 | #define I40IW_CCQ_OPRETVAL_SHIFT 0 | |
274 | #define I40IW_CCQ_OPRETVAL_MASK (0xffffffffUL << I40IW_CCQ_OPRETVAL_SHIFT) | |
275 | ||
276 | #define I40IW_CQ_MINERR_SHIFT 0 | |
277 | #define I40IW_CQ_MINERR_MASK (0xffffUL << I40IW_CQ_MINERR_SHIFT) | |
278 | ||
279 | #define I40IW_CQ_MAJERR_SHIFT 16 | |
280 | #define I40IW_CQ_MAJERR_MASK (0xffffUL << I40IW_CQ_MAJERR_SHIFT) | |
281 | ||
282 | #define I40IW_CQ_WQEIDX_SHIFT 32 | |
283 | #define I40IW_CQ_WQEIDX_MASK (0x3fffULL << I40IW_CQ_WQEIDX_SHIFT) | |
284 | ||
285 | #define I40IW_CQ_ERROR_SHIFT 55 | |
286 | #define I40IW_CQ_ERROR_MASK (1ULL << I40IW_CQ_ERROR_SHIFT) | |
287 | ||
288 | #define I40IW_CQ_SQ_SHIFT 62 | |
289 | #define I40IW_CQ_SQ_MASK (1ULL << I40IW_CQ_SQ_SHIFT) | |
290 | ||
291 | #define I40IW_CQ_VALID_SHIFT 63 | |
292 | #define I40IW_CQ_VALID_MASK (1ULL << I40IW_CQ_VALID_SHIFT) | |
293 | ||
294 | #define I40IWCQ_PAYLDLEN_SHIFT 0 | |
295 | #define I40IWCQ_PAYLDLEN_MASK (0xffffffffUL << I40IWCQ_PAYLDLEN_SHIFT) | |
296 | ||
297 | #define I40IWCQ_TCPSEQNUM_SHIFT 32 | |
298 | #define I40IWCQ_TCPSEQNUM_MASK (0xffffffffULL << I40IWCQ_TCPSEQNUM_SHIFT) | |
299 | ||
300 | #define I40IWCQ_INVSTAG_SHIFT 0 | |
301 | #define I40IWCQ_INVSTAG_MASK (0xffffffffUL << I40IWCQ_INVSTAG_SHIFT) | |
302 | ||
303 | #define I40IWCQ_QPID_SHIFT 32 | |
304 | #define I40IWCQ_QPID_MASK (0x3ffffULL << I40IWCQ_QPID_SHIFT) | |
305 | ||
306 | #define I40IWCQ_PSHDROP_SHIFT 51 | |
307 | #define I40IWCQ_PSHDROP_MASK (1ULL << I40IWCQ_PSHDROP_SHIFT) | |
308 | ||
309 | #define I40IWCQ_SRQ_SHIFT 52 | |
310 | #define I40IWCQ_SRQ_MASK (1ULL << I40IWCQ_SRQ_SHIFT) | |
311 | ||
312 | #define I40IWCQ_STAG_SHIFT 53 | |
313 | #define I40IWCQ_STAG_MASK (1ULL << I40IWCQ_STAG_SHIFT) | |
314 | ||
315 | #define I40IWCQ_SOEVENT_SHIFT 54 | |
316 | #define I40IWCQ_SOEVENT_MASK (1ULL << I40IWCQ_SOEVENT_SHIFT) | |
317 | ||
318 | #define I40IWCQ_OP_SHIFT 56 | |
319 | #define I40IWCQ_OP_MASK (0x3fULL << I40IWCQ_OP_SHIFT) | |
320 | ||
321 | /* CEQE format */ | |
322 | #define I40IW_CEQE_CQCTX_SHIFT 0 | |
323 | #define I40IW_CEQE_CQCTX_MASK \ | |
324 | (0x7fffffffffffffffULL << I40IW_CEQE_CQCTX_SHIFT) | |
325 | ||
326 | #define I40IW_CEQE_VALID_SHIFT 63 | |
327 | #define I40IW_CEQE_VALID_MASK (1ULL << I40IW_CEQE_VALID_SHIFT) | |
328 | ||
329 | /* AEQE format */ | |
330 | #define I40IW_AEQE_COMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
331 | #define I40IW_AEQE_COMPCTX_MASK I40IW_CQPHC_QPCTX_MASK | |
332 | ||
333 | #define I40IW_AEQE_QPCQID_SHIFT 0 | |
334 | #define I40IW_AEQE_QPCQID_MASK (0x3ffffUL << I40IW_AEQE_QPCQID_SHIFT) | |
335 | ||
336 | #define I40IW_AEQE_WQDESCIDX_SHIFT 18 | |
337 | #define I40IW_AEQE_WQDESCIDX_MASK (0x3fffULL << I40IW_AEQE_WQDESCIDX_SHIFT) | |
338 | ||
339 | #define I40IW_AEQE_OVERFLOW_SHIFT 33 | |
340 | #define I40IW_AEQE_OVERFLOW_MASK (1ULL << I40IW_AEQE_OVERFLOW_SHIFT) | |
341 | ||
342 | #define I40IW_AEQE_AECODE_SHIFT 34 | |
343 | #define I40IW_AEQE_AECODE_MASK (0xffffULL << I40IW_AEQE_AECODE_SHIFT) | |
344 | ||
345 | #define I40IW_AEQE_AESRC_SHIFT 50 | |
346 | #define I40IW_AEQE_AESRC_MASK (0xfULL << I40IW_AEQE_AESRC_SHIFT) | |
347 | ||
348 | #define I40IW_AEQE_IWSTATE_SHIFT 54 | |
349 | #define I40IW_AEQE_IWSTATE_MASK (0x7ULL << I40IW_AEQE_IWSTATE_SHIFT) | |
350 | ||
351 | #define I40IW_AEQE_TCPSTATE_SHIFT 57 | |
352 | #define I40IW_AEQE_TCPSTATE_MASK (0xfULL << I40IW_AEQE_TCPSTATE_SHIFT) | |
353 | ||
354 | #define I40IW_AEQE_Q2DATA_SHIFT 61 | |
355 | #define I40IW_AEQE_Q2DATA_MASK (0x3ULL << I40IW_AEQE_Q2DATA_SHIFT) | |
356 | ||
357 | #define I40IW_AEQE_VALID_SHIFT 63 | |
358 | #define I40IW_AEQE_VALID_MASK (1ULL << I40IW_AEQE_VALID_SHIFT) | |
359 | ||
360 | /* CQP SQ WQES */ | |
361 | #define I40IW_QP_TYPE_IWARP 1 | |
362 | #define I40IW_QP_TYPE_UDA 2 | |
363 | #define I40IW_QP_TYPE_CQP 4 | |
364 | ||
365 | #define I40IW_CQ_TYPE_IWARP 1 | |
366 | #define I40IW_CQ_TYPE_ILQ 2 | |
367 | #define I40IW_CQ_TYPE_IEQ 3 | |
368 | #define I40IW_CQ_TYPE_CQP 4 | |
369 | ||
370 | #define I40IWQP_TERM_SEND_TERM_AND_FIN 0 | |
371 | #define I40IWQP_TERM_SEND_TERM_ONLY 1 | |
372 | #define I40IWQP_TERM_SEND_FIN_ONLY 2 | |
373 | #define I40IWQP_TERM_DONOT_SEND_TERM_OR_FIN 3 | |
374 | ||
375 | #define I40IW_CQP_OP_CREATE_QP 0 | |
376 | #define I40IW_CQP_OP_MODIFY_QP 0x1 | |
377 | #define I40IW_CQP_OP_DESTROY_QP 0x02 | |
378 | #define I40IW_CQP_OP_CREATE_CQ 0x03 | |
379 | #define I40IW_CQP_OP_MODIFY_CQ 0x04 | |
380 | #define I40IW_CQP_OP_DESTROY_CQ 0x05 | |
381 | #define I40IW_CQP_OP_CREATE_SRQ 0x06 | |
382 | #define I40IW_CQP_OP_MODIFY_SRQ 0x07 | |
383 | #define I40IW_CQP_OP_DESTROY_SRQ 0x08 | |
384 | #define I40IW_CQP_OP_ALLOC_STAG 0x09 | |
385 | #define I40IW_CQP_OP_REG_MR 0x0a | |
386 | #define I40IW_CQP_OP_QUERY_STAG 0x0b | |
387 | #define I40IW_CQP_OP_REG_SMR 0x0c | |
388 | #define I40IW_CQP_OP_DEALLOC_STAG 0x0d | |
389 | #define I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE 0x0e | |
390 | #define I40IW_CQP_OP_MANAGE_ARP 0x0f | |
391 | #define I40IW_CQP_OP_MANAGE_VF_PBLE_BP 0x10 | |
392 | #define I40IW_CQP_OP_MANAGE_PUSH_PAGES 0x11 | |
393 | #define I40IW_CQP_OP_MANAGE_PE_TEAM 0x12 | |
394 | #define I40IW_CQP_OP_UPLOAD_CONTEXT 0x13 | |
395 | #define I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY 0x14 | |
396 | #define I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15 | |
397 | #define I40IW_CQP_OP_CREATE_CEQ 0x16 | |
398 | #define I40IW_CQP_OP_DESTROY_CEQ 0x18 | |
399 | #define I40IW_CQP_OP_CREATE_AEQ 0x19 | |
400 | #define I40IW_CQP_OP_DESTROY_AEQ 0x1b | |
401 | #define I40IW_CQP_OP_CREATE_ADDR_VECT 0x1c | |
402 | #define I40IW_CQP_OP_MODIFY_ADDR_VECT 0x1d | |
403 | #define I40IW_CQP_OP_DESTROY_ADDR_VECT 0x1e | |
404 | #define I40IW_CQP_OP_UPDATE_PE_SDS 0x1f | |
405 | #define I40IW_CQP_OP_QUERY_FPM_VALUES 0x20 | |
406 | #define I40IW_CQP_OP_COMMIT_FPM_VALUES 0x21 | |
407 | #define I40IW_CQP_OP_FLUSH_WQES 0x22 | |
408 | #define I40IW_CQP_OP_MANAGE_APBVT 0x23 | |
409 | #define I40IW_CQP_OP_NOP 0x24 | |
410 | #define I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25 | |
411 | #define I40IW_CQP_OP_CREATE_UDA_MCAST_GROUP 0x26 | |
412 | #define I40IW_CQP_OP_MODIFY_UDA_MCAST_GROUP 0x27 | |
413 | #define I40IW_CQP_OP_DESTROY_UDA_MCAST_GROUP 0x28 | |
414 | #define I40IW_CQP_OP_SUSPEND_QP 0x29 | |
415 | #define I40IW_CQP_OP_RESUME_QP 0x2a | |
416 | #define I40IW_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b | |
417 | #define I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE 0x2d | |
418 | ||
419 | #define I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT 16 | |
420 | #define I40IW_UDA_QPSQ_NEXT_HEADER_MASK ((u64)0xff << I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT) | |
421 | ||
422 | #define I40IW_UDA_QPSQ_OPCODE_SHIFT 32 | |
423 | #define I40IW_UDA_QPSQ_OPCODE_MASK ((u64)0x3f << I40IW_UDA_QPSQ_OPCODE_SHIFT) | |
424 | ||
425 | #define I40IW_UDA_QPSQ_MACLEN_SHIFT 56 | |
426 | #define I40IW_UDA_QPSQ_MACLEN_MASK \ | |
427 | ((u64)0x7f << I40IW_UDA_QPSQ_MACLEN_SHIFT) | |
428 | ||
429 | #define I40IW_UDA_QPSQ_IPLEN_SHIFT 48 | |
430 | #define I40IW_UDA_QPSQ_IPLEN_MASK \ | |
431 | ((u64)0x7f << I40IW_UDA_QPSQ_IPLEN_SHIFT) | |
432 | ||
433 | #define I40IW_UDA_QPSQ_L4T_SHIFT 30 | |
434 | #define I40IW_UDA_QPSQ_L4T_MASK \ | |
435 | ((u64)0x3 << I40IW_UDA_QPSQ_L4T_SHIFT) | |
436 | ||
437 | #define I40IW_UDA_QPSQ_IIPT_SHIFT 28 | |
438 | #define I40IW_UDA_QPSQ_IIPT_MASK \ | |
439 | ((u64)0x3 << I40IW_UDA_QPSQ_IIPT_SHIFT) | |
440 | ||
441 | #define I40IW_UDA_QPSQ_L4LEN_SHIFT 24 | |
442 | #define I40IW_UDA_QPSQ_L4LEN_MASK ((u64)0xf << I40IW_UDA_QPSQ_L4LEN_SHIFT) | |
443 | ||
444 | #define I40IW_UDA_QPSQ_AVIDX_SHIFT 0 | |
445 | #define I40IW_UDA_QPSQ_AVIDX_MASK ((u64)0xffff << I40IW_UDA_QPSQ_AVIDX_SHIFT) | |
446 | ||
447 | #define I40IW_UDA_QPSQ_VALID_SHIFT 63 | |
448 | #define I40IW_UDA_QPSQ_VALID_MASK \ | |
449 | ((u64)0x1 << I40IW_UDA_QPSQ_VALID_SHIFT) | |
450 | ||
451 | #define I40IW_UDA_QPSQ_SIGCOMPL_SHIFT 62 | |
452 | #define I40IW_UDA_QPSQ_SIGCOMPL_MASK ((u64)0x1 << I40IW_UDA_QPSQ_SIGCOMPL_SHIFT) | |
453 | ||
454 | #define I40IW_UDA_PAYLOADLEN_SHIFT 0 | |
455 | #define I40IW_UDA_PAYLOADLEN_MASK ((u64)0x3fff << I40IW_UDA_PAYLOADLEN_SHIFT) | |
456 | ||
457 | #define I40IW_UDA_HDRLEN_SHIFT 16 | |
458 | #define I40IW_UDA_HDRLEN_MASK ((u64)0x1ff << I40IW_UDA_HDRLEN_SHIFT) | |
459 | ||
460 | #define I40IW_VLAN_TAG_VALID_SHIFT 50 | |
461 | #define I40IW_VLAN_TAG_VALID_MASK ((u64)0x1 << I40IW_VLAN_TAG_VALID_SHIFT) | |
462 | ||
463 | #define I40IW_UDA_L3PROTO_SHIFT 0 | |
464 | #define I40IW_UDA_L3PROTO_MASK ((u64)0x3 << I40IW_UDA_L3PROTO_SHIFT) | |
465 | ||
466 | #define I40IW_UDA_L4PROTO_SHIFT 16 | |
467 | #define I40IW_UDA_L4PROTO_MASK ((u64)0x3 << I40IW_UDA_L4PROTO_SHIFT) | |
468 | ||
469 | #define I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT 44 | |
470 | #define I40IW_UDA_QPSQ_DOLOOPBACK_MASK \ | |
471 | ((u64)0x1 << I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT) | |
472 | ||
473 | /* CQP SQ WQE common fields */ | |
474 | #define I40IW_CQPSQ_OPCODE_SHIFT 32 | |
475 | #define I40IW_CQPSQ_OPCODE_MASK (0x3fULL << I40IW_CQPSQ_OPCODE_SHIFT) | |
476 | ||
477 | #define I40IW_CQPSQ_WQEVALID_SHIFT 63 | |
478 | #define I40IW_CQPSQ_WQEVALID_MASK (1ULL << I40IW_CQPSQ_WQEVALID_SHIFT) | |
479 | ||
480 | #define I40IW_CQPSQ_TPHVAL_SHIFT 0 | |
481 | #define I40IW_CQPSQ_TPHVAL_MASK (0xffUL << I40IW_CQPSQ_TPHVAL_SHIFT) | |
482 | ||
483 | #define I40IW_CQPSQ_TPHEN_SHIFT 60 | |
484 | #define I40IW_CQPSQ_TPHEN_MASK (1ULL << I40IW_CQPSQ_TPHEN_SHIFT) | |
485 | ||
486 | #define I40IW_CQPSQ_PBUFADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
487 | #define I40IW_CQPSQ_PBUFADDR_MASK I40IW_CQPHC_QPCTX_MASK | |
488 | ||
489 | /* Create/Modify/Destroy QP */ | |
490 | ||
491 | #define I40IW_CQPSQ_QP_NEWMSS_SHIFT 32 | |
492 | #define I40IW_CQPSQ_QP_NEWMSS_MASK (0x3fffULL << I40IW_CQPSQ_QP_NEWMSS_SHIFT) | |
493 | ||
494 | #define I40IW_CQPSQ_QP_TERMLEN_SHIFT 48 | |
495 | #define I40IW_CQPSQ_QP_TERMLEN_MASK (0xfULL << I40IW_CQPSQ_QP_TERMLEN_SHIFT) | |
496 | ||
497 | #define I40IW_CQPSQ_QP_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
498 | #define I40IW_CQPSQ_QP_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK | |
499 | ||
500 | #define I40IW_CQPSQ_QP_QPID_SHIFT 0 | |
501 | #define I40IW_CQPSQ_QP_QPID_MASK (0x3FFFFUL) | |
502 | /* I40IWCQ_QPID_MASK */ | |
503 | ||
504 | #define I40IW_CQPSQ_QP_OP_SHIFT 32 | |
505 | #define I40IW_CQPSQ_QP_OP_MASK I40IWCQ_OP_MASK | |
506 | ||
507 | #define I40IW_CQPSQ_QP_ORDVALID_SHIFT 42 | |
508 | #define I40IW_CQPSQ_QP_ORDVALID_MASK (1ULL << I40IW_CQPSQ_QP_ORDVALID_SHIFT) | |
509 | ||
510 | #define I40IW_CQPSQ_QP_TOECTXVALID_SHIFT 43 | |
511 | #define I40IW_CQPSQ_QP_TOECTXVALID_MASK \ | |
512 | (1ULL << I40IW_CQPSQ_QP_TOECTXVALID_SHIFT) | |
513 | ||
514 | #define I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT 44 | |
515 | #define I40IW_CQPSQ_QP_CACHEDVARVALID_MASK \ | |
516 | (1ULL << I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT) | |
517 | ||
518 | #define I40IW_CQPSQ_QP_VQ_SHIFT 45 | |
519 | #define I40IW_CQPSQ_QP_VQ_MASK (1ULL << I40IW_CQPSQ_QP_VQ_SHIFT) | |
520 | ||
521 | #define I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT 46 | |
522 | #define I40IW_CQPSQ_QP_FORCELOOPBACK_MASK \ | |
523 | (1ULL << I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT) | |
524 | ||
525 | #define I40IW_CQPSQ_QP_CQNUMVALID_SHIFT 47 | |
526 | #define I40IW_CQPSQ_QP_CQNUMVALID_MASK \ | |
527 | (1ULL << I40IW_CQPSQ_QP_CQNUMVALID_SHIFT) | |
528 | ||
529 | #define I40IW_CQPSQ_QP_QPTYPE_SHIFT 48 | |
530 | #define I40IW_CQPSQ_QP_QPTYPE_MASK (0x3ULL << I40IW_CQPSQ_QP_QPTYPE_SHIFT) | |
531 | ||
532 | #define I40IW_CQPSQ_QP_MSSCHANGE_SHIFT 52 | |
533 | #define I40IW_CQPSQ_QP_MSSCHANGE_MASK (1ULL << I40IW_CQPSQ_QP_MSSCHANGE_SHIFT) | |
534 | ||
535 | #define I40IW_CQPSQ_QP_STATRSRC_SHIFT 53 | |
536 | #define I40IW_CQPSQ_QP_STATRSRC_MASK (1ULL << I40IW_CQPSQ_QP_STATRSRC_SHIFT) | |
537 | ||
538 | #define I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT 54 | |
539 | #define I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK \ | |
540 | (1ULL << I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT) | |
541 | ||
542 | #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT 55 | |
543 | #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_MASK \ | |
544 | (1ULL << I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT) | |
545 | ||
546 | #define I40IW_CQPSQ_QP_TERMACT_SHIFT 56 | |
547 | #define I40IW_CQPSQ_QP_TERMACT_MASK (0x3ULL << I40IW_CQPSQ_QP_TERMACT_SHIFT) | |
548 | ||
549 | #define I40IW_CQPSQ_QP_RESETCON_SHIFT 58 | |
550 | #define I40IW_CQPSQ_QP_RESETCON_MASK (1ULL << I40IW_CQPSQ_QP_RESETCON_SHIFT) | |
551 | ||
552 | #define I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT 59 | |
553 | #define I40IW_CQPSQ_QP_ARPTABIDXVALID_MASK \ | |
554 | (1ULL << I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT) | |
555 | ||
556 | #define I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT 60 | |
557 | #define I40IW_CQPSQ_QP_NEXTIWSTATE_MASK \ | |
558 | (0x7ULL << I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT) | |
559 | ||
560 | #define I40IW_CQPSQ_QP_DBSHADOWADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
561 | #define I40IW_CQPSQ_QP_DBSHADOWADDR_MASK I40IW_CQPHC_QPCTX_MASK | |
562 | ||
563 | /* Create/Modify/Destroy CQ */ | |
564 | #define I40IW_CQPSQ_CQ_CQSIZE_SHIFT 0 | |
565 | #define I40IW_CQPSQ_CQ_CQSIZE_MASK (0x3ffffUL << I40IW_CQPSQ_CQ_CQSIZE_SHIFT) | |
566 | ||
567 | #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0 | |
568 | #define I40IW_CQPSQ_CQ_CQCTX_MASK \ | |
569 | (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT) | |
570 | ||
571 | #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0 | |
572 | #define I40IW_CQPSQ_CQ_CQCTX_MASK \ | |
573 | (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT) | |
574 | ||
575 | #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT 0 | |
576 | #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_MASK \ | |
577 | (0x3ffff << I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT) | |
578 | ||
579 | #define I40IW_CQPSQ_CQ_CEQID_SHIFT 24 | |
580 | #define I40IW_CQPSQ_CQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CQ_CEQID_SHIFT) | |
581 | ||
582 | #define I40IW_CQPSQ_CQ_OP_SHIFT 32 | |
583 | #define I40IW_CQPSQ_CQ_OP_MASK (0x3fULL << I40IW_CQPSQ_CQ_OP_SHIFT) | |
584 | ||
585 | #define I40IW_CQPSQ_CQ_CQRESIZE_SHIFT 43 | |
586 | #define I40IW_CQPSQ_CQ_CQRESIZE_MASK (1ULL << I40IW_CQPSQ_CQ_CQRESIZE_SHIFT) | |
587 | ||
588 | #define I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 44 | |
589 | #define I40IW_CQPSQ_CQ_LPBLSIZE_MASK (3ULL << I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT) | |
590 | ||
591 | #define I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT 46 | |
592 | #define I40IW_CQPSQ_CQ_CHKOVERFLOW_MASK \ | |
593 | (1ULL << I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT) | |
594 | ||
595 | #define I40IW_CQPSQ_CQ_VIRTMAP_SHIFT 47 | |
596 | #define I40IW_CQPSQ_CQ_VIRTMAP_MASK (1ULL << I40IW_CQPSQ_CQ_VIRTMAP_SHIFT) | |
597 | ||
598 | #define I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT 48 | |
599 | #define I40IW_CQPSQ_CQ_ENCEQEMASK_MASK \ | |
600 | (1ULL << I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT) | |
601 | ||
602 | #define I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT 49 | |
603 | #define I40IW_CQPSQ_CQ_CEQIDVALID_MASK \ | |
604 | (1ULL << I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT) | |
605 | ||
606 | #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT 61 | |
607 | #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_MASK \ | |
608 | (1ULL << I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT) | |
609 | ||
610 | /* Create/Modify/Destroy Shared Receive Queue */ | |
611 | ||
612 | #define I40IW_CQPSQ_SRQ_RQSIZE_SHIFT 0 | |
613 | #define I40IW_CQPSQ_SRQ_RQSIZE_MASK (0xfUL << I40IW_CQPSQ_SRQ_RQSIZE_SHIFT) | |
614 | ||
615 | #define I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT 4 | |
616 | #define I40IW_CQPSQ_SRQ_RQWQESIZE_MASK \ | |
617 | (0x7UL << I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT) | |
618 | ||
619 | #define I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT 32 | |
620 | #define I40IW_CQPSQ_SRQ_SRQLIMIT_MASK \ | |
621 | (0xfffULL << I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT) | |
622 | ||
623 | #define I40IW_CQPSQ_SRQ_SRQCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
624 | #define I40IW_CQPSQ_SRQ_SRQCTX_MASK I40IW_CQPHC_QPCTX_MASK | |
625 | ||
626 | #define I40IW_CQPSQ_SRQ_PDID_SHIFT 16 | |
627 | #define I40IW_CQPSQ_SRQ_PDID_MASK \ | |
628 | (0x7fffULL << I40IW_CQPSQ_SRQ_PDID_SHIFT) | |
629 | ||
630 | #define I40IW_CQPSQ_SRQ_SRQID_SHIFT 0 | |
631 | #define I40IW_CQPSQ_SRQ_SRQID_MASK (0x7fffUL << I40IW_CQPSQ_SRQ_SRQID_SHIFT) | |
632 | ||
633 | #define I40IW_CQPSQ_SRQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT | |
634 | #define I40IW_CQPSQ_SRQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK | |
635 | ||
636 | #define I40IW_CQPSQ_SRQ_VIRTMAP_SHIFT I40IW_CQPSQ_CQ_VIRTMAP_SHIFT | |
637 | #define I40IW_CQPSQ_SRQ_VIRTMAP_MASK I40IW_CQPSQ_CQ_VIRTMAP_MASK | |
638 | ||
639 | #define I40IW_CQPSQ_SRQ_TPHEN_SHIFT I40IW_CQPSQ_TPHEN_SHIFT | |
640 | #define I40IW_CQPSQ_SRQ_TPHEN_MASK I40IW_CQPSQ_TPHEN_MASK | |
641 | ||
642 | #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT 61 | |
643 | #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_MASK \ | |
644 | (1ULL << I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT) | |
645 | ||
646 | #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT 6 | |
647 | #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_MASK \ | |
648 | (0x3ffffffffffffffULL << I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT) | |
649 | ||
650 | #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT 0 | |
651 | #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_MASK \ | |
652 | (0xfffffffUL << I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT) | |
653 | ||
654 | /* Allocate/Register/Register Shared/Deallocate Stag */ | |
655 | #define I40IW_CQPSQ_STAG_VA_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
656 | #define I40IW_CQPSQ_STAG_VA_FBO_MASK I40IW_CQPHC_QPCTX_MASK | |
657 | ||
658 | #define I40IW_CQPSQ_STAG_STAGLEN_SHIFT 0 | |
659 | #define I40IW_CQPSQ_STAG_STAGLEN_MASK \ | |
660 | (0x3fffffffffffULL << I40IW_CQPSQ_STAG_STAGLEN_SHIFT) | |
661 | ||
662 | #define I40IW_CQPSQ_STAG_PDID_SHIFT 48 | |
663 | #define I40IW_CQPSQ_STAG_PDID_MASK (0x7fffULL << I40IW_CQPSQ_STAG_PDID_SHIFT) | |
664 | ||
665 | #define I40IW_CQPSQ_STAG_KEY_SHIFT 0 | |
666 | #define I40IW_CQPSQ_STAG_KEY_MASK (0xffUL << I40IW_CQPSQ_STAG_KEY_SHIFT) | |
667 | ||
668 | #define I40IW_CQPSQ_STAG_IDX_SHIFT 8 | |
669 | #define I40IW_CQPSQ_STAG_IDX_MASK (0xffffffUL << I40IW_CQPSQ_STAG_IDX_SHIFT) | |
670 | ||
671 | #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT 32 | |
672 | #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_MASK \ | |
673 | (0xffffffULL << I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT) | |
674 | ||
675 | #define I40IW_CQPSQ_STAG_MR_SHIFT 43 | |
676 | #define I40IW_CQPSQ_STAG_MR_MASK (1ULL << I40IW_CQPSQ_STAG_MR_SHIFT) | |
677 | ||
678 | #define I40IW_CQPSQ_STAG_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT | |
679 | #define I40IW_CQPSQ_STAG_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK | |
680 | ||
681 | #define I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT 46 | |
682 | #define I40IW_CQPSQ_STAG_HPAGESIZE_MASK \ | |
683 | (1ULL << I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT) | |
684 | ||
685 | #define I40IW_CQPSQ_STAG_ARIGHTS_SHIFT 48 | |
686 | #define I40IW_CQPSQ_STAG_ARIGHTS_MASK \ | |
687 | (0x1fULL << I40IW_CQPSQ_STAG_ARIGHTS_SHIFT) | |
688 | ||
689 | #define I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT 53 | |
690 | #define I40IW_CQPSQ_STAG_REMACCENABLED_MASK \ | |
691 | (1ULL << I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT) | |
692 | ||
693 | #define I40IW_CQPSQ_STAG_VABASEDTO_SHIFT 59 | |
694 | #define I40IW_CQPSQ_STAG_VABASEDTO_MASK \ | |
695 | (1ULL << I40IW_CQPSQ_STAG_VABASEDTO_SHIFT) | |
696 | ||
697 | #define I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT 60 | |
698 | #define I40IW_CQPSQ_STAG_USEHMCFNIDX_MASK \ | |
699 | (1ULL << I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT) | |
700 | ||
701 | #define I40IW_CQPSQ_STAG_USEPFRID_SHIFT 61 | |
702 | #define I40IW_CQPSQ_STAG_USEPFRID_MASK \ | |
703 | (1ULL << I40IW_CQPSQ_STAG_USEPFRID_SHIFT) | |
704 | ||
705 | #define I40IW_CQPSQ_STAG_PBA_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
706 | #define I40IW_CQPSQ_STAG_PBA_MASK I40IW_CQPHC_QPCTX_MASK | |
707 | ||
708 | #define I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT 0 | |
709 | #define I40IW_CQPSQ_STAG_HMCFNIDX_MASK \ | |
710 | (0x3fUL << I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT) | |
711 | ||
712 | #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT 0 | |
713 | #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_MASK \ | |
714 | (0xfffffffUL << I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT) | |
715 | ||
716 | /* Query stag */ | |
717 | #define I40IW_CQPSQ_QUERYSTAG_IDX_SHIFT I40IW_CQPSQ_STAG_IDX_SHIFT | |
718 | #define I40IW_CQPSQ_QUERYSTAG_IDX_MASK I40IW_CQPSQ_STAG_IDX_MASK | |
719 | ||
720 | /* Allocate Local IP Address Entry */ | |
721 | ||
722 | /* Manage Local IP Address Table - MLIPA */ | |
723 | #define I40IW_CQPSQ_MLIPA_IPV6LO_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
724 | #define I40IW_CQPSQ_MLIPA_IPV6LO_MASK I40IW_CQPHC_QPCTX_MASK | |
725 | ||
726 | #define I40IW_CQPSQ_MLIPA_IPV6HI_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
727 | #define I40IW_CQPSQ_MLIPA_IPV6HI_MASK I40IW_CQPHC_QPCTX_MASK | |
728 | ||
729 | #define I40IW_CQPSQ_MLIPA_IPV4_SHIFT 0 | |
730 | #define I40IW_CQPSQ_MLIPA_IPV4_MASK \ | |
731 | (0xffffffffUL << I40IW_CQPSQ_MLIPA_IPV4_SHIFT) | |
732 | ||
733 | #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT 0 | |
734 | #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_MASK \ | |
735 | (0x3fUL << I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT) | |
736 | ||
737 | #define I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT 42 | |
738 | #define I40IW_CQPSQ_MLIPA_IPV4VALID_MASK \ | |
739 | (1ULL << I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT) | |
740 | ||
741 | #define I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT 43 | |
742 | #define I40IW_CQPSQ_MLIPA_IPV6VALID_MASK \ | |
743 | (1ULL << I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT) | |
744 | ||
745 | #define I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT 62 | |
746 | #define I40IW_CQPSQ_MLIPA_FREEENTRY_MASK \ | |
747 | (1ULL << I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT) | |
748 | ||
749 | #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT 61 | |
750 | #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_MASK \ | |
751 | (1ULL << I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT) | |
752 | ||
753 | #define I40IW_CQPSQ_MLIPA_MAC0_SHIFT 0 | |
754 | #define I40IW_CQPSQ_MLIPA_MAC0_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC0_SHIFT) | |
755 | ||
756 | #define I40IW_CQPSQ_MLIPA_MAC1_SHIFT 8 | |
757 | #define I40IW_CQPSQ_MLIPA_MAC1_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC1_SHIFT) | |
758 | ||
759 | #define I40IW_CQPSQ_MLIPA_MAC2_SHIFT 16 | |
760 | #define I40IW_CQPSQ_MLIPA_MAC2_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC2_SHIFT) | |
761 | ||
762 | #define I40IW_CQPSQ_MLIPA_MAC3_SHIFT 24 | |
763 | #define I40IW_CQPSQ_MLIPA_MAC3_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC3_SHIFT) | |
764 | ||
765 | #define I40IW_CQPSQ_MLIPA_MAC4_SHIFT 32 | |
766 | #define I40IW_CQPSQ_MLIPA_MAC4_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC4_SHIFT) | |
767 | ||
768 | #define I40IW_CQPSQ_MLIPA_MAC5_SHIFT 40 | |
769 | #define I40IW_CQPSQ_MLIPA_MAC5_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC5_SHIFT) | |
770 | ||
771 | /* Manage ARP Table - MAT */ | |
772 | #define I40IW_CQPSQ_MAT_REACHMAX_SHIFT 0 | |
773 | #define I40IW_CQPSQ_MAT_REACHMAX_MASK \ | |
774 | (0xffffffffUL << I40IW_CQPSQ_MAT_REACHMAX_SHIFT) | |
775 | ||
776 | #define I40IW_CQPSQ_MAT_MACADDR_SHIFT 0 | |
777 | #define I40IW_CQPSQ_MAT_MACADDR_MASK \ | |
778 | (0xffffffffffffULL << I40IW_CQPSQ_MAT_MACADDR_SHIFT) | |
779 | ||
780 | #define I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT 0 | |
781 | #define I40IW_CQPSQ_MAT_ARPENTRYIDX_MASK \ | |
782 | (0xfffUL << I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT) | |
783 | ||
784 | #define I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT 42 | |
785 | #define I40IW_CQPSQ_MAT_ENTRYVALID_MASK \ | |
786 | (1ULL << I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT) | |
787 | ||
788 | #define I40IW_CQPSQ_MAT_PERMANENT_SHIFT 43 | |
789 | #define I40IW_CQPSQ_MAT_PERMANENT_MASK \ | |
790 | (1ULL << I40IW_CQPSQ_MAT_PERMANENT_SHIFT) | |
791 | ||
792 | #define I40IW_CQPSQ_MAT_QUERY_SHIFT 44 | |
793 | #define I40IW_CQPSQ_MAT_QUERY_MASK (1ULL << I40IW_CQPSQ_MAT_QUERY_SHIFT) | |
794 | ||
795 | /* Manage VF PBLE Backing Pages - MVPBP*/ | |
796 | #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT 0 | |
797 | #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_MASK \ | |
798 | (0x3ffULL << I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT) | |
799 | ||
800 | #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT 16 | |
801 | #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_MASK \ | |
802 | (0x1ffULL << I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT) | |
803 | ||
804 | #define I40IW_CQPSQ_MVPBP_SD_INX_SHIFT 32 | |
805 | #define I40IW_CQPSQ_MVPBP_SD_INX_MASK \ | |
806 | (0xfffULL << I40IW_CQPSQ_MVPBP_SD_INX_SHIFT) | |
807 | ||
808 | #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT 62 | |
809 | #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_MASK \ | |
810 | (0x1ULL << I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT) | |
811 | ||
812 | #define I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT 3 | |
813 | #define I40IW_CQPSQ_MVPBP_PD_PLPBA_MASK \ | |
814 | (0x1fffffffffffffffULL << I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT) | |
815 | ||
816 | /* Manage Push Page - MPP */ | |
817 | #define I40IW_INVALID_PUSH_PAGE_INDEX 0xffff | |
818 | ||
819 | #define I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT 0 | |
820 | #define I40IW_CQPSQ_MPP_QS_HANDLE_MASK (0xffffUL << \ | |
821 | I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT) | |
822 | ||
823 | #define I40IW_CQPSQ_MPP_PPIDX_SHIFT 0 | |
824 | #define I40IW_CQPSQ_MPP_PPIDX_MASK (0x3ffUL << I40IW_CQPSQ_MPP_PPIDX_SHIFT) | |
825 | ||
826 | #define I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT 62 | |
827 | #define I40IW_CQPSQ_MPP_FREE_PAGE_MASK (1ULL << I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT) | |
828 | ||
829 | /* Upload Context - UCTX */ | |
830 | #define I40IW_CQPSQ_UCTX_QPCTXADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
831 | #define I40IW_CQPSQ_UCTX_QPCTXADDR_MASK I40IW_CQPHC_QPCTX_MASK | |
832 | ||
833 | #define I40IW_CQPSQ_UCTX_QPID_SHIFT 0 | |
834 | #define I40IW_CQPSQ_UCTX_QPID_MASK (0x3ffffUL << I40IW_CQPSQ_UCTX_QPID_SHIFT) | |
835 | ||
836 | #define I40IW_CQPSQ_UCTX_QPTYPE_SHIFT 48 | |
837 | #define I40IW_CQPSQ_UCTX_QPTYPE_MASK (0xfULL << I40IW_CQPSQ_UCTX_QPTYPE_SHIFT) | |
838 | ||
839 | #define I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT 61 | |
840 | #define I40IW_CQPSQ_UCTX_RAWFORMAT_MASK \ | |
841 | (1ULL << I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT) | |
842 | ||
843 | #define I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT 62 | |
844 | #define I40IW_CQPSQ_UCTX_FREEZEQP_MASK \ | |
845 | (1ULL << I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT) | |
846 | ||
847 | /* Manage HMC PM Function Table - MHMC */ | |
848 | #define I40IW_CQPSQ_MHMC_VFIDX_SHIFT 0 | |
849 | #define I40IW_CQPSQ_MHMC_VFIDX_MASK (0x7fUL << I40IW_CQPSQ_MHMC_VFIDX_SHIFT) | |
850 | ||
851 | #define I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT 62 | |
852 | #define I40IW_CQPSQ_MHMC_FREEPMFN_MASK \ | |
853 | (1ULL << I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT) | |
854 | ||
855 | /* Set HMC Resource Profile - SHMCRP */ | |
856 | #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT 0 | |
857 | #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_MASK \ | |
858 | (0x7ULL << I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT) | |
859 | #define I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT 32 | |
860 | #define I40IW_CQPSQ_SHMCRP_VFNUM_MASK (0x3fULL << I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT) | |
861 | ||
862 | /* Create/Destroy CEQ */ | |
863 | #define I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT 0 | |
864 | #define I40IW_CQPSQ_CEQ_CEQSIZE_MASK \ | |
865 | (0x1ffffUL << I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT) | |
866 | ||
867 | #define I40IW_CQPSQ_CEQ_CEQID_SHIFT 0 | |
868 | #define I40IW_CQPSQ_CEQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CEQ_CEQID_SHIFT) | |
869 | ||
870 | #define I40IW_CQPSQ_CEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT | |
871 | #define I40IW_CQPSQ_CEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK | |
872 | ||
873 | #define I40IW_CQPSQ_CEQ_VMAP_SHIFT 47 | |
874 | #define I40IW_CQPSQ_CEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_CEQ_VMAP_SHIFT) | |
875 | ||
876 | #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT 0 | |
877 | #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_MASK \ | |
878 | (0xfffffffUL << I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT) | |
879 | ||
880 | /* Create/Destroy AEQ */ | |
881 | #define I40IW_CQPSQ_AEQ_AEQECNT_SHIFT 0 | |
882 | #define I40IW_CQPSQ_AEQ_AEQECNT_MASK \ | |
883 | (0x7ffffUL << I40IW_CQPSQ_AEQ_AEQECNT_SHIFT) | |
884 | ||
885 | #define I40IW_CQPSQ_AEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT | |
886 | #define I40IW_CQPSQ_AEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK | |
887 | ||
888 | #define I40IW_CQPSQ_AEQ_VMAP_SHIFT 47 | |
889 | #define I40IW_CQPSQ_AEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_AEQ_VMAP_SHIFT) | |
890 | ||
891 | #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT 0 | |
892 | #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_MASK \ | |
893 | (0xfffffffUL << I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT) | |
894 | ||
895 | /* Commit FPM Values - CFPM */ | |
896 | #define I40IW_CQPSQ_CFPM_HMCFNID_SHIFT 0 | |
897 | #define I40IW_CQPSQ_CFPM_HMCFNID_MASK (0x3fUL << I40IW_CQPSQ_CFPM_HMCFNID_SHIFT) | |
898 | ||
899 | /* Flush WQEs - FWQE */ | |
900 | #define I40IW_CQPSQ_FWQE_AECODE_SHIFT 0 | |
901 | #define I40IW_CQPSQ_FWQE_AECODE_MASK (0xffffUL << I40IW_CQPSQ_FWQE_AECODE_SHIFT) | |
902 | ||
903 | #define I40IW_CQPSQ_FWQE_AESOURCE_SHIFT 16 | |
904 | #define I40IW_CQPSQ_FWQE_AESOURCE_MASK \ | |
905 | (0xfUL << I40IW_CQPSQ_FWQE_AESOURCE_SHIFT) | |
906 | ||
907 | #define I40IW_CQPSQ_FWQE_RQMNERR_SHIFT 0 | |
908 | #define I40IW_CQPSQ_FWQE_RQMNERR_MASK \ | |
909 | (0xffffUL << I40IW_CQPSQ_FWQE_RQMNERR_SHIFT) | |
910 | ||
911 | #define I40IW_CQPSQ_FWQE_RQMJERR_SHIFT 16 | |
912 | #define I40IW_CQPSQ_FWQE_RQMJERR_MASK \ | |
913 | (0xffffUL << I40IW_CQPSQ_FWQE_RQMJERR_SHIFT) | |
914 | ||
915 | #define I40IW_CQPSQ_FWQE_SQMNERR_SHIFT 32 | |
916 | #define I40IW_CQPSQ_FWQE_SQMNERR_MASK \ | |
917 | (0xffffULL << I40IW_CQPSQ_FWQE_SQMNERR_SHIFT) | |
918 | ||
919 | #define I40IW_CQPSQ_FWQE_SQMJERR_SHIFT 48 | |
920 | #define I40IW_CQPSQ_FWQE_SQMJERR_MASK \ | |
921 | (0xffffULL << I40IW_CQPSQ_FWQE_SQMJERR_SHIFT) | |
922 | ||
923 | #define I40IW_CQPSQ_FWQE_QPID_SHIFT 0 | |
924 | #define I40IW_CQPSQ_FWQE_QPID_MASK (0x3ffffULL << I40IW_CQPSQ_FWQE_QPID_SHIFT) | |
925 | ||
926 | #define I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT 59 | |
927 | #define I40IW_CQPSQ_FWQE_GENERATE_AE_MASK (1ULL << \ | |
928 | I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT) | |
929 | ||
930 | #define I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT 60 | |
931 | #define I40IW_CQPSQ_FWQE_USERFLCODE_MASK \ | |
932 | (1ULL << I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT) | |
933 | ||
934 | #define I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT 61 | |
935 | #define I40IW_CQPSQ_FWQE_FLUSHSQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT) | |
936 | ||
937 | #define I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT 62 | |
938 | #define I40IW_CQPSQ_FWQE_FLUSHRQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT) | |
939 | ||
940 | /* Manage Accelerated Port Table - MAPT */ | |
941 | #define I40IW_CQPSQ_MAPT_PORT_SHIFT 0 | |
942 | #define I40IW_CQPSQ_MAPT_PORT_MASK (0xffffUL << I40IW_CQPSQ_MAPT_PORT_SHIFT) | |
943 | ||
944 | #define I40IW_CQPSQ_MAPT_ADDPORT_SHIFT 62 | |
945 | #define I40IW_CQPSQ_MAPT_ADDPORT_MASK (1ULL << I40IW_CQPSQ_MAPT_ADDPORT_SHIFT) | |
946 | ||
947 | /* Update Protocol Engine SDs */ | |
948 | #define I40IW_CQPSQ_UPESD_SDCMD_SHIFT 0 | |
949 | #define I40IW_CQPSQ_UPESD_SDCMD_MASK (0xffffffffUL << I40IW_CQPSQ_UPESD_SDCMD_SHIFT) | |
950 | ||
951 | #define I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT 0 | |
952 | #define I40IW_CQPSQ_UPESD_SDDATALOW_MASK \ | |
953 | (0xffffffffUL << I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT) | |
954 | ||
955 | #define I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT 32 | |
956 | #define I40IW_CQPSQ_UPESD_SDDATAHI_MASK \ | |
957 | (0xffffffffULL << I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT) | |
958 | #define I40IW_CQPSQ_UPESD_HMCFNID_SHIFT 0 | |
959 | #define I40IW_CQPSQ_UPESD_HMCFNID_MASK \ | |
960 | (0x3fUL << I40IW_CQPSQ_UPESD_HMCFNID_SHIFT) | |
961 | ||
962 | #define I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT 63 | |
963 | #define I40IW_CQPSQ_UPESD_ENTRY_VALID_MASK \ | |
964 | ((u64)1 << I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT) | |
965 | ||
966 | #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT 0 | |
967 | #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_MASK \ | |
968 | (0xfUL << I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT) | |
969 | ||
970 | #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT 7 | |
971 | #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_MASK \ | |
972 | (0x1UL << I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT) | |
973 | ||
974 | /* Suspend QP */ | |
975 | #define I40IW_CQPSQ_SUSPENDQP_QPID_SHIFT 0 | |
976 | #define I40IW_CQPSQ_SUSPENDQP_QPID_MASK (0x3FFFFUL) | |
977 | /* I40IWCQ_QPID_MASK */ | |
978 | ||
979 | /* Resume QP */ | |
980 | #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT 0 | |
981 | #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_MASK \ | |
982 | (0xffffffffUL << I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT) | |
983 | ||
984 | #define I40IW_CQPSQ_RESUMEQP_QPID_SHIFT 0 | |
985 | #define I40IW_CQPSQ_RESUMEQP_QPID_MASK (0x3FFFFUL) | |
986 | /* I40IWCQ_QPID_MASK */ | |
987 | ||
988 | /* IW QP Context */ | |
989 | #define I40IWQPC_DDP_VER_SHIFT 0 | |
990 | #define I40IWQPC_DDP_VER_MASK (3UL << I40IWQPC_DDP_VER_SHIFT) | |
991 | ||
992 | #define I40IWQPC_SNAP_SHIFT 2 | |
993 | #define I40IWQPC_SNAP_MASK (1UL << I40IWQPC_SNAP_SHIFT) | |
994 | ||
995 | #define I40IWQPC_IPV4_SHIFT 3 | |
996 | #define I40IWQPC_IPV4_MASK (1UL << I40IWQPC_IPV4_SHIFT) | |
997 | ||
998 | #define I40IWQPC_NONAGLE_SHIFT 4 | |
999 | #define I40IWQPC_NONAGLE_MASK (1UL << I40IWQPC_NONAGLE_SHIFT) | |
1000 | ||
1001 | #define I40IWQPC_INSERTVLANTAG_SHIFT 5 | |
1002 | #define I40IWQPC_INSERTVLANTAG_MASK (1 << I40IWQPC_INSERTVLANTAG_SHIFT) | |
1003 | ||
1004 | #define I40IWQPC_USESRQ_SHIFT 6 | |
1005 | #define I40IWQPC_USESRQ_MASK (1UL << I40IWQPC_USESRQ_SHIFT) | |
1006 | ||
1007 | #define I40IWQPC_TIMESTAMP_SHIFT 7 | |
1008 | #define I40IWQPC_TIMESTAMP_MASK (1UL << I40IWQPC_TIMESTAMP_SHIFT) | |
1009 | ||
1010 | #define I40IWQPC_RQWQESIZE_SHIFT 8 | |
1011 | #define I40IWQPC_RQWQESIZE_MASK (3UL << I40IWQPC_RQWQESIZE_SHIFT) | |
1012 | ||
1013 | #define I40IWQPC_INSERTL2TAG2_SHIFT 11 | |
1014 | #define I40IWQPC_INSERTL2TAG2_MASK (1UL << I40IWQPC_INSERTL2TAG2_SHIFT) | |
1015 | ||
1016 | #define I40IWQPC_LIMIT_SHIFT 12 | |
1017 | #define I40IWQPC_LIMIT_MASK (3UL << I40IWQPC_LIMIT_SHIFT) | |
1018 | ||
1019 | #define I40IWQPC_DROPOOOSEG_SHIFT 15 | |
1020 | #define I40IWQPC_DROPOOOSEG_MASK (1UL << I40IWQPC_DROPOOOSEG_SHIFT) | |
1021 | ||
1022 | #define I40IWQPC_DUPACK_THRESH_SHIFT 16 | |
1023 | #define I40IWQPC_DUPACK_THRESH_MASK (7UL << I40IWQPC_DUPACK_THRESH_SHIFT) | |
1024 | ||
1025 | #define I40IWQPC_ERR_RQ_IDX_VALID_SHIFT 19 | |
1026 | #define I40IWQPC_ERR_RQ_IDX_VALID_MASK (1UL << I40IWQPC_ERR_RQ_IDX_VALID_SHIFT) | |
1027 | ||
1028 | #define I40IWQPC_DIS_VLAN_CHECKS_SHIFT 19 | |
1029 | #define I40IWQPC_DIS_VLAN_CHECKS_MASK (7UL << I40IWQPC_DIS_VLAN_CHECKS_SHIFT) | |
1030 | ||
1031 | #define I40IWQPC_RCVTPHEN_SHIFT 28 | |
1032 | #define I40IWQPC_RCVTPHEN_MASK (1UL << I40IWQPC_RCVTPHEN_SHIFT) | |
1033 | ||
1034 | #define I40IWQPC_XMITTPHEN_SHIFT 29 | |
1035 | #define I40IWQPC_XMITTPHEN_MASK (1ULL << I40IWQPC_XMITTPHEN_SHIFT) | |
1036 | ||
1037 | #define I40IWQPC_RQTPHEN_SHIFT 30 | |
1038 | #define I40IWQPC_RQTPHEN_MASK (1UL << I40IWQPC_RQTPHEN_SHIFT) | |
1039 | ||
1040 | #define I40IWQPC_SQTPHEN_SHIFT 31 | |
1041 | #define I40IWQPC_SQTPHEN_MASK (1ULL << I40IWQPC_SQTPHEN_SHIFT) | |
1042 | ||
1043 | #define I40IWQPC_PPIDX_SHIFT 32 | |
1044 | #define I40IWQPC_PPIDX_MASK (0x3ffULL << I40IWQPC_PPIDX_SHIFT) | |
1045 | ||
1046 | #define I40IWQPC_PMENA_SHIFT 47 | |
1047 | #define I40IWQPC_PMENA_MASK (1ULL << I40IWQPC_PMENA_SHIFT) | |
1048 | ||
1049 | #define I40IWQPC_RDMAP_VER_SHIFT 62 | |
1050 | #define I40IWQPC_RDMAP_VER_MASK (3ULL << I40IWQPC_RDMAP_VER_SHIFT) | |
1051 | ||
1052 | #define I40IWQPC_SQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1053 | #define I40IWQPC_SQADDR_MASK I40IW_CQPHC_QPCTX_MASK | |
1054 | ||
1055 | #define I40IWQPC_RQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1056 | #define I40IWQPC_RQADDR_MASK I40IW_CQPHC_QPCTX_MASK | |
1057 | ||
1058 | #define I40IWQPC_TTL_SHIFT 0 | |
1059 | #define I40IWQPC_TTL_MASK (0xffUL << I40IWQPC_TTL_SHIFT) | |
1060 | ||
1061 | #define I40IWQPC_RQSIZE_SHIFT 8 | |
1062 | #define I40IWQPC_RQSIZE_MASK (0xfUL << I40IWQPC_RQSIZE_SHIFT) | |
1063 | ||
1064 | #define I40IWQPC_SQSIZE_SHIFT 12 | |
1065 | #define I40IWQPC_SQSIZE_MASK (0xfUL << I40IWQPC_SQSIZE_SHIFT) | |
1066 | ||
1067 | #define I40IWQPC_SRCMACADDRIDX_SHIFT 16 | |
1068 | #define I40IWQPC_SRCMACADDRIDX_MASK (0x3fUL << I40IWQPC_SRCMACADDRIDX_SHIFT) | |
1069 | ||
1070 | #define I40IWQPC_AVOIDSTRETCHACK_SHIFT 23 | |
1071 | #define I40IWQPC_AVOIDSTRETCHACK_MASK (1UL << I40IWQPC_AVOIDSTRETCHACK_SHIFT) | |
1072 | ||
1073 | #define I40IWQPC_TOS_SHIFT 24 | |
1074 | #define I40IWQPC_TOS_MASK (0xffUL << I40IWQPC_TOS_SHIFT) | |
1075 | ||
1076 | #define I40IWQPC_SRCPORTNUM_SHIFT 32 | |
1077 | #define I40IWQPC_SRCPORTNUM_MASK (0xffffULL << I40IWQPC_SRCPORTNUM_SHIFT) | |
1078 | ||
1079 | #define I40IWQPC_DESTPORTNUM_SHIFT 48 | |
1080 | #define I40IWQPC_DESTPORTNUM_MASK (0xffffULL << I40IWQPC_DESTPORTNUM_SHIFT) | |
1081 | ||
1082 | #define I40IWQPC_DESTIPADDR0_SHIFT 32 | |
1083 | #define I40IWQPC_DESTIPADDR0_MASK \ | |
1084 | (0xffffffffULL << I40IWQPC_DESTIPADDR0_SHIFT) | |
1085 | ||
1086 | #define I40IWQPC_DESTIPADDR1_SHIFT 0 | |
1087 | #define I40IWQPC_DESTIPADDR1_MASK \ | |
1088 | (0xffffffffULL << I40IWQPC_DESTIPADDR1_SHIFT) | |
1089 | ||
1090 | #define I40IWQPC_DESTIPADDR2_SHIFT 32 | |
1091 | #define I40IWQPC_DESTIPADDR2_MASK \ | |
1092 | (0xffffffffULL << I40IWQPC_DESTIPADDR2_SHIFT) | |
1093 | ||
1094 | #define I40IWQPC_DESTIPADDR3_SHIFT 0 | |
1095 | #define I40IWQPC_DESTIPADDR3_MASK \ | |
1096 | (0xffffffffULL << I40IWQPC_DESTIPADDR3_SHIFT) | |
1097 | ||
1098 | #define I40IWQPC_SNDMSS_SHIFT 16 | |
1099 | #define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT) | |
1100 | ||
1101 | #define I40IWQPC_VLANTAG_SHIFT 32 | |
1102 | #define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT) | |
1103 | ||
1104 | #define I40IWQPC_ARPIDX_SHIFT 48 | |
1105 | #define I40IWQPC_ARPIDX_MASK (0xfffULL << I40IWQPC_ARPIDX_SHIFT) | |
1106 | ||
1107 | #define I40IWQPC_FLOWLABEL_SHIFT 0 | |
1108 | #define I40IWQPC_FLOWLABEL_MASK (0xfffffUL << I40IWQPC_FLOWLABEL_SHIFT) | |
1109 | ||
1110 | #define I40IWQPC_WSCALE_SHIFT 20 | |
1111 | #define I40IWQPC_WSCALE_MASK (1UL << I40IWQPC_WSCALE_SHIFT) | |
1112 | ||
1113 | #define I40IWQPC_KEEPALIVE_SHIFT 21 | |
1114 | #define I40IWQPC_KEEPALIVE_MASK (1UL << I40IWQPC_KEEPALIVE_SHIFT) | |
1115 | ||
1116 | #define I40IWQPC_IGNORE_TCP_OPT_SHIFT 22 | |
1117 | #define I40IWQPC_IGNORE_TCP_OPT_MASK (1UL << I40IWQPC_IGNORE_TCP_OPT_SHIFT) | |
1118 | ||
1119 | #define I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT 23 | |
1120 | #define I40IWQPC_IGNORE_TCP_UNS_OPT_MASK \ | |
1121 | (1UL << I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT) | |
1122 | ||
1123 | #define I40IWQPC_TCPSTATE_SHIFT 28 | |
1124 | #define I40IWQPC_TCPSTATE_MASK (0xfUL << I40IWQPC_TCPSTATE_SHIFT) | |
1125 | ||
1126 | #define I40IWQPC_RCVSCALE_SHIFT 32 | |
1127 | #define I40IWQPC_RCVSCALE_MASK (0xfULL << I40IWQPC_RCVSCALE_SHIFT) | |
1128 | ||
1129 | #define I40IWQPC_SNDSCALE_SHIFT 40 | |
1130 | #define I40IWQPC_SNDSCALE_MASK (0xfULL << I40IWQPC_SNDSCALE_SHIFT) | |
1131 | ||
1132 | #define I40IWQPC_PDIDX_SHIFT 48 | |
1133 | #define I40IWQPC_PDIDX_MASK (0x7fffULL << I40IWQPC_PDIDX_SHIFT) | |
1134 | ||
1135 | #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT 16 | |
1136 | #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_MASK \ | |
1137 | (0xffUL << I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT) | |
1138 | ||
1139 | #define I40IWQPC_KEEPALIVE_INTERVAL_SHIFT 24 | |
1140 | #define I40IWQPC_KEEPALIVE_INTERVAL_MASK \ | |
1141 | (0xffUL << I40IWQPC_KEEPALIVE_INTERVAL_SHIFT) | |
1142 | ||
1143 | #define I40IWQPC_TIMESTAMP_RECENT_SHIFT 0 | |
1144 | #define I40IWQPC_TIMESTAMP_RECENT_MASK \ | |
1145 | (0xffffffffUL << I40IWQPC_TIMESTAMP_RECENT_SHIFT) | |
1146 | ||
1147 | #define I40IWQPC_TIMESTAMP_AGE_SHIFT 32 | |
1148 | #define I40IWQPC_TIMESTAMP_AGE_MASK \ | |
1149 | (0xffffffffULL << I40IWQPC_TIMESTAMP_AGE_SHIFT) | |
1150 | ||
1151 | #define I40IWQPC_SNDNXT_SHIFT 0 | |
1152 | #define I40IWQPC_SNDNXT_MASK (0xffffffffUL << I40IWQPC_SNDNXT_SHIFT) | |
1153 | ||
1154 | #define I40IWQPC_SNDWND_SHIFT 32 | |
1155 | #define I40IWQPC_SNDWND_MASK (0xffffffffULL << I40IWQPC_SNDWND_SHIFT) | |
1156 | ||
1157 | #define I40IWQPC_RCVNXT_SHIFT 0 | |
1158 | #define I40IWQPC_RCVNXT_MASK (0xffffffffUL << I40IWQPC_RCVNXT_SHIFT) | |
1159 | ||
1160 | #define I40IWQPC_RCVWND_SHIFT 32 | |
1161 | #define I40IWQPC_RCVWND_MASK (0xffffffffULL << I40IWQPC_RCVWND_SHIFT) | |
1162 | ||
1163 | #define I40IWQPC_SNDMAX_SHIFT 0 | |
1164 | #define I40IWQPC_SNDMAX_MASK (0xffffffffUL << I40IWQPC_SNDMAX_SHIFT) | |
1165 | ||
1166 | #define I40IWQPC_SNDUNA_SHIFT 32 | |
1167 | #define I40IWQPC_SNDUNA_MASK (0xffffffffULL << I40IWQPC_SNDUNA_SHIFT) | |
1168 | ||
1169 | #define I40IWQPC_SRTT_SHIFT 0 | |
1170 | #define I40IWQPC_SRTT_MASK (0xffffffffUL << I40IWQPC_SRTT_SHIFT) | |
1171 | ||
1172 | #define I40IWQPC_RTTVAR_SHIFT 32 | |
1173 | #define I40IWQPC_RTTVAR_MASK (0xffffffffULL << I40IWQPC_RTTVAR_SHIFT) | |
1174 | ||
1175 | #define I40IWQPC_SSTHRESH_SHIFT 0 | |
1176 | #define I40IWQPC_SSTHRESH_MASK (0xffffffffUL << I40IWQPC_SSTHRESH_SHIFT) | |
1177 | ||
1178 | #define I40IWQPC_CWND_SHIFT 32 | |
1179 | #define I40IWQPC_CWND_MASK (0xffffffffULL << I40IWQPC_CWND_SHIFT) | |
1180 | ||
1181 | #define I40IWQPC_SNDWL1_SHIFT 0 | |
1182 | #define I40IWQPC_SNDWL1_MASK (0xffffffffUL << I40IWQPC_SNDWL1_SHIFT) | |
1183 | ||
1184 | #define I40IWQPC_SNDWL2_SHIFT 32 | |
1185 | #define I40IWQPC_SNDWL2_MASK (0xffffffffULL << I40IWQPC_SNDWL2_SHIFT) | |
1186 | ||
1187 | #define I40IWQPC_ERR_RQ_IDX_SHIFT 32 | |
1188 | #define I40IWQPC_ERR_RQ_IDX_MASK (0x3fffULL << I40IWQPC_ERR_RQ_IDX_SHIFT) | |
1189 | ||
1190 | #define I40IWQPC_MAXSNDWND_SHIFT 0 | |
1191 | #define I40IWQPC_MAXSNDWND_MASK (0xffffffffUL << I40IWQPC_MAXSNDWND_SHIFT) | |
1192 | ||
1193 | #define I40IWQPC_REXMIT_THRESH_SHIFT 48 | |
1194 | #define I40IWQPC_REXMIT_THRESH_MASK (0x3fULL << I40IWQPC_REXMIT_THRESH_SHIFT) | |
1195 | ||
1196 | #define I40IWQPC_TXCQNUM_SHIFT 0 | |
1197 | #define I40IWQPC_TXCQNUM_MASK (0x1ffffUL << I40IWQPC_TXCQNUM_SHIFT) | |
1198 | ||
1199 | #define I40IWQPC_RXCQNUM_SHIFT 32 | |
1200 | #define I40IWQPC_RXCQNUM_MASK (0x1ffffULL << I40IWQPC_RXCQNUM_SHIFT) | |
1201 | ||
1202 | #define I40IWQPC_Q2ADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1203 | #define I40IWQPC_Q2ADDR_MASK I40IW_CQPHC_QPCTX_MASK | |
1204 | ||
1205 | #define I40IWQPC_LASTBYTESENT_SHIFT 0 | |
1206 | #define I40IWQPC_LASTBYTESENT_MASK (0xffUL << I40IWQPC_LASTBYTESENT_SHIFT) | |
1207 | ||
1208 | #define I40IWQPC_SRQID_SHIFT 32 | |
1209 | #define I40IWQPC_SRQID_MASK (0xffULL << I40IWQPC_SRQID_SHIFT) | |
1210 | ||
1211 | #define I40IWQPC_ORDSIZE_SHIFT 0 | |
1212 | #define I40IWQPC_ORDSIZE_MASK (0x7fUL << I40IWQPC_ORDSIZE_SHIFT) | |
1213 | ||
1214 | #define I40IWQPC_IRDSIZE_SHIFT 16 | |
1215 | #define I40IWQPC_IRDSIZE_MASK (0x3UL << I40IWQPC_IRDSIZE_SHIFT) | |
1216 | ||
1217 | #define I40IWQPC_WRRDRSPOK_SHIFT 20 | |
1218 | #define I40IWQPC_WRRDRSPOK_MASK (1UL << I40IWQPC_WRRDRSPOK_SHIFT) | |
1219 | ||
1220 | #define I40IWQPC_RDOK_SHIFT 21 | |
1221 | #define I40IWQPC_RDOK_MASK (1UL << I40IWQPC_RDOK_SHIFT) | |
1222 | ||
1223 | #define I40IWQPC_SNDMARKERS_SHIFT 22 | |
1224 | #define I40IWQPC_SNDMARKERS_MASK (1UL << I40IWQPC_SNDMARKERS_SHIFT) | |
1225 | ||
1226 | #define I40IWQPC_BINDEN_SHIFT 23 | |
1227 | #define I40IWQPC_BINDEN_MASK (1UL << I40IWQPC_BINDEN_SHIFT) | |
1228 | ||
1229 | #define I40IWQPC_FASTREGEN_SHIFT 24 | |
1230 | #define I40IWQPC_FASTREGEN_MASK (1UL << I40IWQPC_FASTREGEN_SHIFT) | |
1231 | ||
1232 | #define I40IWQPC_PRIVEN_SHIFT 25 | |
1233 | #define I40IWQPC_PRIVEN_MASK (1UL << I40IWQPC_PRIVEN_SHIFT) | |
1234 | ||
1235 | #define I40IWQPC_LSMMPRESENT_SHIFT 26 | |
1236 | #define I40IWQPC_LSMMPRESENT_MASK (1UL << I40IWQPC_LSMMPRESENT_SHIFT) | |
1237 | ||
1238 | #define I40IWQPC_ADJUSTFORLSMM_SHIFT 27 | |
1239 | #define I40IWQPC_ADJUSTFORLSMM_MASK (1UL << I40IWQPC_ADJUSTFORLSMM_SHIFT) | |
1240 | ||
1241 | #define I40IWQPC_IWARPMODE_SHIFT 28 | |
1242 | #define I40IWQPC_IWARPMODE_MASK (1UL << I40IWQPC_IWARPMODE_SHIFT) | |
1243 | ||
1244 | #define I40IWQPC_RCVMARKERS_SHIFT 29 | |
1245 | #define I40IWQPC_RCVMARKERS_MASK (1UL << I40IWQPC_RCVMARKERS_SHIFT) | |
1246 | ||
1247 | #define I40IWQPC_ALIGNHDRS_SHIFT 30 | |
1248 | #define I40IWQPC_ALIGNHDRS_MASK (1UL << I40IWQPC_ALIGNHDRS_SHIFT) | |
1249 | ||
1250 | #define I40IWQPC_RCVNOMPACRC_SHIFT 31 | |
1251 | #define I40IWQPC_RCVNOMPACRC_MASK (1UL << I40IWQPC_RCVNOMPACRC_SHIFT) | |
1252 | ||
1253 | #define I40IWQPC_RCVMARKOFFSET_SHIFT 33 | |
1254 | #define I40IWQPC_RCVMARKOFFSET_MASK (0x1ffULL << I40IWQPC_RCVMARKOFFSET_SHIFT) | |
1255 | ||
1256 | #define I40IWQPC_SNDMARKOFFSET_SHIFT 48 | |
1257 | #define I40IWQPC_SNDMARKOFFSET_MASK (0x1ffULL << I40IWQPC_SNDMARKOFFSET_SHIFT) | |
1258 | ||
1259 | #define I40IWQPC_QPCOMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1260 | #define I40IWQPC_QPCOMPCTX_MASK I40IW_CQPHC_QPCTX_MASK | |
1261 | ||
1262 | #define I40IWQPC_SQTPHVAL_SHIFT 0 | |
1263 | #define I40IWQPC_SQTPHVAL_MASK (0xffUL << I40IWQPC_SQTPHVAL_SHIFT) | |
1264 | ||
1265 | #define I40IWQPC_RQTPHVAL_SHIFT 8 | |
1266 | #define I40IWQPC_RQTPHVAL_MASK (0xffUL << I40IWQPC_RQTPHVAL_SHIFT) | |
1267 | ||
1268 | #define I40IWQPC_QSHANDLE_SHIFT 16 | |
1269 | #define I40IWQPC_QSHANDLE_MASK (0x3ffUL << I40IWQPC_QSHANDLE_SHIFT) | |
1270 | ||
1271 | #define I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT 32 | |
1272 | #define I40IWQPC_EXCEPTION_LAN_QUEUE_MASK (0xfffULL << \ | |
1273 | I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT) | |
1274 | ||
1275 | #define I40IWQPC_LOCAL_IPADDR3_SHIFT 0 | |
1276 | #define I40IWQPC_LOCAL_IPADDR3_MASK \ | |
1277 | (0xffffffffUL << I40IWQPC_LOCAL_IPADDR3_SHIFT) | |
1278 | ||
1279 | #define I40IWQPC_LOCAL_IPADDR2_SHIFT 32 | |
1280 | #define I40IWQPC_LOCAL_IPADDR2_MASK \ | |
1281 | (0xffffffffULL << I40IWQPC_LOCAL_IPADDR2_SHIFT) | |
1282 | ||
1283 | #define I40IWQPC_LOCAL_IPADDR1_SHIFT 0 | |
1284 | #define I40IWQPC_LOCAL_IPADDR1_MASK \ | |
1285 | (0xffffffffUL << I40IWQPC_LOCAL_IPADDR1_SHIFT) | |
1286 | ||
1287 | #define I40IWQPC_LOCAL_IPADDR0_SHIFT 32 | |
1288 | #define I40IWQPC_LOCAL_IPADDR0_MASK \ | |
1289 | (0xffffffffULL << I40IWQPC_LOCAL_IPADDR0_SHIFT) | |
1290 | ||
1291 | /* wqe size considering 32 bytes per wqe*/ | |
1292 | #define I40IWQP_SW_MIN_WQSIZE 4 /* 128 bytes */ | |
23ef48ad | 1293 | #define I40IWQP_SW_MAX_WQSIZE 2048 /* 2048 bytes */ |
89517b55 FL |
1294 | |
1295 | #define I40IWQP_OP_RDMA_WRITE 0 | |
1296 | #define I40IWQP_OP_RDMA_READ 1 | |
1297 | #define I40IWQP_OP_RDMA_SEND 3 | |
1298 | #define I40IWQP_OP_RDMA_SEND_INV 4 | |
1299 | #define I40IWQP_OP_RDMA_SEND_SOL_EVENT 5 | |
1300 | #define I40IWQP_OP_RDMA_SEND_SOL_EVENT_INV 6 | |
1301 | #define I40IWQP_OP_BIND_MW 8 | |
1302 | #define I40IWQP_OP_FAST_REGISTER 9 | |
1303 | #define I40IWQP_OP_LOCAL_INVALIDATE 10 | |
1304 | #define I40IWQP_OP_RDMA_READ_LOC_INV 11 | |
1305 | #define I40IWQP_OP_NOP 12 | |
1306 | ||
1307 | #define I40IW_RSVD_SHIFT 41 | |
1308 | #define I40IW_RSVD_MASK (0x7fffULL << I40IW_RSVD_SHIFT) | |
1309 | ||
1310 | /* iwarp QP SQ WQE common fields */ | |
1311 | #define I40IWQPSQ_OPCODE_SHIFT 32 | |
1312 | #define I40IWQPSQ_OPCODE_MASK (0x3fULL << I40IWQPSQ_OPCODE_SHIFT) | |
1313 | ||
1314 | #define I40IWQPSQ_ADDFRAGCNT_SHIFT 38 | |
1315 | #define I40IWQPSQ_ADDFRAGCNT_MASK (0x7ULL << I40IWQPSQ_ADDFRAGCNT_SHIFT) | |
1316 | ||
1317 | #define I40IWQPSQ_PUSHWQE_SHIFT 56 | |
1318 | #define I40IWQPSQ_PUSHWQE_MASK (1ULL << I40IWQPSQ_PUSHWQE_SHIFT) | |
1319 | ||
1320 | #define I40IWQPSQ_STREAMMODE_SHIFT 58 | |
1321 | #define I40IWQPSQ_STREAMMODE_MASK (1ULL << I40IWQPSQ_STREAMMODE_SHIFT) | |
1322 | ||
1323 | #define I40IWQPSQ_WAITFORRCVPDU_SHIFT 59 | |
1324 | #define I40IWQPSQ_WAITFORRCVPDU_MASK (1ULL << I40IWQPSQ_WAITFORRCVPDU_SHIFT) | |
1325 | ||
1326 | #define I40IWQPSQ_READFENCE_SHIFT 60 | |
1327 | #define I40IWQPSQ_READFENCE_MASK (1ULL << I40IWQPSQ_READFENCE_SHIFT) | |
1328 | ||
1329 | #define I40IWQPSQ_LOCALFENCE_SHIFT 61 | |
1330 | #define I40IWQPSQ_LOCALFENCE_MASK (1ULL << I40IWQPSQ_LOCALFENCE_SHIFT) | |
1331 | ||
1332 | #define I40IWQPSQ_SIGCOMPL_SHIFT 62 | |
1333 | #define I40IWQPSQ_SIGCOMPL_MASK (1ULL << I40IWQPSQ_SIGCOMPL_SHIFT) | |
1334 | ||
1335 | #define I40IWQPSQ_VALID_SHIFT 63 | |
1336 | #define I40IWQPSQ_VALID_MASK (1ULL << I40IWQPSQ_VALID_SHIFT) | |
1337 | ||
1338 | #define I40IWQPSQ_FRAG_TO_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1339 | #define I40IWQPSQ_FRAG_TO_MASK I40IW_CQPHC_QPCTX_MASK | |
1340 | ||
1341 | #define I40IWQPSQ_FRAG_LEN_SHIFT 0 | |
1342 | #define I40IWQPSQ_FRAG_LEN_MASK (0xffffffffUL << I40IWQPSQ_FRAG_LEN_SHIFT) | |
1343 | ||
1344 | #define I40IWQPSQ_FRAG_STAG_SHIFT 32 | |
1345 | #define I40IWQPSQ_FRAG_STAG_MASK (0xffffffffULL << I40IWQPSQ_FRAG_STAG_SHIFT) | |
1346 | ||
1347 | #define I40IWQPSQ_REMSTAGINV_SHIFT 0 | |
1348 | #define I40IWQPSQ_REMSTAGINV_MASK (0xffffffffUL << I40IWQPSQ_REMSTAGINV_SHIFT) | |
1349 | ||
1350 | #define I40IWQPSQ_INLINEDATAFLAG_SHIFT 57 | |
1351 | #define I40IWQPSQ_INLINEDATAFLAG_MASK (1ULL << I40IWQPSQ_INLINEDATAFLAG_SHIFT) | |
1352 | ||
1353 | #define I40IWQPSQ_INLINEDATALEN_SHIFT 48 | |
1354 | #define I40IWQPSQ_INLINEDATALEN_MASK \ | |
1355 | (0x7fULL << I40IWQPSQ_INLINEDATALEN_SHIFT) | |
1356 | ||
1357 | /* iwarp send with push mode */ | |
1358 | #define I40IWQPSQ_WQDESCIDX_SHIFT 0 | |
1359 | #define I40IWQPSQ_WQDESCIDX_MASK (0x3fffUL << I40IWQPSQ_WQDESCIDX_SHIFT) | |
1360 | ||
1361 | /* rdma write */ | |
1362 | #define I40IWQPSQ_REMSTAG_SHIFT 0 | |
1363 | #define I40IWQPSQ_REMSTAG_MASK (0xffffffffUL << I40IWQPSQ_REMSTAG_SHIFT) | |
1364 | ||
1365 | #define I40IWQPSQ_REMTO_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1366 | #define I40IWQPSQ_REMTO_MASK I40IW_CQPHC_QPCTX_MASK | |
1367 | ||
1368 | /* memory window */ | |
1369 | #define I40IWQPSQ_STAGRIGHTS_SHIFT 48 | |
1370 | #define I40IWQPSQ_STAGRIGHTS_MASK (0x1fULL << I40IWQPSQ_STAGRIGHTS_SHIFT) | |
1371 | ||
1372 | #define I40IWQPSQ_VABASEDTO_SHIFT 53 | |
1373 | #define I40IWQPSQ_VABASEDTO_MASK (1ULL << I40IWQPSQ_VABASEDTO_SHIFT) | |
1374 | ||
1375 | #define I40IWQPSQ_MWLEN_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1376 | #define I40IWQPSQ_MWLEN_MASK I40IW_CQPHC_QPCTX_MASK | |
1377 | ||
1378 | #define I40IWQPSQ_PARENTMRSTAG_SHIFT 0 | |
1379 | #define I40IWQPSQ_PARENTMRSTAG_MASK \ | |
1380 | (0xffffffffUL << I40IWQPSQ_PARENTMRSTAG_SHIFT) | |
1381 | ||
1382 | #define I40IWQPSQ_MWSTAG_SHIFT 32 | |
1383 | #define I40IWQPSQ_MWSTAG_MASK (0xffffffffULL << I40IWQPSQ_MWSTAG_SHIFT) | |
1384 | ||
1385 | #define I40IWQPSQ_BASEVA_TO_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1386 | #define I40IWQPSQ_BASEVA_TO_FBO_MASK I40IW_CQPHC_QPCTX_MASK | |
1387 | ||
1388 | /* Local Invalidate */ | |
1389 | #define I40IWQPSQ_LOCSTAG_SHIFT 32 | |
1390 | #define I40IWQPSQ_LOCSTAG_MASK (0xffffffffULL << I40IWQPSQ_LOCSTAG_SHIFT) | |
1391 | ||
1392 | /* Fast Register */ | |
1393 | #define I40IWQPSQ_STAGKEY_SHIFT 0 | |
1394 | #define I40IWQPSQ_STAGKEY_MASK (0xffUL << I40IWQPSQ_STAGKEY_SHIFT) | |
1395 | ||
1396 | #define I40IWQPSQ_STAGINDEX_SHIFT 8 | |
1397 | #define I40IWQPSQ_STAGINDEX_MASK (0xffffffUL << I40IWQPSQ_STAGINDEX_SHIFT) | |
1398 | ||
1399 | #define I40IWQPSQ_COPYHOSTPBLS_SHIFT 43 | |
1400 | #define I40IWQPSQ_COPYHOSTPBLS_MASK (1ULL << I40IWQPSQ_COPYHOSTPBLS_SHIFT) | |
1401 | ||
1402 | #define I40IWQPSQ_LPBLSIZE_SHIFT 44 | |
1403 | #define I40IWQPSQ_LPBLSIZE_MASK (3ULL << I40IWQPSQ_LPBLSIZE_SHIFT) | |
1404 | ||
1405 | #define I40IWQPSQ_HPAGESIZE_SHIFT 46 | |
1406 | #define I40IWQPSQ_HPAGESIZE_MASK (3ULL << I40IWQPSQ_HPAGESIZE_SHIFT) | |
1407 | ||
1408 | #define I40IWQPSQ_STAGLEN_SHIFT 0 | |
1409 | #define I40IWQPSQ_STAGLEN_MASK (0x1ffffffffffULL << I40IWQPSQ_STAGLEN_SHIFT) | |
1410 | ||
1411 | #define I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT 48 | |
1412 | #define I40IWQPSQ_FIRSTPMPBLIDXLO_MASK \ | |
1413 | (0xffffULL << I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT) | |
1414 | ||
1415 | #define I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT 0 | |
1416 | #define I40IWQPSQ_FIRSTPMPBLIDXHI_MASK \ | |
1417 | (0xfffUL << I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT) | |
1418 | ||
1419 | #define I40IWQPSQ_PBLADDR_SHIFT 12 | |
1420 | #define I40IWQPSQ_PBLADDR_MASK (0xfffffffffffffULL << I40IWQPSQ_PBLADDR_SHIFT) | |
1421 | ||
1422 | /* iwarp QP RQ WQE common fields */ | |
1423 | #define I40IWQPRQ_ADDFRAGCNT_SHIFT I40IWQPSQ_ADDFRAGCNT_SHIFT | |
1424 | #define I40IWQPRQ_ADDFRAGCNT_MASK I40IWQPSQ_ADDFRAGCNT_MASK | |
1425 | ||
1426 | #define I40IWQPRQ_VALID_SHIFT I40IWQPSQ_VALID_SHIFT | |
1427 | #define I40IWQPRQ_VALID_MASK I40IWQPSQ_VALID_MASK | |
1428 | ||
1429 | #define I40IWQPRQ_COMPLCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT | |
1430 | #define I40IWQPRQ_COMPLCTX_MASK I40IW_CQPHC_QPCTX_MASK | |
1431 | ||
1432 | #define I40IWQPRQ_FRAG_LEN_SHIFT I40IWQPSQ_FRAG_LEN_SHIFT | |
1433 | #define I40IWQPRQ_FRAG_LEN_MASK I40IWQPSQ_FRAG_LEN_MASK | |
1434 | ||
1435 | #define I40IWQPRQ_STAG_SHIFT I40IWQPSQ_FRAG_STAG_SHIFT | |
1436 | #define I40IWQPRQ_STAG_MASK I40IWQPSQ_FRAG_STAG_MASK | |
1437 | ||
1438 | #define I40IWQPRQ_TO_SHIFT I40IWQPSQ_FRAG_TO_SHIFT | |
1439 | #define I40IWQPRQ_TO_MASK I40IWQPSQ_FRAG_TO_MASK | |
1440 | ||
1441 | /* Query FPM CQP buf */ | |
1442 | #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0 | |
1443 | #define I40IW_QUERY_FPM_MAX_QPS_MASK \ | |
1444 | (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT) | |
1445 | ||
1446 | #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0 | |
1447 | #define I40IW_QUERY_FPM_MAX_CQS_MASK \ | |
1448 | (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT) | |
1449 | ||
1450 | #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT 0 | |
1451 | #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_MASK \ | |
1452 | (0x3fffUL << I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT) | |
1453 | ||
1454 | #define I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT 32 | |
1455 | #define I40IW_QUERY_FPM_MAX_PE_SDS_MASK \ | |
1456 | (0x3fffULL << I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT) | |
1457 | ||
1458 | #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0 | |
1459 | #define I40IW_QUERY_FPM_MAX_QPS_MASK \ | |
1460 | (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT) | |
1461 | ||
1462 | #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0 | |
1463 | #define I40IW_QUERY_FPM_MAX_CQS_MASK \ | |
1464 | (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT) | |
1465 | ||
1466 | #define I40IW_QUERY_FPM_MAX_CEQS_SHIFT 0 | |
1467 | #define I40IW_QUERY_FPM_MAX_CEQS_MASK \ | |
1468 | (0xffUL << I40IW_QUERY_FPM_MAX_CEQS_SHIFT) | |
1469 | ||
1470 | #define I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT 32 | |
1471 | #define I40IW_QUERY_FPM_XFBLOCKSIZE_MASK \ | |
1472 | (0xffffffffULL << I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT) | |
1473 | ||
1474 | #define I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT 32 | |
1475 | #define I40IW_QUERY_FPM_Q1BLOCKSIZE_MASK \ | |
1476 | (0xffffffffULL << I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT) | |
1477 | ||
1478 | #define I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT 16 | |
1479 | #define I40IW_QUERY_FPM_HTMULTIPLIER_MASK \ | |
1480 | (0xfUL << I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT) | |
1481 | ||
1482 | #define I40IW_QUERY_FPM_TIMERBUCKET_SHIFT 32 | |
1483 | #define I40IW_QUERY_FPM_TIMERBUCKET_MASK \ | |
1484 | (0xffFFULL << I40IW_QUERY_FPM_TIMERBUCKET_SHIFT) | |
1485 | ||
1486 | /* Static HMC pages allocated buf */ | |
1487 | #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT 0 | |
1488 | #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_MASK \ | |
1489 | (0x3fUL << I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT) | |
1490 | ||
1491 | #define I40IW_HW_PAGE_SIZE 4096 | |
1492 | #define I40IW_DONE_COUNT 1000 | |
1493 | #define I40IW_SLEEP_COUNT 10 | |
1494 | ||
1495 | enum { | |
1496 | I40IW_QUEUES_ALIGNMENT_MASK = (128 - 1), | |
1497 | I40IW_AEQ_ALIGNMENT_MASK = (256 - 1), | |
1498 | I40IW_Q2_ALIGNMENT_MASK = (256 - 1), | |
1499 | I40IW_CEQ_ALIGNMENT_MASK = (256 - 1), | |
1500 | I40IW_CQ0_ALIGNMENT_MASK = (256 - 1), | |
1501 | I40IW_HOST_CTX_ALIGNMENT_MASK = (4 - 1), | |
1502 | I40IW_SHADOWAREA_MASK = (128 - 1), | |
1503 | I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK = 0, | |
1504 | I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK = 0 | |
1505 | }; | |
1506 | ||
1507 | enum i40iw_alignment { | |
1508 | I40IW_CQP_ALIGNMENT = 0x200, | |
1509 | I40IW_AEQ_ALIGNMENT = 0x100, | |
1510 | I40IW_CEQ_ALIGNMENT = 0x100, | |
1511 | I40IW_CQ0_ALIGNMENT = 0x100, | |
1512 | I40IW_SD_BUF_ALIGNMENT = 0x100 | |
1513 | }; | |
1514 | ||
9510b066 SS |
1515 | #define I40IW_WQE_SIZE_64 64 |
1516 | ||
89517b55 FL |
1517 | #define I40IW_QP_WQE_MIN_SIZE 32 |
1518 | #define I40IW_QP_WQE_MAX_SIZE 128 | |
1519 | ||
1520 | #define I40IW_CQE_QTYPE_RQ 0 | |
1521 | #define I40IW_CQE_QTYPE_SQ 1 | |
1522 | ||
1523 | #define I40IW_RING_INIT(_ring, _size) \ | |
1524 | { \ | |
1525 | (_ring).head = 0; \ | |
1526 | (_ring).tail = 0; \ | |
1527 | (_ring).size = (_size); \ | |
1528 | } | |
1529 | #define I40IW_RING_GETSIZE(_ring) ((_ring).size) | |
1530 | #define I40IW_RING_GETCURRENT_HEAD(_ring) ((_ring).head) | |
1531 | #define I40IW_RING_GETCURRENT_TAIL(_ring) ((_ring).tail) | |
1532 | ||
1533 | #define I40IW_RING_MOVE_HEAD(_ring, _retcode) \ | |
1534 | { \ | |
1535 | register u32 size; \ | |
1536 | size = (_ring).size; \ | |
1537 | if (!I40IW_RING_FULL_ERR(_ring)) { \ | |
1538 | (_ring).head = ((_ring).head + 1) % size; \ | |
1539 | (_retcode) = 0; \ | |
1540 | } else { \ | |
1541 | (_retcode) = I40IW_ERR_RING_FULL; \ | |
1542 | } \ | |
1543 | } | |
1544 | ||
1545 | #define I40IW_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ | |
1546 | { \ | |
1547 | register u32 size; \ | |
1548 | size = (_ring).size; \ | |
1549 | if ((I40IW_RING_WORK_AVAILABLE(_ring) + (_count)) < size) { \ | |
1550 | (_ring).head = ((_ring).head + (_count)) % size; \ | |
1551 | (_retcode) = 0; \ | |
1552 | } else { \ | |
1553 | (_retcode) = I40IW_ERR_RING_FULL; \ | |
1554 | } \ | |
1555 | } | |
1556 | ||
1557 | #define I40IW_RING_MOVE_TAIL(_ring) \ | |
1558 | (_ring).tail = ((_ring).tail + 1) % (_ring).size | |
1559 | ||
c5d057d3 MI |
1560 | #define I40IW_RING_MOVE_HEAD_NOCHECK(_ring) \ |
1561 | (_ring).head = ((_ring).head + 1) % (_ring).size | |
1562 | ||
89517b55 FL |
1563 | #define I40IW_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \ |
1564 | (_ring).tail = ((_ring).tail + (_count)) % (_ring).size | |
1565 | ||
1566 | #define I40IW_RING_SET_TAIL(_ring, _pos) \ | |
1567 | (_ring).tail = (_pos) % (_ring).size | |
1568 | ||
1569 | #define I40IW_RING_FULL_ERR(_ring) \ | |
1570 | ( \ | |
1571 | (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 1)) \ | |
1572 | ) | |
1573 | ||
1574 | #define I40IW_ERR_RING_FULL2(_ring) \ | |
1575 | ( \ | |
1576 | (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 2)) \ | |
1577 | ) | |
1578 | ||
1579 | #define I40IW_ERR_RING_FULL3(_ring) \ | |
1580 | ( \ | |
1581 | (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 3)) \ | |
1582 | ) | |
1583 | ||
1584 | #define I40IW_RING_MORE_WORK(_ring) \ | |
1585 | ( \ | |
1586 | (I40IW_RING_WORK_AVAILABLE(_ring) != 0) \ | |
1587 | ) | |
1588 | ||
1589 | #define I40IW_RING_WORK_AVAILABLE(_ring) \ | |
1590 | ( \ | |
1591 | (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \ | |
1592 | ) | |
1593 | ||
1594 | #define I40IW_RING_GET_WQES_AVAILABLE(_ring) \ | |
1595 | ( \ | |
1596 | ((_ring).size - I40IW_RING_WORK_AVAILABLE(_ring) - 1) \ | |
1597 | ) | |
1598 | ||
1599 | #define I40IW_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \ | |
1600 | { \ | |
1601 | index = I40IW_RING_GETCURRENT_HEAD(_ring); \ | |
1602 | I40IW_RING_MOVE_HEAD(_ring, _retcode); \ | |
1603 | } | |
1604 | ||
1605 | /* Async Events codes */ | |
1606 | #define I40IW_AE_AMP_UNALLOCATED_STAG 0x0102 | |
1607 | #define I40IW_AE_AMP_INVALID_STAG 0x0103 | |
1608 | #define I40IW_AE_AMP_BAD_QP 0x0104 | |
1609 | #define I40IW_AE_AMP_BAD_PD 0x0105 | |
1610 | #define I40IW_AE_AMP_BAD_STAG_KEY 0x0106 | |
1611 | #define I40IW_AE_AMP_BAD_STAG_INDEX 0x0107 | |
1612 | #define I40IW_AE_AMP_BOUNDS_VIOLATION 0x0108 | |
1613 | #define I40IW_AE_AMP_RIGHTS_VIOLATION 0x0109 | |
1614 | #define I40IW_AE_AMP_TO_WRAP 0x010a | |
1615 | #define I40IW_AE_AMP_FASTREG_SHARED 0x010b | |
1616 | #define I40IW_AE_AMP_FASTREG_VALID_STAG 0x010c | |
1617 | #define I40IW_AE_AMP_FASTREG_MW_STAG 0x010d | |
1618 | #define I40IW_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e | |
1619 | #define I40IW_AE_AMP_FASTREG_PBL_TABLE_OVERFLOW 0x010f | |
1620 | #define I40IW_AE_AMP_FASTREG_INVALID_LENGTH 0x0110 | |
1621 | #define I40IW_AE_AMP_INVALIDATE_SHARED 0x0111 | |
1622 | #define I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112 | |
1623 | #define I40IW_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113 | |
1624 | #define I40IW_AE_AMP_MWBIND_VALID_STAG 0x0114 | |
1625 | #define I40IW_AE_AMP_MWBIND_OF_MR_STAG 0x0115 | |
1626 | #define I40IW_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116 | |
1627 | #define I40IW_AE_AMP_MWBIND_TO_MW_STAG 0x0117 | |
1628 | #define I40IW_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118 | |
1629 | #define I40IW_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 | |
1630 | #define I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a | |
1631 | #define I40IW_AE_AMP_MWBIND_BIND_DISABLED 0x011b | |
1632 | #define I40IW_AE_AMP_WQE_INVALID_PARAMETER 0x0130 | |
1633 | #define I40IW_AE_BAD_CLOSE 0x0201 | |
1634 | #define I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 | |
1635 | #define I40IW_AE_CQ_OPERATION_ERROR 0x0203 | |
1636 | #define I40IW_AE_PRIV_OPERATION_DENIED 0x011c | |
1637 | #define I40IW_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 | |
1638 | #define I40IW_AE_STAG_ZERO_INVALID 0x0206 | |
1639 | #define I40IW_AE_IB_RREQ_AND_Q1_FULL 0x0207 | |
1640 | #define I40IW_AE_SRQ_LIMIT 0x0209 | |
1641 | #define I40IW_AE_WQE_UNEXPECTED_OPCODE 0x020a | |
1642 | #define I40IW_AE_WQE_INVALID_PARAMETER 0x020b | |
1643 | #define I40IW_AE_WQE_LSMM_TOO_LONG 0x0220 | |
1644 | #define I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 | |
1645 | #define I40IW_AE_DDP_INVALID_MSN_RANGE_IS_NOT_VALID 0x0302 | |
1646 | #define I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 | |
1647 | #define I40IW_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 | |
1648 | #define I40IW_AE_DDP_UBE_INVALID_MO 0x0305 | |
1649 | #define I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306 | |
1650 | #define I40IW_AE_DDP_UBE_INVALID_QN 0x0307 | |
1651 | #define I40IW_AE_DDP_NO_L_BIT 0x0308 | |
1652 | #define I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311 | |
1653 | #define I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312 | |
1654 | #define I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313 | |
1655 | #define I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314 | |
1656 | #define I40IW_AE_INVALID_ARP_ENTRY 0x0401 | |
1657 | #define I40IW_AE_INVALID_TCP_OPTION_RCVD 0x0402 | |
1658 | #define I40IW_AE_STALE_ARP_ENTRY 0x0403 | |
1659 | #define I40IW_AE_INVALID_WQE_LENGTH 0x0404 | |
1660 | #define I40IW_AE_INVALID_MAC_ENTRY 0x0405 | |
1661 | #define I40IW_AE_LLP_CLOSE_COMPLETE 0x0501 | |
1662 | #define I40IW_AE_LLP_CONNECTION_RESET 0x0502 | |
1663 | #define I40IW_AE_LLP_FIN_RECEIVED 0x0503 | |
1664 | #define I40IW_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504 | |
1665 | #define I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 | |
1666 | #define I40IW_AE_LLP_SEGMENT_TOO_LARGE 0x0506 | |
1667 | #define I40IW_AE_LLP_SEGMENT_TOO_SMALL 0x0507 | |
1668 | #define I40IW_AE_LLP_SYN_RECEIVED 0x0508 | |
1669 | #define I40IW_AE_LLP_TERMINATE_RECEIVED 0x0509 | |
1670 | #define I40IW_AE_LLP_TOO_MANY_RETRIES 0x050a | |
1671 | #define I40IW_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b | |
1672 | #define I40IW_AE_LLP_DOUBT_REACHABILITY 0x050c | |
1673 | #define I40IW_AE_LLP_RX_VLAN_MISMATCH 0x050d | |
1674 | #define I40IW_AE_RESOURCE_EXHAUSTION 0x0520 | |
1675 | #define I40IW_AE_RESET_SENT 0x0601 | |
1676 | #define I40IW_AE_TERMINATE_SENT 0x0602 | |
1677 | #define I40IW_AE_RESET_NOT_SENT 0x0603 | |
1678 | #define I40IW_AE_LCE_QP_CATASTROPHIC 0x0700 | |
1679 | #define I40IW_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 | |
1680 | #define I40IW_AE_LCE_CQ_CATASTROPHIC 0x0702 | |
1681 | #define I40IW_AE_UDA_XMIT_FRAG_SEQ 0x0800 | |
1682 | #define I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0801 | |
1683 | #define I40IW_AE_UDA_XMIT_IPADDR_MISMATCH 0x0802 | |
1684 | #define I40IW_AE_QP_SUSPEND_COMPLETE 0x0900 | |
1685 | ||
1686 | #define OP_DELETE_LOCAL_MAC_IPADDR_ENTRY 1 | |
1687 | #define OP_CEQ_DESTROY 2 | |
1688 | #define OP_AEQ_DESTROY 3 | |
1689 | #define OP_DELETE_ARP_CACHE_ENTRY 4 | |
1690 | #define OP_MANAGE_APBVT_ENTRY 5 | |
1691 | #define OP_CEQ_CREATE 6 | |
1692 | #define OP_AEQ_CREATE 7 | |
1693 | #define OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY 8 | |
1694 | #define OP_ADD_LOCAL_MAC_IPADDR_ENTRY 9 | |
1695 | #define OP_MANAGE_QHASH_TABLE_ENTRY 10 | |
1696 | #define OP_QP_MODIFY 11 | |
1697 | #define OP_QP_UPLOAD_CONTEXT 12 | |
1698 | #define OP_CQ_CREATE 13 | |
1699 | #define OP_CQ_DESTROY 14 | |
1700 | #define OP_QP_CREATE 15 | |
1701 | #define OP_QP_DESTROY 16 | |
1702 | #define OP_ALLOC_STAG 17 | |
1703 | #define OP_MR_REG_NON_SHARED 18 | |
1704 | #define OP_DEALLOC_STAG 19 | |
1705 | #define OP_MW_ALLOC 20 | |
1706 | #define OP_QP_FLUSH_WQES 21 | |
1707 | #define OP_ADD_ARP_CACHE_ENTRY 22 | |
1708 | #define OP_MANAGE_PUSH_PAGE 23 | |
1709 | #define OP_UPDATE_PE_SDS 24 | |
1710 | #define OP_MANAGE_HMC_PM_FUNC_TABLE 25 | |
1711 | #define OP_SUSPEND 26 | |
1712 | #define OP_RESUME 27 | |
1713 | #define OP_MANAGE_VF_PBLE_BP 28 | |
1714 | #define OP_QUERY_FPM_VALUES 29 | |
1715 | #define OP_COMMIT_FPM_VALUES 30 | |
1716 | #define OP_SIZE_CQP_STAT_ARRAY 31 | |
1717 | ||
1718 | #endif |