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[PATCH] IB/ipath: use vmalloc to allocate struct ipath_devdata
[deliverable/linux.git] / drivers / infiniband / hw / ipath / ipath_kernel.h
CommitLineData
d41d3aeb
BS		 1#ifndef _IPATH_KERNEL_H
2#define _IPATH_KERNEL_H
3/*
759d5768 4 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
d41d3aeb
BS		 5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36/*
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
39 */
40
41#include <linux/interrupt.h>
42#include <asm/io.h>
43
44#include "ipath_common.h"
45#include "ipath_debug.h"
46#include "ipath_registers.h"
47
48/* only s/w major version of InfiniPath we can handle */
49#define IPATH_CHIP_VERS_MAJ 2U
50
51/* don't care about this except printing */
52#define IPATH_CHIP_VERS_MIN 0U
53
54/* temporary, maybe always */
55extern struct infinipath_stats ipath_stats;
56
57#define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
58
59struct ipath_portdata {
60 void **port_rcvegrbuf;
61 dma_addr_t *port_rcvegrbuf_phys;
62 /* rcvhdrq base, needs mmap before useful */
63 void *port_rcvhdrq;
64 /* kernel virtual address where hdrqtail is updated */
65 u64 *port_rcvhdrtail_kvaddr;
66 /* page * used for uaddr */
67 struct page *port_rcvhdrtail_pagep;
68 /*
69 * temp buffer for expected send setup, allocated at open, instead
70 * of each setup call
71 */
72 void *port_tid_pg_list;
73 /* when waiting for rcv or pioavail */
74 wait_queue_head_t port_wait;
75 /*
76 * rcvegr bufs base, physical, must fit
77 * in 44 bits so 32 bit programs mmap64 44 bit works)
78 */
79 dma_addr_t port_rcvegr_phys;
80 /* mmap of hdrq, must fit in 44 bits */
81 dma_addr_t port_rcvhdrq_phys;
82 /*
83 * the actual user address that we ipath_mlock'ed, so we can
84 * ipath_munlock it at close
85 */
86 unsigned long port_rcvhdrtail_uaddr;
87 /*
88 * number of opens on this instance (0 or 1; ignoring forks, dup,
89 * etc. for now)
90 */
91 int port_cnt;
92 /*
93 * how much space to leave at start of eager TID entries for
94 * protocol use, on each TID
95 */
96 /* instead of calculating it */
97 unsigned port_port;
98 /* chip offset of PIO buffers for this port */
99 u32 port_piobufs;
100 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
101 u32 port_rcvegrbuf_chunks;
102 /* how many egrbufs per chunk */
103 u32 port_rcvegrbufs_perchunk;
104 /* order for port_rcvegrbuf_pages */
105 size_t port_rcvegrbuf_size;
106 /* rcvhdrq size (for freeing) */
107 size_t port_rcvhdrq_size;
108 /* next expected TID to check when looking for free */
109 u32 port_tidcursor;
110 /* next expected TID to check */
111 unsigned long port_flag;
112 /* WAIT_RCV that timed out, no interrupt */
113 u32 port_rcvwait_to;
114 /* WAIT_PIO that timed out, no interrupt */
115 u32 port_piowait_to;
116 /* WAIT_RCV already happened, no wait */
117 u32 port_rcvnowait;
118 /* WAIT_PIO already happened, no wait */
119 u32 port_pionowait;
120 /* total number of rcvhdrqfull errors */
121 u32 port_hdrqfull;
122 /* pid of process using this port */
123 pid_t port_pid;
124 /* same size as task_struct .comm[] */
125 char port_comm[16];
126 /* pkeys set by this use of this port */
127 u16 port_pkeys[4];
128 /* so file ops can get at unit */
129 struct ipath_devdata *port_dd;
130};
131
132struct sk_buff;
133
134/*
135 * control information for layered drivers
136 */
137struct _ipath_layer {
138 void *l_arg;
139};
140
141/* Verbs layer interface */
142struct _verbs_layer {
143 void *l_arg;
144 struct timer_list l_timer;
145};
146
147struct ipath_devdata {
148 struct list_head ipath_list;
149
150 struct ipath_kregs const *ipath_kregs;
151 struct ipath_cregs const *ipath_cregs;
152
153 /* mem-mapped pointer to base of chip regs */
154 u64 __iomem *ipath_kregbase;
155 /* end of mem-mapped chip space; range checking */
156 u64 __iomem *ipath_kregend;
157 /* physical address of chip for io_remap, etc. */
158 unsigned long ipath_physaddr;
159 /* base of memory alloced for ipath_kregbase, for free */
160 u64 *ipath_kregalloc;
d41d3aeb
BS		 161 /*
162 * virtual address where port0 rcvhdrqtail updated for this unit.
163 * only written to by the chip, not the driver.
164 */
165 volatile __le64 *ipath_hdrqtailptr;
d41d3aeb
BS		 166 /* ipath_cfgports pointers */
167 struct ipath_portdata **ipath_pd;
168 /* sk_buffs used by port 0 eager receive queue */
169 struct sk_buff **ipath_port0_skbs;
170 /* kvirt address of 1st 2k pio buffer */
171 void __iomem *ipath_pio2kbase;
172 /* kvirt address of 1st 4k pio buffer */
173 void __iomem *ipath_pio4kbase;
174 /*
175 * points to area where PIOavail registers will be DMA'ed.
176 * Has to be on a page of it's own, because the page will be
177 * mapped into user program space. This copy is *ONLY* ever
178 * written by DMA, not by the driver! Need a copy per device
179 * when we get to multiple devices
180 */
181 volatile __le64 *ipath_pioavailregs_dma;
182 /* physical address where updates occur */
183 dma_addr_t ipath_pioavailregs_phys;
184 struct _ipath_layer ipath_layer;
185 /* setup intr */
186 int (*ipath_f_intrsetup)(struct ipath_devdata *);
187 /* setup on-chip bus config */
188 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
189 /* hard reset chip */
190 int (*ipath_f_reset)(struct ipath_devdata *);
191 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
192 size_t);
193 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
194 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
195 size_t);
196 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
197 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
198 int (*ipath_f_early_init)(struct ipath_devdata *);
199 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
200 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
201 u32, unsigned long);
202 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
203 void (*ipath_f_cleanup)(struct ipath_devdata *);
204 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
205 /* fill out chip-specific fields */
206 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
207 struct _verbs_layer verbs_layer;
208 /* total dwords sent (summed from counter) */
209 u64 ipath_sword;
210 /* total dwords rcvd (summed from counter) */
211 u64 ipath_rword;
212 /* total packets sent (summed from counter) */
213 u64 ipath_spkts;
214 /* total packets rcvd (summed from counter) */
215 u64 ipath_rpkts;
216 /* ipath_statusp initially points to this. */
217 u64 _ipath_status;
218 /* GUID for this interface, in network order */
219 __be64 ipath_guid;
220 /*
221 * aggregrate of error bits reported since last cleared, for
222 * limiting of error reporting
223 */
224 ipath_err_t ipath_lasterror;
225 /*
226 * aggregrate of error bits reported since last cleared, for
227 * limiting of hwerror reporting
228 */
229 ipath_err_t ipath_lasthwerror;
230 /*
231 * errors masked because they occur too fast, also includes errors
232 * that are always ignored (ipath_ignorederrs)
233 */
234 ipath_err_t ipath_maskederrs;
235 /* time in jiffies at which to re-enable maskederrs */
236 unsigned long ipath_unmasktime;
237 /*
238 * errors always ignored (masked), at least for a given
239 * chip/device, because they are wrong or not useful
240 */
241 ipath_err_t ipath_ignorederrs;
242 /* count of egrfull errors, combined for all ports */
243 u64 ipath_last_tidfull;
244 /* for ipath_qcheck() */
245 u64 ipath_lastport0rcv_cnt;
246 /* template for writing TIDs */
247 u64 ipath_tidtemplate;
248 /* value to write to free TIDs */
249 u64 ipath_tidinvalid;
250 /* PE-800 rcv interrupt setup */
251 u64 ipath_rhdrhead_intr_off;
252
253 /* size of memory at ipath_kregbase */
254 u32 ipath_kregsize;
255 /* number of registers used for pioavail */
256 u32 ipath_pioavregs;
257 /* IPATH_POLL, etc. */
258 u32 ipath_flags;
259 /* ipath_flags sma is waiting for */
260 u32 ipath_sma_state_wanted;
261 /* last buffer for user use, first buf for kernel use is this
262 * index. */
263 u32 ipath_lastport_piobuf;
264 /* is a stats timer active */
265 u32 ipath_stats_timer_active;
266 /* dwords sent read from counter */
267 u32 ipath_lastsword;
268 /* dwords received read from counter */
269 u32 ipath_lastrword;
270 /* sent packets read from counter */
271 u32 ipath_lastspkts;
272 /* received packets read from counter */
273 u32 ipath_lastrpkts;
274 /* pio bufs allocated per port */
275 u32 ipath_pbufsport;
276 /*
277 * number of ports configured as max; zero is set to number chip
278 * supports, less gives more pio bufs/port, etc.
279 */
280 u32 ipath_cfgports;
281 /* port0 rcvhdrq head offset */
282 u32 ipath_port0head;
283 /* count of port 0 hdrqfull errors */
284 u32 ipath_p0_hdrqfull;
285
286 /*
287 * (*cfgports) used to suppress multiple instances of same
288 * port staying stuck at same point
289 */
290 u32 *ipath_lastrcvhdrqtails;
291 /*
292 * (*cfgports) used to suppress multiple instances of same
293 * port staying stuck at same point
294 */
295 u32 *ipath_lastegrheads;
296 /*
297 * index of last piobuffer we used. Speeds up searching, by
298 * starting at this point. Doesn't matter if multiple cpu's use and
299 * update, last updater is only write that matters. Whenever it
300 * wraps, we update shadow copies. Need a copy per device when we
301 * get to multiple devices
302 */
303 u32 ipath_lastpioindex;
304 /* max length of freezemsg */
305 u32 ipath_freezelen;
306 /*
307 * consecutive times we wanted a PIO buffer but were unable to
308 * get one
309 */
310 u32 ipath_consec_nopiobuf;
311 /*
312 * hint that we should update ipath_pioavailshadow before
313 * looking for a PIO buffer
314 */
315 u32 ipath_upd_pio_shadow;
316 /* so we can rewrite it after a chip reset */
317 u32 ipath_pcibar0;
318 /* so we can rewrite it after a chip reset */
319 u32 ipath_pcibar1;
320 /* sequential tries for SMA send and no bufs */
321 u32 ipath_nosma_bufs;
322 /* duration (seconds) ipath_nosma_bufs set */
323 u32 ipath_nosma_secs;
324
325 /* HT/PCI Vendor ID (here for NodeInfo) */
326 u16 ipath_vendorid;
327 /* HT/PCI Device ID (here for NodeInfo) */
328 u16 ipath_deviceid;
329 /* offset in HT config space of slave/primary interface block */
330 u8 ipath_ht_slave_off;
331 /* for write combining settings */
332 unsigned long ipath_wc_cookie;
333 /* ref count for each pkey */
334 atomic_t ipath_pkeyrefs[4];
335 /* shadow copy of all exptids physaddr; used only by funcsim */
336 u64 *ipath_tidsimshadow;
337 /* shadow copy of struct page *'s for exp tid pages */
338 struct page **ipath_pageshadow;
339 /* lock to workaround chip bug 9437 */
340 spinlock_t ipath_tid_lock;
341
342 /*
343 * IPATH_STATUS_*,
344 * this address is mapped readonly into user processes so they can
345 * get status cheaply, whenever they want.
346 */
347 u64 *ipath_statusp;
348 /* freeze msg if hw error put chip in freeze */
349 char *ipath_freezemsg;
350 /* pci access data structure */
351 struct pci_dev *pcidev;
a2acb2ff
BS		 352 struct cdev *user_cdev;
353 struct cdev *diag_cdev;
354 struct class_device *user_class_dev;
355 struct class_device *diag_class_dev;
d41d3aeb
BS		 356 /* timer used to prevent stats overflow, error throttling, etc. */
357 struct timer_list ipath_stats_timer;
358 /* check for stale messages in rcv queue */
359 /* only allow one intr at a time. */
360 unsigned long ipath_rcv_pending;
361
362 /*
363 * Shadow copies of registers; size indicates read access size.
364 * Most of them are readonly, but some are write-only register,
365 * where we manipulate the bits in the shadow copy, and then write
366 * the shadow copy to infinipath.
367 *
368 * We deliberately make most of these 32 bits, since they have
369 * restricted range. For any that we read, we won't to generate 32
370 * bit accesses, since Opteron will generate 2 separate 32 bit HT
371 * transactions for a 64 bit read, and we want to avoid unnecessary
372 * HT transactions.
373 */
374
375 /* This is the 64 bit group */
376
377 /*
378 * shadow of pioavail, check to be sure it's large enough at
379 * init time.
380 */
381 unsigned long ipath_pioavailshadow[8];
382 /* shadow of kr_gpio_out, for rmw ops */
383 u64 ipath_gpio_out;
384 /* kr_revision shadow */
385 u64 ipath_revision;
386 /*
387 * shadow of ibcctrl, for interrupt handling of link changes,
388 * etc.
389 */
390 u64 ipath_ibcctrl;
391 /*
392 * last ibcstatus, to suppress "duplicate" status change messages,
393 * mostly from 2 to 3
394 */
395 u64 ipath_lastibcstat;
396 /* hwerrmask shadow */
397 ipath_err_t ipath_hwerrmask;
398 /* interrupt config reg shadow */
399 u64 ipath_intconfig;
400 /* kr_sendpiobufbase value */
401 u64 ipath_piobufbase;
402
403 /* these are the "32 bit" regs */
404
405 /*
406 * number of GUIDs in the flash for this interface; may need some
407 * rethinking for setting on other ifaces
408 */
409 u32 ipath_nguid;
410 /*
411 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
412 * all expect bit fields to be "unsigned long"
413 */
414 /* shadow kr_rcvctrl */
415 unsigned long ipath_rcvctrl;
416 /* shadow kr_sendctrl */
417 unsigned long ipath_sendctrl;
418
419 /* value we put in kr_rcvhdrcnt */
420 u32 ipath_rcvhdrcnt;
421 /* value we put in kr_rcvhdrsize */
422 u32 ipath_rcvhdrsize;
423 /* value we put in kr_rcvhdrentsize */
424 u32 ipath_rcvhdrentsize;
425 /* offset of last entry in rcvhdrq */
426 u32 ipath_hdrqlast;
427 /* kr_portcnt value */
428 u32 ipath_portcnt;
429 /* kr_pagealign value */
430 u32 ipath_palign;
431 /* number of "2KB" PIO buffers */
432 u32 ipath_piobcnt2k;
433 /* size in bytes of "2KB" PIO buffers */
434 u32 ipath_piosize2k;
435 /* number of "4KB" PIO buffers */
436 u32 ipath_piobcnt4k;
437 /* size in bytes of "4KB" PIO buffers */
438 u32 ipath_piosize4k;
439 /* kr_rcvegrbase value */
440 u32 ipath_rcvegrbase;
441 /* kr_rcvegrcnt value */
442 u32 ipath_rcvegrcnt;
443 /* kr_rcvtidbase value */
444 u32 ipath_rcvtidbase;
445 /* kr_rcvtidcnt value */
446 u32 ipath_rcvtidcnt;
447 /* kr_sendregbase */
448 u32 ipath_sregbase;
449 /* kr_userregbase */
450 u32 ipath_uregbase;
451 /* kr_counterregbase */
452 u32 ipath_cregbase;
453 /* shadow the control register contents */
454 u32 ipath_control;
455 /* shadow the gpio output contents */
456 u32 ipath_extctrl;
457 /* PCI revision register (HTC rev on FPGA) */
458 u32 ipath_pcirev;
459
460 /* chip address space used by 4k pio buffers */
461 u32 ipath_4kalign;
462 /* The MTU programmed for this unit */
463 u32 ipath_ibmtu;
464 /*
465 * The max size IB packet, included IB headers that we can send.
466 * Starts same as ipath_piosize, but is affected when ibmtu is
467 * changed, or by size of eager buffers
468 */
469 u32 ipath_ibmaxlen;
470 /*
471 * ibmaxlen at init time, limited by chip and by receive buffer
472 * size. Not changed after init.
473 */
474 u32 ipath_init_ibmaxlen;
475 /* size of each rcvegrbuffer */
476 u32 ipath_rcvegrbufsize;
477 /* width (2,4,8,16,32) from HT config reg */
478 u32 ipath_htwidth;
479 /* HT speed (200,400,800,1000) from HT config */
480 u32 ipath_htspeed;
481 /* ports waiting for PIOavail intr */
482 unsigned long ipath_portpiowait;
483 /*
484 * number of sequential ibcstatus change for polling active/quiet
485 * (i.e., link not coming up).
486 */
487 u32 ipath_ibpollcnt;
488 /* low and high portions of MSI capability/vector */
489 u32 ipath_msi_lo;
490 /* saved after PCIe init for restore after reset */
491 u32 ipath_msi_hi;
492 /* MSI data (vector) saved for restore */
493 u16 ipath_msi_data;
494 /* MLID programmed for this instance */
495 u16 ipath_mlid;
496 /* LID programmed for this instance */
497 u16 ipath_lid;
498 /* list of pkeys programmed; 0 if not set */
499 u16 ipath_pkeys[4];
500 /* ASCII serial number, from flash */
501 u8 ipath_serial[12];
502 /* human readable board version */
503 u8 ipath_boardversion[80];
504 /* chip major rev, from ipath_revision */
505 u8 ipath_majrev;
506 /* chip minor rev, from ipath_revision */
507 u8 ipath_minrev;
508 /* board rev, from ipath_revision */
509 u8 ipath_boardrev;
510 /* unit # of this chip, if present */
511 int ipath_unit;
512 /* saved for restore after reset */
513 u8 ipath_pci_cacheline;
514 /* LID mask control */
515 u8 ipath_lmc;
516};
517
518extern volatile __le64 *ipath_port0_rcvhdrtail;
519extern dma_addr_t ipath_port0_rcvhdrtail_dma;
520
521#define IPATH_PORT0_RCVHDRTAIL_SIZE PAGE_SIZE
522
523extern struct list_head ipath_dev_list;
524extern spinlock_t ipath_devs_lock;
525extern struct ipath_devdata *ipath_lookup(int unit);
526
527extern u16 ipath_layer_rcv_opcode;
d41d3aeb
BS		 528extern int __ipath_layer_intr(struct ipath_devdata *, u32);
529extern int ipath_layer_intr(struct ipath_devdata *, u32);
530extern int __ipath_layer_rcv(struct ipath_devdata *, void *,
531 struct sk_buff *);
532extern int __ipath_layer_rcv_lid(struct ipath_devdata *, void *);
533extern int __ipath_verbs_piobufavail(struct ipath_devdata *);
534extern int __ipath_verbs_rcv(struct ipath_devdata *, void *, void *, u32);
535
536void ipath_layer_add(struct ipath_devdata *);
a2acb2ff 537void ipath_layer_remove(struct ipath_devdata *);
d41d3aeb
BS		 538
539int ipath_init_chip(struct ipath_devdata *, int);
540int ipath_enable_wc(struct ipath_devdata *dd);
541void ipath_disable_wc(struct ipath_devdata *dd);
542int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
543void ipath_shutdown_device(struct ipath_devdata *);
544
545struct file_operations;
546int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
547 struct cdev **cdevp, struct class_device **class_devp);
548void ipath_cdev_cleanup(struct cdev **cdevp,
549 struct class_device **class_devp);
550
a2acb2ff
BS		 551int ipath_diag_add(struct ipath_devdata *);
552void ipath_diag_remove(struct ipath_devdata *);
d41d3aeb
BS		 553void ipath_diag_bringup_link(struct ipath_devdata *);
554
555extern wait_queue_head_t ipath_sma_state_wait;
556
557int ipath_user_add(struct ipath_devdata *dd);
a2acb2ff 558void ipath_user_remove(struct ipath_devdata *dd);
d41d3aeb
BS		 559
560struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
561
562extern int ipath_diag_inuse;
563
564irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
565void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
566#if __IPATH_INFO || __IPATH_DBG
567extern const char *ipath_ibcstatus_str[];
568#endif
569
570/* clean up any per-chip chip-specific stuff */
571void ipath_chip_cleanup(struct ipath_devdata *);
572/* clean up any chip type-specific stuff */
573void ipath_chip_done(void);
574
575/* check to see if we have to force ordering for write combining */
576int ipath_unordered_wc(void);
577
578void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
579 unsigned cnt);
580
581int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
582void ipath_free_pddata(struct ipath_devdata *, u32, int);
583
584int ipath_parse_ushort(const char *str, unsigned short *valp);
585
586int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
587void ipath_set_ib_lstate(struct ipath_devdata *, int);
588void ipath_kreceive(struct ipath_devdata *);
589int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
590int ipath_reset_device(int);
591void ipath_get_faststats(unsigned long);
592
593/* for use in system calls, where we want to know device type, etc. */
594#define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
595
596/*
597 * values for ipath_flags
598 */
599/* The chip is up and initted */
600#define IPATH_INITTED 0x2
601 /* set if any user code has set kr_rcvhdrsize */
602#define IPATH_RCVHDRSZ_SET 0x4
603 /* The chip is present and valid for accesses */
604#define IPATH_PRESENT 0x8
605 /* HT link0 is only 8 bits wide, ignore upper byte crc
606 * errors, etc. */
607#define IPATH_8BIT_IN_HT0 0x10
608 /* HT link1 is only 8 bits wide, ignore upper byte crc
609 * errors, etc. */
610#define IPATH_8BIT_IN_HT1 0x20
611 /* The link is down */
612#define IPATH_LINKDOWN 0x40
613 /* The link level is up (0x11) */
614#define IPATH_LINKINIT 0x80
615 /* The link is in the armed (0x21) state */
616#define IPATH_LINKARMED 0x100
617 /* The link is in the active (0x31) state */
618#define IPATH_LINKACTIVE 0x200
619 /* link current state is unknown */
620#define IPATH_LINKUNK 0x400
621 /* no IB cable, or no device on IB cable */
622#define IPATH_NOCABLE 0x4000
623 /* Supports port zero per packet receive interrupts via
624 * GPIO */
625#define IPATH_GPIO_INTR 0x8000
626 /* uses the coded 4byte TID, not 8 byte */
627#define IPATH_4BYTE_TID 0x10000
628 /* packet/word counters are 32 bit, else those 4 counters
629 * are 64bit */
630#define IPATH_32BITCOUNTERS 0x20000
631 /* can miss port0 rx interrupts */
632#define IPATH_POLL_RX_INTR 0x40000
633#define IPATH_DISABLED 0x80000 /* administratively disabled */
634
635/* portdata flag bit offsets */
636 /* waiting for a packet to arrive */
637#define IPATH_PORT_WAITING_RCV 2
638 /* waiting for a PIO buffer to be available */
639#define IPATH_PORT_WAITING_PIO 3
640
641/* free up any allocated data at closes */
642void ipath_free_data(struct ipath_portdata *dd);
643int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
644int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
645u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
646/* init PE-800-specific func */
647void ipath_init_pe800_funcs(struct ipath_devdata *);
648/* init HT-400-specific func */
649void ipath_init_ht400_funcs(struct ipath_devdata *);
f2080fa3 650void ipath_get_eeprom_info(struct ipath_devdata *);
d41d3aeb
BS		 651u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
652
653/*
654 * number of words used for protocol header if not set by ipath_userinit();
655 */
656#define IPATH_DFLT_RCVHDRSIZE 9
657
658#define IPATH_MDIO_CMD_WRITE 1
659#define IPATH_MDIO_CMD_READ 2
660#define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
661#define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
662#define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
663#define IPATH_MDIO_CTRL_STD 0x0
664
665static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
666{
667 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
668 (cmd << 26) |
669 (dev << 21) |
670 (reg << 16) |
671 (data & 0xFFFF);
672}
673
674 /* signal and fifo status, in bank 31 */
675#define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
676 /* controls loopback, redundancy */
677#define IPATH_MDIO_CTRL_8355_REG_1 0x10
678 /* premph, encdec, etc. */
679#define IPATH_MDIO_CTRL_8355_REG_2 0x11
680 /* Kchars, etc. */
681#define IPATH_MDIO_CTRL_8355_REG_6 0x15
682#define IPATH_MDIO_CTRL_8355_REG_9 0x18
683#define IPATH_MDIO_CTRL_8355_REG_10 0x1D
684
685int ipath_get_user_pages(unsigned long, size_t, struct page **);
686int ipath_get_user_pages_nocopy(unsigned long, struct page **);
687void ipath_release_user_pages(struct page **, size_t);
688void ipath_release_user_pages_on_close(struct page **, size_t);
689int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
690int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
691
692/* these are used for the registers that vary with port */
693void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
694 unsigned, u64);
695u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
696 unsigned);
697
698/*
699 * We could have a single register get/put routine, that takes a group type,
700 * but this is somewhat clearer and cleaner. It also gives us some error
701 * checking. 64 bit register reads should always work, but are inefficient
702 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
703 * so we use kreg32 wherever possible. User register and counter register
704 * reads are always 32 bit reads, so only one form of those routines.
705 */
706
707/*
708 * At the moment, none of the s-registers are writable, so no
709 * ipath_write_sreg(), and none of the c-registers are writable, so no
710 * ipath_write_creg().
711 */
712
713/**
714 * ipath_read_ureg32 - read 32-bit virtualized per-port register
715 * @dd: device
716 * @regno: register number
717 * @port: port number
718 *
719 * Return the contents of a register that is virtualized to be per port.
685f97e8
BS		 720 * Returns -1 on errors (not distinguishable from valid contents at
721 * runtime; we may add a separate error variable at some point).
d41d3aeb
BS		 722 */
723static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
724 ipath_ureg regno, int port)
725{
c71c30dc 726 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 727 return 0;
728
729 return readl(regno + (u64 __iomem *)
730 (dd->ipath_uregbase +
731 (char __iomem *)dd->ipath_kregbase +
732 dd->ipath_palign * port));
733}
734
735/**
736 * ipath_write_ureg - write 32-bit virtualized per-port register
737 * @dd: device
738 * @regno: register number
739 * @value: value
740 * @port: port
741 *
742 * Write the contents of a register that is virtualized to be per port.
743 */
744static inline void ipath_write_ureg(const struct ipath_devdata *dd,
745 ipath_ureg regno, u64 value, int port)
746{
747 u64 __iomem *ubase = (u64 __iomem *)
748 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
749 dd->ipath_palign * port);
750 if (dd->ipath_kregbase)
751 writeq(value, &ubase[regno]);
752}
753
754static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
755 ipath_kreg regno)
756{
c71c30dc 757 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 758 return -1;
759 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
760}
761
762static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
763 ipath_kreg regno)
764{
c71c30dc 765 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 766 return -1;
767
768 return readq(&dd->ipath_kregbase[regno]);
769}
770
771static inline void ipath_write_kreg(const struct ipath_devdata *dd,
772 ipath_kreg regno, u64 value)
773{
774 if (dd->ipath_kregbase)
775 writeq(value, &dd->ipath_kregbase[regno]);
776}
777
778static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
779 ipath_sreg regno)
780{
c71c30dc 781 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 782 return 0;
783
784 return readq(regno + (u64 __iomem *)
785 (dd->ipath_cregbase +
786 (char __iomem *)dd->ipath_kregbase));
787}
788
789static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
790 ipath_sreg regno)
791{
c71c30dc 792 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 793 return 0;
794 return readl(regno + (u64 __iomem *)
795 (dd->ipath_cregbase +
796 (char __iomem *)dd->ipath_kregbase));
797}
798
799/*
800 * sysfs interface.
801 */
802
803struct device_driver;
804
805extern const char ipath_core_version[];
806
807int ipath_driver_create_group(struct device_driver *);
808void ipath_driver_remove_group(struct device_driver *);
809
810int ipath_device_create_group(struct device *, struct ipath_devdata *);
811void ipath_device_remove_group(struct device *, struct ipath_devdata *);
812int ipath_expose_reset(struct device *);
813
814int ipath_init_ipathfs(void);
815void ipath_exit_ipathfs(void);
816int ipathfs_add_device(struct ipath_devdata *);
817int ipathfs_remove_device(struct ipath_devdata *);
818
819/*
820 * Flush write combining store buffers (if present) and perform a write
821 * barrier.
822 */
823#if defined(CONFIG_X86_64)
824#define ipath_flush_wc() asm volatile("sfence" ::: "memory")
825#else
826#define ipath_flush_wc() wmb()
827#endif
828
829extern unsigned ipath_debug; /* debugging bit mask */
830
831const char *ipath_get_unit_name(int unit);
832
833extern struct mutex ipath_mutex;
834
835#define IPATH_DRV_NAME "ipath_core"
836#define IPATH_MAJOR 233
a2acb2ff 837#define IPATH_USER_MINOR_BASE 0
d41d3aeb 838#define IPATH_SMA_MINOR 128
a2acb2ff
BS		 839#define IPATH_DIAG_MINOR_BASE 129
840#define IPATH_NMINORS 255
d41d3aeb
BS		 841
842#define ipath_dev_err(dd,fmt,...) \
843 do { \
844 const struct ipath_devdata *__dd = (dd); \
845 if (__dd->pcidev) \
846 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
847 ipath_get_unit_name(__dd->ipath_unit), \
848 ##__VA_ARGS__); \
849 else \
850 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
851 ipath_get_unit_name(__dd->ipath_unit), \
852 ##__VA_ARGS__); \
853 } while (0)
854
855#if _IPATH_DEBUGGING
856
857# define __IPATH_DBG_WHICH(which,fmt,...) \
858 do { \
859 if(unlikely(ipath_debug&(which))) \
860 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
861 __func__,##__VA_ARGS__); \
862 } while(0)
863
864# define ipath_dbg(fmt,...) \
865 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
866# define ipath_cdbg(which,fmt,...) \
867 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
868
869#else /* ! _IPATH_DEBUGGING */
870
871# define ipath_dbg(fmt,...)
872# define ipath_cdbg(which,fmt,...)
873
874#endif /* _IPATH_DEBUGGING */
875
876#endif /* _IPATH_KERNEL_H */
Linux kernel - Deliverables
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