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IB/ipath: simplify layering code
[deliverable/linux.git] / drivers / infiniband / hw / ipath / ipath_kernel.h
CommitLineData
d41d3aeb
BS		 1#ifndef _IPATH_KERNEL_H
2#define _IPATH_KERNEL_H
3/*
759d5768 4 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
d41d3aeb
BS		 5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36/*
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
39 */
40
41#include <linux/interrupt.h>
42#include <asm/io.h>
43
44#include "ipath_common.h"
45#include "ipath_debug.h"
46#include "ipath_registers.h"
47
48/* only s/w major version of InfiniPath we can handle */
49#define IPATH_CHIP_VERS_MAJ 2U
50
51/* don't care about this except printing */
52#define IPATH_CHIP_VERS_MIN 0U
53
54/* temporary, maybe always */
55extern struct infinipath_stats ipath_stats;
56
57#define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
58
59struct ipath_portdata {
60 void **port_rcvegrbuf;
61 dma_addr_t *port_rcvegrbuf_phys;
62 /* rcvhdrq base, needs mmap before useful */
63 void *port_rcvhdrq;
64 /* kernel virtual address where hdrqtail is updated */
f37bda92 65 volatile __le64 *port_rcvhdrtail_kvaddr;
d41d3aeb
BS		 66 /*
67 * temp buffer for expected send setup, allocated at open, instead
68 * of each setup call
69 */
70 void *port_tid_pg_list;
71 /* when waiting for rcv or pioavail */
72 wait_queue_head_t port_wait;
73 /*
74 * rcvegr bufs base, physical, must fit
75 * in 44 bits so 32 bit programs mmap64 44 bit works)
76 */
77 dma_addr_t port_rcvegr_phys;
78 /* mmap of hdrq, must fit in 44 bits */
79 dma_addr_t port_rcvhdrq_phys;
f37bda92 80 dma_addr_t port_rcvhdrqtailaddr_phys;
d41d3aeb
BS		 81 /*
82 * number of opens on this instance (0 or 1; ignoring forks, dup,
83 * etc. for now)
84 */
85 int port_cnt;
86 /*
87 * how much space to leave at start of eager TID entries for
88 * protocol use, on each TID
89 */
90 /* instead of calculating it */
91 unsigned port_port;
92 /* chip offset of PIO buffers for this port */
93 u32 port_piobufs;
94 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
95 u32 port_rcvegrbuf_chunks;
96 /* how many egrbufs per chunk */
97 u32 port_rcvegrbufs_perchunk;
98 /* order for port_rcvegrbuf_pages */
99 size_t port_rcvegrbuf_size;
100 /* rcvhdrq size (for freeing) */
101 size_t port_rcvhdrq_size;
102 /* next expected TID to check when looking for free */
103 u32 port_tidcursor;
104 /* next expected TID to check */
105 unsigned long port_flag;
106 /* WAIT_RCV that timed out, no interrupt */
107 u32 port_rcvwait_to;
108 /* WAIT_PIO that timed out, no interrupt */
109 u32 port_piowait_to;
110 /* WAIT_RCV already happened, no wait */
111 u32 port_rcvnowait;
112 /* WAIT_PIO already happened, no wait */
113 u32 port_pionowait;
114 /* total number of rcvhdrqfull errors */
115 u32 port_hdrqfull;
116 /* pid of process using this port */
117 pid_t port_pid;
118 /* same size as task_struct .comm[] */
119 char port_comm[16];
120 /* pkeys set by this use of this port */
121 u16 port_pkeys[4];
122 /* so file ops can get at unit */
123 struct ipath_devdata *port_dd;
124};
125
126struct sk_buff;
127
128/*
129 * control information for layered drivers
130 */
131struct _ipath_layer {
132 void *l_arg;
133};
134
d41d3aeb
BS		 135struct ipath_devdata {
136 struct list_head ipath_list;
137
138 struct ipath_kregs const *ipath_kregs;
139 struct ipath_cregs const *ipath_cregs;
140
141 /* mem-mapped pointer to base of chip regs */
142 u64 __iomem *ipath_kregbase;
143 /* end of mem-mapped chip space; range checking */
144 u64 __iomem *ipath_kregend;
145 /* physical address of chip for io_remap, etc. */
146 unsigned long ipath_physaddr;
147 /* base of memory alloced for ipath_kregbase, for free */
148 u64 *ipath_kregalloc;
d41d3aeb
BS		 149 /*
150 * virtual address where port0 rcvhdrqtail updated for this unit.
151 * only written to by the chip, not the driver.
152 */
153 volatile __le64 *ipath_hdrqtailptr;
d41d3aeb
BS		 154 /* ipath_cfgports pointers */
155 struct ipath_portdata **ipath_pd;
156 /* sk_buffs used by port 0 eager receive queue */
157 struct sk_buff **ipath_port0_skbs;
158 /* kvirt address of 1st 2k pio buffer */
159 void __iomem *ipath_pio2kbase;
160 /* kvirt address of 1st 4k pio buffer */
161 void __iomem *ipath_pio4kbase;
162 /*
163 * points to area where PIOavail registers will be DMA'ed.
164 * Has to be on a page of it's own, because the page will be
165 * mapped into user program space. This copy is *ONLY* ever
166 * written by DMA, not by the driver! Need a copy per device
167 * when we get to multiple devices
168 */
169 volatile __le64 *ipath_pioavailregs_dma;
170 /* physical address where updates occur */
171 dma_addr_t ipath_pioavailregs_phys;
172 struct _ipath_layer ipath_layer;
173 /* setup intr */
174 int (*ipath_f_intrsetup)(struct ipath_devdata *);
175 /* setup on-chip bus config */
176 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
177 /* hard reset chip */
178 int (*ipath_f_reset)(struct ipath_devdata *);
179 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
180 size_t);
181 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
182 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
183 size_t);
184 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
185 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
186 int (*ipath_f_early_init)(struct ipath_devdata *);
187 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
188 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
189 u32, unsigned long);
190 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
191 void (*ipath_f_cleanup)(struct ipath_devdata *);
192 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
193 /* fill out chip-specific fields */
194 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
b1c1b6a3
BS		 195 struct ipath_ibdev *verbs_dev;
196 struct timer_list verbs_timer;
d41d3aeb
BS		 197 /* total dwords sent (summed from counter) */
198 u64 ipath_sword;
199 /* total dwords rcvd (summed from counter) */
200 u64 ipath_rword;
201 /* total packets sent (summed from counter) */
202 u64 ipath_spkts;
203 /* total packets rcvd (summed from counter) */
204 u64 ipath_rpkts;
205 /* ipath_statusp initially points to this. */
206 u64 _ipath_status;
207 /* GUID for this interface, in network order */
208 __be64 ipath_guid;
209 /*
210 * aggregrate of error bits reported since last cleared, for
211 * limiting of error reporting
212 */
213 ipath_err_t ipath_lasterror;
214 /*
215 * aggregrate of error bits reported since last cleared, for
216 * limiting of hwerror reporting
217 */
218 ipath_err_t ipath_lasthwerror;
219 /*
220 * errors masked because they occur too fast, also includes errors
221 * that are always ignored (ipath_ignorederrs)
222 */
223 ipath_err_t ipath_maskederrs;
224 /* time in jiffies at which to re-enable maskederrs */
225 unsigned long ipath_unmasktime;
226 /*
227 * errors always ignored (masked), at least for a given
228 * chip/device, because they are wrong or not useful
229 */
230 ipath_err_t ipath_ignorederrs;
231 /* count of egrfull errors, combined for all ports */
232 u64 ipath_last_tidfull;
233 /* for ipath_qcheck() */
234 u64 ipath_lastport0rcv_cnt;
235 /* template for writing TIDs */
236 u64 ipath_tidtemplate;
237 /* value to write to free TIDs */
238 u64 ipath_tidinvalid;
239 /* PE-800 rcv interrupt setup */
240 u64 ipath_rhdrhead_intr_off;
241
242 /* size of memory at ipath_kregbase */
243 u32 ipath_kregsize;
244 /* number of registers used for pioavail */
245 u32 ipath_pioavregs;
246 /* IPATH_POLL, etc. */
247 u32 ipath_flags;
248 /* ipath_flags sma is waiting for */
249 u32 ipath_sma_state_wanted;
250 /* last buffer for user use, first buf for kernel use is this
251 * index. */
252 u32 ipath_lastport_piobuf;
253 /* is a stats timer active */
254 u32 ipath_stats_timer_active;
255 /* dwords sent read from counter */
256 u32 ipath_lastsword;
257 /* dwords received read from counter */
258 u32 ipath_lastrword;
259 /* sent packets read from counter */
260 u32 ipath_lastspkts;
261 /* received packets read from counter */
262 u32 ipath_lastrpkts;
263 /* pio bufs allocated per port */
264 u32 ipath_pbufsport;
265 /*
266 * number of ports configured as max; zero is set to number chip
267 * supports, less gives more pio bufs/port, etc.
268 */
269 u32 ipath_cfgports;
270 /* port0 rcvhdrq head offset */
271 u32 ipath_port0head;
272 /* count of port 0 hdrqfull errors */
273 u32 ipath_p0_hdrqfull;
274
275 /*
276 * (*cfgports) used to suppress multiple instances of same
277 * port staying stuck at same point
278 */
279 u32 *ipath_lastrcvhdrqtails;
280 /*
281 * (*cfgports) used to suppress multiple instances of same
282 * port staying stuck at same point
283 */
284 u32 *ipath_lastegrheads;
285 /*
286 * index of last piobuffer we used. Speeds up searching, by
287 * starting at this point. Doesn't matter if multiple cpu's use and
288 * update, last updater is only write that matters. Whenever it
289 * wraps, we update shadow copies. Need a copy per device when we
290 * get to multiple devices
291 */
292 u32 ipath_lastpioindex;
293 /* max length of freezemsg */
294 u32 ipath_freezelen;
295 /*
296 * consecutive times we wanted a PIO buffer but were unable to
297 * get one
298 */
299 u32 ipath_consec_nopiobuf;
300 /*
301 * hint that we should update ipath_pioavailshadow before
302 * looking for a PIO buffer
303 */
304 u32 ipath_upd_pio_shadow;
305 /* so we can rewrite it after a chip reset */
306 u32 ipath_pcibar0;
307 /* so we can rewrite it after a chip reset */
308 u32 ipath_pcibar1;
309 /* sequential tries for SMA send and no bufs */
310 u32 ipath_nosma_bufs;
311 /* duration (seconds) ipath_nosma_bufs set */
312 u32 ipath_nosma_secs;
313
314 /* HT/PCI Vendor ID (here for NodeInfo) */
315 u16 ipath_vendorid;
316 /* HT/PCI Device ID (here for NodeInfo) */
317 u16 ipath_deviceid;
318 /* offset in HT config space of slave/primary interface block */
319 u8 ipath_ht_slave_off;
320 /* for write combining settings */
321 unsigned long ipath_wc_cookie;
322 /* ref count for each pkey */
323 atomic_t ipath_pkeyrefs[4];
324 /* shadow copy of all exptids physaddr; used only by funcsim */
325 u64 *ipath_tidsimshadow;
326 /* shadow copy of struct page *'s for exp tid pages */
327 struct page **ipath_pageshadow;
328 /* lock to workaround chip bug 9437 */
329 spinlock_t ipath_tid_lock;
330
331 /*
332 * IPATH_STATUS_*,
333 * this address is mapped readonly into user processes so they can
334 * get status cheaply, whenever they want.
335 */
336 u64 *ipath_statusp;
337 /* freeze msg if hw error put chip in freeze */
338 char *ipath_freezemsg;
339 /* pci access data structure */
340 struct pci_dev *pcidev;
a2acb2ff
BS		 341 struct cdev *user_cdev;
342 struct cdev *diag_cdev;
343 struct class_device *user_class_dev;
344 struct class_device *diag_class_dev;
d41d3aeb
BS		 345 /* timer used to prevent stats overflow, error throttling, etc. */
346 struct timer_list ipath_stats_timer;
347 /* check for stale messages in rcv queue */
348 /* only allow one intr at a time. */
349 unsigned long ipath_rcv_pending;
35783ec0
BS		 350 void *ipath_dummy_hdrq; /* used after port close */
351 dma_addr_t ipath_dummy_hdrq_phys;
d41d3aeb
BS		 352
353 /*
354 * Shadow copies of registers; size indicates read access size.
355 * Most of them are readonly, but some are write-only register,
356 * where we manipulate the bits in the shadow copy, and then write
357 * the shadow copy to infinipath.
358 *
359 * We deliberately make most of these 32 bits, since they have
360 * restricted range. For any that we read, we won't to generate 32
361 * bit accesses, since Opteron will generate 2 separate 32 bit HT
362 * transactions for a 64 bit read, and we want to avoid unnecessary
363 * HT transactions.
364 */
365
366 /* This is the 64 bit group */
367
368 /*
369 * shadow of pioavail, check to be sure it's large enough at
370 * init time.
371 */
372 unsigned long ipath_pioavailshadow[8];
373 /* shadow of kr_gpio_out, for rmw ops */
374 u64 ipath_gpio_out;
375 /* kr_revision shadow */
376 u64 ipath_revision;
377 /*
378 * shadow of ibcctrl, for interrupt handling of link changes,
379 * etc.
380 */
381 u64 ipath_ibcctrl;
382 /*
383 * last ibcstatus, to suppress "duplicate" status change messages,
384 * mostly from 2 to 3
385 */
386 u64 ipath_lastibcstat;
387 /* hwerrmask shadow */
388 ipath_err_t ipath_hwerrmask;
389 /* interrupt config reg shadow */
390 u64 ipath_intconfig;
391 /* kr_sendpiobufbase value */
392 u64 ipath_piobufbase;
393
394 /* these are the "32 bit" regs */
395
396 /*
397 * number of GUIDs in the flash for this interface; may need some
398 * rethinking for setting on other ifaces
399 */
400 u32 ipath_nguid;
401 /*
402 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
403 * all expect bit fields to be "unsigned long"
404 */
405 /* shadow kr_rcvctrl */
406 unsigned long ipath_rcvctrl;
407 /* shadow kr_sendctrl */
408 unsigned long ipath_sendctrl;
409
410 /* value we put in kr_rcvhdrcnt */
411 u32 ipath_rcvhdrcnt;
412 /* value we put in kr_rcvhdrsize */
413 u32 ipath_rcvhdrsize;
414 /* value we put in kr_rcvhdrentsize */
415 u32 ipath_rcvhdrentsize;
416 /* offset of last entry in rcvhdrq */
417 u32 ipath_hdrqlast;
418 /* kr_portcnt value */
419 u32 ipath_portcnt;
420 /* kr_pagealign value */
421 u32 ipath_palign;
422 /* number of "2KB" PIO buffers */
423 u32 ipath_piobcnt2k;
424 /* size in bytes of "2KB" PIO buffers */
425 u32 ipath_piosize2k;
426 /* number of "4KB" PIO buffers */
427 u32 ipath_piobcnt4k;
428 /* size in bytes of "4KB" PIO buffers */
429 u32 ipath_piosize4k;
430 /* kr_rcvegrbase value */
431 u32 ipath_rcvegrbase;
432 /* kr_rcvegrcnt value */
433 u32 ipath_rcvegrcnt;
434 /* kr_rcvtidbase value */
435 u32 ipath_rcvtidbase;
436 /* kr_rcvtidcnt value */
437 u32 ipath_rcvtidcnt;
438 /* kr_sendregbase */
439 u32 ipath_sregbase;
440 /* kr_userregbase */
441 u32 ipath_uregbase;
442 /* kr_counterregbase */
443 u32 ipath_cregbase;
444 /* shadow the control register contents */
445 u32 ipath_control;
446 /* shadow the gpio output contents */
447 u32 ipath_extctrl;
448 /* PCI revision register (HTC rev on FPGA) */
449 u32 ipath_pcirev;
450
451 /* chip address space used by 4k pio buffers */
452 u32 ipath_4kalign;
453 /* The MTU programmed for this unit */
454 u32 ipath_ibmtu;
455 /*
456 * The max size IB packet, included IB headers that we can send.
457 * Starts same as ipath_piosize, but is affected when ibmtu is
458 * changed, or by size of eager buffers
459 */
460 u32 ipath_ibmaxlen;
461 /*
462 * ibmaxlen at init time, limited by chip and by receive buffer
463 * size. Not changed after init.
464 */
465 u32 ipath_init_ibmaxlen;
466 /* size of each rcvegrbuffer */
467 u32 ipath_rcvegrbufsize;
468 /* width (2,4,8,16,32) from HT config reg */
469 u32 ipath_htwidth;
470 /* HT speed (200,400,800,1000) from HT config */
471 u32 ipath_htspeed;
472 /* ports waiting for PIOavail intr */
473 unsigned long ipath_portpiowait;
474 /*
475 * number of sequential ibcstatus change for polling active/quiet
476 * (i.e., link not coming up).
477 */
478 u32 ipath_ibpollcnt;
479 /* low and high portions of MSI capability/vector */
480 u32 ipath_msi_lo;
481 /* saved after PCIe init for restore after reset */
482 u32 ipath_msi_hi;
483 /* MSI data (vector) saved for restore */
484 u16 ipath_msi_data;
485 /* MLID programmed for this instance */
486 u16 ipath_mlid;
487 /* LID programmed for this instance */
488 u16 ipath_lid;
489 /* list of pkeys programmed; 0 if not set */
490 u16 ipath_pkeys[4];
8307c28e
BS		 491 /*
492 * ASCII serial number, from flash, large enough for original
493 * all digit strings, and longer QLogic serial number format
494 */
495 u8 ipath_serial[16];
d41d3aeb
BS		 496 /* human readable board version */
497 u8 ipath_boardversion[80];
498 /* chip major rev, from ipath_revision */
499 u8 ipath_majrev;
500 /* chip minor rev, from ipath_revision */
501 u8 ipath_minrev;
502 /* board rev, from ipath_revision */
503 u8 ipath_boardrev;
504 /* unit # of this chip, if present */
505 int ipath_unit;
506 /* saved for restore after reset */
507 u8 ipath_pci_cacheline;
508 /* LID mask control */
509 u8 ipath_lmc;
fba75200
BS		 510
511 /* local link integrity counter */
512 u32 ipath_lli_counter;
513 /* local link integrity errors */
514 u32 ipath_lli_errors;
d41d3aeb
BS		 515};
516
d41d3aeb
BS		 517extern struct list_head ipath_dev_list;
518extern spinlock_t ipath_devs_lock;
519extern struct ipath_devdata *ipath_lookup(int unit);
520
d41d3aeb
BS		 521int ipath_init_chip(struct ipath_devdata *, int);
522int ipath_enable_wc(struct ipath_devdata *dd);
523void ipath_disable_wc(struct ipath_devdata *dd);
524int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
525void ipath_shutdown_device(struct ipath_devdata *);
526
527struct file_operations;
528int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
529 struct cdev **cdevp, struct class_device **class_devp);
530void ipath_cdev_cleanup(struct cdev **cdevp,
531 struct class_device **class_devp);
532
a2acb2ff
BS		 533int ipath_diag_add(struct ipath_devdata *);
534void ipath_diag_remove(struct ipath_devdata *);
d41d3aeb
BS		 535void ipath_diag_bringup_link(struct ipath_devdata *);
536
537extern wait_queue_head_t ipath_sma_state_wait;
538
539int ipath_user_add(struct ipath_devdata *dd);
a2acb2ff 540void ipath_user_remove(struct ipath_devdata *dd);
d41d3aeb
BS		 541
542struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
543
544extern int ipath_diag_inuse;
545
546irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
547void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
548#if __IPATH_INFO || __IPATH_DBG
549extern const char *ipath_ibcstatus_str[];
550#endif
551
552/* clean up any per-chip chip-specific stuff */
553void ipath_chip_cleanup(struct ipath_devdata *);
554/* clean up any chip type-specific stuff */
555void ipath_chip_done(void);
556
557/* check to see if we have to force ordering for write combining */
558int ipath_unordered_wc(void);
559
560void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
561 unsigned cnt);
562
563int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
f37bda92 564void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
d41d3aeb
BS		 565
566int ipath_parse_ushort(const char *str, unsigned short *valp);
567
d41d3aeb
BS		 568void ipath_kreceive(struct ipath_devdata *);
569int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
570int ipath_reset_device(int);
571void ipath_get_faststats(unsigned long);
34b2aafe
BS		 572int ipath_set_linkstate(struct ipath_devdata *, u8);
573int ipath_set_mtu(struct ipath_devdata *, u16);
574int ipath_set_lid(struct ipath_devdata *, u32, u8);
d41d3aeb
BS		 575
576/* for use in system calls, where we want to know device type, etc. */
577#define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
578
579/*
580 * values for ipath_flags
581 */
582/* The chip is up and initted */
583#define IPATH_INITTED 0x2
584 /* set if any user code has set kr_rcvhdrsize */
585#define IPATH_RCVHDRSZ_SET 0x4
586 /* The chip is present and valid for accesses */
587#define IPATH_PRESENT 0x8
588 /* HT link0 is only 8 bits wide, ignore upper byte crc
589 * errors, etc. */
590#define IPATH_8BIT_IN_HT0 0x10
591 /* HT link1 is only 8 bits wide, ignore upper byte crc
592 * errors, etc. */
593#define IPATH_8BIT_IN_HT1 0x20
594 /* The link is down */
595#define IPATH_LINKDOWN 0x40
596 /* The link level is up (0x11) */
597#define IPATH_LINKINIT 0x80
598 /* The link is in the armed (0x21) state */
599#define IPATH_LINKARMED 0x100
600 /* The link is in the active (0x31) state */
601#define IPATH_LINKACTIVE 0x200
602 /* link current state is unknown */
603#define IPATH_LINKUNK 0x400
604 /* no IB cable, or no device on IB cable */
605#define IPATH_NOCABLE 0x4000
606 /* Supports port zero per packet receive interrupts via
607 * GPIO */
608#define IPATH_GPIO_INTR 0x8000
609 /* uses the coded 4byte TID, not 8 byte */
610#define IPATH_4BYTE_TID 0x10000
611 /* packet/word counters are 32 bit, else those 4 counters
612 * are 64bit */
613#define IPATH_32BITCOUNTERS 0x20000
614 /* can miss port0 rx interrupts */
615#define IPATH_POLL_RX_INTR 0x40000
616#define IPATH_DISABLED 0x80000 /* administratively disabled */
617
618/* portdata flag bit offsets */
619 /* waiting for a packet to arrive */
620#define IPATH_PORT_WAITING_RCV 2
621 /* waiting for a PIO buffer to be available */
622#define IPATH_PORT_WAITING_PIO 3
623
624/* free up any allocated data at closes */
625void ipath_free_data(struct ipath_portdata *dd);
626int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
627int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
628u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
629/* init PE-800-specific func */
630void ipath_init_pe800_funcs(struct ipath_devdata *);
631/* init HT-400-specific func */
632void ipath_init_ht400_funcs(struct ipath_devdata *);
f2080fa3 633void ipath_get_eeprom_info(struct ipath_devdata *);
d41d3aeb
BS		 634u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
635
636/*
637 * number of words used for protocol header if not set by ipath_userinit();
638 */
639#define IPATH_DFLT_RCVHDRSIZE 9
640
641#define IPATH_MDIO_CMD_WRITE 1
642#define IPATH_MDIO_CMD_READ 2
643#define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
644#define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
645#define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
646#define IPATH_MDIO_CTRL_STD 0x0
647
648static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
649{
650 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
651 (cmd << 26) |
652 (dev << 21) |
653 (reg << 16) |
654 (data & 0xFFFF);
655}
656
657 /* signal and fifo status, in bank 31 */
658#define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
659 /* controls loopback, redundancy */
660#define IPATH_MDIO_CTRL_8355_REG_1 0x10
661 /* premph, encdec, etc. */
662#define IPATH_MDIO_CTRL_8355_REG_2 0x11
663 /* Kchars, etc. */
664#define IPATH_MDIO_CTRL_8355_REG_6 0x15
665#define IPATH_MDIO_CTRL_8355_REG_9 0x18
666#define IPATH_MDIO_CTRL_8355_REG_10 0x1D
667
668int ipath_get_user_pages(unsigned long, size_t, struct page **);
669int ipath_get_user_pages_nocopy(unsigned long, struct page **);
670void ipath_release_user_pages(struct page **, size_t);
671void ipath_release_user_pages_on_close(struct page **, size_t);
672int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
673int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
674
675/* these are used for the registers that vary with port */
676void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
677 unsigned, u64);
678u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
679 unsigned);
680
681/*
682 * We could have a single register get/put routine, that takes a group type,
683 * but this is somewhat clearer and cleaner. It also gives us some error
684 * checking. 64 bit register reads should always work, but are inefficient
685 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
686 * so we use kreg32 wherever possible. User register and counter register
687 * reads are always 32 bit reads, so only one form of those routines.
688 */
689
690/*
691 * At the moment, none of the s-registers are writable, so no
692 * ipath_write_sreg(), and none of the c-registers are writable, so no
693 * ipath_write_creg().
694 */
695
696/**
697 * ipath_read_ureg32 - read 32-bit virtualized per-port register
698 * @dd: device
699 * @regno: register number
700 * @port: port number
701 *
702 * Return the contents of a register that is virtualized to be per port.
685f97e8
BS		 703 * Returns -1 on errors (not distinguishable from valid contents at
704 * runtime; we may add a separate error variable at some point).
d41d3aeb
BS		 705 */
706static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
707 ipath_ureg regno, int port)
708{
c71c30dc 709 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 710 return 0;
711
712 return readl(regno + (u64 __iomem *)
713 (dd->ipath_uregbase +
714 (char __iomem *)dd->ipath_kregbase +
715 dd->ipath_palign * port));
716}
717
718/**
719 * ipath_write_ureg - write 32-bit virtualized per-port register
720 * @dd: device
721 * @regno: register number
722 * @value: value
723 * @port: port
724 *
725 * Write the contents of a register that is virtualized to be per port.
726 */
727static inline void ipath_write_ureg(const struct ipath_devdata *dd,
728 ipath_ureg regno, u64 value, int port)
729{
730 u64 __iomem *ubase = (u64 __iomem *)
731 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
732 dd->ipath_palign * port);
733 if (dd->ipath_kregbase)
734 writeq(value, &ubase[regno]);
735}
736
737static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
738 ipath_kreg regno)
739{
c71c30dc 740 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 741 return -1;
742 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
743}
744
745static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
746 ipath_kreg regno)
747{
c71c30dc 748 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 749 return -1;
750
751 return readq(&dd->ipath_kregbase[regno]);
752}
753
754static inline void ipath_write_kreg(const struct ipath_devdata *dd,
755 ipath_kreg regno, u64 value)
756{
757 if (dd->ipath_kregbase)
758 writeq(value, &dd->ipath_kregbase[regno]);
759}
760
761static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
762 ipath_sreg regno)
763{
c71c30dc 764 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 765 return 0;
766
767 return readq(regno + (u64 __iomem *)
768 (dd->ipath_cregbase +
769 (char __iomem *)dd->ipath_kregbase));
770}
771
772static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
773 ipath_sreg regno)
774{
c71c30dc 775 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 776 return 0;
777 return readl(regno + (u64 __iomem *)
778 (dd->ipath_cregbase +
779 (char __iomem *)dd->ipath_kregbase));
780}
781
782/*
783 * sysfs interface.
784 */
785
786struct device_driver;
787
788extern const char ipath_core_version[];
789
790int ipath_driver_create_group(struct device_driver *);
791void ipath_driver_remove_group(struct device_driver *);
792
793int ipath_device_create_group(struct device *, struct ipath_devdata *);
794void ipath_device_remove_group(struct device *, struct ipath_devdata *);
795int ipath_expose_reset(struct device *);
796
797int ipath_init_ipathfs(void);
798void ipath_exit_ipathfs(void);
799int ipathfs_add_device(struct ipath_devdata *);
800int ipathfs_remove_device(struct ipath_devdata *);
801
802/*
803 * Flush write combining store buffers (if present) and perform a write
804 * barrier.
805 */
806#if defined(CONFIG_X86_64)
807#define ipath_flush_wc() asm volatile("sfence" ::: "memory")
808#else
809#define ipath_flush_wc() wmb()
810#endif
811
812extern unsigned ipath_debug; /* debugging bit mask */
813
814const char *ipath_get_unit_name(int unit);
815
816extern struct mutex ipath_mutex;
817
818#define IPATH_DRV_NAME "ipath_core"
819#define IPATH_MAJOR 233
a2acb2ff 820#define IPATH_USER_MINOR_BASE 0
d41d3aeb 821#define IPATH_SMA_MINOR 128
a2acb2ff
BS		 822#define IPATH_DIAG_MINOR_BASE 129
823#define IPATH_NMINORS 255
d41d3aeb
BS		 824
825#define ipath_dev_err(dd,fmt,...) \
826 do { \
827 const struct ipath_devdata *__dd = (dd); \
828 if (__dd->pcidev) \
829 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
830 ipath_get_unit_name(__dd->ipath_unit), \
831 ##__VA_ARGS__); \
832 else \
833 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
834 ipath_get_unit_name(__dd->ipath_unit), \
835 ##__VA_ARGS__); \
836 } while (0)
837
838#if _IPATH_DEBUGGING
839
840# define __IPATH_DBG_WHICH(which,fmt,...) \
841 do { \
842 if(unlikely(ipath_debug&(which))) \
843 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
844 __func__,##__VA_ARGS__); \
845 } while(0)
846
847# define ipath_dbg(fmt,...) \
848 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
849# define ipath_cdbg(which,fmt,...) \
850 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
851
852#else /* ! _IPATH_DEBUGGING */
853
854# define ipath_dbg(fmt,...)
855# define ipath_cdbg(which,fmt,...)
856
857#endif /* _IPATH_DEBUGGING */
858
859#endif /* _IPATH_KERNEL_H */
Linux kernel - Deliverables
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