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IB/ipath: core driver header files
[deliverable/linux.git] / drivers / infiniband / hw / ipath / ipath_kernel.h
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d41d3aeb
BS		 1#ifndef _IPATH_KERNEL_H
2#define _IPATH_KERNEL_H
3/*
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35/*
36 * This header file is the base header file for infinipath kernel code
37 * ipath_user.h serves a similar purpose for user code.
38 */
39
40#include <linux/interrupt.h>
41#include <asm/io.h>
42
43#include "ipath_common.h"
44#include "ipath_debug.h"
45#include "ipath_registers.h"
46
47/* only s/w major version of InfiniPath we can handle */
48#define IPATH_CHIP_VERS_MAJ 2U
49
50/* don't care about this except printing */
51#define IPATH_CHIP_VERS_MIN 0U
52
53/* temporary, maybe always */
54extern struct infinipath_stats ipath_stats;
55
56#define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
57
58struct ipath_portdata {
59 void **port_rcvegrbuf;
60 dma_addr_t *port_rcvegrbuf_phys;
61 /* rcvhdrq base, needs mmap before useful */
62 void *port_rcvhdrq;
63 /* kernel virtual address where hdrqtail is updated */
64 u64 *port_rcvhdrtail_kvaddr;
65 /* page * used for uaddr */
66 struct page *port_rcvhdrtail_pagep;
67 /*
68 * temp buffer for expected send setup, allocated at open, instead
69 * of each setup call
70 */
71 void *port_tid_pg_list;
72 /* when waiting for rcv or pioavail */
73 wait_queue_head_t port_wait;
74 /*
75 * rcvegr bufs base, physical, must fit
76 * in 44 bits so 32 bit programs mmap64 44 bit works)
77 */
78 dma_addr_t port_rcvegr_phys;
79 /* mmap of hdrq, must fit in 44 bits */
80 dma_addr_t port_rcvhdrq_phys;
81 /*
82 * the actual user address that we ipath_mlock'ed, so we can
83 * ipath_munlock it at close
84 */
85 unsigned long port_rcvhdrtail_uaddr;
86 /*
87 * number of opens on this instance (0 or 1; ignoring forks, dup,
88 * etc. for now)
89 */
90 int port_cnt;
91 /*
92 * how much space to leave at start of eager TID entries for
93 * protocol use, on each TID
94 */
95 /* instead of calculating it */
96 unsigned port_port;
97 /* chip offset of PIO buffers for this port */
98 u32 port_piobufs;
99 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
100 u32 port_rcvegrbuf_chunks;
101 /* how many egrbufs per chunk */
102 u32 port_rcvegrbufs_perchunk;
103 /* order for port_rcvegrbuf_pages */
104 size_t port_rcvegrbuf_size;
105 /* rcvhdrq size (for freeing) */
106 size_t port_rcvhdrq_size;
107 /* next expected TID to check when looking for free */
108 u32 port_tidcursor;
109 /* next expected TID to check */
110 unsigned long port_flag;
111 /* WAIT_RCV that timed out, no interrupt */
112 u32 port_rcvwait_to;
113 /* WAIT_PIO that timed out, no interrupt */
114 u32 port_piowait_to;
115 /* WAIT_RCV already happened, no wait */
116 u32 port_rcvnowait;
117 /* WAIT_PIO already happened, no wait */
118 u32 port_pionowait;
119 /* total number of rcvhdrqfull errors */
120 u32 port_hdrqfull;
121 /* pid of process using this port */
122 pid_t port_pid;
123 /* same size as task_struct .comm[] */
124 char port_comm[16];
125 /* pkeys set by this use of this port */
126 u16 port_pkeys[4];
127 /* so file ops can get at unit */
128 struct ipath_devdata *port_dd;
129};
130
131struct sk_buff;
132
133/*
134 * control information for layered drivers
135 */
136struct _ipath_layer {
137 void *l_arg;
138};
139
140/* Verbs layer interface */
141struct _verbs_layer {
142 void *l_arg;
143 struct timer_list l_timer;
144};
145
146struct ipath_devdata {
147 struct list_head ipath_list;
148
149 struct ipath_kregs const *ipath_kregs;
150 struct ipath_cregs const *ipath_cregs;
151
152 /* mem-mapped pointer to base of chip regs */
153 u64 __iomem *ipath_kregbase;
154 /* end of mem-mapped chip space; range checking */
155 u64 __iomem *ipath_kregend;
156 /* physical address of chip for io_remap, etc. */
157 unsigned long ipath_physaddr;
158 /* base of memory alloced for ipath_kregbase, for free */
159 u64 *ipath_kregalloc;
160 /*
161 * version of kregbase that doesn't have high bits set (for 32 bit
162 * programs, so mmap64 44 bit works)
163 */
164 u64 __iomem *ipath_kregvirt;
165 /*
166 * virtual address where port0 rcvhdrqtail updated for this unit.
167 * only written to by the chip, not the driver.
168 */
169 volatile __le64 *ipath_hdrqtailptr;
170 dma_addr_t ipath_dma_addr;
171 /* ipath_cfgports pointers */
172 struct ipath_portdata **ipath_pd;
173 /* sk_buffs used by port 0 eager receive queue */
174 struct sk_buff **ipath_port0_skbs;
175 /* kvirt address of 1st 2k pio buffer */
176 void __iomem *ipath_pio2kbase;
177 /* kvirt address of 1st 4k pio buffer */
178 void __iomem *ipath_pio4kbase;
179 /*
180 * points to area where PIOavail registers will be DMA'ed.
181 * Has to be on a page of it's own, because the page will be
182 * mapped into user program space. This copy is *ONLY* ever
183 * written by DMA, not by the driver! Need a copy per device
184 * when we get to multiple devices
185 */
186 volatile __le64 *ipath_pioavailregs_dma;
187 /* physical address where updates occur */
188 dma_addr_t ipath_pioavailregs_phys;
189 struct _ipath_layer ipath_layer;
190 /* setup intr */
191 int (*ipath_f_intrsetup)(struct ipath_devdata *);
192 /* setup on-chip bus config */
193 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
194 /* hard reset chip */
195 int (*ipath_f_reset)(struct ipath_devdata *);
196 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
197 size_t);
198 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
199 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
200 size_t);
201 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
202 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
203 int (*ipath_f_early_init)(struct ipath_devdata *);
204 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
205 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
206 u32, unsigned long);
207 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
208 void (*ipath_f_cleanup)(struct ipath_devdata *);
209 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
210 /* fill out chip-specific fields */
211 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
212 struct _verbs_layer verbs_layer;
213 /* total dwords sent (summed from counter) */
214 u64 ipath_sword;
215 /* total dwords rcvd (summed from counter) */
216 u64 ipath_rword;
217 /* total packets sent (summed from counter) */
218 u64 ipath_spkts;
219 /* total packets rcvd (summed from counter) */
220 u64 ipath_rpkts;
221 /* ipath_statusp initially points to this. */
222 u64 _ipath_status;
223 /* GUID for this interface, in network order */
224 __be64 ipath_guid;
225 /*
226 * aggregrate of error bits reported since last cleared, for
227 * limiting of error reporting
228 */
229 ipath_err_t ipath_lasterror;
230 /*
231 * aggregrate of error bits reported since last cleared, for
232 * limiting of hwerror reporting
233 */
234 ipath_err_t ipath_lasthwerror;
235 /*
236 * errors masked because they occur too fast, also includes errors
237 * that are always ignored (ipath_ignorederrs)
238 */
239 ipath_err_t ipath_maskederrs;
240 /* time in jiffies at which to re-enable maskederrs */
241 unsigned long ipath_unmasktime;
242 /*
243 * errors always ignored (masked), at least for a given
244 * chip/device, because they are wrong or not useful
245 */
246 ipath_err_t ipath_ignorederrs;
247 /* count of egrfull errors, combined for all ports */
248 u64 ipath_last_tidfull;
249 /* for ipath_qcheck() */
250 u64 ipath_lastport0rcv_cnt;
251 /* template for writing TIDs */
252 u64 ipath_tidtemplate;
253 /* value to write to free TIDs */
254 u64 ipath_tidinvalid;
255 /* PE-800 rcv interrupt setup */
256 u64 ipath_rhdrhead_intr_off;
257
258 /* size of memory at ipath_kregbase */
259 u32 ipath_kregsize;
260 /* number of registers used for pioavail */
261 u32 ipath_pioavregs;
262 /* IPATH_POLL, etc. */
263 u32 ipath_flags;
264 /* ipath_flags sma is waiting for */
265 u32 ipath_sma_state_wanted;
266 /* last buffer for user use, first buf for kernel use is this
267 * index. */
268 u32 ipath_lastport_piobuf;
269 /* is a stats timer active */
270 u32 ipath_stats_timer_active;
271 /* dwords sent read from counter */
272 u32 ipath_lastsword;
273 /* dwords received read from counter */
274 u32 ipath_lastrword;
275 /* sent packets read from counter */
276 u32 ipath_lastspkts;
277 /* received packets read from counter */
278 u32 ipath_lastrpkts;
279 /* pio bufs allocated per port */
280 u32 ipath_pbufsport;
281 /*
282 * number of ports configured as max; zero is set to number chip
283 * supports, less gives more pio bufs/port, etc.
284 */
285 u32 ipath_cfgports;
286 /* port0 rcvhdrq head offset */
287 u32 ipath_port0head;
288 /* count of port 0 hdrqfull errors */
289 u32 ipath_p0_hdrqfull;
290
291 /*
292 * (*cfgports) used to suppress multiple instances of same
293 * port staying stuck at same point
294 */
295 u32 *ipath_lastrcvhdrqtails;
296 /*
297 * (*cfgports) used to suppress multiple instances of same
298 * port staying stuck at same point
299 */
300 u32 *ipath_lastegrheads;
301 /*
302 * index of last piobuffer we used. Speeds up searching, by
303 * starting at this point. Doesn't matter if multiple cpu's use and
304 * update, last updater is only write that matters. Whenever it
305 * wraps, we update shadow copies. Need a copy per device when we
306 * get to multiple devices
307 */
308 u32 ipath_lastpioindex;
309 /* max length of freezemsg */
310 u32 ipath_freezelen;
311 /*
312 * consecutive times we wanted a PIO buffer but were unable to
313 * get one
314 */
315 u32 ipath_consec_nopiobuf;
316 /*
317 * hint that we should update ipath_pioavailshadow before
318 * looking for a PIO buffer
319 */
320 u32 ipath_upd_pio_shadow;
321 /* so we can rewrite it after a chip reset */
322 u32 ipath_pcibar0;
323 /* so we can rewrite it after a chip reset */
324 u32 ipath_pcibar1;
325 /* sequential tries for SMA send and no bufs */
326 u32 ipath_nosma_bufs;
327 /* duration (seconds) ipath_nosma_bufs set */
328 u32 ipath_nosma_secs;
329
330 /* HT/PCI Vendor ID (here for NodeInfo) */
331 u16 ipath_vendorid;
332 /* HT/PCI Device ID (here for NodeInfo) */
333 u16 ipath_deviceid;
334 /* offset in HT config space of slave/primary interface block */
335 u8 ipath_ht_slave_off;
336 /* for write combining settings */
337 unsigned long ipath_wc_cookie;
338 /* ref count for each pkey */
339 atomic_t ipath_pkeyrefs[4];
340 /* shadow copy of all exptids physaddr; used only by funcsim */
341 u64 *ipath_tidsimshadow;
342 /* shadow copy of struct page *'s for exp tid pages */
343 struct page **ipath_pageshadow;
344 /* lock to workaround chip bug 9437 */
345 spinlock_t ipath_tid_lock;
346
347 /*
348 * IPATH_STATUS_*,
349 * this address is mapped readonly into user processes so they can
350 * get status cheaply, whenever they want.
351 */
352 u64 *ipath_statusp;
353 /* freeze msg if hw error put chip in freeze */
354 char *ipath_freezemsg;
355 /* pci access data structure */
356 struct pci_dev *pcidev;
357 struct cdev *cdev;
358 struct class_device *class_dev;
359 /* timer used to prevent stats overflow, error throttling, etc. */
360 struct timer_list ipath_stats_timer;
361 /* check for stale messages in rcv queue */
362 /* only allow one intr at a time. */
363 unsigned long ipath_rcv_pending;
364
365 /*
366 * Shadow copies of registers; size indicates read access size.
367 * Most of them are readonly, but some are write-only register,
368 * where we manipulate the bits in the shadow copy, and then write
369 * the shadow copy to infinipath.
370 *
371 * We deliberately make most of these 32 bits, since they have
372 * restricted range. For any that we read, we won't to generate 32
373 * bit accesses, since Opteron will generate 2 separate 32 bit HT
374 * transactions for a 64 bit read, and we want to avoid unnecessary
375 * HT transactions.
376 */
377
378 /* This is the 64 bit group */
379
380 /*
381 * shadow of pioavail, check to be sure it's large enough at
382 * init time.
383 */
384 unsigned long ipath_pioavailshadow[8];
385 /* shadow of kr_gpio_out, for rmw ops */
386 u64 ipath_gpio_out;
387 /* kr_revision shadow */
388 u64 ipath_revision;
389 /*
390 * shadow of ibcctrl, for interrupt handling of link changes,
391 * etc.
392 */
393 u64 ipath_ibcctrl;
394 /*
395 * last ibcstatus, to suppress "duplicate" status change messages,
396 * mostly from 2 to 3
397 */
398 u64 ipath_lastibcstat;
399 /* hwerrmask shadow */
400 ipath_err_t ipath_hwerrmask;
401 /* interrupt config reg shadow */
402 u64 ipath_intconfig;
403 /* kr_sendpiobufbase value */
404 u64 ipath_piobufbase;
405
406 /* these are the "32 bit" regs */
407
408 /*
409 * number of GUIDs in the flash for this interface; may need some
410 * rethinking for setting on other ifaces
411 */
412 u32 ipath_nguid;
413 /*
414 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
415 * all expect bit fields to be "unsigned long"
416 */
417 /* shadow kr_rcvctrl */
418 unsigned long ipath_rcvctrl;
419 /* shadow kr_sendctrl */
420 unsigned long ipath_sendctrl;
421
422 /* value we put in kr_rcvhdrcnt */
423 u32 ipath_rcvhdrcnt;
424 /* value we put in kr_rcvhdrsize */
425 u32 ipath_rcvhdrsize;
426 /* value we put in kr_rcvhdrentsize */
427 u32 ipath_rcvhdrentsize;
428 /* offset of last entry in rcvhdrq */
429 u32 ipath_hdrqlast;
430 /* kr_portcnt value */
431 u32 ipath_portcnt;
432 /* kr_pagealign value */
433 u32 ipath_palign;
434 /* number of "2KB" PIO buffers */
435 u32 ipath_piobcnt2k;
436 /* size in bytes of "2KB" PIO buffers */
437 u32 ipath_piosize2k;
438 /* number of "4KB" PIO buffers */
439 u32 ipath_piobcnt4k;
440 /* size in bytes of "4KB" PIO buffers */
441 u32 ipath_piosize4k;
442 /* kr_rcvegrbase value */
443 u32 ipath_rcvegrbase;
444 /* kr_rcvegrcnt value */
445 u32 ipath_rcvegrcnt;
446 /* kr_rcvtidbase value */
447 u32 ipath_rcvtidbase;
448 /* kr_rcvtidcnt value */
449 u32 ipath_rcvtidcnt;
450 /* kr_sendregbase */
451 u32 ipath_sregbase;
452 /* kr_userregbase */
453 u32 ipath_uregbase;
454 /* kr_counterregbase */
455 u32 ipath_cregbase;
456 /* shadow the control register contents */
457 u32 ipath_control;
458 /* shadow the gpio output contents */
459 u32 ipath_extctrl;
460 /* PCI revision register (HTC rev on FPGA) */
461 u32 ipath_pcirev;
462
463 /* chip address space used by 4k pio buffers */
464 u32 ipath_4kalign;
465 /* The MTU programmed for this unit */
466 u32 ipath_ibmtu;
467 /*
468 * The max size IB packet, included IB headers that we can send.
469 * Starts same as ipath_piosize, but is affected when ibmtu is
470 * changed, or by size of eager buffers
471 */
472 u32 ipath_ibmaxlen;
473 /*
474 * ibmaxlen at init time, limited by chip and by receive buffer
475 * size. Not changed after init.
476 */
477 u32 ipath_init_ibmaxlen;
478 /* size of each rcvegrbuffer */
479 u32 ipath_rcvegrbufsize;
480 /* width (2,4,8,16,32) from HT config reg */
481 u32 ipath_htwidth;
482 /* HT speed (200,400,800,1000) from HT config */
483 u32 ipath_htspeed;
484 /* ports waiting for PIOavail intr */
485 unsigned long ipath_portpiowait;
486 /*
487 * number of sequential ibcstatus change for polling active/quiet
488 * (i.e., link not coming up).
489 */
490 u32 ipath_ibpollcnt;
491 /* low and high portions of MSI capability/vector */
492 u32 ipath_msi_lo;
493 /* saved after PCIe init for restore after reset */
494 u32 ipath_msi_hi;
495 /* MSI data (vector) saved for restore */
496 u16 ipath_msi_data;
497 /* MLID programmed for this instance */
498 u16 ipath_mlid;
499 /* LID programmed for this instance */
500 u16 ipath_lid;
501 /* list of pkeys programmed; 0 if not set */
502 u16 ipath_pkeys[4];
503 /* ASCII serial number, from flash */
504 u8 ipath_serial[12];
505 /* human readable board version */
506 u8 ipath_boardversion[80];
507 /* chip major rev, from ipath_revision */
508 u8 ipath_majrev;
509 /* chip minor rev, from ipath_revision */
510 u8 ipath_minrev;
511 /* board rev, from ipath_revision */
512 u8 ipath_boardrev;
513 /* unit # of this chip, if present */
514 int ipath_unit;
515 /* saved for restore after reset */
516 u8 ipath_pci_cacheline;
517 /* LID mask control */
518 u8 ipath_lmc;
519};
520
521extern volatile __le64 *ipath_port0_rcvhdrtail;
522extern dma_addr_t ipath_port0_rcvhdrtail_dma;
523
524#define IPATH_PORT0_RCVHDRTAIL_SIZE PAGE_SIZE
525
526extern struct list_head ipath_dev_list;
527extern spinlock_t ipath_devs_lock;
528extern struct ipath_devdata *ipath_lookup(int unit);
529
530extern u16 ipath_layer_rcv_opcode;
531extern int ipath_verbs_registered;
532extern int __ipath_layer_intr(struct ipath_devdata *, u32);
533extern int ipath_layer_intr(struct ipath_devdata *, u32);
534extern int __ipath_layer_rcv(struct ipath_devdata *, void *,
535 struct sk_buff *);
536extern int __ipath_layer_rcv_lid(struct ipath_devdata *, void *);
537extern int __ipath_verbs_piobufavail(struct ipath_devdata *);
538extern int __ipath_verbs_rcv(struct ipath_devdata *, void *, void *, u32);
539
540void ipath_layer_add(struct ipath_devdata *);
541void ipath_layer_del(struct ipath_devdata *);
542
543int ipath_init_chip(struct ipath_devdata *, int);
544int ipath_enable_wc(struct ipath_devdata *dd);
545void ipath_disable_wc(struct ipath_devdata *dd);
546int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
547void ipath_shutdown_device(struct ipath_devdata *);
548
549struct file_operations;
550int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
551 struct cdev **cdevp, struct class_device **class_devp);
552void ipath_cdev_cleanup(struct cdev **cdevp,
553 struct class_device **class_devp);
554
555int ipath_diag_init(void);
556void ipath_diag_cleanup(void);
557void ipath_diag_bringup_link(struct ipath_devdata *);
558
559extern wait_queue_head_t ipath_sma_state_wait;
560
561int ipath_user_add(struct ipath_devdata *dd);
562void ipath_user_del(struct ipath_devdata *dd);
563
564struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
565
566extern int ipath_diag_inuse;
567
568irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
569void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
570#if __IPATH_INFO || __IPATH_DBG
571extern const char *ipath_ibcstatus_str[];
572#endif
573
574/* clean up any per-chip chip-specific stuff */
575void ipath_chip_cleanup(struct ipath_devdata *);
576/* clean up any chip type-specific stuff */
577void ipath_chip_done(void);
578
579/* check to see if we have to force ordering for write combining */
580int ipath_unordered_wc(void);
581
582void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
583 unsigned cnt);
584
585int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
586void ipath_free_pddata(struct ipath_devdata *, u32, int);
587
588int ipath_parse_ushort(const char *str, unsigned short *valp);
589
590int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
591void ipath_set_ib_lstate(struct ipath_devdata *, int);
592void ipath_kreceive(struct ipath_devdata *);
593int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
594int ipath_reset_device(int);
595void ipath_get_faststats(unsigned long);
596
597/* for use in system calls, where we want to know device type, etc. */
598#define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
599
600/*
601 * values for ipath_flags
602 */
603/* The chip is up and initted */
604#define IPATH_INITTED 0x2
605 /* set if any user code has set kr_rcvhdrsize */
606#define IPATH_RCVHDRSZ_SET 0x4
607 /* The chip is present and valid for accesses */
608#define IPATH_PRESENT 0x8
609 /* HT link0 is only 8 bits wide, ignore upper byte crc
610 * errors, etc. */
611#define IPATH_8BIT_IN_HT0 0x10
612 /* HT link1 is only 8 bits wide, ignore upper byte crc
613 * errors, etc. */
614#define IPATH_8BIT_IN_HT1 0x20
615 /* The link is down */
616#define IPATH_LINKDOWN 0x40
617 /* The link level is up (0x11) */
618#define IPATH_LINKINIT 0x80
619 /* The link is in the armed (0x21) state */
620#define IPATH_LINKARMED 0x100
621 /* The link is in the active (0x31) state */
622#define IPATH_LINKACTIVE 0x200
623 /* link current state is unknown */
624#define IPATH_LINKUNK 0x400
625 /* no IB cable, or no device on IB cable */
626#define IPATH_NOCABLE 0x4000
627 /* Supports port zero per packet receive interrupts via
628 * GPIO */
629#define IPATH_GPIO_INTR 0x8000
630 /* uses the coded 4byte TID, not 8 byte */
631#define IPATH_4BYTE_TID 0x10000
632 /* packet/word counters are 32 bit, else those 4 counters
633 * are 64bit */
634#define IPATH_32BITCOUNTERS 0x20000
635 /* can miss port0 rx interrupts */
636#define IPATH_POLL_RX_INTR 0x40000
637#define IPATH_DISABLED 0x80000 /* administratively disabled */
638
639/* portdata flag bit offsets */
640 /* waiting for a packet to arrive */
641#define IPATH_PORT_WAITING_RCV 2
642 /* waiting for a PIO buffer to be available */
643#define IPATH_PORT_WAITING_PIO 3
644
645/* free up any allocated data at closes */
646void ipath_free_data(struct ipath_portdata *dd);
647int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
648int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
649u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
650/* init PE-800-specific func */
651void ipath_init_pe800_funcs(struct ipath_devdata *);
652/* init HT-400-specific func */
653void ipath_init_ht400_funcs(struct ipath_devdata *);
654void ipath_get_guid(struct ipath_devdata *);
655u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
656
657/*
658 * number of words used for protocol header if not set by ipath_userinit();
659 */
660#define IPATH_DFLT_RCVHDRSIZE 9
661
662#define IPATH_MDIO_CMD_WRITE 1
663#define IPATH_MDIO_CMD_READ 2
664#define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
665#define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
666#define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
667#define IPATH_MDIO_CTRL_STD 0x0
668
669static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
670{
671 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
672 (cmd << 26) |
673 (dev << 21) |
674 (reg << 16) |
675 (data & 0xFFFF);
676}
677
678 /* signal and fifo status, in bank 31 */
679#define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
680 /* controls loopback, redundancy */
681#define IPATH_MDIO_CTRL_8355_REG_1 0x10
682 /* premph, encdec, etc. */
683#define IPATH_MDIO_CTRL_8355_REG_2 0x11
684 /* Kchars, etc. */
685#define IPATH_MDIO_CTRL_8355_REG_6 0x15
686#define IPATH_MDIO_CTRL_8355_REG_9 0x18
687#define IPATH_MDIO_CTRL_8355_REG_10 0x1D
688
689int ipath_get_user_pages(unsigned long, size_t, struct page **);
690int ipath_get_user_pages_nocopy(unsigned long, struct page **);
691void ipath_release_user_pages(struct page **, size_t);
692void ipath_release_user_pages_on_close(struct page **, size_t);
693int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
694int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
695
696/* these are used for the registers that vary with port */
697void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
698 unsigned, u64);
699u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
700 unsigned);
701
702/*
703 * We could have a single register get/put routine, that takes a group type,
704 * but this is somewhat clearer and cleaner. It also gives us some error
705 * checking. 64 bit register reads should always work, but are inefficient
706 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
707 * so we use kreg32 wherever possible. User register and counter register
708 * reads are always 32 bit reads, so only one form of those routines.
709 */
710
711/*
712 * At the moment, none of the s-registers are writable, so no
713 * ipath_write_sreg(), and none of the c-registers are writable, so no
714 * ipath_write_creg().
715 */
716
717/**
718 * ipath_read_ureg32 - read 32-bit virtualized per-port register
719 * @dd: device
720 * @regno: register number
721 * @port: port number
722 *
723 * Return the contents of a register that is virtualized to be per port.
724 * Prints a debug message and returns -1 on errors (not distinguishable from
725 * valid contents at runtime; we may add a separate error variable at some
726 * point).
727 *
728 * This is normally not used by the kernel, but may be for debugging, and
729 * has a different implementation than user mode, which is why it's not in
730 * _common.h.
731 */
732static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
733 ipath_ureg regno, int port)
734{
735 if (!dd->ipath_kregbase)
736 return 0;
737
738 return readl(regno + (u64 __iomem *)
739 (dd->ipath_uregbase +
740 (char __iomem *)dd->ipath_kregbase +
741 dd->ipath_palign * port));
742}
743
744/**
745 * ipath_write_ureg - write 32-bit virtualized per-port register
746 * @dd: device
747 * @regno: register number
748 * @value: value
749 * @port: port
750 *
751 * Write the contents of a register that is virtualized to be per port.
752 */
753static inline void ipath_write_ureg(const struct ipath_devdata *dd,
754 ipath_ureg regno, u64 value, int port)
755{
756 u64 __iomem *ubase = (u64 __iomem *)
757 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
758 dd->ipath_palign * port);
759 if (dd->ipath_kregbase)
760 writeq(value, &ubase[regno]);
761}
762
763static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
764 ipath_kreg regno)
765{
766 if (!dd->ipath_kregbase)
767 return -1;
768 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
769}
770
771static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
772 ipath_kreg regno)
773{
774 if (!dd->ipath_kregbase)
775 return -1;
776
777 return readq(&dd->ipath_kregbase[regno]);
778}
779
780static inline void ipath_write_kreg(const struct ipath_devdata *dd,
781 ipath_kreg regno, u64 value)
782{
783 if (dd->ipath_kregbase)
784 writeq(value, &dd->ipath_kregbase[regno]);
785}
786
787static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
788 ipath_sreg regno)
789{
790 if (!dd->ipath_kregbase)
791 return 0;
792
793 return readq(regno + (u64 __iomem *)
794 (dd->ipath_cregbase +
795 (char __iomem *)dd->ipath_kregbase));
796}
797
798static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
799 ipath_sreg regno)
800{
801 if (!dd->ipath_kregbase)
802 return 0;
803 return readl(regno + (u64 __iomem *)
804 (dd->ipath_cregbase +
805 (char __iomem *)dd->ipath_kregbase));
806}
807
808/*
809 * sysfs interface.
810 */
811
812struct device_driver;
813
814extern const char ipath_core_version[];
815
816int ipath_driver_create_group(struct device_driver *);
817void ipath_driver_remove_group(struct device_driver *);
818
819int ipath_device_create_group(struct device *, struct ipath_devdata *);
820void ipath_device_remove_group(struct device *, struct ipath_devdata *);
821int ipath_expose_reset(struct device *);
822
823int ipath_init_ipathfs(void);
824void ipath_exit_ipathfs(void);
825int ipathfs_add_device(struct ipath_devdata *);
826int ipathfs_remove_device(struct ipath_devdata *);
827
828/*
829 * Flush write combining store buffers (if present) and perform a write
830 * barrier.
831 */
832#if defined(CONFIG_X86_64)
833#define ipath_flush_wc() asm volatile("sfence" ::: "memory")
834#else
835#define ipath_flush_wc() wmb()
836#endif
837
838extern unsigned ipath_debug; /* debugging bit mask */
839
840const char *ipath_get_unit_name(int unit);
841
842extern struct mutex ipath_mutex;
843
844#define IPATH_DRV_NAME "ipath_core"
845#define IPATH_MAJOR 233
846#define IPATH_SMA_MINOR 128
847#define IPATH_DIAG_MINOR 129
848#define IPATH_NMINORS 130
849
850#define ipath_dev_err(dd,fmt,...) \
851 do { \
852 const struct ipath_devdata *__dd = (dd); \
853 if (__dd->pcidev) \
854 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
855 ipath_get_unit_name(__dd->ipath_unit), \
856 ##__VA_ARGS__); \
857 else \
858 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
859 ipath_get_unit_name(__dd->ipath_unit), \
860 ##__VA_ARGS__); \
861 } while (0)
862
863#if _IPATH_DEBUGGING
864
865# define __IPATH_DBG_WHICH(which,fmt,...) \
866 do { \
867 if(unlikely(ipath_debug&(which))) \
868 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
869 __func__,##__VA_ARGS__); \
870 } while(0)
871
872# define ipath_dbg(fmt,...) \
873 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
874# define ipath_cdbg(which,fmt,...) \
875 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
876
877#else /* ! _IPATH_DEBUGGING */
878
879# define ipath_dbg(fmt,...)
880# define ipath_cdbg(which,fmt,...)
881
882#endif /* _IPATH_DEBUGGING */
883
884#endif /* _IPATH_KERNEL_H */
Linux kernel - Deliverables
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