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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
35 | #include <linux/mlx4/qp.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
225c7b1f RD |
37 | |
38 | #include "mlx4_ib.h" | |
39 | #include "user.h" | |
40 | ||
41 | static void mlx4_ib_cq_comp(struct mlx4_cq *cq) | |
42 | { | |
43 | struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; | |
44 | ibcq->comp_handler(ibcq, ibcq->cq_context); | |
45 | } | |
46 | ||
47 | static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) | |
48 | { | |
49 | struct ib_event event; | |
50 | struct ib_cq *ibcq; | |
51 | ||
52 | if (type != MLX4_EVENT_TYPE_CQ_ERROR) { | |
987c8f8f | 53 | pr_warn("Unexpected event type %d " |
225c7b1f RD |
54 | "on CQ %06x\n", type, cq->cqn); |
55 | return; | |
56 | } | |
57 | ||
58 | ibcq = &to_mibcq(cq)->ibcq; | |
59 | if (ibcq->event_handler) { | |
60 | event.device = ibcq->device; | |
61 | event.event = IB_EVENT_CQ_ERR; | |
62 | event.element.cq = ibcq; | |
63 | ibcq->event_handler(&event, ibcq->cq_context); | |
64 | } | |
65 | } | |
66 | ||
67 | static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) | |
68 | { | |
08ff3235 | 69 | return mlx4_buf_offset(&buf->buf, n * buf->entry_size); |
225c7b1f RD |
70 | } |
71 | ||
72 | static void *get_cqe(struct mlx4_ib_cq *cq, int n) | |
73 | { | |
74 | return get_cqe_from_buf(&cq->buf, n); | |
75 | } | |
76 | ||
77 | static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) | |
78 | { | |
79 | struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); | |
08ff3235 | 80 | struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); |
225c7b1f | 81 | |
08ff3235 | 82 | return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ |
225c7b1f RD |
83 | !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; |
84 | } | |
85 | ||
86 | static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) | |
87 | { | |
88 | return get_sw_cqe(cq, cq->mcq.cons_index); | |
89 | } | |
90 | ||
3fdcb97f EC |
91 | int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) |
92 | { | |
93 | struct mlx4_ib_cq *mcq = to_mcq(cq); | |
94 | struct mlx4_ib_dev *dev = to_mdev(cq->device); | |
95 | ||
96 | return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); | |
97 | } | |
98 | ||
bbf8eed1 VS |
99 | static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) |
100 | { | |
101 | int err; | |
102 | ||
08ff3235 | 103 | err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, |
bbf8eed1 VS |
104 | PAGE_SIZE * 2, &buf->buf); |
105 | ||
106 | if (err) | |
107 | goto out; | |
108 | ||
08ff3235 | 109 | buf->entry_size = dev->dev->caps.cqe_size; |
bbf8eed1 VS |
110 | err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, |
111 | &buf->mtt); | |
112 | if (err) | |
113 | goto err_buf; | |
114 | ||
115 | err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); | |
116 | if (err) | |
117 | goto err_mtt; | |
118 | ||
119 | return 0; | |
120 | ||
121 | err_mtt: | |
122 | mlx4_mtt_cleanup(dev->dev, &buf->mtt); | |
123 | ||
124 | err_buf: | |
08ff3235 | 125 | mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); |
bbf8eed1 VS |
126 | |
127 | out: | |
128 | return err; | |
129 | } | |
130 | ||
131 | static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) | |
132 | { | |
08ff3235 | 133 | mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); |
bbf8eed1 VS |
134 | } |
135 | ||
136 | static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context, | |
137 | struct mlx4_ib_cq_buf *buf, struct ib_umem **umem, | |
138 | u64 buf_addr, int cqe) | |
139 | { | |
140 | int err; | |
08ff3235 | 141 | int cqe_size = dev->dev->caps.cqe_size; |
bbf8eed1 | 142 | |
08ff3235 | 143 | *umem = ib_umem_get(context, buf_addr, cqe * cqe_size, |
cb9fbc5c | 144 | IB_ACCESS_LOCAL_WRITE, 1); |
bbf8eed1 VS |
145 | if (IS_ERR(*umem)) |
146 | return PTR_ERR(*umem); | |
147 | ||
148 | err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem), | |
149 | ilog2((*umem)->page_size), &buf->mtt); | |
150 | if (err) | |
151 | goto err_buf; | |
152 | ||
153 | err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); | |
154 | if (err) | |
155 | goto err_mtt; | |
156 | ||
157 | return 0; | |
158 | ||
159 | err_mtt: | |
160 | mlx4_mtt_cleanup(dev->dev, &buf->mtt); | |
161 | ||
162 | err_buf: | |
163 | ib_umem_release(*umem); | |
164 | ||
165 | return err; | |
166 | } | |
167 | ||
225c7b1f RD |
168 | struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector, |
169 | struct ib_ucontext *context, | |
170 | struct ib_udata *udata) | |
171 | { | |
172 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
173 | struct mlx4_ib_cq *cq; | |
174 | struct mlx4_uar *uar; | |
225c7b1f RD |
175 | int err; |
176 | ||
177 | if (entries < 1 || entries > dev->dev->caps.max_cqes) | |
178 | return ERR_PTR(-EINVAL); | |
179 | ||
180 | cq = kmalloc(sizeof *cq, GFP_KERNEL); | |
181 | if (!cq) | |
182 | return ERR_PTR(-ENOMEM); | |
183 | ||
184 | entries = roundup_pow_of_two(entries + 1); | |
185 | cq->ibcq.cqe = entries - 1; | |
bbf8eed1 | 186 | mutex_init(&cq->resize_mutex); |
225c7b1f | 187 | spin_lock_init(&cq->lock); |
bbf8eed1 VS |
188 | cq->resize_buf = NULL; |
189 | cq->resize_umem = NULL; | |
225c7b1f RD |
190 | |
191 | if (context) { | |
192 | struct mlx4_ib_create_cq ucmd; | |
193 | ||
194 | if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { | |
195 | err = -EFAULT; | |
196 | goto err_cq; | |
197 | } | |
198 | ||
bbf8eed1 VS |
199 | err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem, |
200 | ucmd.buf_addr, entries); | |
225c7b1f | 201 | if (err) |
bbf8eed1 | 202 | goto err_cq; |
225c7b1f RD |
203 | |
204 | err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr, | |
205 | &cq->db); | |
206 | if (err) | |
207 | goto err_mtt; | |
208 | ||
209 | uar = &to_mucontext(context)->uar; | |
210 | } else { | |
6296883c | 211 | err = mlx4_db_alloc(dev->dev, &cq->db, 1); |
225c7b1f RD |
212 | if (err) |
213 | goto err_cq; | |
214 | ||
215 | cq->mcq.set_ci_db = cq->db.db; | |
216 | cq->mcq.arm_db = cq->db.db + 1; | |
217 | *cq->mcq.set_ci_db = 0; | |
218 | *cq->mcq.arm_db = 0; | |
219 | ||
bbf8eed1 | 220 | err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); |
225c7b1f | 221 | if (err) |
bbf8eed1 | 222 | goto err_db; |
225c7b1f RD |
223 | |
224 | uar = &dev->priv_uar; | |
225 | } | |
226 | ||
e605b743 SP |
227 | if (dev->eq_table) |
228 | vector = dev->eq_table[vector % ibdev->num_comp_vectors]; | |
229 | ||
225c7b1f | 230 | err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, |
b8dd786f | 231 | cq->db.dma, &cq->mcq, vector, 0); |
225c7b1f RD |
232 | if (err) |
233 | goto err_dbmap; | |
234 | ||
235 | cq->mcq.comp = mlx4_ib_cq_comp; | |
236 | cq->mcq.event = mlx4_ib_cq_event; | |
237 | ||
238 | if (context) | |
239 | if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { | |
240 | err = -EFAULT; | |
241 | goto err_dbmap; | |
242 | } | |
243 | ||
244 | return &cq->ibcq; | |
245 | ||
246 | err_dbmap: | |
247 | if (context) | |
248 | mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db); | |
249 | ||
250 | err_mtt: | |
251 | mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); | |
252 | ||
225c7b1f RD |
253 | if (context) |
254 | ib_umem_release(cq->umem); | |
255 | else | |
3ae15e16 | 256 | mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); |
225c7b1f RD |
257 | |
258 | err_db: | |
259 | if (!context) | |
6296883c | 260 | mlx4_db_free(dev->dev, &cq->db); |
225c7b1f RD |
261 | |
262 | err_cq: | |
263 | kfree(cq); | |
264 | ||
265 | return ERR_PTR(err); | |
266 | } | |
267 | ||
bbf8eed1 VS |
268 | static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, |
269 | int entries) | |
270 | { | |
271 | int err; | |
272 | ||
273 | if (cq->resize_buf) | |
274 | return -EBUSY; | |
275 | ||
276 | cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC); | |
277 | if (!cq->resize_buf) | |
278 | return -ENOMEM; | |
279 | ||
280 | err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); | |
281 | if (err) { | |
282 | kfree(cq->resize_buf); | |
283 | cq->resize_buf = NULL; | |
284 | return err; | |
285 | } | |
286 | ||
287 | cq->resize_buf->cqe = entries - 1; | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, | |
293 | int entries, struct ib_udata *udata) | |
294 | { | |
295 | struct mlx4_ib_resize_cq ucmd; | |
296 | int err; | |
297 | ||
298 | if (cq->resize_umem) | |
299 | return -EBUSY; | |
300 | ||
301 | if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) | |
302 | return -EFAULT; | |
303 | ||
304 | cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC); | |
305 | if (!cq->resize_buf) | |
306 | return -ENOMEM; | |
307 | ||
308 | err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf, | |
309 | &cq->resize_umem, ucmd.buf_addr, entries); | |
310 | if (err) { | |
311 | kfree(cq->resize_buf); | |
312 | cq->resize_buf = NULL; | |
313 | return err; | |
314 | } | |
315 | ||
316 | cq->resize_buf->cqe = entries - 1; | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) | |
322 | { | |
323 | u32 i; | |
324 | ||
325 | i = cq->mcq.cons_index; | |
326 | while (get_sw_cqe(cq, i & cq->ibcq.cqe)) | |
327 | ++i; | |
328 | ||
329 | return i - cq->mcq.cons_index; | |
330 | } | |
331 | ||
332 | static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) | |
333 | { | |
7798dbf4 | 334 | struct mlx4_cqe *cqe, *new_cqe; |
bbf8eed1 | 335 | int i; |
08ff3235 OG |
336 | int cqe_size = cq->buf.entry_size; |
337 | int cqe_inc = cqe_size == 64 ? 1 : 0; | |
bbf8eed1 VS |
338 | |
339 | i = cq->mcq.cons_index; | |
340 | cqe = get_cqe(cq, i & cq->ibcq.cqe); | |
08ff3235 OG |
341 | cqe += cqe_inc; |
342 | ||
bbf8eed1 | 343 | while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { |
7798dbf4 JM |
344 | new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, |
345 | (i + 1) & cq->resize_buf->cqe); | |
08ff3235 OG |
346 | memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); |
347 | new_cqe += cqe_inc; | |
348 | ||
7798dbf4 JM |
349 | new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | |
350 | (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); | |
bbf8eed1 | 351 | cqe = get_cqe(cq, ++i & cq->ibcq.cqe); |
08ff3235 | 352 | cqe += cqe_inc; |
bbf8eed1 VS |
353 | } |
354 | ++cq->mcq.cons_index; | |
355 | } | |
356 | ||
357 | int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) | |
358 | { | |
359 | struct mlx4_ib_dev *dev = to_mdev(ibcq->device); | |
360 | struct mlx4_ib_cq *cq = to_mcq(ibcq); | |
42ab01c3 | 361 | struct mlx4_mtt mtt; |
bbf8eed1 VS |
362 | int outst_cqe; |
363 | int err; | |
364 | ||
365 | mutex_lock(&cq->resize_mutex); | |
366 | ||
367 | if (entries < 1 || entries > dev->dev->caps.max_cqes) { | |
368 | err = -EINVAL; | |
369 | goto out; | |
370 | } | |
371 | ||
372 | entries = roundup_pow_of_two(entries + 1); | |
373 | if (entries == ibcq->cqe + 1) { | |
374 | err = 0; | |
375 | goto out; | |
376 | } | |
377 | ||
378 | if (ibcq->uobject) { | |
379 | err = mlx4_alloc_resize_umem(dev, cq, entries, udata); | |
380 | if (err) | |
381 | goto out; | |
382 | } else { | |
025dfdaf | 383 | /* Can't be smaller than the number of outstanding CQEs */ |
bbf8eed1 VS |
384 | outst_cqe = mlx4_ib_get_outstanding_cqes(cq); |
385 | if (entries < outst_cqe + 1) { | |
386 | err = 0; | |
387 | goto out; | |
388 | } | |
389 | ||
390 | err = mlx4_alloc_resize_buf(dev, cq, entries); | |
391 | if (err) | |
392 | goto out; | |
393 | } | |
394 | ||
42ab01c3 JM |
395 | mtt = cq->buf.mtt; |
396 | ||
bbf8eed1 VS |
397 | err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); |
398 | if (err) | |
399 | goto err_buf; | |
400 | ||
42ab01c3 | 401 | mlx4_mtt_cleanup(dev->dev, &mtt); |
bbf8eed1 VS |
402 | if (ibcq->uobject) { |
403 | cq->buf = cq->resize_buf->buf; | |
404 | cq->ibcq.cqe = cq->resize_buf->cqe; | |
405 | ib_umem_release(cq->umem); | |
406 | cq->umem = cq->resize_umem; | |
407 | ||
408 | kfree(cq->resize_buf); | |
409 | cq->resize_buf = NULL; | |
410 | cq->resize_umem = NULL; | |
411 | } else { | |
3afa9f19 VS |
412 | struct mlx4_ib_cq_buf tmp_buf; |
413 | int tmp_cqe = 0; | |
414 | ||
bbf8eed1 VS |
415 | spin_lock_irq(&cq->lock); |
416 | if (cq->resize_buf) { | |
417 | mlx4_ib_cq_resize_copy_cqes(cq); | |
3afa9f19 VS |
418 | tmp_buf = cq->buf; |
419 | tmp_cqe = cq->ibcq.cqe; | |
bbf8eed1 VS |
420 | cq->buf = cq->resize_buf->buf; |
421 | cq->ibcq.cqe = cq->resize_buf->cqe; | |
422 | ||
423 | kfree(cq->resize_buf); | |
424 | cq->resize_buf = NULL; | |
425 | } | |
426 | spin_unlock_irq(&cq->lock); | |
3afa9f19 VS |
427 | |
428 | if (tmp_cqe) | |
429 | mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); | |
bbf8eed1 VS |
430 | } |
431 | ||
432 | goto out; | |
433 | ||
434 | err_buf: | |
42ab01c3 | 435 | mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); |
bbf8eed1 VS |
436 | if (!ibcq->uobject) |
437 | mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, | |
438 | cq->resize_buf->cqe); | |
439 | ||
440 | kfree(cq->resize_buf); | |
441 | cq->resize_buf = NULL; | |
442 | ||
443 | if (cq->resize_umem) { | |
444 | ib_umem_release(cq->resize_umem); | |
445 | cq->resize_umem = NULL; | |
446 | } | |
447 | ||
448 | out: | |
449 | mutex_unlock(&cq->resize_mutex); | |
08ff3235 | 450 | |
bbf8eed1 VS |
451 | return err; |
452 | } | |
453 | ||
225c7b1f RD |
454 | int mlx4_ib_destroy_cq(struct ib_cq *cq) |
455 | { | |
456 | struct mlx4_ib_dev *dev = to_mdev(cq->device); | |
457 | struct mlx4_ib_cq *mcq = to_mcq(cq); | |
458 | ||
459 | mlx4_cq_free(dev->dev, &mcq->mcq); | |
460 | mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); | |
461 | ||
462 | if (cq->uobject) { | |
463 | mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db); | |
464 | ib_umem_release(mcq->umem); | |
465 | } else { | |
3ae15e16 | 466 | mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); |
6296883c | 467 | mlx4_db_free(dev->dev, &mcq->db); |
225c7b1f RD |
468 | } |
469 | ||
470 | kfree(mcq); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static void dump_cqe(void *cqe) | |
476 | { | |
477 | __be32 *buf = cqe; | |
478 | ||
987c8f8f | 479 | pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", |
225c7b1f RD |
480 | be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), |
481 | be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), | |
482 | be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); | |
483 | } | |
484 | ||
485 | static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, | |
486 | struct ib_wc *wc) | |
487 | { | |
488 | if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { | |
987c8f8f | 489 | pr_debug("local QP operation err " |
225c7b1f RD |
490 | "(QPN %06x, WQE index %x, vendor syndrome %02x, " |
491 | "opcode = %02x)\n", | |
492 | be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), | |
493 | cqe->vendor_err_syndrome, | |
494 | cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); | |
495 | dump_cqe(cqe); | |
496 | } | |
497 | ||
498 | switch (cqe->syndrome) { | |
499 | case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: | |
500 | wc->status = IB_WC_LOC_LEN_ERR; | |
501 | break; | |
502 | case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: | |
503 | wc->status = IB_WC_LOC_QP_OP_ERR; | |
504 | break; | |
505 | case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: | |
506 | wc->status = IB_WC_LOC_PROT_ERR; | |
507 | break; | |
508 | case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: | |
509 | wc->status = IB_WC_WR_FLUSH_ERR; | |
510 | break; | |
511 | case MLX4_CQE_SYNDROME_MW_BIND_ERR: | |
512 | wc->status = IB_WC_MW_BIND_ERR; | |
513 | break; | |
514 | case MLX4_CQE_SYNDROME_BAD_RESP_ERR: | |
515 | wc->status = IB_WC_BAD_RESP_ERR; | |
516 | break; | |
517 | case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: | |
518 | wc->status = IB_WC_LOC_ACCESS_ERR; | |
519 | break; | |
520 | case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: | |
521 | wc->status = IB_WC_REM_INV_REQ_ERR; | |
522 | break; | |
523 | case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: | |
524 | wc->status = IB_WC_REM_ACCESS_ERR; | |
525 | break; | |
526 | case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: | |
527 | wc->status = IB_WC_REM_OP_ERR; | |
528 | break; | |
529 | case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: | |
530 | wc->status = IB_WC_RETRY_EXC_ERR; | |
531 | break; | |
532 | case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: | |
533 | wc->status = IB_WC_RNR_RETRY_EXC_ERR; | |
534 | break; | |
535 | case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: | |
536 | wc->status = IB_WC_REM_ABORT_ERR; | |
537 | break; | |
538 | default: | |
539 | wc->status = IB_WC_GENERAL_ERR; | |
540 | break; | |
541 | } | |
542 | ||
543 | wc->vendor_err = cqe->vendor_err_syndrome; | |
544 | } | |
545 | ||
f780a9f1 | 546 | static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) |
8ff095ec | 547 | { |
f780a9f1 YP |
548 | return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | |
549 | MLX4_CQE_STATUS_IPV4F | | |
550 | MLX4_CQE_STATUS_IPV4OPT | | |
551 | MLX4_CQE_STATUS_IPV6 | | |
552 | MLX4_CQE_STATUS_IPOK)) == | |
553 | cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
554 | MLX4_CQE_STATUS_IPOK)) && | |
555 | (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | | |
556 | MLX4_CQE_STATUS_TCP)) && | |
8ff095ec EC |
557 | checksum == cpu_to_be16(0xffff); |
558 | } | |
559 | ||
1ffeb2eb JM |
560 | static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, |
561 | unsigned tail, struct mlx4_cqe *cqe) | |
562 | { | |
563 | struct mlx4_ib_proxy_sqp_hdr *hdr; | |
564 | ||
565 | ib_dma_sync_single_for_cpu(qp->ibqp.device, | |
566 | qp->sqp_proxy_rcv[tail].map, | |
567 | sizeof (struct mlx4_ib_proxy_sqp_hdr), | |
568 | DMA_FROM_DEVICE); | |
569 | hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); | |
570 | wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); | |
571 | wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); | |
572 | wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); | |
573 | wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; | |
574 | wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; | |
575 | wc->dlid_path_bits = 0; | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
225c7b1f RD |
580 | static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, |
581 | struct mlx4_ib_qp **cur_qp, | |
582 | struct ib_wc *wc) | |
583 | { | |
584 | struct mlx4_cqe *cqe; | |
585 | struct mlx4_qp *mqp; | |
586 | struct mlx4_ib_wq *wq; | |
587 | struct mlx4_ib_srq *srq; | |
588 | int is_send; | |
589 | int is_error; | |
b3226184 | 590 | u32 g_mlpath_rqpn; |
225c7b1f | 591 | u16 wqe_ctr; |
1ffeb2eb | 592 | unsigned tail = 0; |
225c7b1f | 593 | |
bbf8eed1 | 594 | repoll: |
225c7b1f RD |
595 | cqe = next_cqe_sw(cq); |
596 | if (!cqe) | |
597 | return -EAGAIN; | |
598 | ||
08ff3235 OG |
599 | if (cq->buf.entry_size == 64) |
600 | cqe++; | |
601 | ||
225c7b1f RD |
602 | ++cq->mcq.cons_index; |
603 | ||
604 | /* | |
605 | * Make sure we read CQ entry contents after we've checked the | |
606 | * ownership bit. | |
607 | */ | |
608 | rmb(); | |
609 | ||
610 | is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; | |
611 | is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
612 | MLX4_CQE_OPCODE_ERROR; | |
613 | ||
ea54b10c JM |
614 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP && |
615 | is_send)) { | |
987c8f8f | 616 | pr_warn("Completion for NOP opcode detected!\n"); |
ea54b10c JM |
617 | return -EINVAL; |
618 | } | |
619 | ||
bbf8eed1 VS |
620 | /* Resize CQ in progress */ |
621 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { | |
622 | if (cq->resize_buf) { | |
623 | struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); | |
624 | ||
625 | mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); | |
626 | cq->buf = cq->resize_buf->buf; | |
627 | cq->ibcq.cqe = cq->resize_buf->cqe; | |
628 | ||
629 | kfree(cq->resize_buf); | |
630 | cq->resize_buf = NULL; | |
631 | } | |
632 | ||
633 | goto repoll; | |
634 | } | |
635 | ||
225c7b1f | 636 | if (!*cur_qp || |
f780a9f1 | 637 | (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { |
225c7b1f RD |
638 | /* |
639 | * We do not have to take the QP table lock here, | |
640 | * because CQs will be locked while QPs are removed | |
641 | * from the table. | |
642 | */ | |
643 | mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, | |
f780a9f1 | 644 | be32_to_cpu(cqe->vlan_my_qpn)); |
225c7b1f | 645 | if (unlikely(!mqp)) { |
987c8f8f | 646 | pr_warn("CQ %06x with entry for unknown QPN %06x\n", |
f780a9f1 | 647 | cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK); |
225c7b1f RD |
648 | return -EINVAL; |
649 | } | |
650 | ||
651 | *cur_qp = to_mibqp(mqp); | |
652 | } | |
653 | ||
654 | wc->qp = &(*cur_qp)->ibqp; | |
655 | ||
656 | if (is_send) { | |
657 | wq = &(*cur_qp)->sq; | |
ea54b10c JM |
658 | if (!(*cur_qp)->sq_signal_bits) { |
659 | wqe_ctr = be16_to_cpu(cqe->wqe_index); | |
660 | wq->tail += (u16) (wqe_ctr - (u16) wq->tail); | |
661 | } | |
0e6e7416 | 662 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; |
225c7b1f RD |
663 | ++wq->tail; |
664 | } else if ((*cur_qp)->ibqp.srq) { | |
665 | srq = to_msrq((*cur_qp)->ibqp.srq); | |
666 | wqe_ctr = be16_to_cpu(cqe->wqe_index); | |
667 | wc->wr_id = srq->wrid[wqe_ctr]; | |
668 | mlx4_ib_free_srq_wqe(srq, wqe_ctr); | |
669 | } else { | |
670 | wq = &(*cur_qp)->rq; | |
1ffeb2eb JM |
671 | tail = wq->tail & (wq->wqe_cnt - 1); |
672 | wc->wr_id = wq->wrid[tail]; | |
225c7b1f RD |
673 | ++wq->tail; |
674 | } | |
675 | ||
676 | if (unlikely(is_error)) { | |
677 | mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); | |
678 | return 0; | |
679 | } | |
680 | ||
681 | wc->status = IB_WC_SUCCESS; | |
682 | ||
683 | if (is_send) { | |
684 | wc->wc_flags = 0; | |
685 | switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { | |
686 | case MLX4_OPCODE_RDMA_WRITE_IMM: | |
687 | wc->wc_flags |= IB_WC_WITH_IMM; | |
688 | case MLX4_OPCODE_RDMA_WRITE: | |
689 | wc->opcode = IB_WC_RDMA_WRITE; | |
690 | break; | |
691 | case MLX4_OPCODE_SEND_IMM: | |
692 | wc->wc_flags |= IB_WC_WITH_IMM; | |
693 | case MLX4_OPCODE_SEND: | |
95d04f07 | 694 | case MLX4_OPCODE_SEND_INVAL: |
225c7b1f RD |
695 | wc->opcode = IB_WC_SEND; |
696 | break; | |
697 | case MLX4_OPCODE_RDMA_READ: | |
19891915 | 698 | wc->opcode = IB_WC_RDMA_READ; |
225c7b1f RD |
699 | wc->byte_len = be32_to_cpu(cqe->byte_cnt); |
700 | break; | |
701 | case MLX4_OPCODE_ATOMIC_CS: | |
702 | wc->opcode = IB_WC_COMP_SWAP; | |
703 | wc->byte_len = 8; | |
704 | break; | |
705 | case MLX4_OPCODE_ATOMIC_FA: | |
706 | wc->opcode = IB_WC_FETCH_ADD; | |
707 | wc->byte_len = 8; | |
708 | break; | |
6fa8f719 VS |
709 | case MLX4_OPCODE_MASKED_ATOMIC_CS: |
710 | wc->opcode = IB_WC_MASKED_COMP_SWAP; | |
711 | wc->byte_len = 8; | |
712 | break; | |
713 | case MLX4_OPCODE_MASKED_ATOMIC_FA: | |
714 | wc->opcode = IB_WC_MASKED_FETCH_ADD; | |
715 | wc->byte_len = 8; | |
716 | break; | |
225c7b1f RD |
717 | case MLX4_OPCODE_BIND_MW: |
718 | wc->opcode = IB_WC_BIND_MW; | |
719 | break; | |
b832be1e EC |
720 | case MLX4_OPCODE_LSO: |
721 | wc->opcode = IB_WC_LSO; | |
722 | break; | |
95d04f07 RD |
723 | case MLX4_OPCODE_FMR: |
724 | wc->opcode = IB_WC_FAST_REG_MR; | |
725 | break; | |
726 | case MLX4_OPCODE_LOCAL_INVAL: | |
727 | wc->opcode = IB_WC_LOCAL_INV; | |
728 | break; | |
225c7b1f RD |
729 | } |
730 | } else { | |
731 | wc->byte_len = be32_to_cpu(cqe->byte_cnt); | |
732 | ||
733 | switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { | |
734 | case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: | |
00f7ec36 SW |
735 | wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; |
736 | wc->wc_flags = IB_WC_WITH_IMM; | |
737 | wc->ex.imm_data = cqe->immed_rss_invalid; | |
225c7b1f | 738 | break; |
95d04f07 RD |
739 | case MLX4_RECV_OPCODE_SEND_INVAL: |
740 | wc->opcode = IB_WC_RECV; | |
741 | wc->wc_flags = IB_WC_WITH_INVALIDATE; | |
742 | wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); | |
743 | break; | |
225c7b1f RD |
744 | case MLX4_RECV_OPCODE_SEND: |
745 | wc->opcode = IB_WC_RECV; | |
746 | wc->wc_flags = 0; | |
747 | break; | |
748 | case MLX4_RECV_OPCODE_SEND_IMM: | |
00f7ec36 SW |
749 | wc->opcode = IB_WC_RECV; |
750 | wc->wc_flags = IB_WC_WITH_IMM; | |
751 | wc->ex.imm_data = cqe->immed_rss_invalid; | |
225c7b1f RD |
752 | break; |
753 | } | |
754 | ||
1ffeb2eb JM |
755 | if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { |
756 | if ((*cur_qp)->mlx4_ib_qp_type & | |
757 | (MLX4_IB_QPT_PROXY_SMI_OWNER | | |
758 | MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) | |
759 | return use_tunnel_data(*cur_qp, cq, wc, tail, cqe); | |
760 | } | |
761 | ||
225c7b1f | 762 | wc->slid = be16_to_cpu(cqe->rlid); |
b3226184 RD |
763 | g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); |
764 | wc->src_qp = g_mlpath_rqpn & 0xffffff; | |
765 | wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; | |
766 | wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; | |
e1bb7843 | 767 | wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; |
d927d505 OG |
768 | wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, |
769 | cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; | |
9106c410 OG |
770 | if (rdma_port_get_link_layer(wc->qp->device, |
771 | (*cur_qp)->port) == IB_LINK_LAYER_ETHERNET) | |
772 | wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; | |
773 | else | |
774 | wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; | |
225c7b1f RD |
775 | } |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
780 | int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) | |
781 | { | |
782 | struct mlx4_ib_cq *cq = to_mcq(ibcq); | |
783 | struct mlx4_ib_qp *cur_qp = NULL; | |
784 | unsigned long flags; | |
785 | int npolled; | |
786 | int err = 0; | |
787 | ||
788 | spin_lock_irqsave(&cq->lock, flags); | |
789 | ||
790 | for (npolled = 0; npolled < num_entries; ++npolled) { | |
791 | err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled); | |
792 | if (err) | |
793 | break; | |
794 | } | |
795 | ||
3616f9ce | 796 | mlx4_cq_set_ci(&cq->mcq); |
225c7b1f RD |
797 | |
798 | spin_unlock_irqrestore(&cq->lock, flags); | |
799 | ||
800 | if (err == 0 || err == -EAGAIN) | |
801 | return npolled; | |
802 | else | |
803 | return err; | |
804 | } | |
805 | ||
806 | int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) | |
807 | { | |
808 | mlx4_cq_arm(&to_mcq(ibcq)->mcq, | |
809 | (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? | |
810 | MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, | |
811 | to_mdev(ibcq->device)->uar_map, | |
812 | MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |
818 | { | |
819 | u32 prod_index; | |
820 | int nfreed = 0; | |
082dee32 JM |
821 | struct mlx4_cqe *cqe, *dest; |
822 | u8 owner_bit; | |
08ff3235 | 823 | int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; |
225c7b1f RD |
824 | |
825 | /* | |
826 | * First we need to find the current producer index, so we | |
827 | * know where to start cleaning from. It doesn't matter if HW | |
828 | * adds new entries after this loop -- the QP we're worried | |
829 | * about is already in RESET, so the new entries won't come | |
830 | * from our QP and therefore don't need to be checked. | |
831 | */ | |
832 | for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) | |
833 | if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) | |
834 | break; | |
835 | ||
836 | /* | |
837 | * Now sweep backwards through the CQ, removing CQ entries | |
838 | * that match our QP by copying older entries on top of them. | |
839 | */ | |
840 | while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { | |
841 | cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); | |
08ff3235 OG |
842 | cqe += cqe_inc; |
843 | ||
f780a9f1 | 844 | if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { |
225c7b1f RD |
845 | if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) |
846 | mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); | |
847 | ++nfreed; | |
082dee32 JM |
848 | } else if (nfreed) { |
849 | dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); | |
08ff3235 OG |
850 | dest += cqe_inc; |
851 | ||
082dee32 JM |
852 | owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; |
853 | memcpy(dest, cqe, sizeof *cqe); | |
854 | dest->owner_sr_opcode = owner_bit | | |
855 | (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); | |
856 | } | |
225c7b1f RD |
857 | } |
858 | ||
859 | if (nfreed) { | |
860 | cq->mcq.cons_index += nfreed; | |
861 | /* | |
862 | * Make sure update of buffer contents is done before | |
863 | * updating consumer index. | |
864 | */ | |
865 | wmb(); | |
866 | mlx4_cq_set_ci(&cq->mcq); | |
867 | } | |
868 | } | |
869 | ||
870 | void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |
871 | { | |
872 | spin_lock_irq(&cq->lock); | |
873 | __mlx4_ib_cq_clean(cq, qpn, srq); | |
874 | spin_unlock_irq(&cq->lock); | |
875 | } |