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Merge branch 'pm-sleep'
[deliverable/linux.git] / drivers / infiniband / hw / mlx4 / mad.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <rdma/ib_mad.h>
34#include <rdma/ib_smi.h>
37bfc7c1
JM		 35#include <rdma/ib_sa.h>
36#include <rdma/ib_cache.h>
225c7b1f 37
afa8fd1d 38#include <linux/random.h>
225c7b1f 39#include <linux/mlx4/cmd.h>
5a0e3ad6 40#include <linux/gfp.h>
c3779134 41#include <rdma/ib_pma.h>
225c7b1f
RD		 42
43#include "mlx4_ib.h"
44
45enum {
46 MLX4_IB_VENDOR_CLASS1 = 0x9,
47 MLX4_IB_VENDOR_CLASS2 = 0xa
48};
49
fc06573d
JM		 50#define MLX4_TUN_SEND_WRID_SHIFT 34
51#define MLX4_TUN_QPN_SHIFT 32
52#define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT)
53#define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT)
54
55#define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1)
56#define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3)
57
2a4fae14
JM		 58 /* Port mgmt change event handling */
59
60#define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr)
61#define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask)
62#define NUM_IDX_IN_PKEY_TBL_BLK 32
63#define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */
64#define GUID_TBL_BLK_NUM_ENTRIES 8
65#define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES)
66
fc06573d
JM		 67struct mlx4_mad_rcv_buf {
68 struct ib_grh grh;
69 u8 payload[256];
70} __packed;
71
72struct mlx4_mad_snd_buf {
73 u8 payload[256];
74} __packed;
75
76struct mlx4_tunnel_mad {
77 struct ib_grh grh;
78 struct mlx4_ib_tunnel_header hdr;
79 struct ib_mad mad;
80} __packed;
81
82struct mlx4_rcv_tunnel_mad {
83 struct mlx4_rcv_tunnel_hdr hdr;
84 struct ib_grh grh;
85 struct ib_mad mad;
86} __packed;
87
b9c5d6a6 88static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num);
2a4fae14
JM		 89static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num);
90static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
91 int block, u32 change_bitmap);
b9c5d6a6 92
afa8fd1d
JM		 93__be64 mlx4_ib_gen_node_guid(void)
94{
95#define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40))
50bea5c0 96 return cpu_to_be64(NODE_GUID_HI | prandom_u32());
afa8fd1d
JM		 97}
98
b9c5d6a6
OD		 99__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx)
100{
101 return cpu_to_be64(atomic_inc_return(&ctx->tid)) |
102 cpu_to_be64(0xff00000000000000LL);
103}
104
0a9a0188 105int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
a97e2d86
IW		 106 int port, const struct ib_wc *in_wc,
107 const struct ib_grh *in_grh,
108 const void *in_mad, void *response_mad)
225c7b1f
RD		 109{
110 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
111 void *inbox;
112 int err;
113 u32 in_modifier = port;
114 u8 op_modifier = 0;
115
116 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
117 if (IS_ERR(inmailbox))
118 return PTR_ERR(inmailbox);
119 inbox = inmailbox->buf;
120
121 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
122 if (IS_ERR(outmailbox)) {
123 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
124 return PTR_ERR(outmailbox);
125 }
126
127 memcpy(inbox, in_mad, 256);
128
129 /*
130 * Key check traps can't be generated unless we have in_wc to
131 * tell us where to send the trap.
132 */
0a9a0188 133 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc)
225c7b1f 134 op_modifier |= 0x1;
0a9a0188 135 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc)
225c7b1f 136 op_modifier |= 0x2;
0a9a0188
JM		 137 if (mlx4_is_mfunc(dev->dev) &&
138 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc))
139 op_modifier |= 0x8;
225c7b1f
RD		 140
141 if (in_wc) {
142 struct {
143 __be32 my_qpn;
144 u32 reserved1;
145 __be32 rqpn;
146 u8 sl;
147 u8 g_path;
148 u16 reserved2[2];
149 __be16 pkey;
150 u32 reserved3[11];
151 u8 grh[40];
152 } *ext_info;
153
154 memset(inbox + 256, 0, 256);
155 ext_info = inbox + 256;
156
157 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num);
158 ext_info->rqpn = cpu_to_be32(in_wc->src_qp);
159 ext_info->sl = in_wc->sl << 4;
160 ext_info->g_path = in_wc->dlid_path_bits |
161 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
162 ext_info->pkey = cpu_to_be16(in_wc->pkey_index);
163
164 if (in_grh)
165 memcpy(ext_info->grh, in_grh, 40);
166
167 op_modifier |= 0x4;
168
169 in_modifier |= in_wc->slid << 16;
170 }
171
0a9a0188
JM		 172 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier,
173 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier,
f9baff50 174 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
0a9a0188 175 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED);
225c7b1f 176
fe11cb6b 177 if (!err)
225c7b1f
RD		 178 memcpy(response_mad, outmailbox->buf, 256);
179
180 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
181 mlx4_free_cmd_mailbox(dev->dev, outmailbox);
182
183 return err;
184}
185
186static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl)
187{
188 struct ib_ah *new_ah;
189 struct ib_ah_attr ah_attr;
df7fba66 190 unsigned long flags;
225c7b1f
RD		 191
192 if (!dev->send_agent[port_num - 1][0])
193 return;
194
195 memset(&ah_attr, 0, sizeof ah_attr);
196 ah_attr.dlid = lid;
197 ah_attr.sl = sl;
198 ah_attr.port_num = port_num;
199
200 new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd,
201 &ah_attr);
202 if (IS_ERR(new_ah))
203 return;
204
df7fba66 205 spin_lock_irqsave(&dev->sm_lock, flags);
225c7b1f
RD		 206 if (dev->sm_ah[port_num - 1])
207 ib_destroy_ah(dev->sm_ah[port_num - 1]);
208 dev->sm_ah[port_num - 1] = new_ah;
df7fba66 209 spin_unlock_irqrestore(&dev->sm_lock, flags);
225c7b1f
RD		 210}
211
212/*
00f5ce99
JM		 213 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can
214 * synthesize LID change, Client-Rereg, GID change, and P_Key change events.
225c7b1f 215 */
a97e2d86 216static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad,
00f5ce99 217 u16 prev_lid)
225c7b1f 218{
00f5ce99
JM		 219 struct ib_port_info *pinfo;
220 u16 lid;
54679e14
JM		 221 __be16 *base;
222 u32 bn, pkey_change_bitmap;
223 int i;
224
225c7b1f 225
00f5ce99 226 struct mlx4_ib_dev *dev = to_mdev(ibdev);
225c7b1f
RD		 227 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
228 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
00f5ce99
JM		 229 mad->mad_hdr.method == IB_MGMT_METHOD_SET)
230 switch (mad->mad_hdr.attr_id) {
231 case IB_SMP_ATTR_PORT_INFO:
232 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data;
233 lid = be16_to_cpu(pinfo->lid);
225c7b1f 234
00f5ce99 235 update_sm_ah(dev, port_num,
225c7b1f
RD		 236 be16_to_cpu(pinfo->sm_lid),
237 pinfo->neighbormtu_mastersmsl & 0xf);
238
00f5ce99 239 if (pinfo->clientrereg_resv_subnetto & 0x80)
b9c5d6a6 240 handle_client_rereg_event(dev, port_num);
225c7b1f 241
00f5ce99 242 if (prev_lid != lid)
2a4fae14 243 handle_lid_change_event(dev, port_num);
00f5ce99 244 break;
225c7b1f 245
00f5ce99 246 case IB_SMP_ATTR_PKEY_TABLE:
54679e14
JM		 247 if (!mlx4_is_mfunc(dev->dev)) {
248 mlx4_ib_dispatch_event(dev, port_num,
249 IB_EVENT_PKEY_CHANGE);
250 break;
251 }
252
2a4fae14
JM		 253 /* at this point, we are running in the master.
254 * Slaves do not receive SMPs.
255 */
54679e14
JM		 256 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF;
257 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]);
258 pkey_change_bitmap = 0;
259 for (i = 0; i < 32; i++) {
260 pr_debug("PKEY[%d] = x%x\n",
261 i + bn*32, be16_to_cpu(base[i]));
262 if (be16_to_cpu(base[i]) !=
263 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) {
264 pkey_change_bitmap |= (1 << i);
265 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] =
266 be16_to_cpu(base[i]);
267 }
268 }
269 pr_debug("PKEY Change event: port=%d, "
270 "block=0x%x, change_bitmap=0x%x\n",
271 port_num, bn, pkey_change_bitmap);
272
2a4fae14 273 if (pkey_change_bitmap) {
54679e14
JM		 274 mlx4_ib_dispatch_event(dev, port_num,
275 IB_EVENT_PKEY_CHANGE);
2a4fae14
JM		 276 if (!dev->sriov.is_going_down)
277 __propagate_pkey_ev(dev, port_num, bn,
278 pkey_change_bitmap);
279 }
00f5ce99 280 break;
225c7b1f 281
00f5ce99 282 case IB_SMP_ATTR_GUID_INFO:
6634961c
JM		 283 /* paravirtualized master's guid is guid 0 -- does not change */
284 if (!mlx4_is_master(dev->dev))
285 mlx4_ib_dispatch_event(dev, port_num,
286 IB_EVENT_GID_CHANGE);
2a4fae14
JM		 287 /*if master, notify relevant slaves*/
288 if (mlx4_is_master(dev->dev) &&
289 !dev->sriov.is_going_down) {
290 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod);
291 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num,
292 (u8 *)(&((struct ib_smp *)mad)->data));
293 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num,
294 (u8 *)(&((struct ib_smp *)mad)->data));
295 }
00f5ce99 296 break;
2a4fae14 297
00f5ce99
JM		 298 default:
299 break;
225c7b1f 300 }
225c7b1f
RD		 301}
302
2a4fae14
JM		 303static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
304 int block, u32 change_bitmap)
305{
306 int i, ix, slave, err;
307 int have_event = 0;
308
309 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) {
310 if (slave == mlx4_master_func_num(dev->dev))
311 continue;
312 if (!mlx4_is_slave_active(dev->dev, slave))
313 continue;
314
315 have_event = 0;
316 for (i = 0; i < 32; i++) {
317 if (!(change_bitmap & (1 << i)))
318 continue;
319 for (ix = 0;
320 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) {
321 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1]
322 [ix] == i + 32 * block) {
323 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num);
324 pr_debug("propagate_pkey_ev: slave %d,"
325 " port %d, ix %d (%d)\n",
326 slave, port_num, ix, err);
327 have_event = 1;
328 break;
329 }
330 }
331 if (have_event)
332 break;
333 }
334 }
335}
336
225c7b1f
RD		 337static void node_desc_override(struct ib_device *dev,
338 struct ib_mad *mad)
339{
df7fba66
JM		 340 unsigned long flags;
341
225c7b1f
RD		 342 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
343 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
344 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP &&
345 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) {
df7fba66 346 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags);
225c7b1f 347 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 64);
df7fba66 348 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags);
225c7b1f
RD		 349 }
350}
351
a97e2d86 352static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad)
225c7b1f
RD		 353{
354 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED;
355 struct ib_mad_send_buf *send_buf;
356 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn];
357 int ret;
df7fba66 358 unsigned long flags;
225c7b1f
RD		 359
360 if (agent) {
361 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
da2dfaa3
IW		 362 IB_MGMT_MAD_DATA, GFP_ATOMIC,
363 IB_MGMT_BASE_VERSION);
13974909
DC		 364 if (IS_ERR(send_buf))
365 return;
225c7b1f
RD		 366 /*
367 * We rely here on the fact that MLX QPs don't use the
368 * address handle after the send is posted (this is
369 * wrong following the IB spec strictly, but we know
370 * it's OK for our devices).
371 */
df7fba66 372 spin_lock_irqsave(&dev->sm_lock, flags);
225c7b1f
RD		 373 memcpy(send_buf->mad, mad, sizeof *mad);
374 if ((send_buf->ah = dev->sm_ah[port_num - 1]))
375 ret = ib_post_send_mad(send_buf, NULL);
376 else
377 ret = -EINVAL;
df7fba66 378 spin_unlock_irqrestore(&dev->sm_lock, flags);
225c7b1f
RD		 379
380 if (ret)
381 ib_free_send_mad(send_buf);
382 }
383}
384
37bfc7c1
JM		 385static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave,
386 struct ib_sa_mad *sa_mad)
387{
b9c5d6a6
OD		 388 int ret = 0;
389
390 /* dispatch to different sa handlers */
391 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
392 case IB_SA_ATTR_MC_MEMBER_REC:
393 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad);
394 break;
395 default:
396 break;
397 }
398 return ret;
37bfc7c1
JM		 399}
400
401int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid)
402{
403 struct mlx4_ib_dev *dev = to_mdev(ibdev);
404 int i;
405
406 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
407 if (dev->sriov.demux[port - 1].guid_cache[i] == guid)
408 return i;
409 }
410 return -1;
411}
412
413
2c75d2cc
JM		 414static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave,
415 u8 port, u16 pkey, u16 *ix)
37bfc7c1 416{
2c75d2cc
JM		 417 int i, ret;
418 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF;
419 u16 slot_pkey;
37bfc7c1 420
2c75d2cc
JM		 421 if (slave == mlx4_master_func_num(dev->dev))
422 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix);
37bfc7c1 423
2c75d2cc 424 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1;
37bfc7c1 425
2c75d2cc
JM		 426 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) {
427 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix)
428 continue;
429
430 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i];
431
432 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey);
433 if (ret)
434 continue;
435 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) {
436 if (slot_pkey & 0x8000) {
437 *ix = (u16) pkey_ix;
438 return 0;
439 } else {
440 /* take first partial pkey index found */
441 if (partial_ix == 0xFF)
442 partial_ix = pkey_ix;
443 }
444 }
445 }
446
447 if (partial_ix < 0xFF) {
448 *ix = (u16) partial_ix;
449 return 0;
450 }
451
452 return -EINVAL;
37bfc7c1
JM		 453}
454
455int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
456 enum ib_qp_type dest_qpt, struct ib_wc *wc,
457 struct ib_grh *grh, struct ib_mad *mad)
458{
459 struct ib_sge list;
e622f2f4
CH		 460 struct ib_ud_wr wr;
461 struct ib_send_wr *bad_wr;
37bfc7c1
JM		 462 struct mlx4_ib_demux_pv_ctx *tun_ctx;
463 struct mlx4_ib_demux_pv_qp *tun_qp;
464 struct mlx4_rcv_tunnel_mad *tun_mad;
465 struct ib_ah_attr attr;
466 struct ib_ah *ah;
467 struct ib_qp *src_qp = NULL;
468 unsigned tun_tx_ix = 0;
469 int dqpn;
470 int ret = 0;
37bfc7c1 471 u16 tun_pkey_ix;
2c75d2cc 472 u16 cached_pkey;
6ee51a4e 473 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
37bfc7c1
JM		 474
475 if (dest_qpt > IB_QPT_GSI)
476 return -EINVAL;
477
478 tun_ctx = dev->sriov.demux[port-1].tun[slave];
479
480 /* check if proxy qp created */
481 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE)
482 return -EAGAIN;
483
37bfc7c1
JM		 484 if (!dest_qpt)
485 tun_qp = &tun_ctx->qp[0];
486 else
487 tun_qp = &tun_ctx->qp[1];
488
2c75d2cc 489 /* compute P_Key index to put in tunnel header for slave */
37bfc7c1 490 if (dest_qpt) {
2c75d2cc
JM		 491 u16 pkey_ix;
492 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey);
37bfc7c1
JM		 493 if (ret)
494 return -EINVAL;
495
2c75d2cc
JM		 496 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix);
497 if (ret)
37bfc7c1 498 return -EINVAL;
2c75d2cc 499 tun_pkey_ix = pkey_ix;
37bfc7c1
JM		 500 } else
501 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
502
47605df9 503 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1;
37bfc7c1
JM		 504
505 /* get tunnel tx data buf for slave */
506 src_qp = tun_qp->qp;
507
508 /* create ah. Just need an empty one with the port num for the post send.
509 * The driver will set the force loopback bit in post_send */
510 memset(&attr, 0, sizeof attr);
511 attr.port_num = port;
6ee51a4e 512 if (is_eth) {
b6ffaeff 513 memcpy(&attr.grh.dgid.raw[0], &grh->dgid.raw[0], 16);
6ee51a4e
JM		 514 attr.ah_flags = IB_AH_GRH;
515 }
37bfc7c1
JM		 516 ah = ib_create_ah(tun_ctx->pd, &attr);
517 if (IS_ERR(ah))
518 return -ENOMEM;
519
520 /* allocate tunnel tx buf after pass failure returns */
521 spin_lock(&tun_qp->tx_lock);
522 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >=
523 (MLX4_NUM_TUNNEL_BUFS - 1))
524 ret = -EAGAIN;
525 else
526 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
527 spin_unlock(&tun_qp->tx_lock);
528 if (ret)
529 goto out;
530
531 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr);
532 if (tun_qp->tx_ring[tun_tx_ix].ah)
533 ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah);
534 tun_qp->tx_ring[tun_tx_ix].ah = ah;
535 ib_dma_sync_single_for_cpu(&dev->ib_dev,
536 tun_qp->tx_ring[tun_tx_ix].buf.map,
537 sizeof (struct mlx4_rcv_tunnel_mad),
538 DMA_TO_DEVICE);
539
540 /* copy over to tunnel buffer */
541 if (grh)
542 memcpy(&tun_mad->grh, grh, sizeof *grh);
543 memcpy(&tun_mad->mad, mad, sizeof *mad);
544
545 /* adjust tunnel data */
546 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix);
37bfc7c1
JM		 547 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF);
548 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0;
549
5ea8bbfc
JM		 550 if (is_eth) {
551 u16 vlan = 0;
552 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan,
553 NULL)) {
554 /* VST mode */
555 if (vlan != wc->vlan_id)
556 /* Packet vlan is not the VST-assigned vlan.
557 * Drop the packet.
558 */
559 goto out;
560 else
561 /* Remove the vlan tag before forwarding
562 * the packet to the VF.
563 */
564 vlan = 0xffff;
565 } else {
566 vlan = wc->vlan_id;
567 }
568
569 tun_mad->hdr.sl_vid = cpu_to_be16(vlan);
570 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4);
571 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2);
572 } else {
573 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12);
574 tun_mad->hdr.slid_mac_47_32 = cpu_to_be16(wc->slid);
575 }
576
37bfc7c1
JM		 577 ib_dma_sync_single_for_device(&dev->ib_dev,
578 tun_qp->tx_ring[tun_tx_ix].buf.map,
579 sizeof (struct mlx4_rcv_tunnel_mad),
580 DMA_TO_DEVICE);
581
582 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map;
583 list.length = sizeof (struct mlx4_rcv_tunnel_mad);
7dd97576 584 list.lkey = tun_ctx->pd->local_dma_lkey;
37bfc7c1 585
e622f2f4
CH		 586 wr.ah = ah;
587 wr.port_num = port;
588 wr.remote_qkey = IB_QP_SET_QKEY;
589 wr.remote_qpn = dqpn;
590 wr.wr.next = NULL;
591 wr.wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt);
592 wr.wr.sg_list = &list;
593 wr.wr.num_sge = 1;
594 wr.wr.opcode = IB_WR_SEND;
595 wr.wr.send_flags = IB_SEND_SIGNALED;
596
597 ret = ib_post_send(src_qp, &wr.wr, &bad_wr);
37bfc7c1
JM		 598out:
599 if (ret)
600 ib_destroy_ah(ah);
601 return ret;
602}
603
604static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
605 struct ib_wc *wc, struct ib_grh *grh,
606 struct ib_mad *mad)
607{
608 struct mlx4_ib_dev *dev = to_mdev(ibdev);
609 int err;
610 int slave;
611 u8 *slave_id;
6ee51a4e
JM		 612 int is_eth = 0;
613
614 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
615 is_eth = 0;
616 else
617 is_eth = 1;
618
619 if (is_eth) {
620 if (!(wc->wc_flags & IB_WC_GRH)) {
621 mlx4_ib_warn(ibdev, "RoCE grh not present.\n");
622 return -EINVAL;
623 }
624 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) {
625 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n");
626 return -EINVAL;
627 }
628 if (mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave)) {
629 mlx4_ib_warn(ibdev, "failed matching grh\n");
630 return -ENOENT;
631 }
632 if (slave >= dev->dev->caps.sqp_demux) {
633 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
634 slave, dev->dev->caps.sqp_demux);
635 return -ENOENT;
636 }
637
638 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad))
639 return 0;
640
641 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
642 if (err)
643 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
644 slave, err);
645 return 0;
646 }
37bfc7c1
JM		 647
648 /* Initially assume that this mad is for us */
649 slave = mlx4_master_func_num(dev->dev);
650
651 /* See if the slave id is encoded in a response mad */
652 if (mad->mad_hdr.method & 0x80) {
653 slave_id = (u8 *) &mad->mad_hdr.tid;
654 slave = *slave_id;
655 if (slave != 255) /*255 indicates the dom0*/
656 *slave_id = 0; /* remap tid */
657 }
658
659 /* If a grh is present, we demux according to it */
660 if (wc->wc_flags & IB_WC_GRH) {
661 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id);
662 if (slave < 0) {
663 mlx4_ib_warn(ibdev, "failed matching grh\n");
664 return -ENOENT;
665 }
666 }
667 /* Class-specific handling */
668 switch (mad->mad_hdr.mgmt_class) {
97982f5a
JM		 669 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
670 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
671 /* 255 indicates the dom0 */
672 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) {
673 if (!mlx4_vf_smi_enabled(dev->dev, slave, port))
674 return -EPERM;
675 /* for a VF. drop unsolicited MADs */
676 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) {
677 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n",
678 slave, mad->mad_hdr.mgmt_class,
679 mad->mad_hdr.method);
680 return -EINVAL;
681 }
682 }
683 break;
37bfc7c1
JM		 684 case IB_MGMT_CLASS_SUBN_ADM:
685 if (mlx4_ib_demux_sa_handler(ibdev, port, slave,
686 (struct ib_sa_mad *) mad))
687 return 0;
688 break;
3cf69cc8
AV		 689 case IB_MGMT_CLASS_CM:
690 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad))
691 return 0;
692 break;
37bfc7c1
JM		 693 case IB_MGMT_CLASS_DEVICE_MGMT:
694 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP)
695 return 0;
696 break;
697 default:
698 /* Drop unsupported classes for slaves in tunnel mode */
699 if (slave != mlx4_master_func_num(dev->dev)) {
700 pr_debug("dropping unsupported ingress mad from class:%d "
701 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave);
702 return 0;
703 }
704 }
705 /*make sure that no slave==255 was not handled yet.*/
706 if (slave >= dev->dev->caps.sqp_demux) {
707 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
708 slave, dev->dev->caps.sqp_demux);
709 return -ENOENT;
710 }
711
712 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
713 if (err)
714 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
715 slave, err);
716 return 0;
717}
718
c3779134 719static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86
IW		 720 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
721 const struct ib_mad *in_mad, struct ib_mad *out_mad)
225c7b1f 722{
f0f6f346 723 u16 slid, prev_lid = 0;
225c7b1f 724 int err;
f0f6f346 725 struct ib_port_attr pattr;
225c7b1f 726
b1d8eb5a
JM		 727 if (in_wc && in_wc->qp->qp_num) {
728 pr_debug("received MAD: slid:%d sqpn:%d "
729 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n",
730 in_wc->slid, in_wc->src_qp,
731 in_wc->dlid_path_bits,
732 in_wc->qp->qp_num,
733 in_wc->wc_flags,
734 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method,
735 be16_to_cpu(in_mad->mad_hdr.attr_id));
736 if (in_wc->wc_flags & IB_WC_GRH) {
737 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n",
738 be64_to_cpu(in_grh->sgid.global.subnet_prefix),
739 be64_to_cpu(in_grh->sgid.global.interface_id));
740 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n",
741 be64_to_cpu(in_grh->dgid.global.subnet_prefix),
742 be64_to_cpu(in_grh->dgid.global.interface_id));
743 }
744 }
745
225c7b1f
RD		 746 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE);
747
748 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) {
749 forward_trap(to_mdev(ibdev), port_num, in_mad);
750 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
751 }
752
753 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
754 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
755 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
756 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
757 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
758 return IB_MAD_RESULT_SUCCESS;
759
760 /*
a6f7feae 761 * Don't process SMInfo queries -- the SMA can't handle them.
225c7b1f 762 */
a6f7feae 763 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO)
225c7b1f
RD		 764 return IB_MAD_RESULT_SUCCESS;
765 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
766 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 ||
6578cf33
EC		 767 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 ||
768 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) {
225c7b1f
RD		 769 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
770 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
771 return IB_MAD_RESULT_SUCCESS;
772 } else
773 return IB_MAD_RESULT_SUCCESS;
774
f0f6f346
MS		 775 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
776 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
777 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET &&
778 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO &&
779 !ib_query_port(ibdev, port_num, &pattr))
780 prev_lid = pattr.lid;
781
225c7b1f 782 err = mlx4_MAD_IFC(to_mdev(ibdev),
0a9a0188
JM		 783 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) |
784 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) |
785 MLX4_MAD_IFC_NET_VIEW,
225c7b1f
RD		 786 port_num, in_wc, in_grh, in_mad, out_mad);
787 if (err)
788 return IB_MAD_RESULT_FAILURE;
789
790 if (!out_mad->mad_hdr.status) {
00f5ce99
JM		 791 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV))
792 smp_snoop(ibdev, port_num, in_mad, prev_lid);
992e8e6e
JM		 793 /* slaves get node desc from FW */
794 if (!mlx4_is_slave(to_mdev(ibdev)->dev))
795 node_desc_override(ibdev, out_mad);
225c7b1f
RD		 796 }
797
798 /* set return bit in status of directed route responses */
799 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
800 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
801
802 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
803 /* no response for trap repress */
804 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
805
806 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
807}
808
c3779134
OG		 809static void edit_counter(struct mlx4_counter *cnt,
810 struct ib_pma_portcounters *pma_cnt)
811{
61a3855b
MD		 812 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data,
813 (be64_to_cpu(cnt->tx_bytes) >> 2));
814 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data,
815 (be64_to_cpu(cnt->rx_bytes) >> 2));
816 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets,
817 be64_to_cpu(cnt->tx_frames));
818 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets,
819 be64_to_cpu(cnt->rx_frames));
c3779134
OG		 820}
821
822static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86
IW		 823 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
824 const struct ib_mad *in_mad, struct ib_mad *out_mad)
c3779134 825{
9616982f 826 struct mlx4_counter counter_stats;
c3779134 827 struct mlx4_ib_dev *dev = to_mdev(ibdev);
3ba8e31d
EBE		 828 struct counter_index *tmp_counter;
829 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0;
c3779134
OG		 830
831 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
832 return -EINVAL;
833
9616982f 834 memset(&counter_stats, 0, sizeof(counter_stats));
3ba8e31d
EBE		 835 mutex_lock(&dev->counters_table[port_num - 1].mutex);
836 list_for_each_entry(tmp_counter,
837 &dev->counters_table[port_num - 1].counters_list,
838 list) {
839 err = mlx4_get_counter_stats(dev->dev,
840 tmp_counter->index,
841 &counter_stats, 0);
842 if (err) {
843 err = IB_MAD_RESULT_FAILURE;
844 stats_avail = 0;
845 break;
846 }
847 stats_avail = 1;
848 }
849 mutex_unlock(&dev->counters_table[port_num - 1].mutex);
850 if (stats_avail) {
c3779134 851 memset(out_mad->data, 0, sizeof out_mad->data);
9616982f 852 switch (counter_stats.counter_mode & 0xf) {
c3779134 853 case 0:
9616982f
EBE		 854 edit_counter(&counter_stats,
855 (void *)(out_mad->data + 40));
c3779134
OG		 856 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
857 break;
858 default:
859 err = IB_MAD_RESULT_FAILURE;
860 }
861 }
862
c3779134
OG		 863 return err;
864}
865
866int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86 867 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
4cd7c947
IW		 868 const struct ib_mad_hdr *in, size_t in_mad_size,
869 struct ib_mad_hdr *out, size_t *out_mad_size,
870 u16 *out_mad_pkey_index)
c3779134 871{
7193a141 872 struct mlx4_ib_dev *dev = to_mdev(ibdev);
4cd7c947
IW		 873 const struct ib_mad *in_mad = (const struct ib_mad *)in;
874 struct ib_mad *out_mad = (struct ib_mad *)out;
43bfb972 875 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num);
4cd7c947 876
3b8ab700
IW		 877 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) ||
878 *out_mad_size != sizeof(*out_mad)))
879 return IB_MAD_RESULT_FAILURE;
4cd7c947 880
43bfb972
OG		 881 /* iboe_process_mad() which uses the HCA flow-counters to implement IB PMA
882 * queries, should be called only by VFs and for that specific purpose
883 */
884 if (link == IB_LINK_LAYER_INFINIBAND) {
885 if (mlx4_is_slave(dev->dev) &&
886 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT &&
887 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS)
888 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
889 in_grh, in_mad, out_mad);
890
891 return ib_process_mad(ibdev, mad_flags, port_num, in_wc,
892 in_grh, in_mad, out_mad);
c3779134 893 }
43bfb972
OG		 894
895 if (link == IB_LINK_LAYER_ETHERNET)
896 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
897 in_grh, in_mad, out_mad);
898
899 return -EINVAL;
c3779134
OG		 900}
901
225c7b1f
RD		 902static void send_handler(struct ib_mad_agent *agent,
903 struct ib_mad_send_wc *mad_send_wc)
904{
992e8e6e
JM		 905 if (mad_send_wc->send_buf->context[0])
906 ib_destroy_ah(mad_send_wc->send_buf->context[0]);
225c7b1f
RD		 907 ib_free_send_mad(mad_send_wc->send_buf);
908}
909
910int mlx4_ib_mad_init(struct mlx4_ib_dev *dev)
911{
912 struct ib_mad_agent *agent;
913 int p, q;
914 int ret;
fa417f7b 915 enum rdma_link_layer ll;
225c7b1f 916
fa417f7b
EC		 917 for (p = 0; p < dev->num_ports; ++p) {
918 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1);
225c7b1f 919 for (q = 0; q <= 1; ++q) {
fa417f7b
EC		 920 if (ll == IB_LINK_LAYER_INFINIBAND) {
921 agent = ib_register_mad_agent(&dev->ib_dev, p + 1,
922 q ? IB_QPT_GSI : IB_QPT_SMI,
923 NULL, 0, send_handler,
0f29b46d 924 NULL, NULL, 0);
fa417f7b
EC		 925 if (IS_ERR(agent)) {
926 ret = PTR_ERR(agent);
927 goto err;
928 }
929 dev->send_agent[p][q] = agent;
930 } else
931 dev->send_agent[p][q] = NULL;
225c7b1f 932 }
fa417f7b 933 }
225c7b1f
RD		 934
935 return 0;
936
937err:
7ff93f8b 938 for (p = 0; p < dev->num_ports; ++p)
225c7b1f
RD		 939 for (q = 0; q <= 1; ++q)
940 if (dev->send_agent[p][q])
941 ib_unregister_mad_agent(dev->send_agent[p][q]);
942
943 return ret;
944}
945
946void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev)
947{
948 struct ib_mad_agent *agent;
949 int p, q;
950
7ff93f8b 951 for (p = 0; p < dev->num_ports; ++p) {
225c7b1f
RD		 952 for (q = 0; q <= 1; ++q) {
953 agent = dev->send_agent[p][q];
fa417f7b
EC		 954 if (agent) {
955 dev->send_agent[p][q] = NULL;
956 ib_unregister_mad_agent(agent);
957 }
225c7b1f
RD		 958 }
959
960 if (dev->sm_ah[p])
961 ib_destroy_ah(dev->sm_ah[p]);
962 }
963}
00f5ce99 964
2a4fae14
JM		 965static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num)
966{
967 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE);
968
969 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
970 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
971 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK);
972}
973
b9c5d6a6
OD		 974static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num)
975{
a0c64a17 976 /* re-configure the alias-guid and mcg's */
b9c5d6a6 977 if (mlx4_is_master(dev->dev)) {
a0c64a17
JM		 978 mlx4_ib_invalidate_all_guid_record(dev, port_num);
979
2a4fae14 980 if (!dev->sriov.is_going_down) {
b9c5d6a6 981 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0);
2a4fae14
JM		 982 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
983 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK);
984 }
b9c5d6a6
OD		 985 }
986 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER);
987}
988
2a4fae14
JM		 989static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
990 struct mlx4_eqe *eqe)
991{
992 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe),
993 GET_MASK_FROM_EQE(eqe));
994}
995
996static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num,
997 u32 guid_tbl_blk_num, u32 change_bitmap)
998{
999 struct ib_smp *in_mad = NULL;
1000 struct ib_smp *out_mad = NULL;
1001 u16 i;
1002
1003 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev))
1004 return;
1005
1006 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL);
1007 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1008 if (!in_mad || !out_mad) {
1009 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n");
1010 goto out;
1011 }
1012
1013 guid_tbl_blk_num *= 4;
1014
1015 for (i = 0; i < 4; i++) {
1016 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff)))
1017 continue;
1018 memset(in_mad, 0, sizeof *in_mad);
1019 memset(out_mad, 0, sizeof *out_mad);
1020
1021 in_mad->base_version = 1;
1022 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1023 in_mad->class_version = 1;
1024 in_mad->method = IB_MGMT_METHOD_GET;
1025 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
1026 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i);
1027
1028 if (mlx4_MAD_IFC(dev,
1029 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW,
1030 port_num, NULL, NULL, in_mad, out_mad)) {
1031 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n");
1032 goto out;
1033 }
1034
1035 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i,
1036 port_num,
1037 (u8 *)(&((struct ib_smp *)out_mad)->data));
1038 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i,
1039 port_num,
1040 (u8 *)(&((struct ib_smp *)out_mad)->data));
1041 }
1042
1043out:
1044 kfree(in_mad);
1045 kfree(out_mad);
1046 return;
1047}
1048
00f5ce99
JM		 1049void handle_port_mgmt_change_event(struct work_struct *work)
1050{
1051 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
1052 struct mlx4_ib_dev *dev = ew->ib_dev;
1053 struct mlx4_eqe *eqe = &(ew->ib_eqe);
1054 u8 port = eqe->event.port_mgmt_change.port;
1055 u32 changed_attr;
2a4fae14
JM		 1056 u32 tbl_block;
1057 u32 change_bitmap;
00f5ce99
JM		 1058
1059 switch (eqe->subtype) {
1060 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO:
1061 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr);
1062
1063 /* Update the SM ah - This should be done before handling
1064 the other changed attributes so that MADs can be sent to the SM */
1065 if (changed_attr & MSTR_SM_CHANGE_MASK) {
1066 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid);
1067 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf;
1068 update_sm_ah(dev, port, lid, sl);
1069 }
1070
1071 /* Check if it is a lid change event */
1072 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK)
2a4fae14 1073 handle_lid_change_event(dev, port);
00f5ce99
JM		 1074
1075 /* Generate GUID changed event */
2a4fae14 1076 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) {
00f5ce99 1077 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
2a4fae14
JM		 1078 /*if master, notify all slaves*/
1079 if (mlx4_is_master(dev->dev))
1080 mlx4_gen_slaves_port_mgt_ev(dev->dev, port,
1081 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK);
1082 }
00f5ce99
JM		 1083
1084 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK)
b9c5d6a6 1085 handle_client_rereg_event(dev, port);
00f5ce99
JM		 1086 break;
1087
1088 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE:
1089 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE);
2a4fae14
JM		 1090 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1091 propagate_pkey_ev(dev, port, eqe);
00f5ce99
JM		 1092 break;
1093 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO:
6634961c
JM		 1094 /* paravirtualized master's guid is guid 0 -- does not change */
1095 if (!mlx4_is_master(dev->dev))
1096 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
2a4fae14
JM		 1097 /*if master, notify relevant slaves*/
1098 else if (!dev->sriov.is_going_down) {
1099 tbl_block = GET_BLK_PTR_FROM_EQE(eqe);
1100 change_bitmap = GET_MASK_FROM_EQE(eqe);
1101 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap);
1102 }
00f5ce99
JM		 1103 break;
1104 default:
1105 pr_warn("Unsupported subtype 0x%x for "
1106 "Port Management Change event\n", eqe->subtype);
1107 }
1108
1109 kfree(ew);
1110}
1111
1112void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
1113 enum ib_event_type type)
1114{
1115 struct ib_event event;
1116
1117 event.device = &dev->ib_dev;
1118 event.element.port_num = port_num;
1119 event.event = type;
1120
1121 ib_dispatch_event(&event);
1122}
fc06573d
JM		 1123
1124static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg)
1125{
1126 unsigned long flags;
1127 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context;
1128 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1129 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
1130 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE)
1131 queue_work(ctx->wq, &ctx->work);
1132 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
1133}
1134
1135static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx,
1136 struct mlx4_ib_demux_pv_qp *tun_qp,
1137 int index)
1138{
1139 struct ib_sge sg_list;
1140 struct ib_recv_wr recv_wr, *bad_recv_wr;
1141 int size;
1142
1143 size = (tun_qp->qp->qp_type == IB_QPT_UD) ?
1144 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf);
1145
1146 sg_list.addr = tun_qp->ring[index].map;
1147 sg_list.length = size;
7dd97576 1148 sg_list.lkey = ctx->pd->local_dma_lkey;
fc06573d
JM		 1149
1150 recv_wr.next = NULL;
1151 recv_wr.sg_list = &sg_list;
1152 recv_wr.num_sge = 1;
1153 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV |
1154 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt);
1155 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map,
1156 size, DMA_FROM_DEVICE);
1157 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr);
1158}
1159
37bfc7c1
JM		 1160static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port,
1161 int slave, struct ib_sa_mad *sa_mad)
1162{
b9c5d6a6
OD		 1163 int ret = 0;
1164
1165 /* dispatch to different sa handlers */
1166 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
1167 case IB_SA_ATTR_MC_MEMBER_REC:
1168 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad);
1169 break;
1170 default:
1171 break;
1172 }
1173 return ret;
37bfc7c1
JM		 1174}
1175
1176static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave)
1177{
47605df9 1178 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave;
37bfc7c1 1179
47605df9 1180 return (qpn >= proxy_start && qpn <= proxy_start + 1);
37bfc7c1
JM		 1181}
1182
1183
1184int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
5ea8bbfc
JM		 1185 enum ib_qp_type dest_qpt, u16 pkey_index,
1186 u32 remote_qpn, u32 qkey, struct ib_ah_attr *attr,
dbf727de 1187 u8 *s_mac, u16 vlan_id, struct ib_mad *mad)
37bfc7c1
JM		 1188{
1189 struct ib_sge list;
e622f2f4
CH		 1190 struct ib_ud_wr wr;
1191 struct ib_send_wr *bad_wr;
37bfc7c1
JM		 1192 struct mlx4_ib_demux_pv_ctx *sqp_ctx;
1193 struct mlx4_ib_demux_pv_qp *sqp;
1194 struct mlx4_mad_snd_buf *sqp_mad;
1195 struct ib_ah *ah;
1196 struct ib_qp *send_qp = NULL;
1197 unsigned wire_tx_ix = 0;
1198 int ret = 0;
1199 u16 wire_pkey_ix;
1200 int src_qpnum;
1201 u8 sgid_index;
1202
1203
1204 sqp_ctx = dev->sriov.sqps[port-1];
1205
1206 /* check if proxy qp created */
1207 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE)
1208 return -EAGAIN;
1209
37bfc7c1
JM		 1210 if (dest_qpt == IB_QPT_SMI) {
1211 src_qpnum = 0;
1212 sqp = &sqp_ctx->qp[0];
1213 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
1214 } else {
1215 src_qpnum = 1;
1216 sqp = &sqp_ctx->qp[1];
1217 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index];
1218 }
1219
1220 send_qp = sqp->qp;
1221
1222 /* create ah */
1223 sgid_index = attr->grh.sgid_index;
1224 attr->grh.sgid_index = 0;
1225 ah = ib_create_ah(sqp_ctx->pd, attr);
1226 if (IS_ERR(ah))
1227 return -ENOMEM;
1228 attr->grh.sgid_index = sgid_index;
1229 to_mah(ah)->av.ib.gid_index = sgid_index;
1230 /* get rid of force-loopback bit */
1231 to_mah(ah)->av.ib.port_pd &= cpu_to_be32(0x7FFFFFFF);
1232 spin_lock(&sqp->tx_lock);
1233 if (sqp->tx_ix_head - sqp->tx_ix_tail >=
1234 (MLX4_NUM_TUNNEL_BUFS - 1))
1235 ret = -EAGAIN;
1236 else
1237 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
1238 spin_unlock(&sqp->tx_lock);
1239 if (ret)
1240 goto out;
1241
1242 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr);
1243 if (sqp->tx_ring[wire_tx_ix].ah)
1244 ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah);
1245 sqp->tx_ring[wire_tx_ix].ah = ah;
1246 ib_dma_sync_single_for_cpu(&dev->ib_dev,
1247 sqp->tx_ring[wire_tx_ix].buf.map,
1248 sizeof (struct mlx4_mad_snd_buf),
1249 DMA_TO_DEVICE);
1250
1251 memcpy(&sqp_mad->payload, mad, sizeof *mad);
1252
1253 ib_dma_sync_single_for_device(&dev->ib_dev,
1254 sqp->tx_ring[wire_tx_ix].buf.map,
1255 sizeof (struct mlx4_mad_snd_buf),
1256 DMA_TO_DEVICE);
1257
1258 list.addr = sqp->tx_ring[wire_tx_ix].buf.map;
1259 list.length = sizeof (struct mlx4_mad_snd_buf);
7dd97576 1260 list.lkey = sqp_ctx->pd->local_dma_lkey;
37bfc7c1 1261
e622f2f4
CH		 1262 wr.ah = ah;
1263 wr.port_num = port;
1264 wr.pkey_index = wire_pkey_ix;
1265 wr.remote_qkey = qkey;
1266 wr.remote_qpn = remote_qpn;
1267 wr.wr.next = NULL;
1268 wr.wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum);
1269 wr.wr.sg_list = &list;
1270 wr.wr.num_sge = 1;
1271 wr.wr.opcode = IB_WR_SEND;
1272 wr.wr.send_flags = IB_SEND_SIGNALED;
5ea8bbfc
JM		 1273 if (s_mac)
1274 memcpy(to_mah(ah)->av.eth.s_mac, s_mac, 6);
dbf727de
MB		 1275 if (vlan_id < 0x1000)
1276 vlan_id |= (attr->sl & 7) << 13;
1277 to_mah(ah)->av.eth.vlan = cpu_to_be16(vlan_id);
5ea8bbfc 1278
37bfc7c1 1279
e622f2f4 1280 ret = ib_post_send(send_qp, &wr.wr, &bad_wr);
37bfc7c1
JM		 1281out:
1282 if (ret)
1283 ib_destroy_ah(ah);
1284 return ret;
1285}
1286
b6ffaeff
JM		 1287static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port)
1288{
b6ffaeff
JM		 1289 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1290 return slave;
449fc488 1291 return mlx4_get_base_gid_ix(dev->dev, slave, port);
b6ffaeff
JM		 1292}
1293
1294static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port,
1295 struct ib_ah_attr *ah_attr)
1296{
1297 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1298 ah_attr->grh.sgid_index = slave;
1299 else
1300 ah_attr->grh.sgid_index += get_slave_base_gid_ix(dev, slave, port);
1301}
1302
37bfc7c1
JM		 1303static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc)
1304{
1305 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1306 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)];
1307 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1);
1308 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr;
1309 struct mlx4_ib_ah ah;
1310 struct ib_ah_attr ah_attr;
1311 u8 *slave_id;
1312 int slave;
449fc488 1313 int port;
dbf727de 1314 u16 vlan_id;
37bfc7c1
JM		 1315
1316 /* Get slave that sent this packet */
47605df9
JM		 1317 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn ||
1318 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX ||
37bfc7c1
JM		 1319 (wc->src_qp & 0x1) != ctx->port - 1 ||
1320 wc->src_qp & 0x4) {
1321 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp);
1322 return;
1323 }
47605df9 1324 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8;
37bfc7c1
JM		 1325 if (slave != ctx->slave) {
1326 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: "
1327 "belongs to another slave\n", wc->src_qp);
1328 return;
1329 }
37bfc7c1
JM		 1330
1331 /* Map transaction ID */
1332 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map,
1333 sizeof (struct mlx4_tunnel_mad),
1334 DMA_FROM_DEVICE);
1335 switch (tunnel->mad.mad_hdr.method) {
1336 case IB_MGMT_METHOD_SET:
1337 case IB_MGMT_METHOD_GET:
1338 case IB_MGMT_METHOD_REPORT:
1339 case IB_SA_METHOD_GET_TABLE:
1340 case IB_SA_METHOD_DELETE:
1341 case IB_SA_METHOD_GET_MULTI:
1342 case IB_SA_METHOD_GET_TRACE_TBL:
1343 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid;
1344 if (*slave_id) {
1345 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d "
1346 "class:%d slave:%d\n", *slave_id,
1347 tunnel->mad.mad_hdr.mgmt_class, slave);
1348 return;
1349 } else
1350 *slave_id = slave;
1351 default:
1352 /* nothing */;
1353 }
1354
1355 /* Class-specific handling */
1356 switch (tunnel->mad.mad_hdr.mgmt_class) {
97982f5a
JM		 1357 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
1358 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
1359 if (slave != mlx4_master_func_num(dev->dev) &&
1360 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port))
1361 return;
1362 break;
37bfc7c1
JM		 1363 case IB_MGMT_CLASS_SUBN_ADM:
1364 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave,
1365 (struct ib_sa_mad *) &tunnel->mad))
1366 return;
1367 break;
3cf69cc8
AV		 1368 case IB_MGMT_CLASS_CM:
1369 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave,
1370 (struct ib_mad *) &tunnel->mad))
1371 return;
1372 break;
37bfc7c1
JM		 1373 case IB_MGMT_CLASS_DEVICE_MGMT:
1374 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET &&
1375 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET)
1376 return;
1377 break;
1378 default:
1379 /* Drop unsupported classes for slaves in tunnel mode */
1380 if (slave != mlx4_master_func_num(dev->dev)) {
1381 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d "
1382 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave);
1383 return;
1384 }
1385 }
1386
1387 /* We are using standard ib_core services to send the mad, so generate a
1388 * stadard address handle by decoding the tunnelled mlx4_ah fields */
1389 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av));
1390 ah.ibah.device = ctx->ib_dev;
430910b1
OG		 1391
1392 port = be32_to_cpu(ah.av.ib.port_pd) >> 24;
1393 port = mlx4_slave_convert_port(dev->dev, slave, port);
1394 if (port < 0)
1395 return;
1396 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));
1397
37bfc7c1 1398 mlx4_ib_query_ah(&ah.ibah, &ah_attr);
6ee51a4e 1399 if (ah_attr.ah_flags & IB_AH_GRH)
b6ffaeff 1400 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr);
37bfc7c1 1401
5ea8bbfc 1402 memcpy(ah_attr.dmac, tunnel->hdr.mac, 6);
dbf727de 1403 vlan_id = be16_to_cpu(tunnel->hdr.vlan);
5ea8bbfc
JM		 1404 /* if slave have default vlan use it */
1405 mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave,
dbf727de 1406 &vlan_id, &ah_attr.sl);
5ea8bbfc 1407
37bfc7c1
JM		 1408 mlx4_ib_send_to_wire(dev, slave, ctx->port,
1409 is_proxy_qp0(dev, wc->src_qp, slave) ?
1410 IB_QPT_SMI : IB_QPT_GSI,
1411 be16_to_cpu(tunnel->hdr.pkey_index),
1412 be32_to_cpu(tunnel->hdr.remote_qpn),
1413 be32_to_cpu(tunnel->hdr.qkey),
dbf727de 1414 &ah_attr, wc->smac, vlan_id, &tunnel->mad);
37bfc7c1
JM		 1415}
1416
fc06573d
JM		 1417static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1418 enum ib_qp_type qp_type, int is_tun)
1419{
1420 int i;
1421 struct mlx4_ib_demux_pv_qp *tun_qp;
1422 int rx_buf_size, tx_buf_size;
1423
1424 if (qp_type > IB_QPT_GSI)
1425 return -EINVAL;
1426
1427 tun_qp = &ctx->qp[qp_type];
1428
1429 tun_qp->ring = kzalloc(sizeof (struct mlx4_ib_buf) * MLX4_NUM_TUNNEL_BUFS,
1430 GFP_KERNEL);
1431 if (!tun_qp->ring)
1432 return -ENOMEM;
1433
1434 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1435 sizeof (struct mlx4_ib_tun_tx_buf),
1436 GFP_KERNEL);
1437 if (!tun_qp->tx_ring) {
1438 kfree(tun_qp->ring);
1439 tun_qp->ring = NULL;
1440 return -ENOMEM;
1441 }
1442
1443 if (is_tun) {
1444 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1445 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1446 } else {
1447 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1448 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1449 }
1450
1451 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1452 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL);
1453 if (!tun_qp->ring[i].addr)
1454 goto err;
1455 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev,
1456 tun_qp->ring[i].addr,
1457 rx_buf_size,
1458 DMA_FROM_DEVICE);
cc47d369
SO		 1459 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) {
1460 kfree(tun_qp->ring[i].addr);
1461 goto err;
1462 }
fc06573d
JM		 1463 }
1464
1465 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1466 tun_qp->tx_ring[i].buf.addr =
1467 kmalloc(tx_buf_size, GFP_KERNEL);
1468 if (!tun_qp->tx_ring[i].buf.addr)
1469 goto tx_err;
1470 tun_qp->tx_ring[i].buf.map =
1471 ib_dma_map_single(ctx->ib_dev,
1472 tun_qp->tx_ring[i].buf.addr,
1473 tx_buf_size,
1474 DMA_TO_DEVICE);
cc47d369
SO		 1475 if (ib_dma_mapping_error(ctx->ib_dev,
1476 tun_qp->tx_ring[i].buf.map)) {
1477 kfree(tun_qp->tx_ring[i].buf.addr);
1478 goto tx_err;
1479 }
fc06573d
JM		 1480 tun_qp->tx_ring[i].ah = NULL;
1481 }
1482 spin_lock_init(&tun_qp->tx_lock);
1483 tun_qp->tx_ix_head = 0;
1484 tun_qp->tx_ix_tail = 0;
1485 tun_qp->proxy_qpt = qp_type;
1486
1487 return 0;
1488
1489tx_err:
1490 while (i > 0) {
1491 --i;
1492 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1493 tx_buf_size, DMA_TO_DEVICE);
1494 kfree(tun_qp->tx_ring[i].buf.addr);
1495 }
1496 kfree(tun_qp->tx_ring);
1497 tun_qp->tx_ring = NULL;
1498 i = MLX4_NUM_TUNNEL_BUFS;
1499err:
1500 while (i > 0) {
1501 --i;
1502 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1503 rx_buf_size, DMA_FROM_DEVICE);
1504 kfree(tun_qp->ring[i].addr);
1505 }
1506 kfree(tun_qp->ring);
1507 tun_qp->ring = NULL;
1508 return -ENOMEM;
1509}
1510
1511static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1512 enum ib_qp_type qp_type, int is_tun)
1513{
1514 int i;
1515 struct mlx4_ib_demux_pv_qp *tun_qp;
1516 int rx_buf_size, tx_buf_size;
1517
1518 if (qp_type > IB_QPT_GSI)
1519 return;
1520
1521 tun_qp = &ctx->qp[qp_type];
1522 if (is_tun) {
1523 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1524 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1525 } else {
1526 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1527 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1528 }
1529
1530
1531 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1532 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1533 rx_buf_size, DMA_FROM_DEVICE);
1534 kfree(tun_qp->ring[i].addr);
1535 }
1536
1537 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1538 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1539 tx_buf_size, DMA_TO_DEVICE);
1540 kfree(tun_qp->tx_ring[i].buf.addr);
1541 if (tun_qp->tx_ring[i].ah)
1542 ib_destroy_ah(tun_qp->tx_ring[i].ah);
1543 }
1544 kfree(tun_qp->tx_ring);
1545 kfree(tun_qp->ring);
1546}
1547
1548static void mlx4_ib_tunnel_comp_worker(struct work_struct *work)
1549{
37bfc7c1
JM		 1550 struct mlx4_ib_demux_pv_ctx *ctx;
1551 struct mlx4_ib_demux_pv_qp *tun_qp;
1552 struct ib_wc wc;
1553 int ret;
1554 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1555 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1556
1557 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1558 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1559 if (wc.status == IB_WC_SUCCESS) {
1560 switch (wc.opcode) {
1561 case IB_WC_RECV:
1562 mlx4_ib_multiplex_mad(ctx, &wc);
1563 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp,
1564 wc.wr_id &
1565 (MLX4_NUM_TUNNEL_BUFS - 1));
1566 if (ret)
1567 pr_err("Failed reposting tunnel "
1568 "buf:%lld\n", wc.wr_id);
1569 break;
1570 case IB_WC_SEND:
1571 pr_debug("received tunnel send completion:"
1572 "wrid=0x%llx, status=0x%x\n",
1573 wc.wr_id, wc.status);
1574 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1575 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1576 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1577 = NULL;
1578 spin_lock(&tun_qp->tx_lock);
1579 tun_qp->tx_ix_tail++;
1580 spin_unlock(&tun_qp->tx_lock);
1581
1582 break;
1583 default:
1584 break;
1585 }
1586 } else {
1587 pr_debug("mlx4_ib: completion error in tunnel: %d."
1588 " status = %d, wrid = 0x%llx\n",
1589 ctx->slave, wc.status, wc.wr_id);
1590 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1591 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1592 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1593 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1594 = NULL;
1595 spin_lock(&tun_qp->tx_lock);
1596 tun_qp->tx_ix_tail++;
1597 spin_unlock(&tun_qp->tx_lock);
1598 }
1599 }
1600 }
fc06573d
JM		 1601}
1602
1603static void pv_qp_event_handler(struct ib_event *event, void *qp_context)
1604{
1605 struct mlx4_ib_demux_pv_ctx *sqp = qp_context;
1606
1607 /* It's worse than that! He's dead, Jim! */
1608 pr_err("Fatal error (%d) on a MAD QP on port %d\n",
1609 event->event, sqp->port);
1610}
1611
1612static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx,
1613 enum ib_qp_type qp_type, int create_tun)
1614{
1615 int i, ret;
1616 struct mlx4_ib_demux_pv_qp *tun_qp;
1617 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr;
1618 struct ib_qp_attr attr;
1619 int qp_attr_mask_INIT;
1620
1621 if (qp_type > IB_QPT_GSI)
1622 return -EINVAL;
1623
1624 tun_qp = &ctx->qp[qp_type];
1625
1626 memset(&qp_init_attr, 0, sizeof qp_init_attr);
1627 qp_init_attr.init_attr.send_cq = ctx->cq;
1628 qp_init_attr.init_attr.recv_cq = ctx->cq;
1629 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
1630 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS;
1631 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS;
1632 qp_init_attr.init_attr.cap.max_send_sge = 1;
1633 qp_init_attr.init_attr.cap.max_recv_sge = 1;
1634 if (create_tun) {
1635 qp_init_attr.init_attr.qp_type = IB_QPT_UD;
1636 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP;
1637 qp_init_attr.port = ctx->port;
1638 qp_init_attr.slave = ctx->slave;
1639 qp_init_attr.proxy_qp_type = qp_type;
1640 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX |
1641 IB_QP_QKEY | IB_QP_PORT;
1642 } else {
1643 qp_init_attr.init_attr.qp_type = qp_type;
1644 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP;
1645 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY;
1646 }
1647 qp_init_attr.init_attr.port_num = ctx->port;
1648 qp_init_attr.init_attr.qp_context = ctx;
1649 qp_init_attr.init_attr.event_handler = pv_qp_event_handler;
1650 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr);
1651 if (IS_ERR(tun_qp->qp)) {
1652 ret = PTR_ERR(tun_qp->qp);
1653 tun_qp->qp = NULL;
1654 pr_err("Couldn't create %s QP (%d)\n",
1655 create_tun ? "tunnel" : "special", ret);
1656 return ret;
1657 }
1658
1659 memset(&attr, 0, sizeof attr);
1660 attr.qp_state = IB_QPS_INIT;
3eac103f
JM		 1661 ret = 0;
1662 if (create_tun)
1663 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave,
1664 ctx->port, IB_DEFAULT_PKEY_FULL,
1665 &attr.pkey_index);
1666 if (ret || !create_tun)
1667 attr.pkey_index =
1668 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0];
fc06573d
JM		 1669 attr.qkey = IB_QP1_QKEY;
1670 attr.port_num = ctx->port;
1671 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT);
1672 if (ret) {
1673 pr_err("Couldn't change %s qp state to INIT (%d)\n",
1674 create_tun ? "tunnel" : "special", ret);
1675 goto err_qp;
1676 }
1677 attr.qp_state = IB_QPS_RTR;
1678 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE);
1679 if (ret) {
1680 pr_err("Couldn't change %s qp state to RTR (%d)\n",
1681 create_tun ? "tunnel" : "special", ret);
1682 goto err_qp;
1683 }
1684 attr.qp_state = IB_QPS_RTS;
1685 attr.sq_psn = 0;
1686 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN);
1687 if (ret) {
1688 pr_err("Couldn't change %s qp state to RTS (%d)\n",
1689 create_tun ? "tunnel" : "special", ret);
1690 goto err_qp;
1691 }
1692
1693 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1694 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i);
1695 if (ret) {
1696 pr_err(" mlx4_ib_post_pv_buf error"
1697 " (err = %d, i = %d)\n", ret, i);
1698 goto err_qp;
1699 }
1700 }
1701 return 0;
1702
1703err_qp:
1704 ib_destroy_qp(tun_qp->qp);
1705 tun_qp->qp = NULL;
1706 return ret;
1707}
1708
1709/*
1710 * IB MAD completion callback for real SQPs
1711 */
1712static void mlx4_ib_sqp_comp_worker(struct work_struct *work)
1713{
37bfc7c1
JM		 1714 struct mlx4_ib_demux_pv_ctx *ctx;
1715 struct mlx4_ib_demux_pv_qp *sqp;
1716 struct ib_wc wc;
1717 struct ib_grh *grh;
1718 struct ib_mad *mad;
1719
1720 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1721 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1722
1723 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1724 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1725 if (wc.status == IB_WC_SUCCESS) {
1726 switch (wc.opcode) {
1727 case IB_WC_SEND:
1728 ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1729 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1730 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1731 = NULL;
1732 spin_lock(&sqp->tx_lock);
1733 sqp->tx_ix_tail++;
1734 spin_unlock(&sqp->tx_lock);
1735 break;
1736 case IB_WC_RECV:
1737 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *)
1738 (sqp->ring[wc.wr_id &
1739 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload);
1740 grh = &(((struct mlx4_mad_rcv_buf *)
1741 (sqp->ring[wc.wr_id &
1742 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh);
1743 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad);
1744 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id &
1745 (MLX4_NUM_TUNNEL_BUFS - 1)))
1746 pr_err("Failed reposting SQP "
1747 "buf:%lld\n", wc.wr_id);
1748 break;
1749 default:
1750 BUG_ON(1);
1751 break;
1752 }
1753 } else {
1754 pr_debug("mlx4_ib: completion error in tunnel: %d."
1755 " status = %d, wrid = 0x%llx\n",
1756 ctx->slave, wc.status, wc.wr_id);
1757 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1758 ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1759 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1760 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1761 = NULL;
1762 spin_lock(&sqp->tx_lock);
1763 sqp->tx_ix_tail++;
1764 spin_unlock(&sqp->tx_lock);
1765 }
1766 }
1767 }
fc06573d
JM		 1768}
1769
1770static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port,
1771 struct mlx4_ib_demux_pv_ctx **ret_ctx)
1772{
1773 struct mlx4_ib_demux_pv_ctx *ctx;
1774
1775 *ret_ctx = NULL;
1776 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL);
1777 if (!ctx) {
1778 pr_err("failed allocating pv resource context "
1779 "for port %d, slave %d\n", port, slave);
1780 return -ENOMEM;
1781 }
1782
1783 ctx->ib_dev = &dev->ib_dev;
1784 ctx->port = port;
1785 ctx->slave = slave;
1786 *ret_ctx = ctx;
1787 return 0;
1788}
1789
1790static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port)
1791{
1792 if (dev->sriov.demux[port - 1].tun[slave]) {
1793 kfree(dev->sriov.demux[port - 1].tun[slave]);
1794 dev->sriov.demux[port - 1].tun[slave] = NULL;
1795 }
1796}
1797
1798static int create_pv_resources(struct ib_device *ibdev, int slave, int port,
1799 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx)
1800{
1801 int ret, cq_size;
8e37210b 1802 struct ib_cq_init_attr cq_attr = {};
fc06573d 1803
3806d08c
JM		 1804 if (ctx->state != DEMUX_PV_STATE_DOWN)
1805 return -EEXIST;
1806
fc06573d 1807 ctx->state = DEMUX_PV_STATE_STARTING;
97982f5a
JM		 1808 /* have QP0 only if link layer is IB */
1809 if (rdma_port_get_link_layer(ibdev, ctx->port) ==
1810 IB_LINK_LAYER_INFINIBAND)
fc06573d
JM		 1811 ctx->has_smi = 1;
1812
1813 if (ctx->has_smi) {
1814 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun);
1815 if (ret) {
1816 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret);
1817 goto err_out;
1818 }
1819 }
1820
1821 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun);
1822 if (ret) {
1823 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret);
1824 goto err_out_qp0;
1825 }
1826
1827 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS;
1828 if (ctx->has_smi)
1829 cq_size *= 2;
1830
8e37210b 1831 cq_attr.cqe = cq_size;
fc06573d 1832 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler,
8e37210b 1833 NULL, ctx, &cq_attr);
fc06573d
JM		 1834 if (IS_ERR(ctx->cq)) {
1835 ret = PTR_ERR(ctx->cq);
1836 pr_err("Couldn't create tunnel CQ (%d)\n", ret);
1837 goto err_buf;
1838 }
1839
1840 ctx->pd = ib_alloc_pd(ctx->ib_dev);
1841 if (IS_ERR(ctx->pd)) {
1842 ret = PTR_ERR(ctx->pd);
1843 pr_err("Couldn't create tunnel PD (%d)\n", ret);
1844 goto err_cq;
1845 }
1846
fc06573d
JM		 1847 if (ctx->has_smi) {
1848 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun);
1849 if (ret) {
1850 pr_err("Couldn't create %s QP0 (%d)\n",
1851 create_tun ? "tunnel for" : "", ret);
7dd97576 1852 goto err_pd;
fc06573d
JM		 1853 }
1854 }
1855
1856 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun);
1857 if (ret) {
1858 pr_err("Couldn't create %s QP1 (%d)\n",
1859 create_tun ? "tunnel for" : "", ret);
1860 goto err_qp0;
1861 }
1862
1863 if (create_tun)
1864 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker);
1865 else
1866 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker);
1867
1868 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq;
1869
1870 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1871 if (ret) {
1872 pr_err("Couldn't arm tunnel cq (%d)\n", ret);
1873 goto err_wq;
1874 }
1875 ctx->state = DEMUX_PV_STATE_ACTIVE;
1876 return 0;
1877
1878err_wq:
1879 ctx->wq = NULL;
1880 ib_destroy_qp(ctx->qp[1].qp);
1881 ctx->qp[1].qp = NULL;
1882
1883
1884err_qp0:
1885 if (ctx->has_smi)
1886 ib_destroy_qp(ctx->qp[0].qp);
1887 ctx->qp[0].qp = NULL;
1888
fc06573d
JM		 1889err_pd:
1890 ib_dealloc_pd(ctx->pd);
1891 ctx->pd = NULL;
1892
1893err_cq:
1894 ib_destroy_cq(ctx->cq);
1895 ctx->cq = NULL;
1896
1897err_buf:
1898 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun);
1899
1900err_out_qp0:
1901 if (ctx->has_smi)
1902 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun);
1903err_out:
1904 ctx->state = DEMUX_PV_STATE_DOWN;
1905 return ret;
1906}
1907
1908static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port,
1909 struct mlx4_ib_demux_pv_ctx *ctx, int flush)
1910{
1911 if (!ctx)
1912 return;
1913 if (ctx->state > DEMUX_PV_STATE_DOWN) {
1914 ctx->state = DEMUX_PV_STATE_DOWNING;
1915 if (flush)
1916 flush_workqueue(ctx->wq);
1917 if (ctx->has_smi) {
1918 ib_destroy_qp(ctx->qp[0].qp);
1919 ctx->qp[0].qp = NULL;
1920 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1);
1921 }
1922 ib_destroy_qp(ctx->qp[1].qp);
1923 ctx->qp[1].qp = NULL;
1924 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1);
fc06573d
JM		 1925 ib_dealloc_pd(ctx->pd);
1926 ctx->pd = NULL;
1927 ib_destroy_cq(ctx->cq);
1928 ctx->cq = NULL;
1929 ctx->state = DEMUX_PV_STATE_DOWN;
1930 }
1931}
1932
1933static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave,
1934 int port, int do_init)
1935{
1936 int ret = 0;
1937
1938 if (!do_init) {
b9c5d6a6 1939 clean_vf_mcast(&dev->sriov.demux[port - 1], slave);
fc06573d
JM		 1940 /* for master, destroy real sqp resources */
1941 if (slave == mlx4_master_func_num(dev->dev))
1942 destroy_pv_resources(dev, slave, port,
1943 dev->sriov.sqps[port - 1], 1);
1944 /* destroy the tunnel qp resources */
1945 destroy_pv_resources(dev, slave, port,
1946 dev->sriov.demux[port - 1].tun[slave], 1);
1947 return 0;
1948 }
1949
1950 /* create the tunnel qp resources */
1951 ret = create_pv_resources(&dev->ib_dev, slave, port, 1,
1952 dev->sriov.demux[port - 1].tun[slave]);
1953
1954 /* for master, create the real sqp resources */
1955 if (!ret && slave == mlx4_master_func_num(dev->dev))
1956 ret = create_pv_resources(&dev->ib_dev, slave, port, 0,
1957 dev->sriov.sqps[port - 1]);
1958 return ret;
1959}
1960
1961void mlx4_ib_tunnels_update_work(struct work_struct *work)
1962{
1963 struct mlx4_ib_demux_work *dmxw;
1964
1965 dmxw = container_of(work, struct mlx4_ib_demux_work, work);
1966 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port,
1967 dmxw->do_init);
1968 kfree(dmxw);
1969 return;
1970}
1971
1972static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev,
1973 struct mlx4_ib_demux_ctx *ctx,
1974 int port)
1975{
1976 char name[12];
1977 int ret = 0;
1978 int i;
1979
1980 ctx->tun = kcalloc(dev->dev->caps.sqp_demux,
1981 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL);
1982 if (!ctx->tun)
1983 return -ENOMEM;
1984
1985 ctx->dev = dev;
1986 ctx->port = port;
1987 ctx->ib_dev = &dev->ib_dev;
1988
449fc488 1989 for (i = 0;
872bf2fb
YH		 1990 i < min(dev->dev->caps.sqp_demux,
1991 (u16)(dev->dev->persist->num_vfs + 1));
449fc488
MB		 1992 i++) {
1993 struct mlx4_active_ports actv_ports =
1994 mlx4_get_active_ports(dev->dev, i);
1995
1996 if (!test_bit(port - 1, actv_ports.ports))
1997 continue;
1998
fc06573d
JM		 1999 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]);
2000 if (ret) {
2001 ret = -ENOMEM;
b9c5d6a6 2002 goto err_mcg;
fc06573d
JM		 2003 }
2004 }
2005
b9c5d6a6
OD		 2006 ret = mlx4_ib_mcg_port_init(ctx);
2007 if (ret) {
2008 pr_err("Failed initializing mcg para-virt (%d)\n", ret);
2009 goto err_mcg;
2010 }
2011
fc06573d
JM		 2012 snprintf(name, sizeof name, "mlx4_ibt%d", port);
2013 ctx->wq = create_singlethread_workqueue(name);
2014 if (!ctx->wq) {
2015 pr_err("Failed to create tunnelling WQ for port %d\n", port);
2016 ret = -ENOMEM;
2017 goto err_wq;
2018 }
2019
2020 snprintf(name, sizeof name, "mlx4_ibud%d", port);
2021 ctx->ud_wq = create_singlethread_workqueue(name);
2022 if (!ctx->ud_wq) {
2023 pr_err("Failed to create up/down WQ for port %d\n", port);
2024 ret = -ENOMEM;
2025 goto err_udwq;
2026 }
2027
2028 return 0;
2029
2030err_udwq:
2031 destroy_workqueue(ctx->wq);
2032 ctx->wq = NULL;
2033
2034err_wq:
b9c5d6a6
OD		 2035 mlx4_ib_mcg_port_cleanup(ctx, 1);
2036err_mcg:
fc06573d
JM		 2037 for (i = 0; i < dev->dev->caps.sqp_demux; i++)
2038 free_pv_object(dev, i, port);
2039 kfree(ctx->tun);
2040 ctx->tun = NULL;
2041 return ret;
2042}
2043
2044static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx)
2045{
2046 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) {
2047 sqp_ctx->state = DEMUX_PV_STATE_DOWNING;
2048 flush_workqueue(sqp_ctx->wq);
2049 if (sqp_ctx->has_smi) {
2050 ib_destroy_qp(sqp_ctx->qp[0].qp);
2051 sqp_ctx->qp[0].qp = NULL;
2052 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0);
2053 }
2054 ib_destroy_qp(sqp_ctx->qp[1].qp);
2055 sqp_ctx->qp[1].qp = NULL;
2056 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0);
fc06573d
JM		 2057 ib_dealloc_pd(sqp_ctx->pd);
2058 sqp_ctx->pd = NULL;
2059 ib_destroy_cq(sqp_ctx->cq);
2060 sqp_ctx->cq = NULL;
2061 sqp_ctx->state = DEMUX_PV_STATE_DOWN;
2062 }
2063}
2064
2065static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx)
2066{
2067 int i;
2068 if (ctx) {
2069 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
b9c5d6a6 2070 mlx4_ib_mcg_port_cleanup(ctx, 1);
fc06573d
JM		 2071 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2072 if (!ctx->tun[i])
2073 continue;
2074 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN)
2075 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING;
2076 }
2077 flush_workqueue(ctx->wq);
2078 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2079 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0);
2080 free_pv_object(dev, i, ctx->port);
2081 }
2082 kfree(ctx->tun);
2083 destroy_workqueue(ctx->ud_wq);
2084 destroy_workqueue(ctx->wq);
2085 }
2086}
2087
2088static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init)
2089{
2090 int i;
2091
2092 if (!mlx4_is_master(dev->dev))
2093 return;
2094 /* initialize or tear down tunnel QPs for the master */
2095 for (i = 0; i < dev->dev->caps.num_ports; i++)
2096 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init);
2097 return;
2098}
2099
2100int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev)
2101{
2102 int i = 0;
2103 int err;
2104
2105 if (!mlx4_is_mfunc(dev->dev))
2106 return 0;
2107
2108 dev->sriov.is_going_down = 0;
2109 spin_lock_init(&dev->sriov.going_down_lock);
3cf69cc8 2110 mlx4_ib_cm_paravirt_init(dev);
fc06573d
JM		 2111
2112 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n");
2113
2114 if (mlx4_is_slave(dev->dev)) {
2115 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n");
2116 return 0;
2117 }
2118
afa8fd1d
JM		 2119 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2120 if (i == mlx4_master_func_num(dev->dev))
2121 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid);
2122 else
2123 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid());
2124 }
2125
a0c64a17
JM		 2126 err = mlx4_ib_init_alias_guid_service(dev);
2127 if (err) {
2128 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n");
2129 goto paravirt_err;
2130 }
c1e7e466
JM		 2131 err = mlx4_ib_device_register_sysfs(dev);
2132 if (err) {
2133 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n");
2134 goto sysfs_err;
2135 }
a0c64a17 2136
fc06573d
JM		 2137 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n",
2138 dev->dev->caps.sqp_demux);
2139 for (i = 0; i < dev->num_ports; i++) {
a0c64a17
JM		 2140 union ib_gid gid;
2141 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1);
2142 if (err)
2143 goto demux_err;
2144 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id;
fc06573d
JM		 2145 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1,
2146 &dev->sriov.sqps[i]);
2147 if (err)
2148 goto demux_err;
2149 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1);
2150 if (err)
cab66d12 2151 goto free_pv;
fc06573d
JM		 2152 }
2153 mlx4_ib_master_tunnels(dev, 1);
2154 return 0;
2155
cab66d12
DC		 2156free_pv:
2157 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
fc06573d 2158demux_err:
cab66d12 2159 while (--i >= 0) {
fc06573d
JM		 2160 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2161 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
fc06573d 2162 }
c1e7e466
JM		 2163 mlx4_ib_device_unregister_sysfs(dev);
2164
2165sysfs_err:
a0c64a17
JM		 2166 mlx4_ib_destroy_alias_guid_service(dev);
2167
2168paravirt_err:
3cf69cc8 2169 mlx4_ib_cm_paravirt_clean(dev, -1);
fc06573d
JM		 2170
2171 return err;
2172}
2173
2174void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev)
2175{
2176 int i;
2177 unsigned long flags;
2178
2179 if (!mlx4_is_mfunc(dev->dev))
2180 return;
2181
2182 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
2183 dev->sriov.is_going_down = 1;
2184 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
3cf69cc8 2185 if (mlx4_is_master(dev->dev)) {
fc06573d
JM		 2186 for (i = 0; i < dev->num_ports; i++) {
2187 flush_workqueue(dev->sriov.demux[i].ud_wq);
2188 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]);
2189 kfree(dev->sriov.sqps[i]);
2190 dev->sriov.sqps[i] = NULL;
2191 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2192 }
3cf69cc8
AV		 2193
2194 mlx4_ib_cm_paravirt_clean(dev, -1);
a0c64a17 2195 mlx4_ib_destroy_alias_guid_service(dev);
c1e7e466 2196 mlx4_ib_device_unregister_sysfs(dev);
3cf69cc8 2197 }
fc06573d 2198}
Linux kernel - Deliverables
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