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net/mlx4_core: Configure mlx4 hardware for mixed RoCE v1/v2 modes
[deliverable/linux.git] / drivers / infiniband / hw / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/module.h>
35#include <linux/init.h>
5a0e3ad6 36#include <linux/slab.h>
225c7b1f 37#include <linux/errno.h>
fa417f7b
EC		 38#include <linux/netdevice.h>
39#include <linux/inetdevice.h>
40#include <linux/rtnetlink.h>
4c3eb3ca 41#include <linux/if_vlan.h>
d487ee77
MS		 42#include <net/ipv6.h>
43#include <net/addrconf.h>
225c7b1f
RD		 44
45#include <rdma/ib_smi.h>
46#include <rdma/ib_user_verbs.h>
fa417f7b 47#include <rdma/ib_addr.h>
e26be1bf
MS		 48#include <rdma/ib_cache.h>
49
50#include <net/bonding.h>
225c7b1f
RD		 51
52#include <linux/mlx4/driver.h>
53#include <linux/mlx4/cmd.h>
9433c188 54#include <linux/mlx4/qp.h>
225c7b1f
RD		 55
56#include "mlx4_ib.h"
57#include "user.h"
58
b1d8eb5a 59#define DRV_NAME MLX4_IB_DRV_NAME
169a1d85
AV		 60#define DRV_VERSION "2.2-1"
61#define DRV_RELDATE "Feb 2014"
225c7b1f 62
f77c0162 63#define MLX4_IB_FLOW_MAX_PRIO 0xFFF
a37a1a42 64#define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
50e2ec91 65#define MLX4_IB_CARD_REV_A0 0xA0
f77c0162 66
225c7b1f
RD		 67MODULE_AUTHOR("Roland Dreier");
68MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
69MODULE_LICENSE("Dual BSD/GPL");
70MODULE_VERSION(DRV_VERSION);
71
56c1d233 72int mlx4_ib_sm_guid_assign = 0;
a0c64a17 73module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
56c1d233 74MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
a0c64a17 75
68f3948d 76static const char mlx4_ib_version[] =
225c7b1f
RD		 77 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
78 DRV_VERSION " (" DRV_RELDATE ")\n";
79
3806d08c
JM		 80static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
81
fa417f7b
EC		 82static struct workqueue_struct *wq;
83
225c7b1f
RD		 84static void init_query_mad(struct ib_smp *mad)
85{
86 mad->base_version = 1;
87 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
88 mad->class_version = 1;
89 mad->method = IB_MGMT_METHOD_GET;
90}
91
f77c0162
HHZ		 92static int check_flow_steering_support(struct mlx4_dev *dev)
93{
0a9b7d59 94 int eth_num_ports = 0;
f77c0162 95 int ib_num_ports = 0;
f77c0162 96
0a9b7d59
MB		 97 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
98
99 if (dmfs) {
100 int i;
101 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
102 eth_num_ports++;
103 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
104 ib_num_ports++;
105 dmfs &= (!ib_num_ports ||
106 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
107 (!eth_num_ports ||
108 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
109 if (ib_num_ports && mlx4_is_mfunc(dev)) {
110 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
111 dmfs = 0;
f77c0162 112 }
f77c0162 113 }
0a9b7d59 114 return dmfs;
f77c0162
HHZ		 115}
116
3dec4878
JM		 117static int num_ib_ports(struct mlx4_dev *dev)
118{
119 int ib_ports = 0;
120 int i;
121
122 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
123 ib_ports++;
124
125 return ib_ports;
126}
127
e26be1bf
MS		 128static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
129{
130 struct mlx4_ib_dev *ibdev = to_mdev(device);
131 struct net_device *dev;
132
133 rcu_read_lock();
134 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
135
136 if (dev) {
137 if (mlx4_is_bonded(ibdev->dev)) {
138 struct net_device *upper = NULL;
139
140 upper = netdev_master_upper_dev_get_rcu(dev);
141 if (upper) {
142 struct net_device *active;
143
144 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
145 if (active)
146 dev = active;
147 }
148 }
149 }
150 if (dev)
151 dev_hold(dev);
152
153 rcu_read_unlock();
154 return dev;
155}
156
157static int mlx4_ib_update_gids(struct gid_entry *gids,
158 struct mlx4_ib_dev *ibdev,
159 u8 port_num)
160{
161 struct mlx4_cmd_mailbox *mailbox;
162 int err;
163 struct mlx4_dev *dev = ibdev->dev;
164 int i;
165 union ib_gid *gid_tbl;
166
167 mailbox = mlx4_alloc_cmd_mailbox(dev);
168 if (IS_ERR(mailbox))
169 return -ENOMEM;
170
171 gid_tbl = mailbox->buf;
172
173 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
174 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
175
176 err = mlx4_cmd(dev, mailbox->dma,
177 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
178 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
179 MLX4_CMD_WRAPPED);
180 if (mlx4_is_bonded(dev))
181 err += mlx4_cmd(dev, mailbox->dma,
182 MLX4_SET_PORT_GID_TABLE << 8 | 2,
183 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
184 MLX4_CMD_WRAPPED);
185
186 mlx4_free_cmd_mailbox(dev, mailbox);
187 return err;
188}
189
190static int mlx4_ib_add_gid(struct ib_device *device,
191 u8 port_num,
192 unsigned int index,
193 const union ib_gid *gid,
194 const struct ib_gid_attr *attr,
195 void **context)
196{
197 struct mlx4_ib_dev *ibdev = to_mdev(device);
198 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
199 struct mlx4_port_gid_table *port_gid_table;
200 int free = -1, found = -1;
201 int ret = 0;
202 int hw_update = 0;
203 int i;
204 struct gid_entry *gids = NULL;
205
206 if (!rdma_cap_roce_gid_table(device, port_num))
207 return -EINVAL;
208
209 if (port_num > MLX4_MAX_PORTS)
210 return -EINVAL;
211
212 if (!context)
213 return -EINVAL;
214
215 port_gid_table = &iboe->gids[port_num - 1];
216 spin_lock_bh(&iboe->lock);
217 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
b699a859
MS		 218 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
219 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
e26be1bf
MS		 220 found = i;
221 break;
222 }
223 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
224 free = i; /* HW has space */
225 }
226
227 if (found < 0) {
228 if (free < 0) {
229 ret = -ENOSPC;
230 } else {
231 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
232 if (!port_gid_table->gids[free].ctx) {
233 ret = -ENOMEM;
234 } else {
235 *context = port_gid_table->gids[free].ctx;
236 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
b699a859 237 port_gid_table->gids[free].gid_type = attr->gid_type;
e26be1bf
MS		 238 port_gid_table->gids[free].ctx->real_index = free;
239 port_gid_table->gids[free].ctx->refcount = 1;
240 hw_update = 1;
241 }
242 }
243 } else {
244 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
245 *context = ctx;
246 ctx->refcount++;
247 }
248 if (!ret && hw_update) {
249 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
250 if (!gids) {
251 ret = -ENOMEM;
252 } else {
b699a859 253 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
e26be1bf 254 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
b699a859
MS		 255 gids[i].gid_type = port_gid_table->gids[i].gid_type;
256 }
e26be1bf
MS		 257 }
258 }
259 spin_unlock_bh(&iboe->lock);
260
261 if (!ret && hw_update) {
262 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
263 kfree(gids);
264 }
265
266 return ret;
267}
268
269static int mlx4_ib_del_gid(struct ib_device *device,
270 u8 port_num,
271 unsigned int index,
272 void **context)
273{
274 struct gid_cache_context *ctx = *context;
275 struct mlx4_ib_dev *ibdev = to_mdev(device);
276 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
277 struct mlx4_port_gid_table *port_gid_table;
278 int ret = 0;
279 int hw_update = 0;
280 struct gid_entry *gids = NULL;
281
282 if (!rdma_cap_roce_gid_table(device, port_num))
283 return -EINVAL;
284
285 if (port_num > MLX4_MAX_PORTS)
286 return -EINVAL;
287
288 port_gid_table = &iboe->gids[port_num - 1];
289 spin_lock_bh(&iboe->lock);
290 if (ctx) {
291 ctx->refcount--;
292 if (!ctx->refcount) {
293 unsigned int real_index = ctx->real_index;
294
295 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
296 kfree(port_gid_table->gids[real_index].ctx);
297 port_gid_table->gids[real_index].ctx = NULL;
298 hw_update = 1;
299 }
300 }
301 if (!ret && hw_update) {
302 int i;
303
304 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
305 if (!gids) {
306 ret = -ENOMEM;
307 } else {
308 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
309 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
310 }
311 }
312 spin_unlock_bh(&iboe->lock);
313
314 if (!ret && hw_update) {
315 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
316 kfree(gids);
317 }
318 return ret;
319}
320
321int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
322 u8 port_num, int index)
323{
324 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
325 struct gid_cache_context *ctx = NULL;
326 union ib_gid gid;
327 struct mlx4_port_gid_table *port_gid_table;
328 int real_index = -EINVAL;
329 int i;
330 int ret;
331 unsigned long flags;
b699a859 332 struct ib_gid_attr attr;
e26be1bf
MS		 333
334 if (port_num > MLX4_MAX_PORTS)
335 return -EINVAL;
336
337 if (mlx4_is_bonded(ibdev->dev))
338 port_num = 1;
339
340 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
341 return index;
342
b699a859 343 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
e26be1bf
MS		 344 if (ret)
345 return ret;
346
b699a859
MS		 347 if (attr.ndev)
348 dev_put(attr.ndev);
349
e26be1bf
MS		 350 if (!memcmp(&gid, &zgid, sizeof(gid)))
351 return -EINVAL;
352
353 spin_lock_irqsave(&iboe->lock, flags);
354 port_gid_table = &iboe->gids[port_num - 1];
355
356 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
b699a859
MS		 357 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
358 attr.gid_type == port_gid_table->gids[i].gid_type) {
e26be1bf
MS		 359 ctx = port_gid_table->gids[i].ctx;
360 break;
361 }
362 if (ctx)
363 real_index = ctx->real_index;
364 spin_unlock_irqrestore(&iboe->lock, flags);
365 return real_index;
366}
367
225c7b1f 368static int mlx4_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 369 struct ib_device_attr *props,
370 struct ib_udata *uhw)
225c7b1f
RD		 371{
372 struct mlx4_ib_dev *dev = to_mdev(ibdev);
373 struct ib_smp *in_mad = NULL;
374 struct ib_smp *out_mad = NULL;
375 int err = -ENOMEM;
3dec4878 376 int have_ib_ports;
4b664c43
MB		 377 struct mlx4_uverbs_ex_query_device cmd;
378 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
379 struct mlx4_clock_params clock_params;
225c7b1f 380
4b664c43
MB		 381 if (uhw->inlen) {
382 if (uhw->inlen < sizeof(cmd))
383 return -EINVAL;
384
385 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
386 if (err)
387 return err;
388
389 if (cmd.comp_mask)
390 return -EINVAL;
391
392 if (cmd.reserved)
393 return -EINVAL;
394 }
2528e33e 395
4b664c43
MB		 396 resp.response_length = offsetof(typeof(resp), response_length) +
397 sizeof(resp.response_length);
225c7b1f
RD		 398 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
399 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
400 if (!in_mad || !out_mad)
401 goto out;
402
403 init_query_mad(in_mad);
404 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
405
0a9a0188
JM		 406 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
407 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 408 if (err)
409 goto out;
410
411 memset(props, 0, sizeof *props);
412
3dec4878
JM		 413 have_ib_ports = num_ib_ports(dev->dev);
414
225c7b1f
RD		 415 props->fw_ver = dev->dev->caps.fw_ver;
416 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
417 IB_DEVICE_PORT_ACTIVE_EVENT |
418 IB_DEVICE_SYS_IMAGE_GUID |
521e575b
RL		 419 IB_DEVICE_RC_RNR_NAK_GEN |
420 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
225c7b1f
RD		 421 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
422 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
423 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
424 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
3dec4878 425 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
225c7b1f
RD		 426 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
427 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
428 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
8ff095ec
EC		 429 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
430 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
50e2ec91
MS		 431 if (dev->dev->caps.max_gso_sz &&
432 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
433 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
b832be1e 434 props->device_cap_flags |= IB_DEVICE_UD_TSO;
95d04f07
RD		 435 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
436 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
437 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
438 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
439 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
440 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
0a1405da
SH		 441 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
442 props->device_cap_flags |= IB_DEVICE_XRC;
b425388d
SM		 443 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
444 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
445 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
446 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
447 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
448 else
449 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
0a9b7d59 450 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
f77c0162 451 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
b425388d 452 }
225c7b1f 453
070b3997
BW		 454 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
455
225c7b1f
RD		 456 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
457 0xffffff;
872bf2fb 458 props->vendor_part_id = dev->dev->persist->pdev->device;
225c7b1f
RD		 459 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
460 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
461
462 props->max_mr_size = ~0ull;
463 props->page_size_cap = dev->dev->caps.page_size_cap;
5a0d0a61 464 props->max_qp = dev->dev->quotas.qp;
fc2d0044 465 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
225c7b1f
RD		 466 props->max_sge = min(dev->dev->caps.max_sq_sg,
467 dev->dev->caps.max_rq_sg);
a5e14ba3 468 props->max_sge_rd = MLX4_MAX_SGE_RD;
5a0d0a61 469 props->max_cq = dev->dev->quotas.cq;
225c7b1f 470 props->max_cqe = dev->dev->caps.max_cqes;
5a0d0a61 471 props->max_mr = dev->dev->quotas.mpt;
225c7b1f
RD		 472 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
473 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
474 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
475 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
5a0d0a61 476 props->max_srq = dev->dev->quotas.srq;
c8681f14 477 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
225c7b1f 478 props->max_srq_sge = dev->dev->caps.max_srq_sge;
5a0fd094 479 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
225c7b1f
RD		 480 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
481 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
482 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
47e956b2 483 props->masked_atomic_cap = props->atomic_cap;
5ae2a7a8 484 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
225c7b1f
RD		 485 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
486 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
487 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
488 props->max_mcast_grp;
a5bbe892 489 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
4b664c43
MB		 490 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
491 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
225c7b1f 492
8a7ff14d
MB		 493 if (!mlx4_is_slave(dev->dev))
494 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
4b664c43
MB		 495
496 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
4b664c43 497 resp.response_length += sizeof(resp.hca_core_clock_offset);
8a7ff14d
MB		 498 if (!err && !mlx4_is_slave(dev->dev)) {
499 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
500 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
501 }
4b664c43
MB		 502 }
503
504 if (uhw->outlen) {
505 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
506 if (err)
507 goto out;
508 }
225c7b1f
RD		 509out:
510 kfree(in_mad);
511 kfree(out_mad);
512
513 return err;
514}
515
fa417f7b
EC		 516static enum rdma_link_layer
517mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
225c7b1f 518{
fa417f7b 519 struct mlx4_dev *dev = to_mdev(device)->dev;
225c7b1f 520
65dab25d 521 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
fa417f7b
EC		 522 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
523}
225c7b1f 524
fa417f7b 525static int ib_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 526 struct ib_port_attr *props, int netw_view)
fa417f7b 527{
a9c766bb
OG		 528 struct ib_smp *in_mad = NULL;
529 struct ib_smp *out_mad = NULL;
a5e12dff 530 int ext_active_speed;
0a9a0188 531 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
a9c766bb
OG		 532 int err = -ENOMEM;
533
534 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
535 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
536 if (!in_mad || !out_mad)
537 goto out;
538
539 init_query_mad(in_mad);
540 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
541 in_mad->attr_mod = cpu_to_be32(port);
542
0a9a0188
JM		 543 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
544 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
545
546 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
a9c766bb
OG		 547 in_mad, out_mad);
548 if (err)
549 goto out;
550
a5e12dff 551
225c7b1f
RD		 552 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
553 props->lmc = out_mad->data[34] & 0x7;
554 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
555 props->sm_sl = out_mad->data[36] & 0xf;
556 props->state = out_mad->data[32] & 0xf;
557 props->phys_state = out_mad->data[33] >> 4;
558 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
0a9a0188
JM		 559 if (netw_view)
560 props->gid_tbl_len = out_mad->data[50];
561 else
562 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
149983af 563 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
5ae2a7a8 564 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
225c7b1f
RD		 565 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
566 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
567 props->active_width = out_mad->data[31] & 0xf;
568 props->active_speed = out_mad->data[35] >> 4;
569 props->max_mtu = out_mad->data[41] & 0xf;
570 props->active_mtu = out_mad->data[36] >> 4;
571 props->subnet_timeout = out_mad->data[51] & 0x1f;
572 props->max_vl_num = out_mad->data[37] >> 4;
573 props->init_type_reply = out_mad->data[41] >> 4;
574
a5e12dff
MA		 575 /* Check if extended speeds (EDR/FDR/...) are supported */
576 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
577 ext_active_speed = out_mad->data[62] >> 4;
578
579 switch (ext_active_speed) {
580 case 1:
2e96691c 581 props->active_speed = IB_SPEED_FDR;
a5e12dff
MA		 582 break;
583 case 2:
2e96691c 584 props->active_speed = IB_SPEED_EDR;
a5e12dff
MA		 585 break;
586 }
587 }
588
589 /* If reported active speed is QDR, check if is FDR-10 */
2e96691c 590 if (props->active_speed == IB_SPEED_QDR) {
8154c07f
OG		 591 init_query_mad(in_mad);
592 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
593 in_mad->attr_mod = cpu_to_be32(port);
594
0a9a0188 595 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
8154c07f
OG		 596 NULL, NULL, in_mad, out_mad);
597 if (err)
bf6b47de 598 goto out;
8154c07f
OG		 599
600 /* Checking LinkSpeedActive for FDR-10 */
601 if (out_mad->data[15] & 0x1)
602 props->active_speed = IB_SPEED_FDR10;
a5e12dff 603 }
d2ef4068
OG		 604
605 /* Avoid wrong speed value returned by FW if the IB link is down. */
606 if (props->state == IB_PORT_DOWN)
607 props->active_speed = IB_SPEED_SDR;
608
a9c766bb
OG		 609out:
610 kfree(in_mad);
611 kfree(out_mad);
612 return err;
fa417f7b
EC		 613}
614
615static u8 state_to_phys_state(enum ib_port_state state)
616{
617 return state == IB_PORT_ACTIVE ? 5 : 3;
618}
619
620static int eth_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 621 struct ib_port_attr *props, int netw_view)
fa417f7b 622{
a9c766bb
OG		 623
624 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
625 struct mlx4_ib_iboe *iboe = &mdev->iboe;
fa417f7b
EC		 626 struct net_device *ndev;
627 enum ib_mtu tmp;
a9c766bb
OG		 628 struct mlx4_cmd_mailbox *mailbox;
629 int err = 0;
a5750090 630 int is_bonded = mlx4_is_bonded(mdev->dev);
a9c766bb
OG		 631
632 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
633 if (IS_ERR(mailbox))
634 return PTR_ERR(mailbox);
fa417f7b 635
a9c766bb
OG		 636 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
637 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
638 MLX4_CMD_WRAPPED);
639 if (err)
640 goto out;
641
642 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ?
643 IB_WIDTH_4X : IB_WIDTH_1X;
2e96691c 644 props->active_speed = IB_SPEED_QDR;
b4a26a27 645 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
a9c766bb
OG		 646 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
647 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
fa417f7b 648 props->pkey_tbl_len = 1;
bcacb897 649 props->max_mtu = IB_MTU_4096;
a9c766bb 650 props->max_vl_num = 2;
fa417f7b
EC		 651 props->state = IB_PORT_DOWN;
652 props->phys_state = state_to_phys_state(props->state);
653 props->active_mtu = IB_MTU_256;
dba3ad2a 654 spin_lock_bh(&iboe->lock);
fa417f7b 655 ndev = iboe->netdevs[port - 1];
5070cd22
MS		 656 if (ndev && is_bonded) {
657 rcu_read_lock(); /* required to get upper dev */
658 ndev = netdev_master_upper_dev_get_rcu(ndev);
659 rcu_read_unlock();
660 }
fa417f7b 661 if (!ndev)
a9c766bb 662 goto out_unlock;
fa417f7b
EC		 663
664 tmp = iboe_get_mtu(ndev->mtu);
665 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
666
21d60609 667 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
fa417f7b
EC		 668 IB_PORT_ACTIVE : IB_PORT_DOWN;
669 props->phys_state = state_to_phys_state(props->state);
a9c766bb 670out_unlock:
dba3ad2a 671 spin_unlock_bh(&iboe->lock);
a9c766bb
OG		 672out:
673 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
674 return err;
fa417f7b
EC		 675}
676
0a9a0188
JM		 677int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
678 struct ib_port_attr *props, int netw_view)
fa417f7b 679{
a9c766bb 680 int err;
fa417f7b
EC		 681
682 memset(props, 0, sizeof *props);
683
fa417f7b 684 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
0a9a0188
JM		 685 ib_link_query_port(ibdev, port, props, netw_view) :
686 eth_link_query_port(ibdev, port, props, netw_view);
225c7b1f
RD		 687
688 return err;
689}
690
0a9a0188
JM		 691static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
692 struct ib_port_attr *props)
693{
694 /* returns host view */
695 return __mlx4_ib_query_port(ibdev, port, props, 0);
696}
697
a0c64a17
JM		 698int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
699 union ib_gid *gid, int netw_view)
225c7b1f
RD		 700{
701 struct ib_smp *in_mad = NULL;
702 struct ib_smp *out_mad = NULL;
703 int err = -ENOMEM;
a0c64a17
JM		 704 struct mlx4_ib_dev *dev = to_mdev(ibdev);
705 int clear = 0;
706 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 707
708 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
709 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
710 if (!in_mad || !out_mad)
711 goto out;
712
713 init_query_mad(in_mad);
714 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
715 in_mad->attr_mod = cpu_to_be32(port);
716
a0c64a17
JM		 717 if (mlx4_is_mfunc(dev->dev) && netw_view)
718 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
719
720 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 721 if (err)
722 goto out;
723
724 memcpy(gid->raw, out_mad->data + 8, 8);
725
a0c64a17
JM		 726 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
727 if (index) {
728 /* For any index > 0, return the null guid */
729 err = 0;
730 clear = 1;
731 goto out;
732 }
733 }
734
225c7b1f
RD		 735 init_query_mad(in_mad);
736 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
737 in_mad->attr_mod = cpu_to_be32(index / 8);
738
a0c64a17 739 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
0a9a0188 740 NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 741 if (err)
742 goto out;
743
744 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
745
746out:
a0c64a17
JM		 747 if (clear)
748 memset(gid->raw + 8, 0, 8);
225c7b1f
RD		 749 kfree(in_mad);
750 kfree(out_mad);
751 return err;
752}
753
fa417f7b
EC		 754static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
755 union ib_gid *gid)
756{
5070cd22
MS		 757 int ret;
758
759 if (rdma_protocol_ib(ibdev, port))
a0c64a17 760 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
5070cd22
MS		 761
762 if (!rdma_protocol_roce(ibdev, port))
763 return -ENODEV;
764
765 if (!rdma_cap_roce_gid_table(ibdev, port))
766 return -ENODEV;
767
55ee3ab2 768 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
5070cd22
MS		 769 if (ret == -EAGAIN) {
770 memcpy(gid, &zgid, sizeof(*gid));
771 return 0;
772 }
773
774 return ret;
fa417f7b
EC		 775}
776
0a9a0188
JM		 777int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
778 u16 *pkey, int netw_view)
225c7b1f
RD		 779{
780 struct ib_smp *in_mad = NULL;
781 struct ib_smp *out_mad = NULL;
0a9a0188 782 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 783 int err = -ENOMEM;
784
785 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
786 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
787 if (!in_mad || !out_mad)
788 goto out;
789
790 init_query_mad(in_mad);
791 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
792 in_mad->attr_mod = cpu_to_be32(index / 32);
793
0a9a0188
JM		 794 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
795 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
796
797 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
798 in_mad, out_mad);
225c7b1f
RD		 799 if (err)
800 goto out;
801
802 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
803
804out:
805 kfree(in_mad);
806 kfree(out_mad);
807 return err;
808}
809
0a9a0188
JM		 810static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
811{
812 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
813}
814
225c7b1f
RD		 815static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
816 struct ib_device_modify *props)
817{
d0d68b86 818 struct mlx4_cmd_mailbox *mailbox;
df7fba66 819 unsigned long flags;
d0d68b86 820
225c7b1f
RD		 821 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
822 return -EOPNOTSUPP;
823
d0d68b86
JM		 824 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
825 return 0;
826
992e8e6e
JM		 827 if (mlx4_is_slave(to_mdev(ibdev)->dev))
828 return -EOPNOTSUPP;
829
df7fba66 830 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86 831 memcpy(ibdev->node_desc, props->node_desc, 64);
df7fba66 832 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86
JM		 833
834 /*
835 * If possible, pass node desc to FW, so it can generate
836 * a 144 trap. If cmd fails, just ignore.
837 */
838 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
839 if (IS_ERR(mailbox))
840 return 0;
841
d0d68b86
JM		 842 memcpy(mailbox->buf, props->node_desc, 64);
843 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
992e8e6e 844 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
d0d68b86
JM		 845
846 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
225c7b1f
RD		 847
848 return 0;
849}
850
61565013
JM		 851static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
852 u32 cap_mask)
225c7b1f
RD		 853{
854 struct mlx4_cmd_mailbox *mailbox;
855 int err;
856
857 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
858 if (IS_ERR(mailbox))
859 return PTR_ERR(mailbox);
860
5ae2a7a8
RD		 861 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
862 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
863 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
864 } else {
865 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
866 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
867 }
225c7b1f 868
a130b590
IS		 869 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
870 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
871 MLX4_CMD_WRAPPED);
225c7b1f
RD		 872
873 mlx4_free_cmd_mailbox(dev->dev, mailbox);
874 return err;
875}
876
877static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
878 struct ib_port_modify *props)
879{
61565013
JM		 880 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
881 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
225c7b1f
RD		 882 struct ib_port_attr attr;
883 u32 cap_mask;
884 int err;
885
61565013
JM		 886 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
887 * of whether port link layer is ETH or IB. For ETH ports, qkey
888 * violations and port capabilities are not meaningful.
889 */
890 if (is_eth)
891 return 0;
892
893 mutex_lock(&mdev->cap_mask_mutex);
225c7b1f
RD		 894
895 err = mlx4_ib_query_port(ibdev, port, &attr);
896 if (err)
897 goto out;
898
899 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
900 ~props->clr_port_cap_mask;
901
61565013
JM		 902 err = mlx4_ib_SET_PORT(mdev, port,
903 !!(mask & IB_PORT_RESET_QKEY_CNTR),
904 cap_mask);
225c7b1f
RD		 905
906out:
907 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
908 return err;
909}
910
911static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
912 struct ib_udata *udata)
913{
914 struct mlx4_ib_dev *dev = to_mdev(ibdev);
915 struct mlx4_ib_ucontext *context;
08ff3235 916 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
225c7b1f
RD		 917 struct mlx4_ib_alloc_ucontext_resp resp;
918 int err;
919
3b4a8cd5
JM		 920 if (!dev->ib_active)
921 return ERR_PTR(-EAGAIN);
922
08ff3235
OG		 923 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
924 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
925 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
926 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
927 } else {
928 resp.dev_caps = dev->dev->caps.userspace_caps;
929 resp.qp_tab_size = dev->dev->caps.num_qps;
930 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
931 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
932 resp.cqe_size = dev->dev->caps.cqe_size;
933 }
225c7b1f 934
ae184dde 935 context = kzalloc(sizeof(*context), GFP_KERNEL);
225c7b1f
RD		 936 if (!context)
937 return ERR_PTR(-ENOMEM);
938
939 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
940 if (err) {
941 kfree(context);
942 return ERR_PTR(err);
943 }
944
945 INIT_LIST_HEAD(&context->db_page_list);
946 mutex_init(&context->db_page_mutex);
947
08ff3235
OG		 948 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
949 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
950 else
951 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
952
225c7b1f
RD		 953 if (err) {
954 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
955 kfree(context);
956 return ERR_PTR(-EFAULT);
957 }
958
959 return &context->ibucontext;
960}
961
962static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
963{
964 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
965
966 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
967 kfree(context);
968
969 return 0;
970}
971
ae184dde
YH		 972static void mlx4_ib_vma_open(struct vm_area_struct *area)
973{
974 /* vma_open is called when a new VMA is created on top of our VMA.
975 * This is done through either mremap flow or split_vma (usually due
976 * to mlock, madvise, munmap, etc.). We do not support a clone of the
977 * vma, as this VMA is strongly hardware related. Therefore we set the
978 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
979 * calling us again and trying to do incorrect actions. We assume that
980 * the original vma size is exactly a single page that there will be no
981 * "splitting" operations on.
982 */
983 area->vm_ops = NULL;
984}
985
986static void mlx4_ib_vma_close(struct vm_area_struct *area)
987{
988 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
989
990 /* It's guaranteed that all VMAs opened on a FD are closed before the
991 * file itself is closed, therefore no sync is needed with the regular
992 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
993 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
994 * The close operation is usually called under mm->mmap_sem except when
995 * process is exiting. The exiting case is handled explicitly as part
996 * of mlx4_ib_disassociate_ucontext.
997 */
998 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
999 area->vm_private_data;
1000
1001 /* set the vma context pointer to null in the mlx4_ib driver's private
1002 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1003 */
1004 mlx4_ib_vma_priv_data->vma = NULL;
1005}
1006
1007static const struct vm_operations_struct mlx4_ib_vm_ops = {
1008 .open = mlx4_ib_vma_open,
1009 .close = mlx4_ib_vma_close
1010};
1011
1012static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1013{
1014 int i;
1015 int ret = 0;
1016 struct vm_area_struct *vma;
1017 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1018 struct task_struct *owning_process = NULL;
1019 struct mm_struct *owning_mm = NULL;
1020
1021 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1022 if (!owning_process)
1023 return;
1024
1025 owning_mm = get_task_mm(owning_process);
1026 if (!owning_mm) {
1027 pr_info("no mm, disassociate ucontext is pending task termination\n");
1028 while (1) {
1029 /* make sure that task is dead before returning, it may
1030 * prevent a rare case of module down in parallel to a
1031 * call to mlx4_ib_vma_close.
1032 */
1033 put_task_struct(owning_process);
1034 msleep(1);
1035 owning_process = get_pid_task(ibcontext->tgid,
1036 PIDTYPE_PID);
1037 if (!owning_process ||
1038 owning_process->state == TASK_DEAD) {
1039 pr_info("disassociate ucontext done, task was terminated\n");
1040 /* in case task was dead need to release the task struct */
1041 if (owning_process)
1042 put_task_struct(owning_process);
1043 return;
1044 }
1045 }
1046 }
1047
1048 /* need to protect from a race on closing the vma as part of
1049 * mlx4_ib_vma_close().
1050 */
1051 down_read(&owning_mm->mmap_sem);
1052 for (i = 0; i < HW_BAR_COUNT; i++) {
1053 vma = context->hw_bar_info[i].vma;
1054 if (!vma)
1055 continue;
1056
1057 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1058 context->hw_bar_info[i].vma->vm_start,
1059 PAGE_SIZE);
1060 if (ret) {
1061 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1062 BUG_ON(1);
1063 }
1064
1065 /* context going to be destroyed, should not access ops any more */
1066 context->hw_bar_info[i].vma->vm_ops = NULL;
1067 }
1068
1069 up_read(&owning_mm->mmap_sem);
1070 mmput(owning_mm);
1071 put_task_struct(owning_process);
1072}
1073
1074static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1075 struct mlx4_ib_vma_private_data *vma_private_data)
1076{
1077 vma_private_data->vma = vma;
1078 vma->vm_private_data = vma_private_data;
1079 vma->vm_ops = &mlx4_ib_vm_ops;
1080}
1081
225c7b1f
RD		 1082static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1083{
1084 struct mlx4_ib_dev *dev = to_mdev(context->device);
ae184dde 1085 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
225c7b1f
RD		 1086
1087 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1088 return -EINVAL;
1089
1090 if (vma->vm_pgoff == 0) {
ae184dde
YH		 1091 /* We prevent double mmaping on same context */
1092 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1093 return -EINVAL;
1094
225c7b1f
RD		 1095 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1096
1097 if (io_remap_pfn_range(vma, vma->vm_start,
1098 to_mucontext(context)->uar.pfn,
1099 PAGE_SIZE, vma->vm_page_prot))
1100 return -EAGAIN;
ae184dde
YH		 1101
1102 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1103
225c7b1f 1104 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
ae184dde
YH		 1105 /* We prevent double mmaping on same context */
1106 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1107 return -EINVAL;
1108
e1d60ec6 1109 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
225c7b1f
RD		 1110
1111 if (io_remap_pfn_range(vma, vma->vm_start,
1112 to_mucontext(context)->uar.pfn +
1113 dev->dev->caps.num_uars,
1114 PAGE_SIZE, vma->vm_page_prot))
1115 return -EAGAIN;
ae184dde
YH		 1116
1117 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1118
52033cfb
MB		 1119 } else if (vma->vm_pgoff == 3) {
1120 struct mlx4_clock_params params;
ae184dde
YH		 1121 int ret;
1122
1123 /* We prevent double mmaping on same context */
1124 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1125 return -EINVAL;
1126
1127 ret = mlx4_get_internal_clock_params(dev->dev, &params);
52033cfb
MB		 1128
1129 if (ret)
1130 return ret;
1131
1132 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1133 if (io_remap_pfn_range(vma, vma->vm_start,
1134 (pci_resource_start(dev->dev->persist->pdev,
1135 params.bar) +
1136 params.offset)
1137 >> PAGE_SHIFT,
1138 PAGE_SIZE, vma->vm_page_prot))
1139 return -EAGAIN;
ae184dde
YH		 1140
1141 mlx4_ib_set_vma_data(vma,
1142 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
52033cfb 1143 } else {
225c7b1f 1144 return -EINVAL;
52033cfb 1145 }
225c7b1f
RD		 1146
1147 return 0;
1148}
1149
1150static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1151 struct ib_ucontext *context,
1152 struct ib_udata *udata)
1153{
1154 struct mlx4_ib_pd *pd;
1155 int err;
1156
1157 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1158 if (!pd)
1159 return ERR_PTR(-ENOMEM);
1160
1161 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1162 if (err) {
1163 kfree(pd);
1164 return ERR_PTR(err);
1165 }
1166
1167 if (context)
1168 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1169 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1170 kfree(pd);
1171 return ERR_PTR(-EFAULT);
1172 }
1173
1174 return &pd->ibpd;
1175}
1176
1177static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1178{
1179 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1180 kfree(pd);
1181
1182 return 0;
1183}
1184
012a8ff5
SH		 1185static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1186 struct ib_ucontext *context,
1187 struct ib_udata *udata)
1188{
1189 struct mlx4_ib_xrcd *xrcd;
8e37210b 1190 struct ib_cq_init_attr cq_attr = {};
012a8ff5
SH		 1191 int err;
1192
1193 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1194 return ERR_PTR(-ENOSYS);
1195
1196 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1197 if (!xrcd)
1198 return ERR_PTR(-ENOMEM);
1199
1200 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1201 if (err)
1202 goto err1;
1203
1204 xrcd->pd = ib_alloc_pd(ibdev);
1205 if (IS_ERR(xrcd->pd)) {
1206 err = PTR_ERR(xrcd->pd);
1207 goto err2;
1208 }
1209
8e37210b
MB		 1210 cq_attr.cqe = 1;
1211 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
012a8ff5
SH		 1212 if (IS_ERR(xrcd->cq)) {
1213 err = PTR_ERR(xrcd->cq);
1214 goto err3;
1215 }
1216
1217 return &xrcd->ibxrcd;
1218
1219err3:
1220 ib_dealloc_pd(xrcd->pd);
1221err2:
1222 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1223err1:
1224 kfree(xrcd);
1225 return ERR_PTR(err);
1226}
1227
1228static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1229{
1230 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1231 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1232 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1233 kfree(xrcd);
1234
1235 return 0;
1236}
1237
fa417f7b
EC		 1238static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1239{
1240 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1241 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1242 struct mlx4_ib_gid_entry *ge;
1243
1244 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1245 if (!ge)
1246 return -ENOMEM;
1247
1248 ge->gid = *gid;
1249 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1250 ge->port = mqp->port;
1251 ge->added = 1;
1252 }
1253
1254 mutex_lock(&mqp->mutex);
1255 list_add_tail(&ge->list, &mqp->gid_list);
1256 mutex_unlock(&mqp->mutex);
1257
1258 return 0;
1259}
1260
3ba8e31d
EBE		 1261static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1262 struct mlx4_ib_counters *ctr_table)
1263{
1264 struct counter_index *counter, *tmp_count;
1265
1266 mutex_lock(&ctr_table->mutex);
1267 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1268 list) {
1269 if (counter->allocated)
1270 mlx4_counter_free(ibdev->dev, counter->index);
1271 list_del(&counter->list);
1272 kfree(counter);
1273 }
1274 mutex_unlock(&ctr_table->mutex);
1275}
1276
fa417f7b
EC		 1277int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1278 union ib_gid *gid)
1279{
fa417f7b
EC		 1280 struct net_device *ndev;
1281 int ret = 0;
1282
1283 if (!mqp->port)
1284 return 0;
1285
dba3ad2a 1286 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1287 ndev = mdev->iboe.netdevs[mqp->port - 1];
1288 if (ndev)
1289 dev_hold(ndev);
dba3ad2a 1290 spin_unlock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1291
1292 if (ndev) {
fa417f7b 1293 ret = 1;
fa417f7b
EC		 1294 dev_put(ndev);
1295 }
1296
1297 return ret;
1298}
1299
0ff1fb65
HHZ		 1300struct mlx4_ib_steering {
1301 struct list_head list;
146d6e19 1302 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1303 union ib_gid gid;
1304};
1305
f77c0162 1306static int parse_flow_attr(struct mlx4_dev *dev,
a37a1a42 1307 u32 qp_num,
f77c0162
HHZ		 1308 union ib_flow_spec *ib_spec,
1309 struct _rule_hw *mlx4_spec)
1310{
1311 enum mlx4_net_trans_rule_id type;
1312
1313 switch (ib_spec->type) {
1314 case IB_FLOW_SPEC_ETH:
1315 type = MLX4_NET_TRANS_RULE_ID_ETH;
1316 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1317 ETH_ALEN);
1318 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1319 ETH_ALEN);
1320 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1321 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1322 break;
a37a1a42
MB		 1323 case IB_FLOW_SPEC_IB:
1324 type = MLX4_NET_TRANS_RULE_ID_IB;
1325 mlx4_spec->ib.l3_qpn =
1326 cpu_to_be32(qp_num);
1327 mlx4_spec->ib.qpn_mask =
1328 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1329 break;
1330
f77c0162
HHZ		 1331
1332 case IB_FLOW_SPEC_IPV4:
1333 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1334 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1335 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1336 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1337 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1338 break;
1339
1340 case IB_FLOW_SPEC_TCP:
1341 case IB_FLOW_SPEC_UDP:
1342 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1343 MLX4_NET_TRANS_RULE_ID_TCP :
1344 MLX4_NET_TRANS_RULE_ID_UDP;
1345 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1346 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1347 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1348 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1349 break;
1350
1351 default:
1352 return -EINVAL;
1353 }
1354 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1355 mlx4_hw_rule_sz(dev, type) < 0)
1356 return -EINVAL;
1357 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1358 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1359 return mlx4_hw_rule_sz(dev, type);
1360}
1361
a37a1a42
MB		 1362struct default_rules {
1363 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1364 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1365 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1366 __u8 link_layer;
1367};
1368static const struct default_rules default_table[] = {
1369 {
1370 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1371 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1372 .rules_create_list = {IB_FLOW_SPEC_IB},
1373 .link_layer = IB_LINK_LAYER_INFINIBAND
1374 }
1375};
1376
1377static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1378 struct ib_flow_attr *flow_attr)
1379{
1380 int i, j, k;
1381 void *ib_flow;
1382 const struct default_rules *pdefault_rules = default_table;
1383 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1384
a57f23f6 1385 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
a37a1a42
MB		 1386 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1387 memset(&field_types, 0, sizeof(field_types));
1388
1389 if (link_layer != pdefault_rules->link_layer)
1390 continue;
1391
1392 ib_flow = flow_attr + 1;
1393 /* we assume the specs are sorted */
1394 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1395 j < flow_attr->num_of_specs; k++) {
1396 union ib_flow_spec *current_flow =
1397 (union ib_flow_spec *)ib_flow;
1398
1399 /* same layer but different type */
1400 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1401 (pdefault_rules->mandatory_fields[k] &
1402 IB_FLOW_SPEC_LAYER_MASK)) &&
1403 (current_flow->type !=
1404 pdefault_rules->mandatory_fields[k]))
1405 goto out;
1406
1407 /* same layer, try match next one */
1408 if (current_flow->type ==
1409 pdefault_rules->mandatory_fields[k]) {
1410 j++;
1411 ib_flow +=
1412 ((union ib_flow_spec *)ib_flow)->size;
1413 }
1414 }
1415
1416 ib_flow = flow_attr + 1;
1417 for (j = 0; j < flow_attr->num_of_specs;
1418 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1419 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1420 /* same layer and same type */
1421 if (((union ib_flow_spec *)ib_flow)->type ==
1422 pdefault_rules->mandatory_not_fields[k])
1423 goto out;
1424
1425 return i;
1426 }
1427out:
1428 return -1;
1429}
1430
1431static int __mlx4_ib_create_default_rules(
1432 struct mlx4_ib_dev *mdev,
1433 struct ib_qp *qp,
1434 const struct default_rules *pdefault_rules,
1435 struct _rule_hw *mlx4_spec) {
1436 int size = 0;
1437 int i;
1438
a57f23f6 1439 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
a37a1a42
MB		 1440 int ret;
1441 union ib_flow_spec ib_spec;
1442 switch (pdefault_rules->rules_create_list[i]) {
1443 case 0:
1444 /* no rule */
1445 continue;
1446 case IB_FLOW_SPEC_IB:
1447 ib_spec.type = IB_FLOW_SPEC_IB;
1448 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1449
1450 break;
1451 default:
1452 /* invalid rule */
1453 return -EINVAL;
1454 }
1455 /* We must put empty rule, qpn is being ignored */
1456 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1457 mlx4_spec);
1458 if (ret < 0) {
1459 pr_info("invalid parsing\n");
1460 return -EINVAL;
1461 }
1462
1463 mlx4_spec = (void *)mlx4_spec + ret;
1464 size += ret;
1465 }
1466 return size;
1467}
1468
f77c0162
HHZ		 1469static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1470 int domain,
1471 enum mlx4_net_trans_promisc_mode flow_type,
1472 u64 *reg_id)
1473{
1474 int ret, i;
1475 int size = 0;
1476 void *ib_flow;
1477 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1478 struct mlx4_cmd_mailbox *mailbox;
1479 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
a37a1a42 1480 int default_flow;
f77c0162
HHZ		 1481
1482 static const u16 __mlx4_domain[] = {
1483 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1484 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1485 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1486 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1487 };
1488
1489 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1490 pr_err("Invalid priority value %d\n", flow_attr->priority);
1491 return -EINVAL;
1492 }
1493
1494 if (domain >= IB_FLOW_DOMAIN_NUM) {
1495 pr_err("Invalid domain value %d\n", domain);
1496 return -EINVAL;
1497 }
1498
1499 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1500 return -EINVAL;
1501
1502 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1503 if (IS_ERR(mailbox))
1504 return PTR_ERR(mailbox);
f77c0162
HHZ		 1505 ctrl = mailbox->buf;
1506
1507 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1508 flow_attr->priority);
1509 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1510 ctrl->port = flow_attr->port;
1511 ctrl->qpn = cpu_to_be32(qp->qp_num);
1512
1513 ib_flow = flow_attr + 1;
1514 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
a37a1a42
MB		 1515 /* Add default flows */
1516 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1517 if (default_flow >= 0) {
1518 ret = __mlx4_ib_create_default_rules(
1519 mdev, qp, default_table + default_flow,
1520 mailbox->buf + size);
1521 if (ret < 0) {
1522 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1523 return -EINVAL;
1524 }
1525 size += ret;
1526 }
f77c0162 1527 for (i = 0; i < flow_attr->num_of_specs; i++) {
a37a1a42
MB		 1528 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1529 mailbox->buf + size);
f77c0162
HHZ		 1530 if (ret < 0) {
1531 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1532 return -EINVAL;
1533 }
1534 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1535 size += ret;
1536 }
1537
1538 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1539 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
48564135 1540 MLX4_CMD_WRAPPED);
f77c0162
HHZ		 1541 if (ret == -ENOMEM)
1542 pr_err("mcg table is full. Fail to register network rule.\n");
1543 else if (ret == -ENXIO)
1544 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1545 else if (ret)
1546 pr_err("Invalid argumant. Fail to register network rule.\n");
1547
1548 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1549 return ret;
1550}
1551
1552static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1553{
1554 int err;
1555 err = mlx4_cmd(dev, reg_id, 0, 0,
1556 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
48564135 1557 MLX4_CMD_WRAPPED);
f77c0162
HHZ		 1558 if (err)
1559 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1560 reg_id);
1561 return err;
1562}
1563
d2fce8a9
OG		 1564static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1565 u64 *reg_id)
1566{
1567 void *ib_flow;
1568 union ib_flow_spec *ib_spec;
1569 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1570 int err = 0;
1571
5eff6dad
OG		 1572 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1573 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
d2fce8a9
OG		 1574 return 0; /* do nothing */
1575
1576 ib_flow = flow_attr + 1;
1577 ib_spec = (union ib_flow_spec *)ib_flow;
1578
1579 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1580 return 0; /* do nothing */
1581
1582 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1583 flow_attr->port, qp->qp_num,
1584 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1585 reg_id);
1586 return err;
1587}
1588
f77c0162
HHZ		 1589static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1590 struct ib_flow_attr *flow_attr,
1591 int domain)
1592{
146d6e19 1593 int err = 0, i = 0, j = 0;
f77c0162
HHZ		 1594 struct mlx4_ib_flow *mflow;
1595 enum mlx4_net_trans_promisc_mode type[2];
146d6e19
MS		 1596 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1597 int is_bonded = mlx4_is_bonded(dev);
f77c0162
HHZ		 1598
1599 memset(type, 0, sizeof(type));
1600
1601 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1602 if (!mflow) {
1603 err = -ENOMEM;
1604 goto err_free;
1605 }
1606
1607 switch (flow_attr->type) {
1608 case IB_FLOW_ATTR_NORMAL:
1609 type[0] = MLX4_FS_REGULAR;
1610 break;
1611
1612 case IB_FLOW_ATTR_ALL_DEFAULT:
1613 type[0] = MLX4_FS_ALL_DEFAULT;
1614 break;
1615
1616 case IB_FLOW_ATTR_MC_DEFAULT:
1617 type[0] = MLX4_FS_MC_DEFAULT;
1618 break;
1619
1620 case IB_FLOW_ATTR_SNIFFER:
1621 type[0] = MLX4_FS_UC_SNIFFER;
1622 type[1] = MLX4_FS_MC_SNIFFER;
1623 break;
1624
1625 default:
1626 err = -EINVAL;
1627 goto err_free;
1628 }
1629
1630 while (i < ARRAY_SIZE(type) && type[i]) {
1631 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
146d6e19 1632 &mflow->reg_id[i].id);
f77c0162 1633 if (err)
571e1b2c 1634 goto err_create_flow;
146d6e19 1635 if (is_bonded) {
824c25c1
MS		 1636 /* Application always sees one port so the mirror rule
1637 * must be on port #2
1638 */
146d6e19
MS		 1639 flow_attr->port = 2;
1640 err = __mlx4_ib_create_flow(qp, flow_attr,
1641 domain, type[j],
1642 &mflow->reg_id[j].mirror);
1643 flow_attr->port = 1;
1644 if (err)
1645 goto err_create_flow;
1646 j++;
1647 }
1648
11562568 1649 i++;
f77c0162
HHZ		 1650 }
1651
d2fce8a9 1652 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
146d6e19
MS		 1653 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1654 &mflow->reg_id[i].id);
d2fce8a9 1655 if (err)
571e1b2c 1656 goto err_create_flow;
11562568 1657
146d6e19
MS		 1658 if (is_bonded) {
1659 flow_attr->port = 2;
1660 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1661 &mflow->reg_id[j].mirror);
1662 flow_attr->port = 1;
1663 if (err)
1664 goto err_create_flow;
1665 j++;
1666 }
1667 /* function to create mirror rule */
11562568 1668 i++;
d2fce8a9
OG		 1669 }
1670
f77c0162
HHZ		 1671 return &mflow->ibflow;
1672
571e1b2c
OG		 1673err_create_flow:
1674 while (i) {
146d6e19
MS		 1675 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1676 mflow->reg_id[i].id);
571e1b2c
OG		 1677 i--;
1678 }
146d6e19
MS		 1679
1680 while (j) {
1681 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1682 mflow->reg_id[j].mirror);
1683 j--;
1684 }
f77c0162
HHZ		 1685err_free:
1686 kfree(mflow);
1687 return ERR_PTR(err);
1688}
1689
1690static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1691{
1692 int err, ret = 0;
1693 int i = 0;
1694 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1695 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1696
146d6e19
MS		 1697 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1698 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
f77c0162
HHZ		 1699 if (err)
1700 ret = err;
146d6e19
MS		 1701 if (mflow->reg_id[i].mirror) {
1702 err = __mlx4_ib_destroy_flow(mdev->dev,
1703 mflow->reg_id[i].mirror);
1704 if (err)
1705 ret = err;
1706 }
f77c0162
HHZ		 1707 i++;
1708 }
1709
1710 kfree(mflow);
1711 return ret;
1712}
1713
225c7b1f
RD		 1714static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1715{
fa417f7b
EC		 1716 int err;
1717 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 1718 struct mlx4_dev *dev = mdev->dev;
fa417f7b 1719 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
0ff1fb65 1720 struct mlx4_ib_steering *ib_steering = NULL;
e9a7faf1 1721 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
146d6e19 1722 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1723
1724 if (mdev->dev->caps.steering_mode ==
1725 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1726 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1727 if (!ib_steering)
1728 return -ENOMEM;
1729 }
fa417f7b 1730
0ff1fb65
HHZ		 1731 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1732 !!(mqp->flags &
1733 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
146d6e19 1734 prot, &reg_id.id);
e9a7faf1
OG		 1735 if (err) {
1736 pr_err("multicast attach op failed, err %d\n", err);
0ff1fb65 1737 goto err_malloc;
e9a7faf1 1738 }
fa417f7b 1739
146d6e19
MS		 1740 reg_id.mirror = 0;
1741 if (mlx4_is_bonded(dev)) {
824c25c1
MS		 1742 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1743 (mqp->port == 1) ? 2 : 1,
146d6e19
MS		 1744 !!(mqp->flags &
1745 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1746 prot, &reg_id.mirror);
1747 if (err)
1748 goto err_add;
1749 }
1750
fa417f7b
EC		 1751 err = add_gid_entry(ibqp, gid);
1752 if (err)
1753 goto err_add;
1754
0ff1fb65
HHZ		 1755 if (ib_steering) {
1756 memcpy(ib_steering->gid.raw, gid->raw, 16);
1757 ib_steering->reg_id = reg_id;
1758 mutex_lock(&mqp->mutex);
1759 list_add(&ib_steering->list, &mqp->steering_rules);
1760 mutex_unlock(&mqp->mutex);
1761 }
fa417f7b
EC		 1762 return 0;
1763
1764err_add:
0ff1fb65 1765 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19
MS		 1766 prot, reg_id.id);
1767 if (reg_id.mirror)
1768 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1769 prot, reg_id.mirror);
0ff1fb65
HHZ		 1770err_malloc:
1771 kfree(ib_steering);
1772
fa417f7b
EC		 1773 return err;
1774}
1775
1776static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1777{
1778 struct mlx4_ib_gid_entry *ge;
1779 struct mlx4_ib_gid_entry *tmp;
1780 struct mlx4_ib_gid_entry *ret = NULL;
1781
1782 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1783 if (!memcmp(raw, ge->gid.raw, 16)) {
1784 ret = ge;
1785 break;
1786 }
1787 }
1788
1789 return ret;
225c7b1f
RD		 1790}
1791
1792static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1793{
fa417f7b
EC		 1794 int err;
1795 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 1796 struct mlx4_dev *dev = mdev->dev;
fa417f7b 1797 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
fa417f7b
EC		 1798 struct net_device *ndev;
1799 struct mlx4_ib_gid_entry *ge;
146d6e19 1800 struct mlx4_flow_reg_id reg_id = {0, 0};
e9a7faf1 1801 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
0ff1fb65
HHZ		 1802
1803 if (mdev->dev->caps.steering_mode ==
1804 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1805 struct mlx4_ib_steering *ib_steering;
1806
1807 mutex_lock(&mqp->mutex);
1808 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
1809 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
1810 list_del(&ib_steering->list);
1811 break;
1812 }
1813 }
1814 mutex_unlock(&mqp->mutex);
1815 if (&ib_steering->list == &mqp->steering_rules) {
1816 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
1817 return -EINVAL;
1818 }
1819 reg_id = ib_steering->reg_id;
1820 kfree(ib_steering);
1821 }
fa417f7b 1822
0ff1fb65 1823 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19 1824 prot, reg_id.id);
fa417f7b
EC		 1825 if (err)
1826 return err;
1827
146d6e19
MS		 1828 if (mlx4_is_bonded(dev)) {
1829 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1830 prot, reg_id.mirror);
1831 if (err)
1832 return err;
1833 }
1834
fa417f7b
EC		 1835 mutex_lock(&mqp->mutex);
1836 ge = find_gid_entry(mqp, gid->raw);
1837 if (ge) {
dba3ad2a 1838 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1839 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
1840 if (ndev)
1841 dev_hold(ndev);
dba3ad2a 1842 spin_unlock_bh(&mdev->iboe.lock);
d487ee77 1843 if (ndev)
fa417f7b 1844 dev_put(ndev);
fa417f7b
EC		 1845 list_del(&ge->list);
1846 kfree(ge);
1847 } else
987c8f8f 1848 pr_warn("could not find mgid entry\n");
fa417f7b
EC		 1849
1850 mutex_unlock(&mqp->mutex);
1851
1852 return 0;
225c7b1f
RD		 1853}
1854
1855static int init_node_data(struct mlx4_ib_dev *dev)
1856{
1857 struct ib_smp *in_mad = NULL;
1858 struct ib_smp *out_mad = NULL;
0a9a0188 1859 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 1860 int err = -ENOMEM;
1861
1862 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
1863 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1864 if (!in_mad || !out_mad)
1865 goto out;
1866
1867 init_query_mad(in_mad);
1868 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
0a9a0188
JM		 1869 if (mlx4_is_master(dev->dev))
1870 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
225c7b1f 1871
0a9a0188 1872 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 1873 if (err)
1874 goto out;
1875
1876 memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
1877
1878 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
1879
0a9a0188 1880 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 1881 if (err)
1882 goto out;
1883
992e8e6e 1884 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
225c7b1f
RD		 1885 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
1886
1887out:
1888 kfree(in_mad);
1889 kfree(out_mad);
1890 return err;
1891}
1892
f4e91eb4
TJ		 1893static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1894 char *buf)
cd9281d8 1895{
f4e91eb4
TJ		 1896 struct mlx4_ib_dev *dev =
1897 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
872bf2fb 1898 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
cd9281d8
JM		 1899}
1900
f4e91eb4
TJ		 1901static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1902 char *buf)
cd9281d8 1903{
f4e91eb4
TJ		 1904 struct mlx4_ib_dev *dev =
1905 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1906 return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
1907 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
1908 (int) dev->dev->caps.fw_ver & 0xffff);
1909}
1910
f4e91eb4
TJ		 1911static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1912 char *buf)
cd9281d8 1913{
f4e91eb4
TJ		 1914 struct mlx4_ib_dev *dev =
1915 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1916 return sprintf(buf, "%x\n", dev->dev->rev_id);
1917}
1918
f4e91eb4
TJ		 1919static ssize_t show_board(struct device *device, struct device_attribute *attr,
1920 char *buf)
cd9281d8 1921{
f4e91eb4
TJ		 1922 struct mlx4_ib_dev *dev =
1923 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
1924 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
1925 dev->dev->board_id);
cd9281d8
JM		 1926}
1927
f4e91eb4
TJ		 1928static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1929static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1930static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1931static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
cd9281d8 1932
f4e91eb4
TJ		 1933static struct device_attribute *mlx4_class_attributes[] = {
1934 &dev_attr_hw_rev,
1935 &dev_attr_fw_ver,
1936 &dev_attr_hca_type,
1937 &dev_attr_board_id
cd9281d8
JM		 1938};
1939
9433c188
MB		 1940#define MLX4_IB_INVALID_MAC ((u64)-1)
1941static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
1942 struct net_device *dev,
1943 int port)
1944{
1945 u64 new_smac = 0;
1946 u64 release_mac = MLX4_IB_INVALID_MAC;
1947 struct mlx4_ib_qp *qp;
1948
1949 read_lock(&dev_base_lock);
1950 new_smac = mlx4_mac_to_u64(dev->dev_addr);
1951 read_unlock(&dev_base_lock);
1952
3e0629cb
JM		 1953 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
1954
d24d9f43
JM		 1955 /* no need for update QP1 and mac registration in non-SRIOV */
1956 if (!mlx4_is_mfunc(ibdev->dev))
1957 return;
1958
9433c188
MB		 1959 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
1960 qp = ibdev->qp1_proxy[port - 1];
1961 if (qp) {
1962 int new_smac_index;
25476b02 1963 u64 old_smac;
9433c188
MB		 1964 struct mlx4_update_qp_params update_params;
1965
25476b02
JM		 1966 mutex_lock(&qp->mutex);
1967 old_smac = qp->pri.smac;
9433c188
MB		 1968 if (new_smac == old_smac)
1969 goto unlock;
1970
1971 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
1972
1973 if (new_smac_index < 0)
1974 goto unlock;
1975
1976 update_params.smac_index = new_smac_index;
09e05c3f 1977 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
9433c188
MB		 1978 &update_params)) {
1979 release_mac = new_smac;
1980 goto unlock;
1981 }
25476b02
JM		 1982 /* if old port was zero, no mac was yet registered for this QP */
1983 if (qp->pri.smac_port)
1984 release_mac = old_smac;
9433c188 1985 qp->pri.smac = new_smac;
25476b02 1986 qp->pri.smac_port = port;
9433c188 1987 qp->pri.smac_index = new_smac_index;
9433c188
MB		 1988 }
1989
1990unlock:
9433c188
MB		 1991 if (release_mac != MLX4_IB_INVALID_MAC)
1992 mlx4_unregister_mac(ibdev->dev, port, release_mac);
25476b02
JM		 1993 if (qp)
1994 mutex_unlock(&qp->mutex);
1995 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
9433c188
MB		 1996}
1997
9433c188
MB		 1998static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
1999 struct net_device *dev,
2000 unsigned long event)
2001
d487ee77 2002{
fa417f7b 2003 struct mlx4_ib_iboe *iboe;
9433c188 2004 int update_qps_port = -1;
fa417f7b
EC		 2005 int port;
2006
5070cd22
MS		 2007 ASSERT_RTNL();
2008
fa417f7b
EC		 2009 iboe = &ibdev->iboe;
2010
dba3ad2a 2011 spin_lock_bh(&iboe->lock);
fa417f7b 2012 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
ad4885d2 2013
fa417f7b 2014 iboe->netdevs[port - 1] =
0345584e 2015 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
fa417f7b 2016
9433c188
MB		 2017 if (dev == iboe->netdevs[port - 1] &&
2018 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2019 event == NETDEV_UP || event == NETDEV_CHANGE))
2020 update_qps_port = port;
2021
d487ee77 2022 }
dba3ad2a 2023 spin_unlock_bh(&iboe->lock);
9433c188
MB		 2024
2025 if (update_qps_port > 0)
2026 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
d487ee77
MS		 2027}
2028
2029static int mlx4_ib_netdev_event(struct notifier_block *this,
2030 unsigned long event, void *ptr)
2031{
2032 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2033 struct mlx4_ib_dev *ibdev;
2034
2035 if (!net_eq(dev_net(dev), &init_net))
2036 return NOTIFY_DONE;
2037
2038 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
9433c188 2039 mlx4_ib_scan_netdevs(ibdev, dev, event);
fa417f7b
EC		 2040
2041 return NOTIFY_DONE;
2042}
2043
54679e14
JM		 2044static void init_pkeys(struct mlx4_ib_dev *ibdev)
2045{
2046 int port;
2047 int slave;
2048 int i;
2049
2050 if (mlx4_is_master(ibdev->dev)) {
872bf2fb
YH		 2051 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2052 ++slave) {
54679e14
JM		 2053 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2054 for (i = 0;
2055 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2056 ++i) {
2057 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2058 /* master has the identity virt2phys pkey mapping */
2059 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2060 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2061 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2062 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2063 }
2064 }
2065 }
2066 /* initialize pkey cache */
2067 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2068 for (i = 0;
2069 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2070 ++i)
2071 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2072 (i) ? 0 : 0xFFFF;
2073 }
2074 }
2075}
2076
e605b743
SP		 2077static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2078{
c66fa19c 2079 int i, j, eq = 0, total_eqs = 0;
e605b743 2080
c66fa19c
MB		 2081 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2082 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
e605b743
SP		 2083 if (!ibdev->eq_table)
2084 return;
2085
c66fa19c
MB		 2086 for (i = 1; i <= dev->caps.num_ports; i++) {
2087 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2088 j++, total_eqs++) {
2089 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2090 continue;
2091 ibdev->eq_table[eq] = total_eqs;
2092 if (!mlx4_assign_eq(dev, i,
2093 &ibdev->eq_table[eq]))
2094 eq++;
2095 else
2096 ibdev->eq_table[eq] = -1;
e605b743
SP		 2097 }
2098 }
2099
c66fa19c
MB		 2100 for (i = eq; i < dev->caps.num_comp_vectors;
2101 ibdev->eq_table[i++] = -1)
2102 ;
e605b743
SP		 2103
2104 /* Advertise the new number of EQs to clients */
c66fa19c 2105 ibdev->ib_dev.num_comp_vectors = eq;
e605b743
SP		 2106}
2107
2108static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2109{
2110 int i;
c66fa19c 2111 int total_eqs = ibdev->ib_dev.num_comp_vectors;
3aac6ff1 2112
c66fa19c 2113 /* no eqs were allocated */
3aac6ff1
SP		 2114 if (!ibdev->eq_table)
2115 return;
e605b743
SP		 2116
2117 /* Reset the advertised EQ number */
c66fa19c 2118 ibdev->ib_dev.num_comp_vectors = 0;
e605b743 2119
c66fa19c 2120 for (i = 0; i < total_eqs; i++)
e605b743 2121 mlx4_release_eq(dev, ibdev->eq_table[i]);
e605b743 2122
e605b743 2123 kfree(ibdev->eq_table);
c66fa19c 2124 ibdev->eq_table = NULL;
e605b743
SP		 2125}
2126
7738613e
IW		 2127static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2128 struct ib_port_immutable *immutable)
2129{
2130 struct ib_port_attr attr;
2131 int err;
2132
2133 err = mlx4_ib_query_port(ibdev, port_num, &attr);
2134 if (err)
2135 return err;
2136
2137 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2138 immutable->gid_tbl_len = attr.gid_tbl_len;
2139
f9b22e35
IW		 2140 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND)
2141 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2142 else
2143 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2144
337877a4
IW		 2145 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2146
7738613e
IW		 2147 return 0;
2148}
2149
225c7b1f
RD		 2150static void *mlx4_ib_add(struct mlx4_dev *dev)
2151{
2152 struct mlx4_ib_dev *ibdev;
22e7ef9c 2153 int num_ports = 0;
035b1032 2154 int i, j;
fa417f7b
EC		 2155 int err;
2156 struct mlx4_ib_iboe *iboe;
4196670b 2157 int ib_num_ports = 0;
a5750090 2158 int num_req_counters;
c3abb51b
EBE		 2159 int allocated;
2160 u32 counter_index;
3ba8e31d 2161 struct counter_index *new_counter_index = NULL;
225c7b1f 2162
987c8f8f 2163 pr_info_once("%s", mlx4_ib_version);
68f3948d 2164
026149cb 2165 num_ports = 0;
fa417f7b 2166 mlx4_foreach_ib_transport_port(i, dev)
22e7ef9c
RD		 2167 num_ports++;
2168
2169 /* No point in registering a device with no ports... */
2170 if (num_ports == 0)
2171 return NULL;
2172
225c7b1f
RD		 2173 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2174 if (!ibdev) {
872bf2fb
YH		 2175 dev_err(&dev->persist->pdev->dev,
2176 "Device struct alloc failed\n");
225c7b1f
RD		 2177 return NULL;
2178 }
2179
fa417f7b
EC		 2180 iboe = &ibdev->iboe;
2181
225c7b1f
RD		 2182 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2183 goto err_dealloc;
2184
2185 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2186 goto err_pd;
2187
4979d18f
RD		 2188 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2189 PAGE_SIZE);
225c7b1f
RD		 2190 if (!ibdev->uar_map)
2191 goto err_uar;
26c6bc7b 2192 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
225c7b1f 2193
225c7b1f 2194 ibdev->dev = dev;
c6215745 2195 ibdev->bond_next_port = 0;
225c7b1f
RD		 2196
2197 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2198 ibdev->ib_dev.owner = THIS_MODULE;
2199 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
95d04f07 2200 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
22e7ef9c 2201 ibdev->num_ports = num_ports;
a5750090
MS		 2202 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2203 1 : ibdev->num_ports;
b8dd786f 2204 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
872bf2fb 2205 ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
5070cd22
MS		 2206 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2207 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2208 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
225c7b1f 2209
08ff3235
OG		 2210 if (dev->caps.userspace_caps)
2211 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2212 else
2213 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2214
225c7b1f
RD		 2215 ibdev->ib_dev.uverbs_cmd_mask =
2216 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2217 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2218 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2219 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2220 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2221 (1ull << IB_USER_VERBS_CMD_REG_MR) |
9376932d 2222 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
225c7b1f
RD		 2223 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2224 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2225 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
bbf8eed1 2226 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
225c7b1f
RD		 2227 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2228 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2229 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6a775e2b 2230 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
225c7b1f
RD		 2231 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2232 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2233 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2234 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2235 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
65541cb7 2236 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
18abd5ea 2237 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
42849b26
SH		 2238 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2239 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
225c7b1f
RD		 2240
2241 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2242 ibdev->ib_dev.query_port = mlx4_ib_query_port;
fa417f7b 2243 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
225c7b1f
RD		 2244 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2245 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2246 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2247 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2248 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2249 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2250 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2251 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2252 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2253 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2254 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2255 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2256 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2257 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
65541cb7 2258 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
225c7b1f
RD		 2259 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2260 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2261 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2262 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
6a775e2b 2263 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
225c7b1f
RD		 2264 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2265 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2266 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2267 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
3fdcb97f 2268 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
bbf8eed1 2269 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
225c7b1f
RD		 2270 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2271 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2272 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2273 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2274 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
9376932d 2275 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
225c7b1f 2276 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
679e34d1 2277 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
1b2cd0fc 2278 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
225c7b1f
RD		 2279 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2280 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2281 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
7738613e 2282 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
ae184dde 2283 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
225c7b1f 2284
992e8e6e
JM		 2285 if (!mlx4_is_slave(ibdev->dev)) {
2286 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2287 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2288 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2289 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2290 }
8ad11fb6 2291
b425388d
SM		 2292 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2293 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2294 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
b425388d
SM		 2295 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2296
2297 ibdev->ib_dev.uverbs_cmd_mask |=
2298 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2299 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2300 }
2301
012a8ff5
SH		 2302 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2303 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2304 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2305 ibdev->ib_dev.uverbs_cmd_mask |=
2306 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2307 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2308 }
2309
f77c0162 2310 if (check_flow_steering_support(dev)) {
0a9b7d59 2311 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
f77c0162
HHZ		 2312 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2313 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2314
f21519b2
YD		 2315 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2316 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2317 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
f77c0162
HHZ		 2318 }
2319
4b664c43
MB		 2320 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2321 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
fbfb6625
EBE		 2322 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2323 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
4b664c43 2324
e605b743
SP		 2325 mlx4_ib_alloc_eqs(dev, ibdev);
2326
fa417f7b
EC		 2327 spin_lock_init(&iboe->lock);
2328
225c7b1f
RD		 2329 if (init_node_data(ibdev))
2330 goto err_map;
2331
3ba8e31d
EBE		 2332 for (i = 0; i < ibdev->num_ports; ++i) {
2333 mutex_init(&ibdev->counters_table[i].mutex);
2334 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2335 }
2336
a5750090
MS		 2337 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2338 for (i = 0; i < num_req_counters; ++i) {
9433c188 2339 mutex_init(&ibdev->qp1_proxy_lock[i]);
c3abb51b 2340 allocated = 0;
cfcde11c
OG		 2341 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2342 IB_LINK_LAYER_ETHERNET) {
c3abb51b
EBE		 2343 err = mlx4_counter_alloc(ibdev->dev, &counter_index);
2344 /* if failed to allocate a new counter, use default */
cfcde11c 2345 if (err)
c3abb51b
EBE		 2346 counter_index =
2347 mlx4_get_default_counter_index(dev,
2348 i + 1);
2349 else
2350 allocated = 1;
2351 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2352 counter_index = mlx4_get_default_counter_index(dev,
2353 i + 1);
3839d8ac 2354 }
3ba8e31d
EBE		 2355 new_counter_index = kmalloc(sizeof(*new_counter_index),
2356 GFP_KERNEL);
2357 if (!new_counter_index) {
2358 if (allocated)
2359 mlx4_counter_free(ibdev->dev, counter_index);
2360 goto err_counter;
2361 }
2362 new_counter_index->index = counter_index;
2363 new_counter_index->allocated = allocated;
2364 list_add_tail(&new_counter_index->list,
2365 &ibdev->counters_table[i].counters_list);
2366 ibdev->counters_table[i].default_counter = counter_index;
c3abb51b
EBE		 2367 pr_info("counter index %d for port %d allocated %d\n",
2368 counter_index, i + 1, allocated);
cfcde11c 2369 }
a5750090 2370 if (mlx4_is_bonded(dev))
c3abb51b 2371 for (i = 1; i < ibdev->num_ports ; ++i) {
3ba8e31d
EBE		 2372 new_counter_index =
2373 kmalloc(sizeof(struct counter_index),
2374 GFP_KERNEL);
2375 if (!new_counter_index)
2376 goto err_counter;
2377 new_counter_index->index = counter_index;
2378 new_counter_index->allocated = 0;
2379 list_add_tail(&new_counter_index->list,
2380 &ibdev->counters_table[i].counters_list);
2381 ibdev->counters_table[i].default_counter =
2382 counter_index;
c3abb51b 2383 }
cfcde11c 2384
4196670b
MB		 2385 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2386 ib_num_ports++;
2387
225c7b1f
RD		 2388 spin_lock_init(&ibdev->sm_lock);
2389 mutex_init(&ibdev->cap_mask_mutex);
35f05dab
YH		 2390 INIT_LIST_HEAD(&ibdev->qp_list);
2391 spin_lock_init(&ibdev->reset_flow_resource_lock);
225c7b1f 2392
4196670b
MB		 2393 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2394 ib_num_ports) {
c1c98501
MB		 2395 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2396 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2397 MLX4_IB_UC_STEER_QPN_ALIGN,
ddae0349 2398 &ibdev->steer_qpn_base, 0);
c1c98501
MB		 2399 if (err)
2400 goto err_counter;
2401
2402 ibdev->ib_uc_qpns_bitmap =
2403 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2404 sizeof(long),
2405 GFP_KERNEL);
2406 if (!ibdev->ib_uc_qpns_bitmap) {
872bf2fb
YH		 2407 dev_err(&dev->persist->pdev->dev,
2408 "bit map alloc failed\n");
c1c98501
MB		 2409 goto err_steer_qp_release;
2410 }
2411
2412 bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
2413
2414 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2415 dev, ibdev->steer_qpn_base,
2416 ibdev->steer_qpn_base +
2417 ibdev->steer_qpn_count - 1);
2418 if (err)
2419 goto err_steer_free_bitmap;
2420 }
2421
3e0629cb
JM		 2422 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2423 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2424
9a6edb60 2425 if (ib_register_device(&ibdev->ib_dev, NULL))
c1c98501 2426 goto err_steer_free_bitmap;
225c7b1f
RD		 2427
2428 if (mlx4_ib_mad_init(ibdev))
2429 goto err_reg;
2430
fc06573d
JM		 2431 if (mlx4_ib_init_sriov(ibdev))
2432 goto err_mad;
2433
d487ee77
MS		 2434 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) {
2435 if (!iboe->nb.notifier_call) {
2436 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2437 err = register_netdevice_notifier(&iboe->nb);
2438 if (err) {
2439 iboe->nb.notifier_call = NULL;
2440 goto err_notif;
2441 }
2442 }
fa417f7b
EC		 2443 }
2444
035b1032 2445 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
f4e91eb4 2446 if (device_create_file(&ibdev->ib_dev.dev,
035b1032 2447 mlx4_class_attributes[j]))
fa417f7b 2448 goto err_notif;
cd9281d8
JM		 2449 }
2450
3b4a8cd5
JM		 2451 ibdev->ib_active = true;
2452
54679e14
JM		 2453 if (mlx4_is_mfunc(ibdev->dev))
2454 init_pkeys(ibdev);
2455
3806d08c
JM		 2456 /* create paravirt contexts for any VFs which are active */
2457 if (mlx4_is_master(ibdev->dev)) {
2458 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2459 if (j == mlx4_master_func_num(ibdev->dev))
2460 continue;
2461 if (mlx4_is_slave_active(ibdev->dev, j))
2462 do_slave_init(ibdev, j, 1);
2463 }
2464 }
225c7b1f
RD		 2465 return ibdev;
2466
fa417f7b 2467err_notif:
d487ee77
MS		 2468 if (ibdev->iboe.nb.notifier_call) {
2469 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2470 pr_warn("failure unregistering notifier\n");
2471 ibdev->iboe.nb.notifier_call = NULL;
2472 }
fa417f7b
EC		 2473 flush_workqueue(wq);
2474
fc06573d
JM		 2475 mlx4_ib_close_sriov(ibdev);
2476
2477err_mad:
2478 mlx4_ib_mad_cleanup(ibdev);
2479
225c7b1f
RD		 2480err_reg:
2481 ib_unregister_device(&ibdev->ib_dev);
2482
c1c98501
MB		 2483err_steer_free_bitmap:
2484 kfree(ibdev->ib_uc_qpns_bitmap);
2485
2486err_steer_qp_release:
2487 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2488 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2489 ibdev->steer_qpn_count);
cfcde11c 2490err_counter:
3ba8e31d
EBE		 2491 for (i = 0; i < ibdev->num_ports; ++i)
2492 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2493
225c7b1f
RD		 2494err_map:
2495 iounmap(ibdev->uar_map);
2496
2497err_uar:
2498 mlx4_uar_free(dev, &ibdev->priv_uar);
2499
2500err_pd:
2501 mlx4_pd_free(dev, ibdev->priv_pdn);
2502
2503err_dealloc:
2504 ib_dealloc_device(&ibdev->ib_dev);
2505
2506 return NULL;
2507}
2508
c1c98501
MB		 2509int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2510{
2511 int offset;
2512
2513 WARN_ON(!dev->ib_uc_qpns_bitmap);
2514
2515 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2516 dev->steer_qpn_count,
2517 get_count_order(count));
2518 if (offset < 0)
2519 return offset;
2520
2521 *qpn = dev->steer_qpn_base + offset;
2522 return 0;
2523}
2524
2525void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2526{
2527 if (!qpn ||
2528 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2529 return;
2530
2531 BUG_ON(qpn < dev->steer_qpn_base);
2532
2533 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2534 qpn - dev->steer_qpn_base,
2535 get_count_order(count));
2536}
2537
2538int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2539 int is_attach)
2540{
2541 int err;
2542 size_t flow_size;
2543 struct ib_flow_attr *flow = NULL;
2544 struct ib_flow_spec_ib *ib_spec;
2545
2546 if (is_attach) {
2547 flow_size = sizeof(struct ib_flow_attr) +
2548 sizeof(struct ib_flow_spec_ib);
2549 flow = kzalloc(flow_size, GFP_KERNEL);
2550 if (!flow)
2551 return -ENOMEM;
2552 flow->port = mqp->port;
2553 flow->num_of_specs = 1;
2554 flow->size = flow_size;
2555 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2556 ib_spec->type = IB_FLOW_SPEC_IB;
2557 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2558 /* Add an empty rule for IB L2 */
2559 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2560
2561 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
2562 IB_FLOW_DOMAIN_NIC,
2563 MLX4_FS_REGULAR,
2564 &mqp->reg_id);
2565 } else {
2566 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
2567 }
2568 kfree(flow);
2569 return err;
2570}
2571
225c7b1f
RD		 2572static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
2573{
2574 struct mlx4_ib_dev *ibdev = ibdev_ptr;
2575 int p;
2576
4bf9715f
MS		 2577 ibdev->ib_active = false;
2578 flush_workqueue(wq);
2579
fc06573d 2580 mlx4_ib_close_sriov(ibdev);
a6a47771
YP		 2581 mlx4_ib_mad_cleanup(ibdev);
2582 ib_unregister_device(&ibdev->ib_dev);
fa417f7b
EC		 2583 if (ibdev->iboe.nb.notifier_call) {
2584 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
987c8f8f 2585 pr_warn("failure unregistering notifier\n");
fa417f7b
EC		 2586 ibdev->iboe.nb.notifier_call = NULL;
2587 }
c1c98501
MB		 2588
2589 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
2590 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2591 ibdev->steer_qpn_count);
2592 kfree(ibdev->ib_uc_qpns_bitmap);
2593 }
2594
fa417f7b 2595 iounmap(ibdev->uar_map);
cfcde11c 2596 for (p = 0; p < ibdev->num_ports; ++p)
3ba8e31d
EBE		 2597 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
2598
fa417f7b 2599 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
225c7b1f
RD		 2600 mlx4_CLOSE_PORT(dev, p);
2601
e605b743
SP		 2602 mlx4_ib_free_eqs(dev, ibdev);
2603
225c7b1f
RD		 2604 mlx4_uar_free(dev, &ibdev->priv_uar);
2605 mlx4_pd_free(dev, ibdev->priv_pdn);
2606 ib_dealloc_device(&ibdev->ib_dev);
2607}
2608
fc06573d
JM		 2609static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
2610{
2611 struct mlx4_ib_demux_work **dm = NULL;
2612 struct mlx4_dev *dev = ibdev->dev;
2613 int i;
2614 unsigned long flags;
449fc488
MB		 2615 struct mlx4_active_ports actv_ports;
2616 unsigned int ports;
2617 unsigned int first_port;
fc06573d
JM		 2618
2619 if (!mlx4_is_master(dev))
2620 return;
2621
449fc488
MB		 2622 actv_ports = mlx4_get_active_ports(dev, slave);
2623 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2624 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2625
2626 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
fc06573d
JM		 2627 if (!dm) {
2628 pr_err("failed to allocate memory for tunneling qp update\n");
a39a98ff 2629 return;
fc06573d
JM		 2630 }
2631
449fc488 2632 for (i = 0; i < ports; i++) {
fc06573d
JM		 2633 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
2634 if (!dm[i]) {
2635 pr_err("failed to allocate memory for tunneling qp update work struct\n");
a39a98ff
MS		 2636 while (--i >= 0)
2637 kfree(dm[i]);
fc06573d
JM		 2638 goto out;
2639 }
fc06573d 2640 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
449fc488 2641 dm[i]->port = first_port + i + 1;
fc06573d
JM		 2642 dm[i]->slave = slave;
2643 dm[i]->do_init = do_init;
2644 dm[i]->dev = ibdev;
d9a047ae
DL		 2645 }
2646 /* initialize or tear down tunnel QPs for the slave */
2647 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
2648 if (!ibdev->sriov.is_going_down) {
2649 for (i = 0; i < ports; i++)
fc06573d
JM		 2650 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
2651 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
d9a047ae
DL		 2652 } else {
2653 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
2654 for (i = 0; i < ports; i++)
2655 kfree(dm[i]);
fc06573d
JM		 2656 }
2657out:
c89d1271 2658 kfree(dm);
fc06573d
JM		 2659 return;
2660}
2661
35f05dab
YH		 2662static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
2663{
2664 struct mlx4_ib_qp *mqp;
2665 unsigned long flags_qp;
2666 unsigned long flags_cq;
2667 struct mlx4_ib_cq *send_mcq, *recv_mcq;
2668 struct list_head cq_notify_list;
2669 struct mlx4_cq *mcq;
2670 unsigned long flags;
2671
2672 pr_warn("mlx4_ib_handle_catas_error was started\n");
2673 INIT_LIST_HEAD(&cq_notify_list);
2674
2675 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2676 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2677
2678 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2679 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2680 if (mqp->sq.tail != mqp->sq.head) {
2681 send_mcq = to_mcq(mqp->ibqp.send_cq);
2682 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2683 if (send_mcq->mcq.comp &&
2684 mqp->ibqp.send_cq->comp_handler) {
2685 if (!send_mcq->mcq.reset_notify_added) {
2686 send_mcq->mcq.reset_notify_added = 1;
2687 list_add_tail(&send_mcq->mcq.reset_notify,
2688 &cq_notify_list);
2689 }
2690 }
2691 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2692 }
2693 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2694 /* Now, handle the QP's receive queue */
2695 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2696 /* no handling is needed for SRQ */
2697 if (!mqp->ibqp.srq) {
2698 if (mqp->rq.tail != mqp->rq.head) {
2699 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2700 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2701 if (recv_mcq->mcq.comp &&
2702 mqp->ibqp.recv_cq->comp_handler) {
2703 if (!recv_mcq->mcq.reset_notify_added) {
2704 recv_mcq->mcq.reset_notify_added = 1;
2705 list_add_tail(&recv_mcq->mcq.reset_notify,
2706 &cq_notify_list);
2707 }
2708 }
2709 spin_unlock_irqrestore(&recv_mcq->lock,
2710 flags_cq);
2711 }
2712 }
2713 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2714 }
2715
2716 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
2717 mcq->comp(mcq);
2718 }
2719 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2720 pr_warn("mlx4_ib_handle_catas_error ended\n");
2721}
2722
a5750090
MS		 2723static void handle_bonded_port_state_event(struct work_struct *work)
2724{
2725 struct ib_event_work *ew =
2726 container_of(work, struct ib_event_work, work);
2727 struct mlx4_ib_dev *ibdev = ew->ib_dev;
2728 enum ib_port_state bonded_port_state = IB_PORT_NOP;
2729 int i;
2730 struct ib_event ibev;
2731
2732 kfree(ew);
2733 spin_lock_bh(&ibdev->iboe.lock);
2734 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
2735 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
217e8b16 2736 enum ib_port_state curr_port_state;
a5750090 2737
217e8b16
MS		 2738 if (!curr_netdev)
2739 continue;
2740
2741 curr_port_state =
a5750090
MS		 2742 (netif_running(curr_netdev) &&
2743 netif_carrier_ok(curr_netdev)) ?
2744 IB_PORT_ACTIVE : IB_PORT_DOWN;
2745
2746 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
2747 curr_port_state : IB_PORT_ACTIVE;
2748 }
2749 spin_unlock_bh(&ibdev->iboe.lock);
2750
2751 ibev.device = &ibdev->ib_dev;
2752 ibev.element.port_num = 1;
2753 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
2754 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2755
2756 ib_dispatch_event(&ibev);
2757}
2758
225c7b1f 2759static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
00f5ce99 2760 enum mlx4_dev_event event, unsigned long param)
225c7b1f
RD		 2761{
2762 struct ib_event ibev;
7ff93f8b 2763 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
00f5ce99
JM		 2764 struct mlx4_eqe *eqe = NULL;
2765 struct ib_event_work *ew;
fc06573d 2766 int p = 0;
00f5ce99 2767
a5750090
MS		 2768 if (mlx4_is_bonded(dev) &&
2769 ((event == MLX4_DEV_EVENT_PORT_UP) ||
2770 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
2771 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
2772 if (!ew)
2773 return;
2774 INIT_WORK(&ew->work, handle_bonded_port_state_event);
2775 ew->ib_dev = ibdev;
2776 queue_work(wq, &ew->work);
2777 return;
2778 }
2779
00f5ce99
JM		 2780 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
2781 eqe = (struct mlx4_eqe *)param;
2782 else
fc06573d 2783 p = (int) param;
225c7b1f
RD		 2784
2785 switch (event) {
37608eea 2786 case MLX4_DEV_EVENT_PORT_UP:
fc06573d
JM		 2787 if (p > ibdev->num_ports)
2788 return;
a0c64a17
JM		 2789 if (mlx4_is_master(dev) &&
2790 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
2791 IB_LINK_LAYER_INFINIBAND) {
2792 mlx4_ib_invalidate_all_guid_record(ibdev, p);
2793 }
37608eea 2794 ibev.event = IB_EVENT_PORT_ACTIVE;
225c7b1f
RD		 2795 break;
2796
37608eea 2797 case MLX4_DEV_EVENT_PORT_DOWN:
fc06573d
JM		 2798 if (p > ibdev->num_ports)
2799 return;
37608eea
RD		 2800 ibev.event = IB_EVENT_PORT_ERR;
2801 break;
2802
2803 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3b4a8cd5 2804 ibdev->ib_active = false;
225c7b1f 2805 ibev.event = IB_EVENT_DEVICE_FATAL;
35f05dab 2806 mlx4_ib_handle_catas_error(ibdev);
225c7b1f
RD		 2807 break;
2808
00f5ce99
JM		 2809 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
2810 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
2811 if (!ew) {
2812 pr_err("failed to allocate memory for events work\n");
2813 break;
2814 }
2815
2816 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
2817 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
2818 ew->ib_dev = ibdev;
992e8e6e
JM		 2819 /* need to queue only for port owner, which uses GEN_EQE */
2820 if (mlx4_is_master(dev))
2821 queue_work(wq, &ew->work);
2822 else
2823 handle_port_mgmt_change_event(&ew->work);
00f5ce99
JM		 2824 return;
2825
fc06573d
JM		 2826 case MLX4_DEV_EVENT_SLAVE_INIT:
2827 /* here, p is the slave id */
2828 do_slave_init(ibdev, p, 1);
ee59fa0d
YH		 2829 if (mlx4_is_master(dev)) {
2830 int i;
2831
2832 for (i = 1; i <= ibdev->num_ports; i++) {
2833 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
2834 == IB_LINK_LAYER_INFINIBAND)
2835 mlx4_ib_slave_alias_guid_event(ibdev,
2836 p, i,
2837 1);
2838 }
2839 }
fc06573d
JM		 2840 return;
2841
2842 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
ee59fa0d
YH		 2843 if (mlx4_is_master(dev)) {
2844 int i;
2845
2846 for (i = 1; i <= ibdev->num_ports; i++) {
2847 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
2848 == IB_LINK_LAYER_INFINIBAND)
2849 mlx4_ib_slave_alias_guid_event(ibdev,
2850 p, i,
2851 0);
2852 }
2853 }
fc06573d
JM		 2854 /* here, p is the slave id */
2855 do_slave_init(ibdev, p, 0);
2856 return;
2857
225c7b1f
RD		 2858 default:
2859 return;
2860 }
2861
2862 ibev.device = ibdev_ptr;
a5750090 2863 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
225c7b1f
RD		 2864
2865 ib_dispatch_event(&ibev);
2866}
2867
2868static struct mlx4_interface mlx4_ib_interface = {
fa417f7b
EC		 2869 .add = mlx4_ib_add,
2870 .remove = mlx4_ib_remove,
2871 .event = mlx4_ib_event,
a5750090
MS		 2872 .protocol = MLX4_PROT_IB_IPV6,
2873 .flags = MLX4_INTFF_BONDING
225c7b1f
RD		 2874};
2875
2876static int __init mlx4_ib_init(void)
2877{
fa417f7b
EC		 2878 int err;
2879
2880 wq = create_singlethread_workqueue("mlx4_ib");
2881 if (!wq)
2882 return -ENOMEM;
2883
b9c5d6a6
OD		 2884 err = mlx4_ib_mcg_init();
2885 if (err)
2886 goto clean_wq;
2887
fa417f7b 2888 err = mlx4_register_interface(&mlx4_ib_interface);
b9c5d6a6
OD		 2889 if (err)
2890 goto clean_mcg;
fa417f7b
EC		 2891
2892 return 0;
b9c5d6a6
OD		 2893
2894clean_mcg:
2895 mlx4_ib_mcg_destroy();
2896
2897clean_wq:
2898 destroy_workqueue(wq);
2899 return err;
225c7b1f
RD		 2900}
2901
2902static void __exit mlx4_ib_cleanup(void)
2903{
2904 mlx4_unregister_interface(&mlx4_ib_interface);
b9c5d6a6 2905 mlx4_ib_mcg_destroy();
fa417f7b 2906 destroy_workqueue(wq);
225c7b1f
RD		 2907}
2908
2909module_init(mlx4_ib_init);
2910module_exit(mlx4_ib_cleanup);
Linux kernel - Deliverables
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