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net/mlx4: Postpone the registration of net_device
[deliverable/linux.git] / drivers / infiniband / hw / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/module.h>
35#include <linux/init.h>
5a0e3ad6 36#include <linux/slab.h>
225c7b1f 37#include <linux/errno.h>
fa417f7b
EC		 38#include <linux/netdevice.h>
39#include <linux/inetdevice.h>
40#include <linux/rtnetlink.h>
4c3eb3ca 41#include <linux/if_vlan.h>
d487ee77
MS		 42#include <net/ipv6.h>
43#include <net/addrconf.h>
225c7b1f
RD		 44
45#include <rdma/ib_smi.h>
46#include <rdma/ib_user_verbs.h>
fa417f7b 47#include <rdma/ib_addr.h>
225c7b1f
RD		 48
49#include <linux/mlx4/driver.h>
50#include <linux/mlx4/cmd.h>
9433c188 51#include <linux/mlx4/qp.h>
225c7b1f
RD		 52
53#include "mlx4_ib.h"
54#include "user.h"
55
b1d8eb5a 56#define DRV_NAME MLX4_IB_DRV_NAME
169a1d85
AV		 57#define DRV_VERSION "2.2-1"
58#define DRV_RELDATE "Feb 2014"
225c7b1f 59
f77c0162 60#define MLX4_IB_FLOW_MAX_PRIO 0xFFF
a37a1a42 61#define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
50e2ec91 62#define MLX4_IB_CARD_REV_A0 0xA0
f77c0162 63
225c7b1f
RD		 64MODULE_AUTHOR("Roland Dreier");
65MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRV_VERSION);
68
56c1d233 69int mlx4_ib_sm_guid_assign = 0;
a0c64a17 70module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
56c1d233 71MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
a0c64a17 72
68f3948d 73static const char mlx4_ib_version[] =
225c7b1f
RD		 74 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
75 DRV_VERSION " (" DRV_RELDATE ")\n";
76
fa417f7b
EC		 77struct update_gid_work {
78 struct work_struct work;
79 union ib_gid gids[128];
80 struct mlx4_ib_dev *dev;
81 int port;
82};
83
3806d08c
JM		 84static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
85
fa417f7b
EC		 86static struct workqueue_struct *wq;
87
225c7b1f
RD		 88static void init_query_mad(struct ib_smp *mad)
89{
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
94}
95
4c3eb3ca
EC		 96static union ib_gid zgid;
97
f77c0162
HHZ		 98static int check_flow_steering_support(struct mlx4_dev *dev)
99{
0a9b7d59 100 int eth_num_ports = 0;
f77c0162 101 int ib_num_ports = 0;
f77c0162 102
0a9b7d59
MB		 103 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
104
105 if (dmfs) {
106 int i;
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
108 eth_num_ports++;
109 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
110 ib_num_ports++;
111 dmfs &= (!ib_num_ports ||
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
113 (!eth_num_ports ||
114 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
115 if (ib_num_ports && mlx4_is_mfunc(dev)) {
116 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
117 dmfs = 0;
f77c0162 118 }
f77c0162 119 }
0a9b7d59 120 return dmfs;
f77c0162
HHZ		 121}
122
3dec4878
JM		 123static int num_ib_ports(struct mlx4_dev *dev)
124{
125 int ib_ports = 0;
126 int i;
127
128 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
129 ib_ports++;
130
131 return ib_ports;
132}
133
225c7b1f 134static int mlx4_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 135 struct ib_device_attr *props,
136 struct ib_udata *uhw)
225c7b1f
RD		 137{
138 struct mlx4_ib_dev *dev = to_mdev(ibdev);
139 struct ib_smp *in_mad = NULL;
140 struct ib_smp *out_mad = NULL;
141 int err = -ENOMEM;
3dec4878 142 int have_ib_ports;
4b664c43
MB		 143 struct mlx4_uverbs_ex_query_device cmd;
144 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
145 struct mlx4_clock_params clock_params;
225c7b1f 146
4b664c43
MB		 147 if (uhw->inlen) {
148 if (uhw->inlen < sizeof(cmd))
149 return -EINVAL;
150
151 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
152 if (err)
153 return err;
154
155 if (cmd.comp_mask)
156 return -EINVAL;
157
158 if (cmd.reserved)
159 return -EINVAL;
160 }
2528e33e 161
4b664c43
MB		 162 resp.response_length = offsetof(typeof(resp), response_length) +
163 sizeof(resp.response_length);
225c7b1f
RD		 164 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
165 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
166 if (!in_mad || !out_mad)
167 goto out;
168
169 init_query_mad(in_mad);
170 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
171
0a9a0188
JM		 172 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
173 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 174 if (err)
175 goto out;
176
177 memset(props, 0, sizeof *props);
178
3dec4878
JM		 179 have_ib_ports = num_ib_ports(dev->dev);
180
225c7b1f
RD		 181 props->fw_ver = dev->dev->caps.fw_ver;
182 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
183 IB_DEVICE_PORT_ACTIVE_EVENT |
184 IB_DEVICE_SYS_IMAGE_GUID |
521e575b
RL		 185 IB_DEVICE_RC_RNR_NAK_GEN |
186 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
225c7b1f
RD		 187 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
188 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
189 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
190 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
3dec4878 191 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
225c7b1f
RD		 192 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
193 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
194 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
8ff095ec
EC		 195 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
196 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
50e2ec91
MS		 197 if (dev->dev->caps.max_gso_sz &&
198 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
199 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
b832be1e 200 props->device_cap_flags |= IB_DEVICE_UD_TSO;
95d04f07
RD		 201 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
202 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
203 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
204 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
205 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
206 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
0a1405da
SH		 207 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
208 props->device_cap_flags |= IB_DEVICE_XRC;
b425388d
SM		 209 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
210 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
211 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
212 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
213 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
214 else
215 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
0a9b7d59 216 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
f77c0162 217 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
b425388d 218 }
225c7b1f
RD		 219
220 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
221 0xffffff;
872bf2fb 222 props->vendor_part_id = dev->dev->persist->pdev->device;
225c7b1f
RD		 223 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
224 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
225
226 props->max_mr_size = ~0ull;
227 props->page_size_cap = dev->dev->caps.page_size_cap;
5a0d0a61 228 props->max_qp = dev->dev->quotas.qp;
fc2d0044 229 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
225c7b1f
RD		 230 props->max_sge = min(dev->dev->caps.max_sq_sg,
231 dev->dev->caps.max_rq_sg);
18ebd407 232 props->max_sge_rd = props->max_sge;
5a0d0a61 233 props->max_cq = dev->dev->quotas.cq;
225c7b1f 234 props->max_cqe = dev->dev->caps.max_cqes;
5a0d0a61 235 props->max_mr = dev->dev->quotas.mpt;
225c7b1f
RD		 236 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
237 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
238 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
239 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
5a0d0a61 240 props->max_srq = dev->dev->quotas.srq;
c8681f14 241 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
225c7b1f 242 props->max_srq_sge = dev->dev->caps.max_srq_sge;
5a0fd094 243 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
225c7b1f
RD		 244 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
245 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
246 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
47e956b2 247 props->masked_atomic_cap = props->atomic_cap;
5ae2a7a8 248 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
225c7b1f
RD		 249 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
250 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
251 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
252 props->max_mcast_grp;
a5bbe892 253 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
4b664c43
MB		 254 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
255 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
225c7b1f 256
8a7ff14d
MB		 257 if (!mlx4_is_slave(dev->dev))
258 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
4b664c43
MB		 259
260 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
4b664c43 261 resp.response_length += sizeof(resp.hca_core_clock_offset);
8a7ff14d
MB		 262 if (!err && !mlx4_is_slave(dev->dev)) {
263 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
264 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
265 }
4b664c43
MB		 266 }
267
268 if (uhw->outlen) {
269 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
270 if (err)
271 goto out;
272 }
225c7b1f
RD		 273out:
274 kfree(in_mad);
275 kfree(out_mad);
276
277 return err;
278}
279
fa417f7b
EC		 280static enum rdma_link_layer
281mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
225c7b1f 282{
fa417f7b 283 struct mlx4_dev *dev = to_mdev(device)->dev;
225c7b1f 284
65dab25d 285 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
fa417f7b
EC		 286 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
287}
225c7b1f 288
fa417f7b 289static int ib_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 290 struct ib_port_attr *props, int netw_view)
fa417f7b 291{
a9c766bb
OG		 292 struct ib_smp *in_mad = NULL;
293 struct ib_smp *out_mad = NULL;
a5e12dff 294 int ext_active_speed;
0a9a0188 295 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
a9c766bb
OG		 296 int err = -ENOMEM;
297
298 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
299 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
300 if (!in_mad || !out_mad)
301 goto out;
302
303 init_query_mad(in_mad);
304 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
305 in_mad->attr_mod = cpu_to_be32(port);
306
0a9a0188
JM		 307 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
308 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
309
310 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
a9c766bb
OG		 311 in_mad, out_mad);
312 if (err)
313 goto out;
314
a5e12dff 315
225c7b1f
RD		 316 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
317 props->lmc = out_mad->data[34] & 0x7;
318 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
319 props->sm_sl = out_mad->data[36] & 0xf;
320 props->state = out_mad->data[32] & 0xf;
321 props->phys_state = out_mad->data[33] >> 4;
322 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
0a9a0188
JM		 323 if (netw_view)
324 props->gid_tbl_len = out_mad->data[50];
325 else
326 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
149983af 327 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
5ae2a7a8 328 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
225c7b1f
RD		 329 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
330 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
331 props->active_width = out_mad->data[31] & 0xf;
332 props->active_speed = out_mad->data[35] >> 4;
333 props->max_mtu = out_mad->data[41] & 0xf;
334 props->active_mtu = out_mad->data[36] >> 4;
335 props->subnet_timeout = out_mad->data[51] & 0x1f;
336 props->max_vl_num = out_mad->data[37] >> 4;
337 props->init_type_reply = out_mad->data[41] >> 4;
338
a5e12dff
MA		 339 /* Check if extended speeds (EDR/FDR/...) are supported */
340 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
341 ext_active_speed = out_mad->data[62] >> 4;
342
343 switch (ext_active_speed) {
344 case 1:
2e96691c 345 props->active_speed = IB_SPEED_FDR;
a5e12dff
MA		 346 break;
347 case 2:
2e96691c 348 props->active_speed = IB_SPEED_EDR;
a5e12dff
MA		 349 break;
350 }
351 }
352
353 /* If reported active speed is QDR, check if is FDR-10 */
2e96691c 354 if (props->active_speed == IB_SPEED_QDR) {
8154c07f
OG		 355 init_query_mad(in_mad);
356 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
357 in_mad->attr_mod = cpu_to_be32(port);
358
0a9a0188 359 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
8154c07f
OG		 360 NULL, NULL, in_mad, out_mad);
361 if (err)
bf6b47de 362 goto out;
8154c07f
OG		 363
364 /* Checking LinkSpeedActive for FDR-10 */
365 if (out_mad->data[15] & 0x1)
366 props->active_speed = IB_SPEED_FDR10;
a5e12dff 367 }
d2ef4068
OG		 368
369 /* Avoid wrong speed value returned by FW if the IB link is down. */
370 if (props->state == IB_PORT_DOWN)
371 props->active_speed = IB_SPEED_SDR;
372
a9c766bb
OG		 373out:
374 kfree(in_mad);
375 kfree(out_mad);
376 return err;
fa417f7b
EC		 377}
378
379static u8 state_to_phys_state(enum ib_port_state state)
380{
381 return state == IB_PORT_ACTIVE ? 5 : 3;
382}
383
384static int eth_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 385 struct ib_port_attr *props, int netw_view)
fa417f7b 386{
a9c766bb
OG		 387
388 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
389 struct mlx4_ib_iboe *iboe = &mdev->iboe;
fa417f7b
EC		 390 struct net_device *ndev;
391 enum ib_mtu tmp;
a9c766bb
OG		 392 struct mlx4_cmd_mailbox *mailbox;
393 int err = 0;
a5750090 394 int is_bonded = mlx4_is_bonded(mdev->dev);
a9c766bb
OG		 395
396 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
397 if (IS_ERR(mailbox))
398 return PTR_ERR(mailbox);
fa417f7b 399
a9c766bb
OG		 400 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
401 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
402 MLX4_CMD_WRAPPED);
403 if (err)
404 goto out;
405
406 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ?
407 IB_WIDTH_4X : IB_WIDTH_1X;
2e96691c 408 props->active_speed = IB_SPEED_QDR;
b4a26a27 409 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
a9c766bb
OG		 410 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
411 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
fa417f7b 412 props->pkey_tbl_len = 1;
bcacb897 413 props->max_mtu = IB_MTU_4096;
a9c766bb 414 props->max_vl_num = 2;
fa417f7b
EC		 415 props->state = IB_PORT_DOWN;
416 props->phys_state = state_to_phys_state(props->state);
417 props->active_mtu = IB_MTU_256;
a5750090
MS		 418 if (is_bonded)
419 rtnl_lock(); /* required to get upper dev */
dba3ad2a 420 spin_lock_bh(&iboe->lock);
fa417f7b 421 ndev = iboe->netdevs[port - 1];
a5750090
MS		 422 if (ndev && is_bonded)
423 ndev = netdev_master_upper_dev_get(ndev);
fa417f7b 424 if (!ndev)
a9c766bb 425 goto out_unlock;
fa417f7b
EC		 426
427 tmp = iboe_get_mtu(ndev->mtu);
428 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
429
21d60609 430 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
fa417f7b
EC		 431 IB_PORT_ACTIVE : IB_PORT_DOWN;
432 props->phys_state = state_to_phys_state(props->state);
a9c766bb 433out_unlock:
dba3ad2a 434 spin_unlock_bh(&iboe->lock);
a5750090
MS		 435 if (is_bonded)
436 rtnl_unlock();
a9c766bb
OG		 437out:
438 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
439 return err;
fa417f7b
EC		 440}
441
0a9a0188
JM		 442int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
443 struct ib_port_attr *props, int netw_view)
fa417f7b 444{
a9c766bb 445 int err;
fa417f7b
EC		 446
447 memset(props, 0, sizeof *props);
448
fa417f7b 449 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
0a9a0188
JM		 450 ib_link_query_port(ibdev, port, props, netw_view) :
451 eth_link_query_port(ibdev, port, props, netw_view);
225c7b1f
RD		 452
453 return err;
454}
455
0a9a0188
JM		 456static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
457 struct ib_port_attr *props)
458{
459 /* returns host view */
460 return __mlx4_ib_query_port(ibdev, port, props, 0);
461}
462
a0c64a17
JM		 463int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
464 union ib_gid *gid, int netw_view)
225c7b1f
RD		 465{
466 struct ib_smp *in_mad = NULL;
467 struct ib_smp *out_mad = NULL;
468 int err = -ENOMEM;
a0c64a17
JM		 469 struct mlx4_ib_dev *dev = to_mdev(ibdev);
470 int clear = 0;
471 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 472
473 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
474 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
475 if (!in_mad || !out_mad)
476 goto out;
477
478 init_query_mad(in_mad);
479 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
480 in_mad->attr_mod = cpu_to_be32(port);
481
a0c64a17
JM		 482 if (mlx4_is_mfunc(dev->dev) && netw_view)
483 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
484
485 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 486 if (err)
487 goto out;
488
489 memcpy(gid->raw, out_mad->data + 8, 8);
490
a0c64a17
JM		 491 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
492 if (index) {
493 /* For any index > 0, return the null guid */
494 err = 0;
495 clear = 1;
496 goto out;
497 }
498 }
499
225c7b1f
RD		 500 init_query_mad(in_mad);
501 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
502 in_mad->attr_mod = cpu_to_be32(index / 8);
503
a0c64a17 504 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
0a9a0188 505 NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 506 if (err)
507 goto out;
508
509 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
510
511out:
a0c64a17
JM		 512 if (clear)
513 memset(gid->raw + 8, 0, 8);
225c7b1f
RD		 514 kfree(in_mad);
515 kfree(out_mad);
516 return err;
517}
518
fa417f7b
EC		 519static int iboe_query_gid(struct ib_device *ibdev, u8 port, int index,
520 union ib_gid *gid)
521{
522 struct mlx4_ib_dev *dev = to_mdev(ibdev);
523
524 *gid = dev->iboe.gid_table[port - 1][index];
525
526 return 0;
527}
528
529static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
530 union ib_gid *gid)
531{
532 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
a0c64a17 533 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
fa417f7b
EC		 534 else
535 return iboe_query_gid(ibdev, port, index, gid);
536}
537
0a9a0188
JM		 538int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
539 u16 *pkey, int netw_view)
225c7b1f
RD		 540{
541 struct ib_smp *in_mad = NULL;
542 struct ib_smp *out_mad = NULL;
0a9a0188 543 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 544 int err = -ENOMEM;
545
546 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
547 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
548 if (!in_mad || !out_mad)
549 goto out;
550
551 init_query_mad(in_mad);
552 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
553 in_mad->attr_mod = cpu_to_be32(index / 32);
554
0a9a0188
JM		 555 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
556 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
557
558 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
559 in_mad, out_mad);
225c7b1f
RD		 560 if (err)
561 goto out;
562
563 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
564
565out:
566 kfree(in_mad);
567 kfree(out_mad);
568 return err;
569}
570
0a9a0188
JM		 571static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
572{
573 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
574}
575
225c7b1f
RD		 576static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
577 struct ib_device_modify *props)
578{
d0d68b86 579 struct mlx4_cmd_mailbox *mailbox;
df7fba66 580 unsigned long flags;
d0d68b86 581
225c7b1f
RD		 582 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
583 return -EOPNOTSUPP;
584
d0d68b86
JM		 585 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
586 return 0;
587
992e8e6e
JM		 588 if (mlx4_is_slave(to_mdev(ibdev)->dev))
589 return -EOPNOTSUPP;
590
df7fba66 591 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86 592 memcpy(ibdev->node_desc, props->node_desc, 64);
df7fba66 593 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86
JM		 594
595 /*
596 * If possible, pass node desc to FW, so it can generate
597 * a 144 trap. If cmd fails, just ignore.
598 */
599 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
600 if (IS_ERR(mailbox))
601 return 0;
602
d0d68b86
JM		 603 memcpy(mailbox->buf, props->node_desc, 64);
604 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
992e8e6e 605 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
d0d68b86
JM		 606
607 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
225c7b1f
RD		 608
609 return 0;
610}
611
61565013
JM		 612static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
613 u32 cap_mask)
225c7b1f
RD		 614{
615 struct mlx4_cmd_mailbox *mailbox;
616 int err;
617
618 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
619 if (IS_ERR(mailbox))
620 return PTR_ERR(mailbox);
621
5ae2a7a8
RD		 622 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
623 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
624 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
625 } else {
626 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
627 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
628 }
225c7b1f 629
a130b590
IS		 630 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
631 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
632 MLX4_CMD_WRAPPED);
225c7b1f
RD		 633
634 mlx4_free_cmd_mailbox(dev->dev, mailbox);
635 return err;
636}
637
638static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
639 struct ib_port_modify *props)
640{
61565013
JM		 641 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
642 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
225c7b1f
RD		 643 struct ib_port_attr attr;
644 u32 cap_mask;
645 int err;
646
61565013
JM		 647 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
648 * of whether port link layer is ETH or IB. For ETH ports, qkey
649 * violations and port capabilities are not meaningful.
650 */
651 if (is_eth)
652 return 0;
653
654 mutex_lock(&mdev->cap_mask_mutex);
225c7b1f
RD		 655
656 err = mlx4_ib_query_port(ibdev, port, &attr);
657 if (err)
658 goto out;
659
660 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
661 ~props->clr_port_cap_mask;
662
61565013
JM		 663 err = mlx4_ib_SET_PORT(mdev, port,
664 !!(mask & IB_PORT_RESET_QKEY_CNTR),
665 cap_mask);
225c7b1f
RD		 666
667out:
668 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
669 return err;
670}
671
672static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
673 struct ib_udata *udata)
674{
675 struct mlx4_ib_dev *dev = to_mdev(ibdev);
676 struct mlx4_ib_ucontext *context;
08ff3235 677 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
225c7b1f
RD		 678 struct mlx4_ib_alloc_ucontext_resp resp;
679 int err;
680
3b4a8cd5
JM		 681 if (!dev->ib_active)
682 return ERR_PTR(-EAGAIN);
683
08ff3235
OG		 684 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
685 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
686 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
687 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
688 } else {
689 resp.dev_caps = dev->dev->caps.userspace_caps;
690 resp.qp_tab_size = dev->dev->caps.num_qps;
691 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
692 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
693 resp.cqe_size = dev->dev->caps.cqe_size;
694 }
225c7b1f
RD		 695
696 context = kmalloc(sizeof *context, GFP_KERNEL);
697 if (!context)
698 return ERR_PTR(-ENOMEM);
699
700 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
701 if (err) {
702 kfree(context);
703 return ERR_PTR(err);
704 }
705
706 INIT_LIST_HEAD(&context->db_page_list);
707 mutex_init(&context->db_page_mutex);
708
08ff3235
OG		 709 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
710 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
711 else
712 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
713
225c7b1f
RD		 714 if (err) {
715 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
716 kfree(context);
717 return ERR_PTR(-EFAULT);
718 }
719
720 return &context->ibucontext;
721}
722
723static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
724{
725 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
726
727 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
728 kfree(context);
729
730 return 0;
731}
732
733static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
734{
735 struct mlx4_ib_dev *dev = to_mdev(context->device);
736
737 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
738 return -EINVAL;
739
740 if (vma->vm_pgoff == 0) {
741 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
742
743 if (io_remap_pfn_range(vma, vma->vm_start,
744 to_mucontext(context)->uar.pfn,
745 PAGE_SIZE, vma->vm_page_prot))
746 return -EAGAIN;
747 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
e1d60ec6 748 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
225c7b1f
RD		 749
750 if (io_remap_pfn_range(vma, vma->vm_start,
751 to_mucontext(context)->uar.pfn +
752 dev->dev->caps.num_uars,
753 PAGE_SIZE, vma->vm_page_prot))
754 return -EAGAIN;
52033cfb
MB		 755 } else if (vma->vm_pgoff == 3) {
756 struct mlx4_clock_params params;
757 int ret = mlx4_get_internal_clock_params(dev->dev, &params);
758
759 if (ret)
760 return ret;
761
762 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
763 if (io_remap_pfn_range(vma, vma->vm_start,
764 (pci_resource_start(dev->dev->persist->pdev,
765 params.bar) +
766 params.offset)
767 >> PAGE_SHIFT,
768 PAGE_SIZE, vma->vm_page_prot))
769 return -EAGAIN;
770 } else {
225c7b1f 771 return -EINVAL;
52033cfb 772 }
225c7b1f
RD		 773
774 return 0;
775}
776
777static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
778 struct ib_ucontext *context,
779 struct ib_udata *udata)
780{
781 struct mlx4_ib_pd *pd;
782 int err;
783
784 pd = kmalloc(sizeof *pd, GFP_KERNEL);
785 if (!pd)
786 return ERR_PTR(-ENOMEM);
787
788 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
789 if (err) {
790 kfree(pd);
791 return ERR_PTR(err);
792 }
793
794 if (context)
795 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
796 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
797 kfree(pd);
798 return ERR_PTR(-EFAULT);
799 }
800
801 return &pd->ibpd;
802}
803
804static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
805{
806 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
807 kfree(pd);
808
809 return 0;
810}
811
012a8ff5
SH		 812static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
813 struct ib_ucontext *context,
814 struct ib_udata *udata)
815{
816 struct mlx4_ib_xrcd *xrcd;
8e37210b 817 struct ib_cq_init_attr cq_attr = {};
012a8ff5
SH		 818 int err;
819
820 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
821 return ERR_PTR(-ENOSYS);
822
823 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
824 if (!xrcd)
825 return ERR_PTR(-ENOMEM);
826
827 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
828 if (err)
829 goto err1;
830
831 xrcd->pd = ib_alloc_pd(ibdev);
832 if (IS_ERR(xrcd->pd)) {
833 err = PTR_ERR(xrcd->pd);
834 goto err2;
835 }
836
8e37210b
MB		 837 cq_attr.cqe = 1;
838 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
012a8ff5
SH		 839 if (IS_ERR(xrcd->cq)) {
840 err = PTR_ERR(xrcd->cq);
841 goto err3;
842 }
843
844 return &xrcd->ibxrcd;
845
846err3:
847 ib_dealloc_pd(xrcd->pd);
848err2:
849 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
850err1:
851 kfree(xrcd);
852 return ERR_PTR(err);
853}
854
855static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
856{
857 ib_destroy_cq(to_mxrcd(xrcd)->cq);
858 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
859 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
860 kfree(xrcd);
861
862 return 0;
863}
864
fa417f7b
EC		 865static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
866{
867 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
868 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
869 struct mlx4_ib_gid_entry *ge;
870
871 ge = kzalloc(sizeof *ge, GFP_KERNEL);
872 if (!ge)
873 return -ENOMEM;
874
875 ge->gid = *gid;
876 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
877 ge->port = mqp->port;
878 ge->added = 1;
879 }
880
881 mutex_lock(&mqp->mutex);
882 list_add_tail(&ge->list, &mqp->gid_list);
883 mutex_unlock(&mqp->mutex);
884
885 return 0;
886}
887
888int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
889 union ib_gid *gid)
890{
fa417f7b
EC		 891 struct net_device *ndev;
892 int ret = 0;
893
894 if (!mqp->port)
895 return 0;
896
dba3ad2a 897 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 898 ndev = mdev->iboe.netdevs[mqp->port - 1];
899 if (ndev)
900 dev_hold(ndev);
dba3ad2a 901 spin_unlock_bh(&mdev->iboe.lock);
fa417f7b
EC		 902
903 if (ndev) {
fa417f7b 904 ret = 1;
fa417f7b
EC		 905 dev_put(ndev);
906 }
907
908 return ret;
909}
910
0ff1fb65
HHZ		 911struct mlx4_ib_steering {
912 struct list_head list;
146d6e19 913 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 914 union ib_gid gid;
915};
916
f77c0162 917static int parse_flow_attr(struct mlx4_dev *dev,
a37a1a42 918 u32 qp_num,
f77c0162
HHZ		 919 union ib_flow_spec *ib_spec,
920 struct _rule_hw *mlx4_spec)
921{
922 enum mlx4_net_trans_rule_id type;
923
924 switch (ib_spec->type) {
925 case IB_FLOW_SPEC_ETH:
926 type = MLX4_NET_TRANS_RULE_ID_ETH;
927 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
928 ETH_ALEN);
929 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
930 ETH_ALEN);
931 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
932 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
933 break;
a37a1a42
MB		 934 case IB_FLOW_SPEC_IB:
935 type = MLX4_NET_TRANS_RULE_ID_IB;
936 mlx4_spec->ib.l3_qpn =
937 cpu_to_be32(qp_num);
938 mlx4_spec->ib.qpn_mask =
939 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
940 break;
941
f77c0162
HHZ		 942
943 case IB_FLOW_SPEC_IPV4:
944 type = MLX4_NET_TRANS_RULE_ID_IPV4;
945 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
946 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
947 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
948 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
949 break;
950
951 case IB_FLOW_SPEC_TCP:
952 case IB_FLOW_SPEC_UDP:
953 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
954 MLX4_NET_TRANS_RULE_ID_TCP :
955 MLX4_NET_TRANS_RULE_ID_UDP;
956 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
957 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
958 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
959 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
960 break;
961
962 default:
963 return -EINVAL;
964 }
965 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
966 mlx4_hw_rule_sz(dev, type) < 0)
967 return -EINVAL;
968 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
969 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
970 return mlx4_hw_rule_sz(dev, type);
971}
972
a37a1a42
MB		 973struct default_rules {
974 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
975 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
976 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
977 __u8 link_layer;
978};
979static const struct default_rules default_table[] = {
980 {
981 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
982 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
983 .rules_create_list = {IB_FLOW_SPEC_IB},
984 .link_layer = IB_LINK_LAYER_INFINIBAND
985 }
986};
987
988static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
989 struct ib_flow_attr *flow_attr)
990{
991 int i, j, k;
992 void *ib_flow;
993 const struct default_rules *pdefault_rules = default_table;
994 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
995
a57f23f6 996 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
a37a1a42
MB		 997 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
998 memset(&field_types, 0, sizeof(field_types));
999
1000 if (link_layer != pdefault_rules->link_layer)
1001 continue;
1002
1003 ib_flow = flow_attr + 1;
1004 /* we assume the specs are sorted */
1005 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1006 j < flow_attr->num_of_specs; k++) {
1007 union ib_flow_spec *current_flow =
1008 (union ib_flow_spec *)ib_flow;
1009
1010 /* same layer but different type */
1011 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1012 (pdefault_rules->mandatory_fields[k] &
1013 IB_FLOW_SPEC_LAYER_MASK)) &&
1014 (current_flow->type !=
1015 pdefault_rules->mandatory_fields[k]))
1016 goto out;
1017
1018 /* same layer, try match next one */
1019 if (current_flow->type ==
1020 pdefault_rules->mandatory_fields[k]) {
1021 j++;
1022 ib_flow +=
1023 ((union ib_flow_spec *)ib_flow)->size;
1024 }
1025 }
1026
1027 ib_flow = flow_attr + 1;
1028 for (j = 0; j < flow_attr->num_of_specs;
1029 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1030 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1031 /* same layer and same type */
1032 if (((union ib_flow_spec *)ib_flow)->type ==
1033 pdefault_rules->mandatory_not_fields[k])
1034 goto out;
1035
1036 return i;
1037 }
1038out:
1039 return -1;
1040}
1041
1042static int __mlx4_ib_create_default_rules(
1043 struct mlx4_ib_dev *mdev,
1044 struct ib_qp *qp,
1045 const struct default_rules *pdefault_rules,
1046 struct _rule_hw *mlx4_spec) {
1047 int size = 0;
1048 int i;
1049
a57f23f6 1050 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
a37a1a42
MB		 1051 int ret;
1052 union ib_flow_spec ib_spec;
1053 switch (pdefault_rules->rules_create_list[i]) {
1054 case 0:
1055 /* no rule */
1056 continue;
1057 case IB_FLOW_SPEC_IB:
1058 ib_spec.type = IB_FLOW_SPEC_IB;
1059 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1060
1061 break;
1062 default:
1063 /* invalid rule */
1064 return -EINVAL;
1065 }
1066 /* We must put empty rule, qpn is being ignored */
1067 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1068 mlx4_spec);
1069 if (ret < 0) {
1070 pr_info("invalid parsing\n");
1071 return -EINVAL;
1072 }
1073
1074 mlx4_spec = (void *)mlx4_spec + ret;
1075 size += ret;
1076 }
1077 return size;
1078}
1079
f77c0162
HHZ		 1080static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1081 int domain,
1082 enum mlx4_net_trans_promisc_mode flow_type,
1083 u64 *reg_id)
1084{
1085 int ret, i;
1086 int size = 0;
1087 void *ib_flow;
1088 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1089 struct mlx4_cmd_mailbox *mailbox;
1090 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
a37a1a42 1091 int default_flow;
f77c0162
HHZ		 1092
1093 static const u16 __mlx4_domain[] = {
1094 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1095 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1096 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1097 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1098 };
1099
1100 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1101 pr_err("Invalid priority value %d\n", flow_attr->priority);
1102 return -EINVAL;
1103 }
1104
1105 if (domain >= IB_FLOW_DOMAIN_NUM) {
1106 pr_err("Invalid domain value %d\n", domain);
1107 return -EINVAL;
1108 }
1109
1110 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1111 return -EINVAL;
1112
1113 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1114 if (IS_ERR(mailbox))
1115 return PTR_ERR(mailbox);
f77c0162
HHZ		 1116 ctrl = mailbox->buf;
1117
1118 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1119 flow_attr->priority);
1120 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1121 ctrl->port = flow_attr->port;
1122 ctrl->qpn = cpu_to_be32(qp->qp_num);
1123
1124 ib_flow = flow_attr + 1;
1125 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
a37a1a42
MB		 1126 /* Add default flows */
1127 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1128 if (default_flow >= 0) {
1129 ret = __mlx4_ib_create_default_rules(
1130 mdev, qp, default_table + default_flow,
1131 mailbox->buf + size);
1132 if (ret < 0) {
1133 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1134 return -EINVAL;
1135 }
1136 size += ret;
1137 }
f77c0162 1138 for (i = 0; i < flow_attr->num_of_specs; i++) {
a37a1a42
MB		 1139 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1140 mailbox->buf + size);
f77c0162
HHZ		 1141 if (ret < 0) {
1142 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1143 return -EINVAL;
1144 }
1145 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1146 size += ret;
1147 }
1148
1149 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1150 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
48564135 1151 MLX4_CMD_WRAPPED);
f77c0162
HHZ		 1152 if (ret == -ENOMEM)
1153 pr_err("mcg table is full. Fail to register network rule.\n");
1154 else if (ret == -ENXIO)
1155 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1156 else if (ret)
1157 pr_err("Invalid argumant. Fail to register network rule.\n");
1158
1159 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1160 return ret;
1161}
1162
1163static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1164{
1165 int err;
1166 err = mlx4_cmd(dev, reg_id, 0, 0,
1167 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
48564135 1168 MLX4_CMD_WRAPPED);
f77c0162
HHZ		 1169 if (err)
1170 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1171 reg_id);
1172 return err;
1173}
1174
d2fce8a9
OG		 1175static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1176 u64 *reg_id)
1177{
1178 void *ib_flow;
1179 union ib_flow_spec *ib_spec;
1180 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1181 int err = 0;
1182
5eff6dad
OG		 1183 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1184 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
d2fce8a9
OG		 1185 return 0; /* do nothing */
1186
1187 ib_flow = flow_attr + 1;
1188 ib_spec = (union ib_flow_spec *)ib_flow;
1189
1190 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1191 return 0; /* do nothing */
1192
1193 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1194 flow_attr->port, qp->qp_num,
1195 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1196 reg_id);
1197 return err;
1198}
1199
f77c0162
HHZ		 1200static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1201 struct ib_flow_attr *flow_attr,
1202 int domain)
1203{
146d6e19 1204 int err = 0, i = 0, j = 0;
f77c0162
HHZ		 1205 struct mlx4_ib_flow *mflow;
1206 enum mlx4_net_trans_promisc_mode type[2];
146d6e19
MS		 1207 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1208 int is_bonded = mlx4_is_bonded(dev);
f77c0162
HHZ		 1209
1210 memset(type, 0, sizeof(type));
1211
1212 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1213 if (!mflow) {
1214 err = -ENOMEM;
1215 goto err_free;
1216 }
1217
1218 switch (flow_attr->type) {
1219 case IB_FLOW_ATTR_NORMAL:
1220 type[0] = MLX4_FS_REGULAR;
1221 break;
1222
1223 case IB_FLOW_ATTR_ALL_DEFAULT:
1224 type[0] = MLX4_FS_ALL_DEFAULT;
1225 break;
1226
1227 case IB_FLOW_ATTR_MC_DEFAULT:
1228 type[0] = MLX4_FS_MC_DEFAULT;
1229 break;
1230
1231 case IB_FLOW_ATTR_SNIFFER:
1232 type[0] = MLX4_FS_UC_SNIFFER;
1233 type[1] = MLX4_FS_MC_SNIFFER;
1234 break;
1235
1236 default:
1237 err = -EINVAL;
1238 goto err_free;
1239 }
1240
1241 while (i < ARRAY_SIZE(type) && type[i]) {
1242 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
146d6e19 1243 &mflow->reg_id[i].id);
f77c0162 1244 if (err)
571e1b2c 1245 goto err_create_flow;
146d6e19 1246 if (is_bonded) {
824c25c1
MS		 1247 /* Application always sees one port so the mirror rule
1248 * must be on port #2
1249 */
146d6e19
MS		 1250 flow_attr->port = 2;
1251 err = __mlx4_ib_create_flow(qp, flow_attr,
1252 domain, type[j],
1253 &mflow->reg_id[j].mirror);
1254 flow_attr->port = 1;
1255 if (err)
1256 goto err_create_flow;
1257 j++;
1258 }
1259
11562568 1260 i++;
f77c0162
HHZ		 1261 }
1262
d2fce8a9 1263 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
146d6e19
MS		 1264 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1265 &mflow->reg_id[i].id);
d2fce8a9 1266 if (err)
571e1b2c 1267 goto err_create_flow;
11562568 1268
146d6e19
MS		 1269 if (is_bonded) {
1270 flow_attr->port = 2;
1271 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1272 &mflow->reg_id[j].mirror);
1273 flow_attr->port = 1;
1274 if (err)
1275 goto err_create_flow;
1276 j++;
1277 }
1278 /* function to create mirror rule */
11562568 1279 i++;
d2fce8a9
OG		 1280 }
1281
f77c0162
HHZ		 1282 return &mflow->ibflow;
1283
571e1b2c
OG		 1284err_create_flow:
1285 while (i) {
146d6e19
MS		 1286 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1287 mflow->reg_id[i].id);
571e1b2c
OG		 1288 i--;
1289 }
146d6e19
MS		 1290
1291 while (j) {
1292 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1293 mflow->reg_id[j].mirror);
1294 j--;
1295 }
f77c0162
HHZ		 1296err_free:
1297 kfree(mflow);
1298 return ERR_PTR(err);
1299}
1300
1301static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1302{
1303 int err, ret = 0;
1304 int i = 0;
1305 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1306 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1307
146d6e19
MS		 1308 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1309 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
f77c0162
HHZ		 1310 if (err)
1311 ret = err;
146d6e19
MS		 1312 if (mflow->reg_id[i].mirror) {
1313 err = __mlx4_ib_destroy_flow(mdev->dev,
1314 mflow->reg_id[i].mirror);
1315 if (err)
1316 ret = err;
1317 }
f77c0162
HHZ		 1318 i++;
1319 }
1320
1321 kfree(mflow);
1322 return ret;
1323}
1324
225c7b1f
RD		 1325static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1326{
fa417f7b
EC		 1327 int err;
1328 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 1329 struct mlx4_dev *dev = mdev->dev;
fa417f7b 1330 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
0ff1fb65 1331 struct mlx4_ib_steering *ib_steering = NULL;
e9a7faf1 1332 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
146d6e19 1333 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1334
1335 if (mdev->dev->caps.steering_mode ==
1336 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1337 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1338 if (!ib_steering)
1339 return -ENOMEM;
1340 }
fa417f7b 1341
0ff1fb65
HHZ		 1342 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1343 !!(mqp->flags &
1344 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
146d6e19 1345 prot, &reg_id.id);
e9a7faf1
OG		 1346 if (err) {
1347 pr_err("multicast attach op failed, err %d\n", err);
0ff1fb65 1348 goto err_malloc;
e9a7faf1 1349 }
fa417f7b 1350
146d6e19
MS		 1351 reg_id.mirror = 0;
1352 if (mlx4_is_bonded(dev)) {
824c25c1
MS		 1353 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1354 (mqp->port == 1) ? 2 : 1,
146d6e19
MS		 1355 !!(mqp->flags &
1356 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1357 prot, &reg_id.mirror);
1358 if (err)
1359 goto err_add;
1360 }
1361
fa417f7b
EC		 1362 err = add_gid_entry(ibqp, gid);
1363 if (err)
1364 goto err_add;
1365
0ff1fb65
HHZ		 1366 if (ib_steering) {
1367 memcpy(ib_steering->gid.raw, gid->raw, 16);
1368 ib_steering->reg_id = reg_id;
1369 mutex_lock(&mqp->mutex);
1370 list_add(&ib_steering->list, &mqp->steering_rules);
1371 mutex_unlock(&mqp->mutex);
1372 }
fa417f7b
EC		 1373 return 0;
1374
1375err_add:
0ff1fb65 1376 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19
MS		 1377 prot, reg_id.id);
1378 if (reg_id.mirror)
1379 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1380 prot, reg_id.mirror);
0ff1fb65
HHZ		 1381err_malloc:
1382 kfree(ib_steering);
1383
fa417f7b
EC		 1384 return err;
1385}
1386
1387static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1388{
1389 struct mlx4_ib_gid_entry *ge;
1390 struct mlx4_ib_gid_entry *tmp;
1391 struct mlx4_ib_gid_entry *ret = NULL;
1392
1393 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1394 if (!memcmp(raw, ge->gid.raw, 16)) {
1395 ret = ge;
1396 break;
1397 }
1398 }
1399
1400 return ret;
225c7b1f
RD		 1401}
1402
1403static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1404{
fa417f7b
EC		 1405 int err;
1406 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 1407 struct mlx4_dev *dev = mdev->dev;
fa417f7b 1408 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
fa417f7b
EC		 1409 struct net_device *ndev;
1410 struct mlx4_ib_gid_entry *ge;
146d6e19 1411 struct mlx4_flow_reg_id reg_id = {0, 0};
e9a7faf1 1412 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
0ff1fb65
HHZ		 1413
1414 if (mdev->dev->caps.steering_mode ==
1415 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1416 struct mlx4_ib_steering *ib_steering;
1417
1418 mutex_lock(&mqp->mutex);
1419 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
1420 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
1421 list_del(&ib_steering->list);
1422 break;
1423 }
1424 }
1425 mutex_unlock(&mqp->mutex);
1426 if (&ib_steering->list == &mqp->steering_rules) {
1427 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
1428 return -EINVAL;
1429 }
1430 reg_id = ib_steering->reg_id;
1431 kfree(ib_steering);
1432 }
fa417f7b 1433
0ff1fb65 1434 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19 1435 prot, reg_id.id);
fa417f7b
EC		 1436 if (err)
1437 return err;
1438
146d6e19
MS		 1439 if (mlx4_is_bonded(dev)) {
1440 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1441 prot, reg_id.mirror);
1442 if (err)
1443 return err;
1444 }
1445
fa417f7b
EC		 1446 mutex_lock(&mqp->mutex);
1447 ge = find_gid_entry(mqp, gid->raw);
1448 if (ge) {
dba3ad2a 1449 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1450 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
1451 if (ndev)
1452 dev_hold(ndev);
dba3ad2a 1453 spin_unlock_bh(&mdev->iboe.lock);
d487ee77 1454 if (ndev)
fa417f7b 1455 dev_put(ndev);
fa417f7b
EC		 1456 list_del(&ge->list);
1457 kfree(ge);
1458 } else
987c8f8f 1459 pr_warn("could not find mgid entry\n");
fa417f7b
EC		 1460
1461 mutex_unlock(&mqp->mutex);
1462
1463 return 0;
225c7b1f
RD		 1464}
1465
1466static int init_node_data(struct mlx4_ib_dev *dev)
1467{
1468 struct ib_smp *in_mad = NULL;
1469 struct ib_smp *out_mad = NULL;
0a9a0188 1470 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 1471 int err = -ENOMEM;
1472
1473 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
1474 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1475 if (!in_mad || !out_mad)
1476 goto out;
1477
1478 init_query_mad(in_mad);
1479 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
0a9a0188
JM		 1480 if (mlx4_is_master(dev->dev))
1481 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
225c7b1f 1482
0a9a0188 1483 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 1484 if (err)
1485 goto out;
1486
1487 memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
1488
1489 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
1490
0a9a0188 1491 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 1492 if (err)
1493 goto out;
1494
992e8e6e 1495 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
225c7b1f
RD		 1496 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
1497
1498out:
1499 kfree(in_mad);
1500 kfree(out_mad);
1501 return err;
1502}
1503
f4e91eb4
TJ		 1504static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1505 char *buf)
cd9281d8 1506{
f4e91eb4
TJ		 1507 struct mlx4_ib_dev *dev =
1508 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
872bf2fb 1509 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
cd9281d8
JM		 1510}
1511
f4e91eb4
TJ		 1512static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1513 char *buf)
cd9281d8 1514{
f4e91eb4
TJ		 1515 struct mlx4_ib_dev *dev =
1516 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1517 return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
1518 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
1519 (int) dev->dev->caps.fw_ver & 0xffff);
1520}
1521
f4e91eb4
TJ		 1522static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1523 char *buf)
cd9281d8 1524{
f4e91eb4
TJ		 1525 struct mlx4_ib_dev *dev =
1526 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1527 return sprintf(buf, "%x\n", dev->dev->rev_id);
1528}
1529
f4e91eb4
TJ		 1530static ssize_t show_board(struct device *device, struct device_attribute *attr,
1531 char *buf)
cd9281d8 1532{
f4e91eb4
TJ		 1533 struct mlx4_ib_dev *dev =
1534 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
1535 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
1536 dev->dev->board_id);
cd9281d8
JM		 1537}
1538
f4e91eb4
TJ		 1539static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1540static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1541static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1542static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
cd9281d8 1543
f4e91eb4
TJ		 1544static struct device_attribute *mlx4_class_attributes[] = {
1545 &dev_attr_hw_rev,
1546 &dev_attr_fw_ver,
1547 &dev_attr_hca_type,
1548 &dev_attr_board_id
cd9281d8
JM		 1549};
1550
acc4fccf
MS		 1551static void mlx4_addrconf_ifid_eui48(u8 *eui, u16 vlan_id,
1552 struct net_device *dev)
1553{
1554 memcpy(eui, dev->dev_addr, 3);
1555 memcpy(eui + 5, dev->dev_addr + 3, 3);
1556 if (vlan_id < 0x1000) {
1557 eui[3] = vlan_id >> 8;
1558 eui[4] = vlan_id & 0xff;
1559 } else {
1560 eui[3] = 0xff;
1561 eui[4] = 0xfe;
1562 }
1563 eui[0] ^= 2;
1564}
1565
fa417f7b
EC		 1566static void update_gids_task(struct work_struct *work)
1567{
1568 struct update_gid_work *gw = container_of(work, struct update_gid_work, work);
1569 struct mlx4_cmd_mailbox *mailbox;
1570 union ib_gid *gids;
1571 int err;
1572 struct mlx4_dev *dev = gw->dev->dev;
a5750090 1573 int is_bonded = mlx4_is_bonded(dev);
fa417f7b 1574
4bf9715f
MS		 1575 if (!gw->dev->ib_active)
1576 return;
1577
fa417f7b
EC		 1578 mailbox = mlx4_alloc_cmd_mailbox(dev);
1579 if (IS_ERR(mailbox)) {
987c8f8f 1580 pr_warn("update gid table failed %ld\n", PTR_ERR(mailbox));
fa417f7b
EC		 1581 return;
1582 }
1583
1584 gids = mailbox->buf;
1585 memcpy(gids, gw->gids, sizeof gw->gids);
1586
1587 err = mlx4_cmd(dev, mailbox->dma, MLX4_SET_PORT_GID_TABLE << 8 | gw->port,
a130b590
IS		 1588 MLX4_SET_PORT_ETH_OPCODE, MLX4_CMD_SET_PORT,
1589 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
fa417f7b 1590 if (err)
987c8f8f 1591 pr_warn("set port command failed\n");
d487ee77 1592 else
a5750090
MS		 1593 if ((gw->port == 1) || !is_bonded)
1594 mlx4_ib_dispatch_event(gw->dev,
1595 is_bonded ? 1 : gw->port,
1596 IB_EVENT_GID_CHANGE);
fa417f7b
EC		 1597
1598 mlx4_free_cmd_mailbox(dev, mailbox);
1599 kfree(gw);
1600}
1601
d487ee77 1602static void reset_gids_task(struct work_struct *work)
fa417f7b 1603{
d487ee77
MS		 1604 struct update_gid_work *gw =
1605 container_of(work, struct update_gid_work, work);
1606 struct mlx4_cmd_mailbox *mailbox;
1607 union ib_gid *gids;
1608 int err;
d487ee77 1609 struct mlx4_dev *dev = gw->dev->dev;
fa417f7b 1610
4bf9715f
MS		 1611 if (!gw->dev->ib_active)
1612 return;
1613
d487ee77
MS		 1614 mailbox = mlx4_alloc_cmd_mailbox(dev);
1615 if (IS_ERR(mailbox)) {
1616 pr_warn("reset gid table failed\n");
1617 goto free;
1618 }
fa417f7b 1619
d487ee77
MS		 1620 gids = mailbox->buf;
1621 memcpy(gids, gw->gids, sizeof(gw->gids));
1622
5071456f
MS		 1623 if (mlx4_ib_port_link_layer(&gw->dev->ib_dev, gw->port) ==
1624 IB_LINK_LAYER_ETHERNET) {
1625 err = mlx4_cmd(dev, mailbox->dma,
1626 MLX4_SET_PORT_GID_TABLE << 8 | gw->port,
a130b590 1627 MLX4_SET_PORT_ETH_OPCODE, MLX4_CMD_SET_PORT,
5071456f
MS		 1628 MLX4_CMD_TIME_CLASS_B,
1629 MLX4_CMD_WRAPPED);
1630 if (err)
f4f01b54 1631 pr_warn("set port %d command failed\n", gw->port);
4c3eb3ca
EC		 1632 }
1633
d487ee77
MS		 1634 mlx4_free_cmd_mailbox(dev, mailbox);
1635free:
1636 kfree(gw);
1637}
4c3eb3ca 1638
d487ee77 1639static int update_gid_table(struct mlx4_ib_dev *dev, int port,
acc4fccf
MS		 1640 union ib_gid *gid, int clear,
1641 int default_gid)
d487ee77
MS		 1642{
1643 struct update_gid_work *work;
1644 int i;
1645 int need_update = 0;
1646 int free = -1;
1647 int found = -1;
1648 int max_gids;
1649
acc4fccf
MS		 1650 if (default_gid) {
1651 free = 0;
1652 } else {
1653 max_gids = dev->dev->caps.gid_table_len[port];
1654 for (i = 1; i < max_gids; ++i) {
1655 if (!memcmp(&dev->iboe.gid_table[port - 1][i], gid,
d487ee77 1656 sizeof(*gid)))
acc4fccf
MS		 1657 found = i;
1658
1659 if (clear) {
1660 if (found >= 0) {
1661 need_update = 1;
1662 dev->iboe.gid_table[port - 1][found] =
1663 zgid;
1664 break;
1665 }
1666 } else {
1667 if (found >= 0)
1668 break;
1669
1670 if (free < 0 &&
1671 !memcmp(&dev->iboe.gid_table[port - 1][i],
1672 &zgid, sizeof(*gid)))
1673 free = i;
1674 }
4c3eb3ca 1675 }
fa417f7b 1676 }
4c3eb3ca 1677
d487ee77
MS		 1678 if (found == -1 && !clear && free >= 0) {
1679 dev->iboe.gid_table[port - 1][free] = *gid;
1680 need_update = 1;
1681 }
fa417f7b 1682
d487ee77
MS		 1683 if (!need_update)
1684 return 0;
1685
1686 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1687 if (!work)
1688 return -ENOMEM;
1689
1690 memcpy(work->gids, dev->iboe.gid_table[port - 1], sizeof(work->gids));
1691 INIT_WORK(&work->work, update_gids_task);
1692 work->port = port;
1693 work->dev = dev;
1694 queue_work(wq, &work->work);
fa417f7b
EC		 1695
1696 return 0;
d487ee77 1697}
4c3eb3ca 1698
acc4fccf 1699static void mlx4_make_default_gid(struct net_device *dev, union ib_gid *gid)
d487ee77 1700{
acc4fccf
MS		 1701 gid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
1702 mlx4_addrconf_ifid_eui48(&gid->raw[8], 0xffff, dev);
1703}
1704
d487ee77 1705
5071456f 1706static int reset_gid_table(struct mlx4_ib_dev *dev, u8 port)
d487ee77
MS		 1707{
1708 struct update_gid_work *work;
d487ee77
MS		 1709
1710 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1711 if (!work)
1712 return -ENOMEM;
5071456f
MS		 1713
1714 memset(dev->iboe.gid_table[port - 1], 0, sizeof(work->gids));
d487ee77
MS		 1715 memset(work->gids, 0, sizeof(work->gids));
1716 INIT_WORK(&work->work, reset_gids_task);
1717 work->dev = dev;
5071456f 1718 work->port = port;
d487ee77
MS		 1719 queue_work(wq, &work->work);
1720 return 0;
fa417f7b
EC		 1721}
1722
d487ee77
MS		 1723static int mlx4_ib_addr_event(int event, struct net_device *event_netdev,
1724 struct mlx4_ib_dev *ibdev, union ib_gid *gid)
fa417f7b 1725{
d487ee77
MS		 1726 struct mlx4_ib_iboe *iboe;
1727 int port = 0;
1728 struct net_device *real_dev = rdma_vlan_dev_real_dev(event_netdev) ?
1729 rdma_vlan_dev_real_dev(event_netdev) :
1730 event_netdev;
acc4fccf
MS		 1731 union ib_gid default_gid;
1732
1733 mlx4_make_default_gid(real_dev, &default_gid);
1734
1735 if (!memcmp(gid, &default_gid, sizeof(*gid)))
1736 return 0;
d487ee77
MS		 1737
1738 if (event != NETDEV_DOWN && event != NETDEV_UP)
1739 return 0;
1740
1741 if ((real_dev != event_netdev) &&
1742 (event == NETDEV_DOWN) &&
1743 rdma_link_local_addr((struct in6_addr *)gid))
1744 return 0;
1745
1746 iboe = &ibdev->iboe;
dba3ad2a 1747 spin_lock_bh(&iboe->lock);
d487ee77 1748
82373701 1749 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port)
d487ee77
MS		 1750 if ((netif_is_bond_master(real_dev) &&
1751 (real_dev == iboe->masters[port - 1])) ||
1752 (!netif_is_bond_master(real_dev) &&
1753 (real_dev == iboe->netdevs[port - 1])))
1754 update_gid_table(ibdev, port, gid,
acc4fccf 1755 event == NETDEV_DOWN, 0);
d487ee77 1756
dba3ad2a 1757 spin_unlock_bh(&iboe->lock);
d487ee77 1758 return 0;
fa417f7b 1759
fa417f7b
EC		 1760}
1761
d487ee77
MS		 1762static u8 mlx4_ib_get_dev_port(struct net_device *dev,
1763 struct mlx4_ib_dev *ibdev)
fa417f7b 1764{
d487ee77
MS		 1765 u8 port = 0;
1766 struct mlx4_ib_iboe *iboe;
1767 struct net_device *real_dev = rdma_vlan_dev_real_dev(dev) ?
1768 rdma_vlan_dev_real_dev(dev) : dev;
1769
1770 iboe = &ibdev->iboe;
d487ee77 1771
82373701 1772 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port)
d487ee77
MS		 1773 if ((netif_is_bond_master(real_dev) &&
1774 (real_dev == iboe->masters[port - 1])) ||
1775 (!netif_is_bond_master(real_dev) &&
1776 (real_dev == iboe->netdevs[port - 1])))
1777 break;
1778
82373701 1779 if ((port == 0) || (port > ibdev->dev->caps.num_ports))
d487ee77
MS		 1780 return 0;
1781 else
1782 return port;
fa417f7b
EC		 1783}
1784
d487ee77
MS		 1785static int mlx4_ib_inet_event(struct notifier_block *this, unsigned long event,
1786 void *ptr)
fa417f7b 1787{
d487ee77
MS		 1788 struct mlx4_ib_dev *ibdev;
1789 struct in_ifaddr *ifa = ptr;
1790 union ib_gid gid;
1791 struct net_device *event_netdev = ifa->ifa_dev->dev;
1792
1793 ipv6_addr_set_v4mapped(ifa->ifa_address, (struct in6_addr *)&gid);
1794
1795 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb_inet);
1796
1797 mlx4_ib_addr_event(event, event_netdev, ibdev, &gid);
1798 return NOTIFY_DONE;
fa417f7b
EC		 1799}
1800
27cdef63 1801#if IS_ENABLED(CONFIG_IPV6)
d487ee77 1802static int mlx4_ib_inet6_event(struct notifier_block *this, unsigned long event,
fa417f7b
EC		 1803 void *ptr)
1804{
fa417f7b 1805 struct mlx4_ib_dev *ibdev;
d487ee77
MS		 1806 struct inet6_ifaddr *ifa = ptr;
1807 union ib_gid *gid = (union ib_gid *)&ifa->addr;
1808 struct net_device *event_netdev = ifa->idev->dev;
1809
1810 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb_inet6);
1811
1812 mlx4_ib_addr_event(event, event_netdev, ibdev, gid);
1813 return NOTIFY_DONE;
1814}
1815#endif
1816
9433c188
MB		 1817#define MLX4_IB_INVALID_MAC ((u64)-1)
1818static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
1819 struct net_device *dev,
1820 int port)
1821{
1822 u64 new_smac = 0;
1823 u64 release_mac = MLX4_IB_INVALID_MAC;
1824 struct mlx4_ib_qp *qp;
1825
1826 read_lock(&dev_base_lock);
1827 new_smac = mlx4_mac_to_u64(dev->dev_addr);
1828 read_unlock(&dev_base_lock);
1829
3e0629cb
JM		 1830 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
1831
d24d9f43
JM		 1832 /* no need for update QP1 and mac registration in non-SRIOV */
1833 if (!mlx4_is_mfunc(ibdev->dev))
1834 return;
1835
9433c188
MB		 1836 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
1837 qp = ibdev->qp1_proxy[port - 1];
1838 if (qp) {
1839 int new_smac_index;
25476b02 1840 u64 old_smac;
9433c188
MB		 1841 struct mlx4_update_qp_params update_params;
1842
25476b02
JM		 1843 mutex_lock(&qp->mutex);
1844 old_smac = qp->pri.smac;
9433c188
MB		 1845 if (new_smac == old_smac)
1846 goto unlock;
1847
1848 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
1849
1850 if (new_smac_index < 0)
1851 goto unlock;
1852
1853 update_params.smac_index = new_smac_index;
09e05c3f 1854 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
9433c188
MB		 1855 &update_params)) {
1856 release_mac = new_smac;
1857 goto unlock;
1858 }
25476b02
JM		 1859 /* if old port was zero, no mac was yet registered for this QP */
1860 if (qp->pri.smac_port)
1861 release_mac = old_smac;
9433c188 1862 qp->pri.smac = new_smac;
25476b02 1863 qp->pri.smac_port = port;
9433c188 1864 qp->pri.smac_index = new_smac_index;
9433c188
MB		 1865 }
1866
1867unlock:
9433c188
MB		 1868 if (release_mac != MLX4_IB_INVALID_MAC)
1869 mlx4_unregister_mac(ibdev->dev, port, release_mac);
25476b02
JM		 1870 if (qp)
1871 mutex_unlock(&qp->mutex);
1872 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
9433c188
MB		 1873}
1874
d487ee77
MS		 1875static void mlx4_ib_get_dev_addr(struct net_device *dev,
1876 struct mlx4_ib_dev *ibdev, u8 port)
1877{
1878 struct in_device *in_dev;
27cdef63 1879#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 1880 struct inet6_dev *in6_dev;
1881 union ib_gid *pgid;
1882 struct inet6_ifaddr *ifp;
f5c4834d 1883 union ib_gid default_gid;
d487ee77
MS		 1884#endif
1885 union ib_gid gid;
1886
1887
82373701 1888 if ((port == 0) || (port > ibdev->dev->caps.num_ports))
d487ee77
MS		 1889 return;
1890
1891 /* IPv4 gids */
1892 in_dev = in_dev_get(dev);
1893 if (in_dev) {
1894 for_ifa(in_dev) {
1895 /*ifa->ifa_address;*/
1896 ipv6_addr_set_v4mapped(ifa->ifa_address,
1897 (struct in6_addr *)&gid);
acc4fccf 1898 update_gid_table(ibdev, port, &gid, 0, 0);
d487ee77
MS		 1899 }
1900 endfor_ifa(in_dev);
1901 in_dev_put(in_dev);
1902 }
27cdef63 1903#if IS_ENABLED(CONFIG_IPV6)
f5c4834d 1904 mlx4_make_default_gid(dev, &default_gid);
d487ee77
MS		 1905 /* IPv6 gids */
1906 in6_dev = in6_dev_get(dev);
1907 if (in6_dev) {
1908 read_lock_bh(&in6_dev->lock);
1909 list_for_each_entry(ifp, &in6_dev->addr_list, if_list) {
1910 pgid = (union ib_gid *)&ifp->addr;
f5c4834d
MS		 1911 if (!memcmp(pgid, &default_gid, sizeof(*pgid)))
1912 continue;
acc4fccf 1913 update_gid_table(ibdev, port, pgid, 0, 0);
d487ee77
MS		 1914 }
1915 read_unlock_bh(&in6_dev->lock);
1916 in6_dev_put(in6_dev);
1917 }
1918#endif
1919}
1920
acc4fccf
MS		 1921static void mlx4_ib_set_default_gid(struct mlx4_ib_dev *ibdev,
1922 struct net_device *dev, u8 port)
1923{
1924 union ib_gid gid;
1925 mlx4_make_default_gid(dev, &gid);
1926 update_gid_table(ibdev, port, &gid, 0, 1);
1927}
1928
d487ee77
MS		 1929static int mlx4_ib_init_gid_table(struct mlx4_ib_dev *ibdev)
1930{
1931 struct net_device *dev;
ddf8bd34 1932 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
5071456f 1933 int i;
655b2aae 1934 int err = 0;
d487ee77 1935
655b2aae
MS		 1936 for (i = 1; i <= ibdev->num_ports; ++i) {
1937 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) ==
1938 IB_LINK_LAYER_ETHERNET) {
1939 err = reset_gid_table(ibdev, i);
1940 if (err)
1941 goto out;
1942 }
1943 }
d487ee77
MS		 1944
1945 read_lock(&dev_base_lock);
dba3ad2a 1946 spin_lock_bh(&iboe->lock);
d487ee77
MS		 1947
1948 for_each_netdev(&init_net, dev) {
1949 u8 port = mlx4_ib_get_dev_port(dev, ibdev);
655b2aae
MS		 1950 /* port will be non-zero only for ETH ports */
1951 if (port) {
1952 mlx4_ib_set_default_gid(ibdev, dev, port);
d487ee77 1953 mlx4_ib_get_dev_addr(dev, ibdev, port);
655b2aae 1954 }
d487ee77
MS		 1955 }
1956
dba3ad2a 1957 spin_unlock_bh(&iboe->lock);
d487ee77 1958 read_unlock(&dev_base_lock);
655b2aae
MS		 1959out:
1960 return err;
d487ee77
MS		 1961}
1962
9433c188
MB		 1963static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
1964 struct net_device *dev,
1965 unsigned long event)
1966
d487ee77 1967{
fa417f7b 1968 struct mlx4_ib_iboe *iboe;
9433c188 1969 int update_qps_port = -1;
fa417f7b
EC		 1970 int port;
1971
fa417f7b
EC		 1972 iboe = &ibdev->iboe;
1973
dba3ad2a 1974 spin_lock_bh(&iboe->lock);
fa417f7b 1975 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
ad4885d2 1976 enum ib_port_state port_state = IB_PORT_NOP;
d487ee77 1977 struct net_device *old_master = iboe->masters[port - 1];
ad4885d2 1978 struct net_device *curr_netdev;
d487ee77 1979 struct net_device *curr_master;
ad4885d2 1980
fa417f7b 1981 iboe->netdevs[port - 1] =
0345584e 1982 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
acc4fccf
MS		 1983 if (iboe->netdevs[port - 1])
1984 mlx4_ib_set_default_gid(ibdev,
1985 iboe->netdevs[port - 1], port);
ad4885d2 1986 curr_netdev = iboe->netdevs[port - 1];
d487ee77
MS		 1987
1988 if (iboe->netdevs[port - 1] &&
1989 netif_is_bond_slave(iboe->netdevs[port - 1])) {
d487ee77
MS		 1990 iboe->masters[port - 1] = netdev_master_upper_dev_get(
1991 iboe->netdevs[port - 1]);
ad4885d2
MS		 1992 } else {
1993 iboe->masters[port - 1] = NULL;
fa417f7b 1994 }
d487ee77 1995 curr_master = iboe->masters[port - 1];
fa417f7b 1996
9433c188
MB		 1997 if (dev == iboe->netdevs[port - 1] &&
1998 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
1999 event == NETDEV_UP || event == NETDEV_CHANGE))
2000 update_qps_port = port;
2001
ad4885d2
MS		 2002 if (curr_netdev) {
2003 port_state = (netif_running(curr_netdev) && netif_carrier_ok(curr_netdev)) ?
2004 IB_PORT_ACTIVE : IB_PORT_DOWN;
2005 mlx4_ib_set_default_gid(ibdev, curr_netdev, port);
bccb84f1
MS		 2006 if (curr_master) {
2007 /* if using bonding/team and a slave port is down, we
2008 * don't want the bond IP based gids in the table since
2009 * flows that select port by gid may get the down port.
2010 */
a5750090
MS		 2011 if (port_state == IB_PORT_DOWN &&
2012 !mlx4_is_bonded(ibdev->dev)) {
bccb84f1
MS		 2013 reset_gid_table(ibdev, port);
2014 mlx4_ib_set_default_gid(ibdev,
2015 curr_netdev,
2016 port);
2017 } else {
2018 /* gids from the upper dev (bond/team)
2019 * should appear in port's gid table
2020 */
2021 mlx4_ib_get_dev_addr(curr_master,
2022 ibdev, port);
2023 }
e381835c
MS		 2024 }
2025 /* if bonding is used it is possible that we add it to
2026 * masters only after IP address is assigned to the
2027 * net bonding interface.
2028 */
2029 if (curr_master && (old_master != curr_master)) {
2030 reset_gid_table(ibdev, port);
2031 mlx4_ib_set_default_gid(ibdev,
2032 curr_netdev, port);
2033 mlx4_ib_get_dev_addr(curr_master, ibdev, port);
2034 }
ad4885d2 2035
e381835c
MS		 2036 if (!curr_master && (old_master != curr_master)) {
2037 reset_gid_table(ibdev, port);
2038 mlx4_ib_set_default_gid(ibdev,
2039 curr_netdev, port);
2040 mlx4_ib_get_dev_addr(curr_netdev, ibdev, port);
2041 }
2042 } else {
ad4885d2 2043 reset_gid_table(ibdev, port);
ad4885d2 2044 }
d487ee77 2045 }
fa417f7b 2046
dba3ad2a 2047 spin_unlock_bh(&iboe->lock);
9433c188
MB		 2048
2049 if (update_qps_port > 0)
2050 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
d487ee77
MS		 2051}
2052
2053static int mlx4_ib_netdev_event(struct notifier_block *this,
2054 unsigned long event, void *ptr)
2055{
2056 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2057 struct mlx4_ib_dev *ibdev;
2058
2059 if (!net_eq(dev_net(dev), &init_net))
2060 return NOTIFY_DONE;
2061
2062 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
9433c188 2063 mlx4_ib_scan_netdevs(ibdev, dev, event);
fa417f7b
EC		 2064
2065 return NOTIFY_DONE;
2066}
2067
54679e14
JM		 2068static void init_pkeys(struct mlx4_ib_dev *ibdev)
2069{
2070 int port;
2071 int slave;
2072 int i;
2073
2074 if (mlx4_is_master(ibdev->dev)) {
872bf2fb
YH		 2075 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2076 ++slave) {
54679e14
JM		 2077 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2078 for (i = 0;
2079 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2080 ++i) {
2081 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2082 /* master has the identity virt2phys pkey mapping */
2083 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2084 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2085 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2086 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2087 }
2088 }
2089 }
2090 /* initialize pkey cache */
2091 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2092 for (i = 0;
2093 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2094 ++i)
2095 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2096 (i) ? 0 : 0xFFFF;
2097 }
2098 }
2099}
2100
e605b743
SP		 2101static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2102{
c66fa19c 2103 int i, j, eq = 0, total_eqs = 0;
e605b743 2104
c66fa19c
MB		 2105 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2106 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
e605b743
SP		 2107 if (!ibdev->eq_table)
2108 return;
2109
c66fa19c
MB		 2110 for (i = 1; i <= dev->caps.num_ports; i++) {
2111 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2112 j++, total_eqs++) {
2113 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2114 continue;
2115 ibdev->eq_table[eq] = total_eqs;
2116 if (!mlx4_assign_eq(dev, i,
2117 &ibdev->eq_table[eq]))
2118 eq++;
2119 else
2120 ibdev->eq_table[eq] = -1;
e605b743
SP		 2121 }
2122 }
2123
c66fa19c
MB		 2124 for (i = eq; i < dev->caps.num_comp_vectors;
2125 ibdev->eq_table[i++] = -1)
2126 ;
e605b743
SP		 2127
2128 /* Advertise the new number of EQs to clients */
c66fa19c 2129 ibdev->ib_dev.num_comp_vectors = eq;
e605b743
SP		 2130}
2131
2132static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2133{
2134 int i;
c66fa19c 2135 int total_eqs = ibdev->ib_dev.num_comp_vectors;
3aac6ff1 2136
c66fa19c 2137 /* no eqs were allocated */
3aac6ff1
SP		 2138 if (!ibdev->eq_table)
2139 return;
e605b743
SP		 2140
2141 /* Reset the advertised EQ number */
c66fa19c 2142 ibdev->ib_dev.num_comp_vectors = 0;
e605b743 2143
c66fa19c 2144 for (i = 0; i < total_eqs; i++)
e605b743 2145 mlx4_release_eq(dev, ibdev->eq_table[i]);
e605b743 2146
e605b743 2147 kfree(ibdev->eq_table);
c66fa19c 2148 ibdev->eq_table = NULL;
e605b743
SP		 2149}
2150
7738613e
IW		 2151static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2152 struct ib_port_immutable *immutable)
2153{
2154 struct ib_port_attr attr;
2155 int err;
2156
2157 err = mlx4_ib_query_port(ibdev, port_num, &attr);
2158 if (err)
2159 return err;
2160
2161 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2162 immutable->gid_tbl_len = attr.gid_tbl_len;
2163
f9b22e35
IW		 2164 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND)
2165 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2166 else
2167 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2168
337877a4
IW		 2169 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2170
7738613e
IW		 2171 return 0;
2172}
2173
225c7b1f
RD		 2174static void *mlx4_ib_add(struct mlx4_dev *dev)
2175{
2176 struct mlx4_ib_dev *ibdev;
22e7ef9c 2177 int num_ports = 0;
035b1032 2178 int i, j;
fa417f7b
EC		 2179 int err;
2180 struct mlx4_ib_iboe *iboe;
4196670b 2181 int ib_num_ports = 0;
a5750090 2182 int num_req_counters;
c3abb51b
EBE		 2183 int allocated;
2184 u32 counter_index;
225c7b1f 2185
987c8f8f 2186 pr_info_once("%s", mlx4_ib_version);
68f3948d 2187
026149cb 2188 num_ports = 0;
fa417f7b 2189 mlx4_foreach_ib_transport_port(i, dev)
22e7ef9c
RD		 2190 num_ports++;
2191
2192 /* No point in registering a device with no ports... */
2193 if (num_ports == 0)
2194 return NULL;
2195
225c7b1f
RD		 2196 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2197 if (!ibdev) {
872bf2fb
YH		 2198 dev_err(&dev->persist->pdev->dev,
2199 "Device struct alloc failed\n");
225c7b1f
RD		 2200 return NULL;
2201 }
2202
fa417f7b
EC		 2203 iboe = &ibdev->iboe;
2204
225c7b1f
RD		 2205 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2206 goto err_dealloc;
2207
2208 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2209 goto err_pd;
2210
4979d18f
RD		 2211 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2212 PAGE_SIZE);
225c7b1f
RD		 2213 if (!ibdev->uar_map)
2214 goto err_uar;
26c6bc7b 2215 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
225c7b1f 2216
225c7b1f 2217 ibdev->dev = dev;
c6215745 2218 ibdev->bond_next_port = 0;
225c7b1f
RD		 2219
2220 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2221 ibdev->ib_dev.owner = THIS_MODULE;
2222 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
95d04f07 2223 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
22e7ef9c 2224 ibdev->num_ports = num_ports;
a5750090
MS		 2225 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2226 1 : ibdev->num_ports;
b8dd786f 2227 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
872bf2fb 2228 ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
225c7b1f 2229
08ff3235
OG		 2230 if (dev->caps.userspace_caps)
2231 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2232 else
2233 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2234
225c7b1f
RD		 2235 ibdev->ib_dev.uverbs_cmd_mask =
2236 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2237 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2238 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2239 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2240 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2241 (1ull << IB_USER_VERBS_CMD_REG_MR) |
9376932d 2242 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
225c7b1f
RD		 2243 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2244 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2245 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
bbf8eed1 2246 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
225c7b1f
RD		 2247 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2248 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2249 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6a775e2b 2250 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
225c7b1f
RD		 2251 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2252 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2253 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2254 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2255 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
65541cb7 2256 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
18abd5ea 2257 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
42849b26
SH		 2258 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2259 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
225c7b1f
RD		 2260
2261 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2262 ibdev->ib_dev.query_port = mlx4_ib_query_port;
fa417f7b 2263 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
225c7b1f
RD		 2264 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2265 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2266 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2267 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2268 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2269 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2270 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2271 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2272 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2273 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2274 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2275 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2276 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2277 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
65541cb7 2278 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
225c7b1f
RD		 2279 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2280 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2281 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2282 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
6a775e2b 2283 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
225c7b1f
RD		 2284 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2285 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2286 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2287 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
3fdcb97f 2288 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
bbf8eed1 2289 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
225c7b1f
RD		 2290 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2291 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2292 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2293 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2294 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
9376932d 2295 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
225c7b1f 2296 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
679e34d1 2297 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
95d04f07
RD		 2298 ibdev->ib_dev.alloc_fast_reg_page_list = mlx4_ib_alloc_fast_reg_page_list;
2299 ibdev->ib_dev.free_fast_reg_page_list = mlx4_ib_free_fast_reg_page_list;
225c7b1f
RD		 2300 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2301 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2302 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
7738613e 2303 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
225c7b1f 2304
992e8e6e
JM		 2305 if (!mlx4_is_slave(ibdev->dev)) {
2306 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2307 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2308 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2309 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2310 }
8ad11fb6 2311
b425388d
SM		 2312 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2313 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2314 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2315 ibdev->ib_dev.bind_mw = mlx4_ib_bind_mw;
2316 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2317
2318 ibdev->ib_dev.uverbs_cmd_mask |=
2319 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2320 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2321 }
2322
012a8ff5
SH		 2323 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2324 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2325 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2326 ibdev->ib_dev.uverbs_cmd_mask |=
2327 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2328 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2329 }
2330
f77c0162 2331 if (check_flow_steering_support(dev)) {
0a9b7d59 2332 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
f77c0162
HHZ		 2333 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2334 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2335
f21519b2
YD		 2336 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2337 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2338 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
f77c0162
HHZ		 2339 }
2340
4b664c43
MB		 2341 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2342 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2343 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ);
2344
e605b743
SP		 2345 mlx4_ib_alloc_eqs(dev, ibdev);
2346
fa417f7b
EC		 2347 spin_lock_init(&iboe->lock);
2348
225c7b1f
RD		 2349 if (init_node_data(ibdev))
2350 goto err_map;
2351
a5750090
MS		 2352 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2353 for (i = 0; i < num_req_counters; ++i) {
9433c188 2354 mutex_init(&ibdev->qp1_proxy_lock[i]);
c3abb51b 2355 allocated = 0;
cfcde11c
OG		 2356 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2357 IB_LINK_LAYER_ETHERNET) {
c3abb51b
EBE		 2358 err = mlx4_counter_alloc(ibdev->dev, &counter_index);
2359 /* if failed to allocate a new counter, use default */
cfcde11c 2360 if (err)
c3abb51b
EBE		 2361 counter_index =
2362 mlx4_get_default_counter_index(dev,
2363 i + 1);
2364 else
2365 allocated = 1;
2366 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2367 counter_index = mlx4_get_default_counter_index(dev,
2368 i + 1);
3839d8ac 2369 }
c3abb51b
EBE		 2370 ibdev->counters[i].index = counter_index;
2371 ibdev->counters[i].allocated = allocated;
2372 pr_info("counter index %d for port %d allocated %d\n",
2373 counter_index, i + 1, allocated);
cfcde11c 2374 }
a5750090 2375 if (mlx4_is_bonded(dev))
c3abb51b
EBE		 2376 for (i = 1; i < ibdev->num_ports ; ++i) {
2377 ibdev->counters[i].index = ibdev->counters[0].index;
2378 ibdev->counters[i].allocated = 0;
2379 }
cfcde11c 2380
4196670b
MB		 2381 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2382 ib_num_ports++;
2383
225c7b1f
RD		 2384 spin_lock_init(&ibdev->sm_lock);
2385 mutex_init(&ibdev->cap_mask_mutex);
35f05dab
YH		 2386 INIT_LIST_HEAD(&ibdev->qp_list);
2387 spin_lock_init(&ibdev->reset_flow_resource_lock);
225c7b1f 2388
4196670b
MB		 2389 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2390 ib_num_ports) {
c1c98501
MB		 2391 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2392 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2393 MLX4_IB_UC_STEER_QPN_ALIGN,
ddae0349 2394 &ibdev->steer_qpn_base, 0);
c1c98501
MB		 2395 if (err)
2396 goto err_counter;
2397
2398 ibdev->ib_uc_qpns_bitmap =
2399 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2400 sizeof(long),
2401 GFP_KERNEL);
2402 if (!ibdev->ib_uc_qpns_bitmap) {
872bf2fb
YH		 2403 dev_err(&dev->persist->pdev->dev,
2404 "bit map alloc failed\n");
c1c98501
MB		 2405 goto err_steer_qp_release;
2406 }
2407
2408 bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
2409
2410 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2411 dev, ibdev->steer_qpn_base,
2412 ibdev->steer_qpn_base +
2413 ibdev->steer_qpn_count - 1);
2414 if (err)
2415 goto err_steer_free_bitmap;
2416 }
2417
3e0629cb
JM		 2418 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2419 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2420
9a6edb60 2421 if (ib_register_device(&ibdev->ib_dev, NULL))
c1c98501 2422 goto err_steer_free_bitmap;
225c7b1f
RD		 2423
2424 if (mlx4_ib_mad_init(ibdev))
2425 goto err_reg;
2426
fc06573d
JM		 2427 if (mlx4_ib_init_sriov(ibdev))
2428 goto err_mad;
2429
d487ee77
MS		 2430 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) {
2431 if (!iboe->nb.notifier_call) {
2432 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2433 err = register_netdevice_notifier(&iboe->nb);
2434 if (err) {
2435 iboe->nb.notifier_call = NULL;
2436 goto err_notif;
2437 }
2438 }
2439 if (!iboe->nb_inet.notifier_call) {
2440 iboe->nb_inet.notifier_call = mlx4_ib_inet_event;
2441 err = register_inetaddr_notifier(&iboe->nb_inet);
2442 if (err) {
2443 iboe->nb_inet.notifier_call = NULL;
2444 goto err_notif;
2445 }
2446 }
27cdef63 2447#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 2448 if (!iboe->nb_inet6.notifier_call) {
2449 iboe->nb_inet6.notifier_call = mlx4_ib_inet6_event;
2450 err = register_inet6addr_notifier(&iboe->nb_inet6);
2451 if (err) {
2452 iboe->nb_inet6.notifier_call = NULL;
2453 goto err_notif;
2454 }
2455 }
2456#endif
655b2aae
MS		 2457 if (mlx4_ib_init_gid_table(ibdev))
2458 goto err_notif;
fa417f7b
EC		 2459 }
2460
035b1032 2461 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
f4e91eb4 2462 if (device_create_file(&ibdev->ib_dev.dev,
035b1032 2463 mlx4_class_attributes[j]))
fa417f7b 2464 goto err_notif;
cd9281d8
JM		 2465 }
2466
3b4a8cd5
JM		 2467 ibdev->ib_active = true;
2468
54679e14
JM		 2469 if (mlx4_is_mfunc(ibdev->dev))
2470 init_pkeys(ibdev);
2471
3806d08c
JM		 2472 /* create paravirt contexts for any VFs which are active */
2473 if (mlx4_is_master(ibdev->dev)) {
2474 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2475 if (j == mlx4_master_func_num(ibdev->dev))
2476 continue;
2477 if (mlx4_is_slave_active(ibdev->dev, j))
2478 do_slave_init(ibdev, j, 1);
2479 }
2480 }
225c7b1f
RD		 2481 return ibdev;
2482
fa417f7b 2483err_notif:
d487ee77
MS		 2484 if (ibdev->iboe.nb.notifier_call) {
2485 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2486 pr_warn("failure unregistering notifier\n");
2487 ibdev->iboe.nb.notifier_call = NULL;
2488 }
2489 if (ibdev->iboe.nb_inet.notifier_call) {
2490 if (unregister_inetaddr_notifier(&ibdev->iboe.nb_inet))
2491 pr_warn("failure unregistering notifier\n");
2492 ibdev->iboe.nb_inet.notifier_call = NULL;
2493 }
27cdef63 2494#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 2495 if (ibdev->iboe.nb_inet6.notifier_call) {
2496 if (unregister_inet6addr_notifier(&ibdev->iboe.nb_inet6))
2497 pr_warn("failure unregistering notifier\n");
2498 ibdev->iboe.nb_inet6.notifier_call = NULL;
2499 }
2500#endif
fa417f7b
EC		 2501 flush_workqueue(wq);
2502
fc06573d
JM		 2503 mlx4_ib_close_sriov(ibdev);
2504
2505err_mad:
2506 mlx4_ib_mad_cleanup(ibdev);
2507
225c7b1f
RD		 2508err_reg:
2509 ib_unregister_device(&ibdev->ib_dev);
2510
c1c98501
MB		 2511err_steer_free_bitmap:
2512 kfree(ibdev->ib_uc_qpns_bitmap);
2513
2514err_steer_qp_release:
2515 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2516 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2517 ibdev->steer_qpn_count);
cfcde11c 2518err_counter:
c3abb51b
EBE		 2519 for (i = 0; i < ibdev->num_ports; ++i) {
2520 if (ibdev->counters[i].index != -1 &&
2521 ibdev->counters[i].allocated)
2522 mlx4_counter_free(ibdev->dev,
2523 ibdev->counters[i].index);
2524 }
225c7b1f
RD		 2525err_map:
2526 iounmap(ibdev->uar_map);
2527
2528err_uar:
2529 mlx4_uar_free(dev, &ibdev->priv_uar);
2530
2531err_pd:
2532 mlx4_pd_free(dev, ibdev->priv_pdn);
2533
2534err_dealloc:
2535 ib_dealloc_device(&ibdev->ib_dev);
2536
2537 return NULL;
2538}
2539
c1c98501
MB		 2540int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2541{
2542 int offset;
2543
2544 WARN_ON(!dev->ib_uc_qpns_bitmap);
2545
2546 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2547 dev->steer_qpn_count,
2548 get_count_order(count));
2549 if (offset < 0)
2550 return offset;
2551
2552 *qpn = dev->steer_qpn_base + offset;
2553 return 0;
2554}
2555
2556void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2557{
2558 if (!qpn ||
2559 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2560 return;
2561
2562 BUG_ON(qpn < dev->steer_qpn_base);
2563
2564 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2565 qpn - dev->steer_qpn_base,
2566 get_count_order(count));
2567}
2568
2569int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2570 int is_attach)
2571{
2572 int err;
2573 size_t flow_size;
2574 struct ib_flow_attr *flow = NULL;
2575 struct ib_flow_spec_ib *ib_spec;
2576
2577 if (is_attach) {
2578 flow_size = sizeof(struct ib_flow_attr) +
2579 sizeof(struct ib_flow_spec_ib);
2580 flow = kzalloc(flow_size, GFP_KERNEL);
2581 if (!flow)
2582 return -ENOMEM;
2583 flow->port = mqp->port;
2584 flow->num_of_specs = 1;
2585 flow->size = flow_size;
2586 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2587 ib_spec->type = IB_FLOW_SPEC_IB;
2588 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2589 /* Add an empty rule for IB L2 */
2590 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2591
2592 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
2593 IB_FLOW_DOMAIN_NIC,
2594 MLX4_FS_REGULAR,
2595 &mqp->reg_id);
2596 } else {
2597 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
2598 }
2599 kfree(flow);
2600 return err;
2601}
2602
225c7b1f
RD		 2603static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
2604{
2605 struct mlx4_ib_dev *ibdev = ibdev_ptr;
2606 int p;
2607
4bf9715f
MS		 2608 ibdev->ib_active = false;
2609 flush_workqueue(wq);
2610
fc06573d 2611 mlx4_ib_close_sriov(ibdev);
a6a47771
YP		 2612 mlx4_ib_mad_cleanup(ibdev);
2613 ib_unregister_device(&ibdev->ib_dev);
fa417f7b
EC		 2614 if (ibdev->iboe.nb.notifier_call) {
2615 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
987c8f8f 2616 pr_warn("failure unregistering notifier\n");
fa417f7b
EC		 2617 ibdev->iboe.nb.notifier_call = NULL;
2618 }
c1c98501
MB		 2619
2620 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
2621 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2622 ibdev->steer_qpn_count);
2623 kfree(ibdev->ib_uc_qpns_bitmap);
2624 }
2625
d487ee77
MS		 2626 if (ibdev->iboe.nb_inet.notifier_call) {
2627 if (unregister_inetaddr_notifier(&ibdev->iboe.nb_inet))
2628 pr_warn("failure unregistering notifier\n");
2629 ibdev->iboe.nb_inet.notifier_call = NULL;
2630 }
27cdef63 2631#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 2632 if (ibdev->iboe.nb_inet6.notifier_call) {
2633 if (unregister_inet6addr_notifier(&ibdev->iboe.nb_inet6))
2634 pr_warn("failure unregistering notifier\n");
2635 ibdev->iboe.nb_inet6.notifier_call = NULL;
2636 }
2637#endif
fb1b5034 2638
fa417f7b 2639 iounmap(ibdev->uar_map);
cfcde11c 2640 for (p = 0; p < ibdev->num_ports; ++p)
c3abb51b
EBE		 2641 if (ibdev->counters[p].index != -1 &&
2642 ibdev->counters[p].allocated)
2643 mlx4_counter_free(ibdev->dev, ibdev->counters[p].index);
fa417f7b 2644 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
225c7b1f
RD		 2645 mlx4_CLOSE_PORT(dev, p);
2646
e605b743
SP		 2647 mlx4_ib_free_eqs(dev, ibdev);
2648
225c7b1f
RD		 2649 mlx4_uar_free(dev, &ibdev->priv_uar);
2650 mlx4_pd_free(dev, ibdev->priv_pdn);
2651 ib_dealloc_device(&ibdev->ib_dev);
2652}
2653
fc06573d
JM		 2654static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
2655{
2656 struct mlx4_ib_demux_work **dm = NULL;
2657 struct mlx4_dev *dev = ibdev->dev;
2658 int i;
2659 unsigned long flags;
449fc488
MB		 2660 struct mlx4_active_ports actv_ports;
2661 unsigned int ports;
2662 unsigned int first_port;
fc06573d
JM		 2663
2664 if (!mlx4_is_master(dev))
2665 return;
2666
449fc488
MB		 2667 actv_ports = mlx4_get_active_ports(dev, slave);
2668 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2669 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2670
2671 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
fc06573d
JM		 2672 if (!dm) {
2673 pr_err("failed to allocate memory for tunneling qp update\n");
a39a98ff 2674 return;
fc06573d
JM		 2675 }
2676
449fc488 2677 for (i = 0; i < ports; i++) {
fc06573d
JM		 2678 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
2679 if (!dm[i]) {
2680 pr_err("failed to allocate memory for tunneling qp update work struct\n");
a39a98ff
MS		 2681 while (--i >= 0)
2682 kfree(dm[i]);
fc06573d
JM		 2683 goto out;
2684 }
fc06573d 2685 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
449fc488 2686 dm[i]->port = first_port + i + 1;
fc06573d
JM		 2687 dm[i]->slave = slave;
2688 dm[i]->do_init = do_init;
2689 dm[i]->dev = ibdev;
d9a047ae
DL		 2690 }
2691 /* initialize or tear down tunnel QPs for the slave */
2692 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
2693 if (!ibdev->sriov.is_going_down) {
2694 for (i = 0; i < ports; i++)
fc06573d
JM		 2695 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
2696 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
d9a047ae
DL		 2697 } else {
2698 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
2699 for (i = 0; i < ports; i++)
2700 kfree(dm[i]);
fc06573d
JM		 2701 }
2702out:
c89d1271 2703 kfree(dm);
fc06573d
JM		 2704 return;
2705}
2706
35f05dab
YH		 2707static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
2708{
2709 struct mlx4_ib_qp *mqp;
2710 unsigned long flags_qp;
2711 unsigned long flags_cq;
2712 struct mlx4_ib_cq *send_mcq, *recv_mcq;
2713 struct list_head cq_notify_list;
2714 struct mlx4_cq *mcq;
2715 unsigned long flags;
2716
2717 pr_warn("mlx4_ib_handle_catas_error was started\n");
2718 INIT_LIST_HEAD(&cq_notify_list);
2719
2720 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2721 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2722
2723 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2724 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2725 if (mqp->sq.tail != mqp->sq.head) {
2726 send_mcq = to_mcq(mqp->ibqp.send_cq);
2727 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2728 if (send_mcq->mcq.comp &&
2729 mqp->ibqp.send_cq->comp_handler) {
2730 if (!send_mcq->mcq.reset_notify_added) {
2731 send_mcq->mcq.reset_notify_added = 1;
2732 list_add_tail(&send_mcq->mcq.reset_notify,
2733 &cq_notify_list);
2734 }
2735 }
2736 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2737 }
2738 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2739 /* Now, handle the QP's receive queue */
2740 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2741 /* no handling is needed for SRQ */
2742 if (!mqp->ibqp.srq) {
2743 if (mqp->rq.tail != mqp->rq.head) {
2744 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2745 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2746 if (recv_mcq->mcq.comp &&
2747 mqp->ibqp.recv_cq->comp_handler) {
2748 if (!recv_mcq->mcq.reset_notify_added) {
2749 recv_mcq->mcq.reset_notify_added = 1;
2750 list_add_tail(&recv_mcq->mcq.reset_notify,
2751 &cq_notify_list);
2752 }
2753 }
2754 spin_unlock_irqrestore(&recv_mcq->lock,
2755 flags_cq);
2756 }
2757 }
2758 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2759 }
2760
2761 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
2762 mcq->comp(mcq);
2763 }
2764 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2765 pr_warn("mlx4_ib_handle_catas_error ended\n");
2766}
2767
a5750090
MS		 2768static void handle_bonded_port_state_event(struct work_struct *work)
2769{
2770 struct ib_event_work *ew =
2771 container_of(work, struct ib_event_work, work);
2772 struct mlx4_ib_dev *ibdev = ew->ib_dev;
2773 enum ib_port_state bonded_port_state = IB_PORT_NOP;
2774 int i;
2775 struct ib_event ibev;
2776
2777 kfree(ew);
2778 spin_lock_bh(&ibdev->iboe.lock);
2779 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
2780 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
217e8b16 2781 enum ib_port_state curr_port_state;
a5750090 2782
217e8b16
MS		 2783 if (!curr_netdev)
2784 continue;
2785
2786 curr_port_state =
a5750090
MS		 2787 (netif_running(curr_netdev) &&
2788 netif_carrier_ok(curr_netdev)) ?
2789 IB_PORT_ACTIVE : IB_PORT_DOWN;
2790
2791 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
2792 curr_port_state : IB_PORT_ACTIVE;
2793 }
2794 spin_unlock_bh(&ibdev->iboe.lock);
2795
2796 ibev.device = &ibdev->ib_dev;
2797 ibev.element.port_num = 1;
2798 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
2799 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2800
2801 ib_dispatch_event(&ibev);
2802}
2803
225c7b1f 2804static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
00f5ce99 2805 enum mlx4_dev_event event, unsigned long param)
225c7b1f
RD		 2806{
2807 struct ib_event ibev;
7ff93f8b 2808 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
00f5ce99
JM		 2809 struct mlx4_eqe *eqe = NULL;
2810 struct ib_event_work *ew;
fc06573d 2811 int p = 0;
00f5ce99 2812
a5750090
MS		 2813 if (mlx4_is_bonded(dev) &&
2814 ((event == MLX4_DEV_EVENT_PORT_UP) ||
2815 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
2816 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
2817 if (!ew)
2818 return;
2819 INIT_WORK(&ew->work, handle_bonded_port_state_event);
2820 ew->ib_dev = ibdev;
2821 queue_work(wq, &ew->work);
2822 return;
2823 }
2824
00f5ce99
JM		 2825 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
2826 eqe = (struct mlx4_eqe *)param;
2827 else
fc06573d 2828 p = (int) param;
225c7b1f
RD		 2829
2830 switch (event) {
37608eea 2831 case MLX4_DEV_EVENT_PORT_UP:
fc06573d
JM		 2832 if (p > ibdev->num_ports)
2833 return;
a0c64a17
JM		 2834 if (mlx4_is_master(dev) &&
2835 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
2836 IB_LINK_LAYER_INFINIBAND) {
2837 mlx4_ib_invalidate_all_guid_record(ibdev, p);
2838 }
37608eea 2839 ibev.event = IB_EVENT_PORT_ACTIVE;
225c7b1f
RD		 2840 break;
2841
37608eea 2842 case MLX4_DEV_EVENT_PORT_DOWN:
fc06573d
JM		 2843 if (p > ibdev->num_ports)
2844 return;
37608eea
RD		 2845 ibev.event = IB_EVENT_PORT_ERR;
2846 break;
2847
2848 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3b4a8cd5 2849 ibdev->ib_active = false;
225c7b1f 2850 ibev.event = IB_EVENT_DEVICE_FATAL;
35f05dab 2851 mlx4_ib_handle_catas_error(ibdev);
225c7b1f
RD		 2852 break;
2853
00f5ce99
JM		 2854 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
2855 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
2856 if (!ew) {
2857 pr_err("failed to allocate memory for events work\n");
2858 break;
2859 }
2860
2861 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
2862 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
2863 ew->ib_dev = ibdev;
992e8e6e
JM		 2864 /* need to queue only for port owner, which uses GEN_EQE */
2865 if (mlx4_is_master(dev))
2866 queue_work(wq, &ew->work);
2867 else
2868 handle_port_mgmt_change_event(&ew->work);
00f5ce99
JM		 2869 return;
2870
fc06573d
JM		 2871 case MLX4_DEV_EVENT_SLAVE_INIT:
2872 /* here, p is the slave id */
2873 do_slave_init(ibdev, p, 1);
ee59fa0d
YH		 2874 if (mlx4_is_master(dev)) {
2875 int i;
2876
2877 for (i = 1; i <= ibdev->num_ports; i++) {
2878 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
2879 == IB_LINK_LAYER_INFINIBAND)
2880 mlx4_ib_slave_alias_guid_event(ibdev,
2881 p, i,
2882 1);
2883 }
2884 }
fc06573d
JM		 2885 return;
2886
2887 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
ee59fa0d
YH		 2888 if (mlx4_is_master(dev)) {
2889 int i;
2890
2891 for (i = 1; i <= ibdev->num_ports; i++) {
2892 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
2893 == IB_LINK_LAYER_INFINIBAND)
2894 mlx4_ib_slave_alias_guid_event(ibdev,
2895 p, i,
2896 0);
2897 }
2898 }
fc06573d
JM		 2899 /* here, p is the slave id */
2900 do_slave_init(ibdev, p, 0);
2901 return;
2902
225c7b1f
RD		 2903 default:
2904 return;
2905 }
2906
2907 ibev.device = ibdev_ptr;
a5750090 2908 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
225c7b1f
RD		 2909
2910 ib_dispatch_event(&ibev);
2911}
2912
2913static struct mlx4_interface mlx4_ib_interface = {
fa417f7b
EC		 2914 .add = mlx4_ib_add,
2915 .remove = mlx4_ib_remove,
2916 .event = mlx4_ib_event,
a5750090
MS		 2917 .protocol = MLX4_PROT_IB_IPV6,
2918 .flags = MLX4_INTFF_BONDING
225c7b1f
RD		 2919};
2920
2921static int __init mlx4_ib_init(void)
2922{
fa417f7b
EC		 2923 int err;
2924
2925 wq = create_singlethread_workqueue("mlx4_ib");
2926 if (!wq)
2927 return -ENOMEM;
2928
b9c5d6a6
OD		 2929 err = mlx4_ib_mcg_init();
2930 if (err)
2931 goto clean_wq;
2932
fa417f7b 2933 err = mlx4_register_interface(&mlx4_ib_interface);
b9c5d6a6
OD		 2934 if (err)
2935 goto clean_mcg;
fa417f7b
EC		 2936
2937 return 0;
b9c5d6a6
OD		 2938
2939clean_mcg:
2940 mlx4_ib_mcg_destroy();
2941
2942clean_wq:
2943 destroy_workqueue(wq);
2944 return err;
225c7b1f
RD		 2945}
2946
2947static void __exit mlx4_ib_cleanup(void)
2948{
2949 mlx4_unregister_interface(&mlx4_ib_interface);
b9c5d6a6 2950 mlx4_ib_mcg_destroy();
fa417f7b 2951 destroy_workqueue(wq);
225c7b1f
RD		 2952}
2953
2954module_init(mlx4_ib_init);
2955module_exit(mlx4_ib_cleanup);
Linux kernel - Deliverables
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