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net/mlx4: Avoid dealing with MAC index in UPDATE_QP wrapper if not needed
[deliverable/linux.git] / drivers / infiniband / hw / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/module.h>
35#include <linux/init.h>
5a0e3ad6 36#include <linux/slab.h>
225c7b1f 37#include <linux/errno.h>
fa417f7b
EC		 38#include <linux/netdevice.h>
39#include <linux/inetdevice.h>
40#include <linux/rtnetlink.h>
4c3eb3ca 41#include <linux/if_vlan.h>
d487ee77
MS		 42#include <net/ipv6.h>
43#include <net/addrconf.h>
225c7b1f
RD		 44
45#include <rdma/ib_smi.h>
46#include <rdma/ib_user_verbs.h>
fa417f7b 47#include <rdma/ib_addr.h>
225c7b1f
RD		 48
49#include <linux/mlx4/driver.h>
50#include <linux/mlx4/cmd.h>
9433c188 51#include <linux/mlx4/qp.h>
225c7b1f
RD		 52
53#include "mlx4_ib.h"
54#include "user.h"
55
b1d8eb5a 56#define DRV_NAME MLX4_IB_DRV_NAME
169a1d85
AV		 57#define DRV_VERSION "2.2-1"
58#define DRV_RELDATE "Feb 2014"
225c7b1f 59
f77c0162 60#define MLX4_IB_FLOW_MAX_PRIO 0xFFF
a37a1a42 61#define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
f77c0162 62
225c7b1f
RD		 63MODULE_AUTHOR("Roland Dreier");
64MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
65MODULE_LICENSE("Dual BSD/GPL");
66MODULE_VERSION(DRV_VERSION);
67
a0c64a17
JM		 68int mlx4_ib_sm_guid_assign = 1;
69module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
70MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 1)");
71
68f3948d 72static const char mlx4_ib_version[] =
225c7b1f
RD		 73 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
74 DRV_VERSION " (" DRV_RELDATE ")\n";
75
fa417f7b
EC		 76struct update_gid_work {
77 struct work_struct work;
78 union ib_gid gids[128];
79 struct mlx4_ib_dev *dev;
80 int port;
81};
82
3806d08c
JM		 83static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
84
fa417f7b
EC		 85static struct workqueue_struct *wq;
86
225c7b1f
RD		 87static void init_query_mad(struct ib_smp *mad)
88{
89 mad->base_version = 1;
90 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
91 mad->class_version = 1;
92 mad->method = IB_MGMT_METHOD_GET;
93}
94
4c3eb3ca
EC		 95static union ib_gid zgid;
96
f77c0162
HHZ		 97static int check_flow_steering_support(struct mlx4_dev *dev)
98{
0a9b7d59 99 int eth_num_ports = 0;
f77c0162 100 int ib_num_ports = 0;
f77c0162 101
0a9b7d59
MB		 102 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
103
104 if (dmfs) {
105 int i;
106 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
107 eth_num_ports++;
108 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
109 ib_num_ports++;
110 dmfs &= (!ib_num_ports ||
111 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
112 (!eth_num_ports ||
113 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
114 if (ib_num_ports && mlx4_is_mfunc(dev)) {
115 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
116 dmfs = 0;
f77c0162 117 }
f77c0162 118 }
0a9b7d59 119 return dmfs;
f77c0162
HHZ		 120}
121
225c7b1f
RD		 122static int mlx4_ib_query_device(struct ib_device *ibdev,
123 struct ib_device_attr *props)
124{
125 struct mlx4_ib_dev *dev = to_mdev(ibdev);
126 struct ib_smp *in_mad = NULL;
127 struct ib_smp *out_mad = NULL;
128 int err = -ENOMEM;
129
130 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
131 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
132 if (!in_mad || !out_mad)
133 goto out;
134
135 init_query_mad(in_mad);
136 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
137
0a9a0188
JM		 138 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
139 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 140 if (err)
141 goto out;
142
143 memset(props, 0, sizeof *props);
144
145 props->fw_ver = dev->dev->caps.fw_ver;
146 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
147 IB_DEVICE_PORT_ACTIVE_EVENT |
148 IB_DEVICE_SYS_IMAGE_GUID |
521e575b
RL		 149 IB_DEVICE_RC_RNR_NAK_GEN |
150 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
225c7b1f
RD		 151 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
152 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
153 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
154 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
155 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM)
156 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
157 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
158 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
8ff095ec
EC		 159 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
160 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
417608c2 161 if (dev->dev->caps.max_gso_sz && dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)
b832be1e 162 props->device_cap_flags |= IB_DEVICE_UD_TSO;
95d04f07
RD		 163 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
164 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
165 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
166 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
167 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
168 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
0a1405da
SH		 169 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
170 props->device_cap_flags |= IB_DEVICE_XRC;
b425388d
SM		 171 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
172 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
173 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
174 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
175 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
176 else
177 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
0a9b7d59 178 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
f77c0162 179 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
b425388d 180 }
225c7b1f
RD		 181
182 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
183 0xffffff;
992e8e6e 184 props->vendor_part_id = dev->dev->pdev->device;
225c7b1f
RD		 185 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
186 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
187
188 props->max_mr_size = ~0ull;
189 props->page_size_cap = dev->dev->caps.page_size_cap;
5a0d0a61 190 props->max_qp = dev->dev->quotas.qp;
fc2d0044 191 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
225c7b1f
RD		 192 props->max_sge = min(dev->dev->caps.max_sq_sg,
193 dev->dev->caps.max_rq_sg);
5a0d0a61 194 props->max_cq = dev->dev->quotas.cq;
225c7b1f 195 props->max_cqe = dev->dev->caps.max_cqes;
5a0d0a61 196 props->max_mr = dev->dev->quotas.mpt;
225c7b1f
RD		 197 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
198 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
199 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
200 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
5a0d0a61 201 props->max_srq = dev->dev->quotas.srq;
c8681f14 202 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
225c7b1f 203 props->max_srq_sge = dev->dev->caps.max_srq_sge;
5a0fd094 204 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
225c7b1f
RD		 205 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
206 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
207 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
47e956b2 208 props->masked_atomic_cap = props->atomic_cap;
5ae2a7a8 209 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
225c7b1f
RD		 210 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
211 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
212 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
213 props->max_mcast_grp;
a5bbe892 214 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
225c7b1f
RD		 215
216out:
217 kfree(in_mad);
218 kfree(out_mad);
219
220 return err;
221}
222
fa417f7b
EC		 223static enum rdma_link_layer
224mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
225c7b1f 225{
fa417f7b 226 struct mlx4_dev *dev = to_mdev(device)->dev;
225c7b1f 227
65dab25d 228 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
fa417f7b
EC		 229 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
230}
225c7b1f 231
fa417f7b 232static int ib_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 233 struct ib_port_attr *props, int netw_view)
fa417f7b 234{
a9c766bb
OG		 235 struct ib_smp *in_mad = NULL;
236 struct ib_smp *out_mad = NULL;
a5e12dff 237 int ext_active_speed;
0a9a0188 238 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
a9c766bb
OG		 239 int err = -ENOMEM;
240
241 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
242 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
243 if (!in_mad || !out_mad)
244 goto out;
245
246 init_query_mad(in_mad);
247 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
248 in_mad->attr_mod = cpu_to_be32(port);
249
0a9a0188
JM		 250 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
251 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
252
253 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
a9c766bb
OG		 254 in_mad, out_mad);
255 if (err)
256 goto out;
257
a5e12dff 258
225c7b1f
RD		 259 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
260 props->lmc = out_mad->data[34] & 0x7;
261 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
262 props->sm_sl = out_mad->data[36] & 0xf;
263 props->state = out_mad->data[32] & 0xf;
264 props->phys_state = out_mad->data[33] >> 4;
265 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
0a9a0188
JM		 266 if (netw_view)
267 props->gid_tbl_len = out_mad->data[50];
268 else
269 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
149983af 270 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
5ae2a7a8 271 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
225c7b1f
RD		 272 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
273 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
274 props->active_width = out_mad->data[31] & 0xf;
275 props->active_speed = out_mad->data[35] >> 4;
276 props->max_mtu = out_mad->data[41] & 0xf;
277 props->active_mtu = out_mad->data[36] >> 4;
278 props->subnet_timeout = out_mad->data[51] & 0x1f;
279 props->max_vl_num = out_mad->data[37] >> 4;
280 props->init_type_reply = out_mad->data[41] >> 4;
281
a5e12dff
MA		 282 /* Check if extended speeds (EDR/FDR/...) are supported */
283 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
284 ext_active_speed = out_mad->data[62] >> 4;
285
286 switch (ext_active_speed) {
287 case 1:
2e96691c 288 props->active_speed = IB_SPEED_FDR;
a5e12dff
MA		 289 break;
290 case 2:
2e96691c 291 props->active_speed = IB_SPEED_EDR;
a5e12dff
MA		 292 break;
293 }
294 }
295
296 /* If reported active speed is QDR, check if is FDR-10 */
2e96691c 297 if (props->active_speed == IB_SPEED_QDR) {
8154c07f
OG		 298 init_query_mad(in_mad);
299 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
300 in_mad->attr_mod = cpu_to_be32(port);
301
0a9a0188 302 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
8154c07f
OG		 303 NULL, NULL, in_mad, out_mad);
304 if (err)
bf6b47de 305 goto out;
8154c07f
OG		 306
307 /* Checking LinkSpeedActive for FDR-10 */
308 if (out_mad->data[15] & 0x1)
309 props->active_speed = IB_SPEED_FDR10;
a5e12dff 310 }
d2ef4068
OG		 311
312 /* Avoid wrong speed value returned by FW if the IB link is down. */
313 if (props->state == IB_PORT_DOWN)
314 props->active_speed = IB_SPEED_SDR;
315
a9c766bb
OG		 316out:
317 kfree(in_mad);
318 kfree(out_mad);
319 return err;
fa417f7b
EC		 320}
321
322static u8 state_to_phys_state(enum ib_port_state state)
323{
324 return state == IB_PORT_ACTIVE ? 5 : 3;
325}
326
327static int eth_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 328 struct ib_port_attr *props, int netw_view)
fa417f7b 329{
a9c766bb
OG		 330
331 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
332 struct mlx4_ib_iboe *iboe = &mdev->iboe;
fa417f7b
EC		 333 struct net_device *ndev;
334 enum ib_mtu tmp;
a9c766bb
OG		 335 struct mlx4_cmd_mailbox *mailbox;
336 int err = 0;
337
338 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
339 if (IS_ERR(mailbox))
340 return PTR_ERR(mailbox);
fa417f7b 341
a9c766bb
OG		 342 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
343 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
344 MLX4_CMD_WRAPPED);
345 if (err)
346 goto out;
347
348 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ?
349 IB_WIDTH_4X : IB_WIDTH_1X;
2e96691c 350 props->active_speed = IB_SPEED_QDR;
b4a26a27 351 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
a9c766bb
OG		 352 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
353 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
fa417f7b 354 props->pkey_tbl_len = 1;
bcacb897 355 props->max_mtu = IB_MTU_4096;
a9c766bb 356 props->max_vl_num = 2;
fa417f7b
EC		 357 props->state = IB_PORT_DOWN;
358 props->phys_state = state_to_phys_state(props->state);
359 props->active_mtu = IB_MTU_256;
360 spin_lock(&iboe->lock);
361 ndev = iboe->netdevs[port - 1];
362 if (!ndev)
a9c766bb 363 goto out_unlock;
fa417f7b
EC		 364
365 tmp = iboe_get_mtu(ndev->mtu);
366 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
367
21d60609 368 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
fa417f7b
EC		 369 IB_PORT_ACTIVE : IB_PORT_DOWN;
370 props->phys_state = state_to_phys_state(props->state);
a9c766bb 371out_unlock:
fa417f7b 372 spin_unlock(&iboe->lock);
a9c766bb
OG		 373out:
374 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
375 return err;
fa417f7b
EC		 376}
377
0a9a0188
JM		 378int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
379 struct ib_port_attr *props, int netw_view)
fa417f7b 380{
a9c766bb 381 int err;
fa417f7b
EC		 382
383 memset(props, 0, sizeof *props);
384
fa417f7b 385 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
0a9a0188
JM		 386 ib_link_query_port(ibdev, port, props, netw_view) :
387 eth_link_query_port(ibdev, port, props, netw_view);
225c7b1f
RD		 388
389 return err;
390}
391
0a9a0188
JM		 392static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
393 struct ib_port_attr *props)
394{
395 /* returns host view */
396 return __mlx4_ib_query_port(ibdev, port, props, 0);
397}
398
a0c64a17
JM		 399int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
400 union ib_gid *gid, int netw_view)
225c7b1f
RD		 401{
402 struct ib_smp *in_mad = NULL;
403 struct ib_smp *out_mad = NULL;
404 int err = -ENOMEM;
a0c64a17
JM		 405 struct mlx4_ib_dev *dev = to_mdev(ibdev);
406 int clear = 0;
407 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 408
409 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
410 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
411 if (!in_mad || !out_mad)
412 goto out;
413
414 init_query_mad(in_mad);
415 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
416 in_mad->attr_mod = cpu_to_be32(port);
417
a0c64a17
JM		 418 if (mlx4_is_mfunc(dev->dev) && netw_view)
419 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
420
421 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 422 if (err)
423 goto out;
424
425 memcpy(gid->raw, out_mad->data + 8, 8);
426
a0c64a17
JM		 427 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
428 if (index) {
429 /* For any index > 0, return the null guid */
430 err = 0;
431 clear = 1;
432 goto out;
433 }
434 }
435
225c7b1f
RD		 436 init_query_mad(in_mad);
437 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
438 in_mad->attr_mod = cpu_to_be32(index / 8);
439
a0c64a17 440 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
0a9a0188 441 NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 442 if (err)
443 goto out;
444
445 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
446
447out:
a0c64a17
JM		 448 if (clear)
449 memset(gid->raw + 8, 0, 8);
225c7b1f
RD		 450 kfree(in_mad);
451 kfree(out_mad);
452 return err;
453}
454
fa417f7b
EC		 455static int iboe_query_gid(struct ib_device *ibdev, u8 port, int index,
456 union ib_gid *gid)
457{
458 struct mlx4_ib_dev *dev = to_mdev(ibdev);
459
460 *gid = dev->iboe.gid_table[port - 1][index];
461
462 return 0;
463}
464
465static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
466 union ib_gid *gid)
467{
468 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
a0c64a17 469 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
fa417f7b
EC		 470 else
471 return iboe_query_gid(ibdev, port, index, gid);
472}
473
0a9a0188
JM		 474int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
475 u16 *pkey, int netw_view)
225c7b1f
RD		 476{
477 struct ib_smp *in_mad = NULL;
478 struct ib_smp *out_mad = NULL;
0a9a0188 479 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 480 int err = -ENOMEM;
481
482 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
483 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
484 if (!in_mad || !out_mad)
485 goto out;
486
487 init_query_mad(in_mad);
488 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
489 in_mad->attr_mod = cpu_to_be32(index / 32);
490
0a9a0188
JM		 491 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
492 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
493
494 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
495 in_mad, out_mad);
225c7b1f
RD		 496 if (err)
497 goto out;
498
499 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
500
501out:
502 kfree(in_mad);
503 kfree(out_mad);
504 return err;
505}
506
0a9a0188
JM		 507static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
508{
509 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
510}
511
225c7b1f
RD		 512static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
513 struct ib_device_modify *props)
514{
d0d68b86 515 struct mlx4_cmd_mailbox *mailbox;
df7fba66 516 unsigned long flags;
d0d68b86 517
225c7b1f
RD		 518 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
519 return -EOPNOTSUPP;
520
d0d68b86
JM		 521 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
522 return 0;
523
992e8e6e
JM		 524 if (mlx4_is_slave(to_mdev(ibdev)->dev))
525 return -EOPNOTSUPP;
526
df7fba66 527 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86 528 memcpy(ibdev->node_desc, props->node_desc, 64);
df7fba66 529 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86
JM		 530
531 /*
532 * If possible, pass node desc to FW, so it can generate
533 * a 144 trap. If cmd fails, just ignore.
534 */
535 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
536 if (IS_ERR(mailbox))
537 return 0;
538
d0d68b86
JM		 539 memcpy(mailbox->buf, props->node_desc, 64);
540 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
992e8e6e 541 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
d0d68b86
JM		 542
543 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
225c7b1f
RD		 544
545 return 0;
546}
547
61565013
JM		 548static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
549 u32 cap_mask)
225c7b1f
RD		 550{
551 struct mlx4_cmd_mailbox *mailbox;
552 int err;
553
554 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
555 if (IS_ERR(mailbox))
556 return PTR_ERR(mailbox);
557
5ae2a7a8
RD		 558 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
559 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
560 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
561 } else {
562 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
563 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
564 }
225c7b1f 565
61565013
JM		 566 err = mlx4_cmd(dev->dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
567 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
225c7b1f
RD		 568
569 mlx4_free_cmd_mailbox(dev->dev, mailbox);
570 return err;
571}
572
573static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
574 struct ib_port_modify *props)
575{
61565013
JM		 576 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
577 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
225c7b1f
RD		 578 struct ib_port_attr attr;
579 u32 cap_mask;
580 int err;
581
61565013
JM		 582 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
583 * of whether port link layer is ETH or IB. For ETH ports, qkey
584 * violations and port capabilities are not meaningful.
585 */
586 if (is_eth)
587 return 0;
588
589 mutex_lock(&mdev->cap_mask_mutex);
225c7b1f
RD		 590
591 err = mlx4_ib_query_port(ibdev, port, &attr);
592 if (err)
593 goto out;
594
595 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
596 ~props->clr_port_cap_mask;
597
61565013
JM		 598 err = mlx4_ib_SET_PORT(mdev, port,
599 !!(mask & IB_PORT_RESET_QKEY_CNTR),
600 cap_mask);
225c7b1f
RD		 601
602out:
603 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
604 return err;
605}
606
607static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
608 struct ib_udata *udata)
609{
610 struct mlx4_ib_dev *dev = to_mdev(ibdev);
611 struct mlx4_ib_ucontext *context;
08ff3235 612 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
225c7b1f
RD		 613 struct mlx4_ib_alloc_ucontext_resp resp;
614 int err;
615
3b4a8cd5
JM		 616 if (!dev->ib_active)
617 return ERR_PTR(-EAGAIN);
618
08ff3235
OG		 619 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
620 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
621 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
622 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
623 } else {
624 resp.dev_caps = dev->dev->caps.userspace_caps;
625 resp.qp_tab_size = dev->dev->caps.num_qps;
626 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
627 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
628 resp.cqe_size = dev->dev->caps.cqe_size;
629 }
225c7b1f
RD		 630
631 context = kmalloc(sizeof *context, GFP_KERNEL);
632 if (!context)
633 return ERR_PTR(-ENOMEM);
634
635 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
636 if (err) {
637 kfree(context);
638 return ERR_PTR(err);
639 }
640
641 INIT_LIST_HEAD(&context->db_page_list);
642 mutex_init(&context->db_page_mutex);
643
08ff3235
OG		 644 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
645 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
646 else
647 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
648
225c7b1f
RD		 649 if (err) {
650 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
651 kfree(context);
652 return ERR_PTR(-EFAULT);
653 }
654
655 return &context->ibucontext;
656}
657
658static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
659{
660 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
661
662 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
663 kfree(context);
664
665 return 0;
666}
667
668static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
669{
670 struct mlx4_ib_dev *dev = to_mdev(context->device);
671
672 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
673 return -EINVAL;
674
675 if (vma->vm_pgoff == 0) {
676 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
677
678 if (io_remap_pfn_range(vma, vma->vm_start,
679 to_mucontext(context)->uar.pfn,
680 PAGE_SIZE, vma->vm_page_prot))
681 return -EAGAIN;
682 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
e1d60ec6 683 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
225c7b1f
RD		 684
685 if (io_remap_pfn_range(vma, vma->vm_start,
686 to_mucontext(context)->uar.pfn +
687 dev->dev->caps.num_uars,
688 PAGE_SIZE, vma->vm_page_prot))
689 return -EAGAIN;
690 } else
691 return -EINVAL;
692
693 return 0;
694}
695
696static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
697 struct ib_ucontext *context,
698 struct ib_udata *udata)
699{
700 struct mlx4_ib_pd *pd;
701 int err;
702
703 pd = kmalloc(sizeof *pd, GFP_KERNEL);
704 if (!pd)
705 return ERR_PTR(-ENOMEM);
706
707 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
708 if (err) {
709 kfree(pd);
710 return ERR_PTR(err);
711 }
712
713 if (context)
714 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
715 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
716 kfree(pd);
717 return ERR_PTR(-EFAULT);
718 }
719
720 return &pd->ibpd;
721}
722
723static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
724{
725 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
726 kfree(pd);
727
728 return 0;
729}
730
012a8ff5
SH		 731static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
732 struct ib_ucontext *context,
733 struct ib_udata *udata)
734{
735 struct mlx4_ib_xrcd *xrcd;
736 int err;
737
738 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
739 return ERR_PTR(-ENOSYS);
740
741 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
742 if (!xrcd)
743 return ERR_PTR(-ENOMEM);
744
745 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
746 if (err)
747 goto err1;
748
749 xrcd->pd = ib_alloc_pd(ibdev);
750 if (IS_ERR(xrcd->pd)) {
751 err = PTR_ERR(xrcd->pd);
752 goto err2;
753 }
754
755 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, 1, 0);
756 if (IS_ERR(xrcd->cq)) {
757 err = PTR_ERR(xrcd->cq);
758 goto err3;
759 }
760
761 return &xrcd->ibxrcd;
762
763err3:
764 ib_dealloc_pd(xrcd->pd);
765err2:
766 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
767err1:
768 kfree(xrcd);
769 return ERR_PTR(err);
770}
771
772static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
773{
774 ib_destroy_cq(to_mxrcd(xrcd)->cq);
775 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
776 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
777 kfree(xrcd);
778
779 return 0;
780}
781
fa417f7b
EC		 782static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
783{
784 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
785 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
786 struct mlx4_ib_gid_entry *ge;
787
788 ge = kzalloc(sizeof *ge, GFP_KERNEL);
789 if (!ge)
790 return -ENOMEM;
791
792 ge->gid = *gid;
793 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
794 ge->port = mqp->port;
795 ge->added = 1;
796 }
797
798 mutex_lock(&mqp->mutex);
799 list_add_tail(&ge->list, &mqp->gid_list);
800 mutex_unlock(&mqp->mutex);
801
802 return 0;
803}
804
805int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
806 union ib_gid *gid)
807{
fa417f7b
EC		 808 struct net_device *ndev;
809 int ret = 0;
810
811 if (!mqp->port)
812 return 0;
813
814 spin_lock(&mdev->iboe.lock);
815 ndev = mdev->iboe.netdevs[mqp->port - 1];
816 if (ndev)
817 dev_hold(ndev);
818 spin_unlock(&mdev->iboe.lock);
819
820 if (ndev) {
fa417f7b 821 ret = 1;
fa417f7b
EC		 822 dev_put(ndev);
823 }
824
825 return ret;
826}
827
0ff1fb65
HHZ		 828struct mlx4_ib_steering {
829 struct list_head list;
830 u64 reg_id;
831 union ib_gid gid;
832};
833
f77c0162 834static int parse_flow_attr(struct mlx4_dev *dev,
a37a1a42 835 u32 qp_num,
f77c0162
HHZ		 836 union ib_flow_spec *ib_spec,
837 struct _rule_hw *mlx4_spec)
838{
839 enum mlx4_net_trans_rule_id type;
840
841 switch (ib_spec->type) {
842 case IB_FLOW_SPEC_ETH:
843 type = MLX4_NET_TRANS_RULE_ID_ETH;
844 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
845 ETH_ALEN);
846 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
847 ETH_ALEN);
848 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
849 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
850 break;
a37a1a42
MB		 851 case IB_FLOW_SPEC_IB:
852 type = MLX4_NET_TRANS_RULE_ID_IB;
853 mlx4_spec->ib.l3_qpn =
854 cpu_to_be32(qp_num);
855 mlx4_spec->ib.qpn_mask =
856 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
857 break;
858
f77c0162
HHZ		 859
860 case IB_FLOW_SPEC_IPV4:
861 type = MLX4_NET_TRANS_RULE_ID_IPV4;
862 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
863 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
864 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
865 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
866 break;
867
868 case IB_FLOW_SPEC_TCP:
869 case IB_FLOW_SPEC_UDP:
870 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
871 MLX4_NET_TRANS_RULE_ID_TCP :
872 MLX4_NET_TRANS_RULE_ID_UDP;
873 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
874 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
875 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
876 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
877 break;
878
879 default:
880 return -EINVAL;
881 }
882 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
883 mlx4_hw_rule_sz(dev, type) < 0)
884 return -EINVAL;
885 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
886 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
887 return mlx4_hw_rule_sz(dev, type);
888}
889
a37a1a42
MB		 890struct default_rules {
891 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
892 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
893 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
894 __u8 link_layer;
895};
896static const struct default_rules default_table[] = {
897 {
898 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
899 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
900 .rules_create_list = {IB_FLOW_SPEC_IB},
901 .link_layer = IB_LINK_LAYER_INFINIBAND
902 }
903};
904
905static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
906 struct ib_flow_attr *flow_attr)
907{
908 int i, j, k;
909 void *ib_flow;
910 const struct default_rules *pdefault_rules = default_table;
911 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
912
a57f23f6 913 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
a37a1a42
MB		 914 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
915 memset(&field_types, 0, sizeof(field_types));
916
917 if (link_layer != pdefault_rules->link_layer)
918 continue;
919
920 ib_flow = flow_attr + 1;
921 /* we assume the specs are sorted */
922 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
923 j < flow_attr->num_of_specs; k++) {
924 union ib_flow_spec *current_flow =
925 (union ib_flow_spec *)ib_flow;
926
927 /* same layer but different type */
928 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
929 (pdefault_rules->mandatory_fields[k] &
930 IB_FLOW_SPEC_LAYER_MASK)) &&
931 (current_flow->type !=
932 pdefault_rules->mandatory_fields[k]))
933 goto out;
934
935 /* same layer, try match next one */
936 if (current_flow->type ==
937 pdefault_rules->mandatory_fields[k]) {
938 j++;
939 ib_flow +=
940 ((union ib_flow_spec *)ib_flow)->size;
941 }
942 }
943
944 ib_flow = flow_attr + 1;
945 for (j = 0; j < flow_attr->num_of_specs;
946 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
947 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
948 /* same layer and same type */
949 if (((union ib_flow_spec *)ib_flow)->type ==
950 pdefault_rules->mandatory_not_fields[k])
951 goto out;
952
953 return i;
954 }
955out:
956 return -1;
957}
958
959static int __mlx4_ib_create_default_rules(
960 struct mlx4_ib_dev *mdev,
961 struct ib_qp *qp,
962 const struct default_rules *pdefault_rules,
963 struct _rule_hw *mlx4_spec) {
964 int size = 0;
965 int i;
966
a57f23f6 967 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
a37a1a42
MB		 968 int ret;
969 union ib_flow_spec ib_spec;
970 switch (pdefault_rules->rules_create_list[i]) {
971 case 0:
972 /* no rule */
973 continue;
974 case IB_FLOW_SPEC_IB:
975 ib_spec.type = IB_FLOW_SPEC_IB;
976 ib_spec.size = sizeof(struct ib_flow_spec_ib);
977
978 break;
979 default:
980 /* invalid rule */
981 return -EINVAL;
982 }
983 /* We must put empty rule, qpn is being ignored */
984 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
985 mlx4_spec);
986 if (ret < 0) {
987 pr_info("invalid parsing\n");
988 return -EINVAL;
989 }
990
991 mlx4_spec = (void *)mlx4_spec + ret;
992 size += ret;
993 }
994 return size;
995}
996
f77c0162
HHZ		 997static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
998 int domain,
999 enum mlx4_net_trans_promisc_mode flow_type,
1000 u64 *reg_id)
1001{
1002 int ret, i;
1003 int size = 0;
1004 void *ib_flow;
1005 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1006 struct mlx4_cmd_mailbox *mailbox;
1007 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
a37a1a42 1008 int default_flow;
f77c0162
HHZ		 1009
1010 static const u16 __mlx4_domain[] = {
1011 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1012 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1013 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1014 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1015 };
1016
1017 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1018 pr_err("Invalid priority value %d\n", flow_attr->priority);
1019 return -EINVAL;
1020 }
1021
1022 if (domain >= IB_FLOW_DOMAIN_NUM) {
1023 pr_err("Invalid domain value %d\n", domain);
1024 return -EINVAL;
1025 }
1026
1027 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1028 return -EINVAL;
1029
1030 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1031 if (IS_ERR(mailbox))
1032 return PTR_ERR(mailbox);
f77c0162
HHZ		 1033 ctrl = mailbox->buf;
1034
1035 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1036 flow_attr->priority);
1037 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1038 ctrl->port = flow_attr->port;
1039 ctrl->qpn = cpu_to_be32(qp->qp_num);
1040
1041 ib_flow = flow_attr + 1;
1042 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
a37a1a42
MB		 1043 /* Add default flows */
1044 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1045 if (default_flow >= 0) {
1046 ret = __mlx4_ib_create_default_rules(
1047 mdev, qp, default_table + default_flow,
1048 mailbox->buf + size);
1049 if (ret < 0) {
1050 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1051 return -EINVAL;
1052 }
1053 size += ret;
1054 }
f77c0162 1055 for (i = 0; i < flow_attr->num_of_specs; i++) {
a37a1a42
MB		 1056 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1057 mailbox->buf + size);
f77c0162
HHZ		 1058 if (ret < 0) {
1059 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1060 return -EINVAL;
1061 }
1062 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1063 size += ret;
1064 }
1065
1066 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1067 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1068 MLX4_CMD_NATIVE);
1069 if (ret == -ENOMEM)
1070 pr_err("mcg table is full. Fail to register network rule.\n");
1071 else if (ret == -ENXIO)
1072 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1073 else if (ret)
1074 pr_err("Invalid argumant. Fail to register network rule.\n");
1075
1076 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1077 return ret;
1078}
1079
1080static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1081{
1082 int err;
1083 err = mlx4_cmd(dev, reg_id, 0, 0,
1084 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1085 MLX4_CMD_NATIVE);
1086 if (err)
1087 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1088 reg_id);
1089 return err;
1090}
1091
d2fce8a9
OG		 1092static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1093 u64 *reg_id)
1094{
1095 void *ib_flow;
1096 union ib_flow_spec *ib_spec;
1097 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1098 int err = 0;
1099
1100 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1101 return 0; /* do nothing */
1102
1103 ib_flow = flow_attr + 1;
1104 ib_spec = (union ib_flow_spec *)ib_flow;
1105
1106 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1107 return 0; /* do nothing */
1108
1109 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1110 flow_attr->port, qp->qp_num,
1111 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1112 reg_id);
1113 return err;
1114}
1115
f77c0162
HHZ		 1116static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1117 struct ib_flow_attr *flow_attr,
1118 int domain)
1119{
1120 int err = 0, i = 0;
1121 struct mlx4_ib_flow *mflow;
1122 enum mlx4_net_trans_promisc_mode type[2];
1123
1124 memset(type, 0, sizeof(type));
1125
1126 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1127 if (!mflow) {
1128 err = -ENOMEM;
1129 goto err_free;
1130 }
1131
1132 switch (flow_attr->type) {
1133 case IB_FLOW_ATTR_NORMAL:
1134 type[0] = MLX4_FS_REGULAR;
1135 break;
1136
1137 case IB_FLOW_ATTR_ALL_DEFAULT:
1138 type[0] = MLX4_FS_ALL_DEFAULT;
1139 break;
1140
1141 case IB_FLOW_ATTR_MC_DEFAULT:
1142 type[0] = MLX4_FS_MC_DEFAULT;
1143 break;
1144
1145 case IB_FLOW_ATTR_SNIFFER:
1146 type[0] = MLX4_FS_UC_SNIFFER;
1147 type[1] = MLX4_FS_MC_SNIFFER;
1148 break;
1149
1150 default:
1151 err = -EINVAL;
1152 goto err_free;
1153 }
1154
1155 while (i < ARRAY_SIZE(type) && type[i]) {
1156 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1157 &mflow->reg_id[i]);
1158 if (err)
1159 goto err_free;
1160 i++;
1161 }
1162
d2fce8a9
OG		 1163 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1164 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, &mflow->reg_id[i]);
1165 if (err)
1166 goto err_free;
1167 }
1168
f77c0162
HHZ		 1169 return &mflow->ibflow;
1170
1171err_free:
1172 kfree(mflow);
1173 return ERR_PTR(err);
1174}
1175
1176static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1177{
1178 int err, ret = 0;
1179 int i = 0;
1180 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1181 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1182
1183 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i]) {
1184 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i]);
1185 if (err)
1186 ret = err;
1187 i++;
1188 }
1189
1190 kfree(mflow);
1191 return ret;
1192}
1193
225c7b1f
RD		 1194static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1195{
fa417f7b
EC		 1196 int err;
1197 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1198 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
0ff1fb65
HHZ		 1199 u64 reg_id;
1200 struct mlx4_ib_steering *ib_steering = NULL;
d487ee77
MS		 1201 enum mlx4_protocol prot = (gid->raw[1] == 0x0e) ?
1202 MLX4_PROT_IB_IPV4 : MLX4_PROT_IB_IPV6;
0ff1fb65
HHZ		 1203
1204 if (mdev->dev->caps.steering_mode ==
1205 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1206 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1207 if (!ib_steering)
1208 return -ENOMEM;
1209 }
fa417f7b 1210
0ff1fb65
HHZ		 1211 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1212 !!(mqp->flags &
1213 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
d487ee77 1214 prot, &reg_id);
fa417f7b 1215 if (err)
0ff1fb65 1216 goto err_malloc;
fa417f7b
EC		 1217
1218 err = add_gid_entry(ibqp, gid);
1219 if (err)
1220 goto err_add;
1221
0ff1fb65
HHZ		 1222 if (ib_steering) {
1223 memcpy(ib_steering->gid.raw, gid->raw, 16);
1224 ib_steering->reg_id = reg_id;
1225 mutex_lock(&mqp->mutex);
1226 list_add(&ib_steering->list, &mqp->steering_rules);
1227 mutex_unlock(&mqp->mutex);
1228 }
fa417f7b
EC		 1229 return 0;
1230
1231err_add:
0ff1fb65 1232 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
d487ee77 1233 prot, reg_id);
0ff1fb65
HHZ		 1234err_malloc:
1235 kfree(ib_steering);
1236
fa417f7b
EC		 1237 return err;
1238}
1239
1240static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1241{
1242 struct mlx4_ib_gid_entry *ge;
1243 struct mlx4_ib_gid_entry *tmp;
1244 struct mlx4_ib_gid_entry *ret = NULL;
1245
1246 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1247 if (!memcmp(raw, ge->gid.raw, 16)) {
1248 ret = ge;
1249 break;
1250 }
1251 }
1252
1253 return ret;
225c7b1f
RD		 1254}
1255
1256static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1257{
fa417f7b
EC		 1258 int err;
1259 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1260 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
fa417f7b
EC		 1261 struct net_device *ndev;
1262 struct mlx4_ib_gid_entry *ge;
0ff1fb65 1263 u64 reg_id = 0;
d487ee77
MS		 1264 enum mlx4_protocol prot = (gid->raw[1] == 0x0e) ?
1265 MLX4_PROT_IB_IPV4 : MLX4_PROT_IB_IPV6;
0ff1fb65
HHZ		 1266
1267 if (mdev->dev->caps.steering_mode ==
1268 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1269 struct mlx4_ib_steering *ib_steering;
1270
1271 mutex_lock(&mqp->mutex);
1272 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
1273 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
1274 list_del(&ib_steering->list);
1275 break;
1276 }
1277 }
1278 mutex_unlock(&mqp->mutex);
1279 if (&ib_steering->list == &mqp->steering_rules) {
1280 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
1281 return -EINVAL;
1282 }
1283 reg_id = ib_steering->reg_id;
1284 kfree(ib_steering);
1285 }
fa417f7b 1286
0ff1fb65 1287 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
d487ee77 1288 prot, reg_id);
fa417f7b
EC		 1289 if (err)
1290 return err;
1291
1292 mutex_lock(&mqp->mutex);
1293 ge = find_gid_entry(mqp, gid->raw);
1294 if (ge) {
1295 spin_lock(&mdev->iboe.lock);
1296 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
1297 if (ndev)
1298 dev_hold(ndev);
1299 spin_unlock(&mdev->iboe.lock);
d487ee77 1300 if (ndev)
fa417f7b 1301 dev_put(ndev);
fa417f7b
EC		 1302 list_del(&ge->list);
1303 kfree(ge);
1304 } else
987c8f8f 1305 pr_warn("could not find mgid entry\n");
fa417f7b
EC		 1306
1307 mutex_unlock(&mqp->mutex);
1308
1309 return 0;
225c7b1f
RD		 1310}
1311
1312static int init_node_data(struct mlx4_ib_dev *dev)
1313{
1314 struct ib_smp *in_mad = NULL;
1315 struct ib_smp *out_mad = NULL;
0a9a0188 1316 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 1317 int err = -ENOMEM;
1318
1319 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
1320 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1321 if (!in_mad || !out_mad)
1322 goto out;
1323
1324 init_query_mad(in_mad);
1325 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
0a9a0188
JM		 1326 if (mlx4_is_master(dev->dev))
1327 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
225c7b1f 1328
0a9a0188 1329 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 1330 if (err)
1331 goto out;
1332
1333 memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
1334
1335 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
1336
0a9a0188 1337 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 1338 if (err)
1339 goto out;
1340
992e8e6e 1341 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
225c7b1f
RD		 1342 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
1343
1344out:
1345 kfree(in_mad);
1346 kfree(out_mad);
1347 return err;
1348}
1349
f4e91eb4
TJ		 1350static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1351 char *buf)
cd9281d8 1352{
f4e91eb4
TJ		 1353 struct mlx4_ib_dev *dev =
1354 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1355 return sprintf(buf, "MT%d\n", dev->dev->pdev->device);
1356}
1357
f4e91eb4
TJ		 1358static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1359 char *buf)
cd9281d8 1360{
f4e91eb4
TJ		 1361 struct mlx4_ib_dev *dev =
1362 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1363 return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
1364 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
1365 (int) dev->dev->caps.fw_ver & 0xffff);
1366}
1367
f4e91eb4
TJ		 1368static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1369 char *buf)
cd9281d8 1370{
f4e91eb4
TJ		 1371 struct mlx4_ib_dev *dev =
1372 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 1373 return sprintf(buf, "%x\n", dev->dev->rev_id);
1374}
1375
f4e91eb4
TJ		 1376static ssize_t show_board(struct device *device, struct device_attribute *attr,
1377 char *buf)
cd9281d8 1378{
f4e91eb4
TJ		 1379 struct mlx4_ib_dev *dev =
1380 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
1381 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
1382 dev->dev->board_id);
cd9281d8
JM		 1383}
1384
f4e91eb4
TJ		 1385static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1386static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1387static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1388static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
cd9281d8 1389
f4e91eb4
TJ		 1390static struct device_attribute *mlx4_class_attributes[] = {
1391 &dev_attr_hw_rev,
1392 &dev_attr_fw_ver,
1393 &dev_attr_hca_type,
1394 &dev_attr_board_id
cd9281d8
JM		 1395};
1396
acc4fccf
MS		 1397static void mlx4_addrconf_ifid_eui48(u8 *eui, u16 vlan_id,
1398 struct net_device *dev)
1399{
1400 memcpy(eui, dev->dev_addr, 3);
1401 memcpy(eui + 5, dev->dev_addr + 3, 3);
1402 if (vlan_id < 0x1000) {
1403 eui[3] = vlan_id >> 8;
1404 eui[4] = vlan_id & 0xff;
1405 } else {
1406 eui[3] = 0xff;
1407 eui[4] = 0xfe;
1408 }
1409 eui[0] ^= 2;
1410}
1411
fa417f7b
EC		 1412static void update_gids_task(struct work_struct *work)
1413{
1414 struct update_gid_work *gw = container_of(work, struct update_gid_work, work);
1415 struct mlx4_cmd_mailbox *mailbox;
1416 union ib_gid *gids;
1417 int err;
1418 struct mlx4_dev *dev = gw->dev->dev;
fa417f7b
EC		 1419
1420 mailbox = mlx4_alloc_cmd_mailbox(dev);
1421 if (IS_ERR(mailbox)) {
987c8f8f 1422 pr_warn("update gid table failed %ld\n", PTR_ERR(mailbox));
fa417f7b
EC		 1423 return;
1424 }
1425
1426 gids = mailbox->buf;
1427 memcpy(gids, gw->gids, sizeof gw->gids);
1428
1429 err = mlx4_cmd(dev, mailbox->dma, MLX4_SET_PORT_GID_TABLE << 8 | gw->port,
f9baff50 1430 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
992e8e6e 1431 MLX4_CMD_WRAPPED);
fa417f7b 1432 if (err)
987c8f8f 1433 pr_warn("set port command failed\n");
d487ee77 1434 else
00f5ce99 1435 mlx4_ib_dispatch_event(gw->dev, gw->port, IB_EVENT_GID_CHANGE);
fa417f7b
EC		 1436
1437 mlx4_free_cmd_mailbox(dev, mailbox);
1438 kfree(gw);
1439}
1440
d487ee77 1441static void reset_gids_task(struct work_struct *work)
fa417f7b 1442{
d487ee77
MS		 1443 struct update_gid_work *gw =
1444 container_of(work, struct update_gid_work, work);
1445 struct mlx4_cmd_mailbox *mailbox;
1446 union ib_gid *gids;
1447 int err;
d487ee77 1448 struct mlx4_dev *dev = gw->dev->dev;
fa417f7b 1449
d487ee77
MS		 1450 mailbox = mlx4_alloc_cmd_mailbox(dev);
1451 if (IS_ERR(mailbox)) {
1452 pr_warn("reset gid table failed\n");
1453 goto free;
1454 }
fa417f7b 1455
d487ee77
MS		 1456 gids = mailbox->buf;
1457 memcpy(gids, gw->gids, sizeof(gw->gids));
1458
5071456f
MS		 1459 if (mlx4_ib_port_link_layer(&gw->dev->ib_dev, gw->port) ==
1460 IB_LINK_LAYER_ETHERNET) {
1461 err = mlx4_cmd(dev, mailbox->dma,
1462 MLX4_SET_PORT_GID_TABLE << 8 | gw->port,
1463 1, MLX4_CMD_SET_PORT,
1464 MLX4_CMD_TIME_CLASS_B,
1465 MLX4_CMD_WRAPPED);
1466 if (err)
1467 pr_warn(KERN_WARNING
1468 "set port %d command failed\n", gw->port);
4c3eb3ca
EC		 1469 }
1470
d487ee77
MS		 1471 mlx4_free_cmd_mailbox(dev, mailbox);
1472free:
1473 kfree(gw);
1474}
4c3eb3ca 1475
d487ee77 1476static int update_gid_table(struct mlx4_ib_dev *dev, int port,
acc4fccf
MS		 1477 union ib_gid *gid, int clear,
1478 int default_gid)
d487ee77
MS		 1479{
1480 struct update_gid_work *work;
1481 int i;
1482 int need_update = 0;
1483 int free = -1;
1484 int found = -1;
1485 int max_gids;
1486
acc4fccf
MS		 1487 if (default_gid) {
1488 free = 0;
1489 } else {
1490 max_gids = dev->dev->caps.gid_table_len[port];
1491 for (i = 1; i < max_gids; ++i) {
1492 if (!memcmp(&dev->iboe.gid_table[port - 1][i], gid,
d487ee77 1493 sizeof(*gid)))
acc4fccf
MS		 1494 found = i;
1495
1496 if (clear) {
1497 if (found >= 0) {
1498 need_update = 1;
1499 dev->iboe.gid_table[port - 1][found] =
1500 zgid;
1501 break;
1502 }
1503 } else {
1504 if (found >= 0)
1505 break;
1506
1507 if (free < 0 &&
1508 !memcmp(&dev->iboe.gid_table[port - 1][i],
1509 &zgid, sizeof(*gid)))
1510 free = i;
1511 }
4c3eb3ca 1512 }
fa417f7b 1513 }
4c3eb3ca 1514
d487ee77
MS		 1515 if (found == -1 && !clear && free >= 0) {
1516 dev->iboe.gid_table[port - 1][free] = *gid;
1517 need_update = 1;
1518 }
fa417f7b 1519
d487ee77
MS		 1520 if (!need_update)
1521 return 0;
1522
1523 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1524 if (!work)
1525 return -ENOMEM;
1526
1527 memcpy(work->gids, dev->iboe.gid_table[port - 1], sizeof(work->gids));
1528 INIT_WORK(&work->work, update_gids_task);
1529 work->port = port;
1530 work->dev = dev;
1531 queue_work(wq, &work->work);
fa417f7b
EC		 1532
1533 return 0;
d487ee77 1534}
4c3eb3ca 1535
acc4fccf 1536static void mlx4_make_default_gid(struct net_device *dev, union ib_gid *gid)
d487ee77 1537{
acc4fccf
MS		 1538 gid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
1539 mlx4_addrconf_ifid_eui48(&gid->raw[8], 0xffff, dev);
1540}
1541
d487ee77 1542
5071456f 1543static int reset_gid_table(struct mlx4_ib_dev *dev, u8 port)
d487ee77
MS		 1544{
1545 struct update_gid_work *work;
d487ee77
MS		 1546
1547 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1548 if (!work)
1549 return -ENOMEM;
5071456f
MS		 1550
1551 memset(dev->iboe.gid_table[port - 1], 0, sizeof(work->gids));
d487ee77
MS		 1552 memset(work->gids, 0, sizeof(work->gids));
1553 INIT_WORK(&work->work, reset_gids_task);
1554 work->dev = dev;
5071456f 1555 work->port = port;
d487ee77
MS		 1556 queue_work(wq, &work->work);
1557 return 0;
fa417f7b
EC		 1558}
1559
d487ee77
MS		 1560static int mlx4_ib_addr_event(int event, struct net_device *event_netdev,
1561 struct mlx4_ib_dev *ibdev, union ib_gid *gid)
fa417f7b 1562{
d487ee77
MS		 1563 struct mlx4_ib_iboe *iboe;
1564 int port = 0;
1565 struct net_device *real_dev = rdma_vlan_dev_real_dev(event_netdev) ?
1566 rdma_vlan_dev_real_dev(event_netdev) :
1567 event_netdev;
acc4fccf
MS		 1568 union ib_gid default_gid;
1569
1570 mlx4_make_default_gid(real_dev, &default_gid);
1571
1572 if (!memcmp(gid, &default_gid, sizeof(*gid)))
1573 return 0;
d487ee77
MS		 1574
1575 if (event != NETDEV_DOWN && event != NETDEV_UP)
1576 return 0;
1577
1578 if ((real_dev != event_netdev) &&
1579 (event == NETDEV_DOWN) &&
1580 rdma_link_local_addr((struct in6_addr *)gid))
1581 return 0;
1582
1583 iboe = &ibdev->iboe;
1584 spin_lock(&iboe->lock);
1585
82373701 1586 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port)
d487ee77
MS		 1587 if ((netif_is_bond_master(real_dev) &&
1588 (real_dev == iboe->masters[port - 1])) ||
1589 (!netif_is_bond_master(real_dev) &&
1590 (real_dev == iboe->netdevs[port - 1])))
1591 update_gid_table(ibdev, port, gid,
acc4fccf 1592 event == NETDEV_DOWN, 0);
d487ee77
MS		 1593
1594 spin_unlock(&iboe->lock);
1595 return 0;
fa417f7b 1596
fa417f7b
EC		 1597}
1598
d487ee77
MS		 1599static u8 mlx4_ib_get_dev_port(struct net_device *dev,
1600 struct mlx4_ib_dev *ibdev)
fa417f7b 1601{
d487ee77
MS		 1602 u8 port = 0;
1603 struct mlx4_ib_iboe *iboe;
1604 struct net_device *real_dev = rdma_vlan_dev_real_dev(dev) ?
1605 rdma_vlan_dev_real_dev(dev) : dev;
1606
1607 iboe = &ibdev->iboe;
d487ee77 1608
82373701 1609 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port)
d487ee77
MS		 1610 if ((netif_is_bond_master(real_dev) &&
1611 (real_dev == iboe->masters[port - 1])) ||
1612 (!netif_is_bond_master(real_dev) &&
1613 (real_dev == iboe->netdevs[port - 1])))
1614 break;
1615
82373701 1616 if ((port == 0) || (port > ibdev->dev->caps.num_ports))
d487ee77
MS		 1617 return 0;
1618 else
1619 return port;
fa417f7b
EC		 1620}
1621
d487ee77
MS		 1622static int mlx4_ib_inet_event(struct notifier_block *this, unsigned long event,
1623 void *ptr)
fa417f7b 1624{
d487ee77
MS		 1625 struct mlx4_ib_dev *ibdev;
1626 struct in_ifaddr *ifa = ptr;
1627 union ib_gid gid;
1628 struct net_device *event_netdev = ifa->ifa_dev->dev;
1629
1630 ipv6_addr_set_v4mapped(ifa->ifa_address, (struct in6_addr *)&gid);
1631
1632 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb_inet);
1633
1634 mlx4_ib_addr_event(event, event_netdev, ibdev, &gid);
1635 return NOTIFY_DONE;
fa417f7b
EC		 1636}
1637
27cdef63 1638#if IS_ENABLED(CONFIG_IPV6)
d487ee77 1639static int mlx4_ib_inet6_event(struct notifier_block *this, unsigned long event,
fa417f7b
EC		 1640 void *ptr)
1641{
fa417f7b 1642 struct mlx4_ib_dev *ibdev;
d487ee77
MS		 1643 struct inet6_ifaddr *ifa = ptr;
1644 union ib_gid *gid = (union ib_gid *)&ifa->addr;
1645 struct net_device *event_netdev = ifa->idev->dev;
1646
1647 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb_inet6);
1648
1649 mlx4_ib_addr_event(event, event_netdev, ibdev, gid);
1650 return NOTIFY_DONE;
1651}
1652#endif
1653
9433c188
MB		 1654#define MLX4_IB_INVALID_MAC ((u64)-1)
1655static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
1656 struct net_device *dev,
1657 int port)
1658{
1659 u64 new_smac = 0;
1660 u64 release_mac = MLX4_IB_INVALID_MAC;
1661 struct mlx4_ib_qp *qp;
1662
1663 read_lock(&dev_base_lock);
1664 new_smac = mlx4_mac_to_u64(dev->dev_addr);
1665 read_unlock(&dev_base_lock);
1666
1667 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
1668 qp = ibdev->qp1_proxy[port - 1];
1669 if (qp) {
1670 int new_smac_index;
1671 u64 old_smac = qp->pri.smac;
1672 struct mlx4_update_qp_params update_params;
1673
1674 if (new_smac == old_smac)
1675 goto unlock;
1676
1677 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
1678
1679 if (new_smac_index < 0)
1680 goto unlock;
1681
1682 update_params.smac_index = new_smac_index;
1683 if (mlx4_update_qp(ibdev->dev, &qp->mqp, MLX4_UPDATE_QP_SMAC,
1684 &update_params)) {
1685 release_mac = new_smac;
1686 goto unlock;
1687 }
1688
1689 qp->pri.smac = new_smac;
1690 qp->pri.smac_index = new_smac_index;
1691
1692 release_mac = old_smac;
1693 }
1694
1695unlock:
1696 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
1697 if (release_mac != MLX4_IB_INVALID_MAC)
1698 mlx4_unregister_mac(ibdev->dev, port, release_mac);
1699}
1700
d487ee77
MS		 1701static void mlx4_ib_get_dev_addr(struct net_device *dev,
1702 struct mlx4_ib_dev *ibdev, u8 port)
1703{
1704 struct in_device *in_dev;
27cdef63 1705#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 1706 struct inet6_dev *in6_dev;
1707 union ib_gid *pgid;
1708 struct inet6_ifaddr *ifp;
1709#endif
1710 union ib_gid gid;
1711
1712
82373701 1713 if ((port == 0) || (port > ibdev->dev->caps.num_ports))
d487ee77
MS		 1714 return;
1715
1716 /* IPv4 gids */
1717 in_dev = in_dev_get(dev);
1718 if (in_dev) {
1719 for_ifa(in_dev) {
1720 /*ifa->ifa_address;*/
1721 ipv6_addr_set_v4mapped(ifa->ifa_address,
1722 (struct in6_addr *)&gid);
acc4fccf 1723 update_gid_table(ibdev, port, &gid, 0, 0);
d487ee77
MS		 1724 }
1725 endfor_ifa(in_dev);
1726 in_dev_put(in_dev);
1727 }
27cdef63 1728#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 1729 /* IPv6 gids */
1730 in6_dev = in6_dev_get(dev);
1731 if (in6_dev) {
1732 read_lock_bh(&in6_dev->lock);
1733 list_for_each_entry(ifp, &in6_dev->addr_list, if_list) {
1734 pgid = (union ib_gid *)&ifp->addr;
acc4fccf 1735 update_gid_table(ibdev, port, pgid, 0, 0);
d487ee77
MS		 1736 }
1737 read_unlock_bh(&in6_dev->lock);
1738 in6_dev_put(in6_dev);
1739 }
1740#endif
1741}
1742
acc4fccf
MS		 1743static void mlx4_ib_set_default_gid(struct mlx4_ib_dev *ibdev,
1744 struct net_device *dev, u8 port)
1745{
1746 union ib_gid gid;
1747 mlx4_make_default_gid(dev, &gid);
1748 update_gid_table(ibdev, port, &gid, 0, 1);
1749}
1750
d487ee77
MS		 1751static int mlx4_ib_init_gid_table(struct mlx4_ib_dev *ibdev)
1752{
1753 struct net_device *dev;
ddf8bd34 1754 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
5071456f 1755 int i;
d487ee77 1756
5071456f
MS		 1757 for (i = 1; i <= ibdev->num_ports; ++i)
1758 if (reset_gid_table(ibdev, i))
1759 return -1;
d487ee77
MS		 1760
1761 read_lock(&dev_base_lock);
ddf8bd34 1762 spin_lock(&iboe->lock);
d487ee77
MS		 1763
1764 for_each_netdev(&init_net, dev) {
1765 u8 port = mlx4_ib_get_dev_port(dev, ibdev);
1766 if (port)
1767 mlx4_ib_get_dev_addr(dev, ibdev, port);
1768 }
1769
ddf8bd34 1770 spin_unlock(&iboe->lock);
d487ee77
MS		 1771 read_unlock(&dev_base_lock);
1772
1773 return 0;
1774}
1775
9433c188
MB		 1776static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
1777 struct net_device *dev,
1778 unsigned long event)
1779
d487ee77 1780{
fa417f7b 1781 struct mlx4_ib_iboe *iboe;
9433c188 1782 int update_qps_port = -1;
fa417f7b
EC		 1783 int port;
1784
fa417f7b
EC		 1785 iboe = &ibdev->iboe;
1786
1787 spin_lock(&iboe->lock);
1788 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
ad4885d2 1789 enum ib_port_state port_state = IB_PORT_NOP;
d487ee77 1790 struct net_device *old_master = iboe->masters[port - 1];
ad4885d2 1791 struct net_device *curr_netdev;
d487ee77 1792 struct net_device *curr_master;
ad4885d2 1793
fa417f7b 1794 iboe->netdevs[port - 1] =
0345584e 1795 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
acc4fccf
MS		 1796 if (iboe->netdevs[port - 1])
1797 mlx4_ib_set_default_gid(ibdev,
1798 iboe->netdevs[port - 1], port);
ad4885d2 1799 curr_netdev = iboe->netdevs[port - 1];
d487ee77
MS		 1800
1801 if (iboe->netdevs[port - 1] &&
1802 netif_is_bond_slave(iboe->netdevs[port - 1])) {
d487ee77
MS		 1803 iboe->masters[port - 1] = netdev_master_upper_dev_get(
1804 iboe->netdevs[port - 1]);
ad4885d2
MS		 1805 } else {
1806 iboe->masters[port - 1] = NULL;
fa417f7b 1807 }
d487ee77 1808 curr_master = iboe->masters[port - 1];
fa417f7b 1809
9433c188
MB		 1810 if (dev == iboe->netdevs[port - 1] &&
1811 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
1812 event == NETDEV_UP || event == NETDEV_CHANGE))
1813 update_qps_port = port;
1814
ad4885d2
MS		 1815 if (curr_netdev) {
1816 port_state = (netif_running(curr_netdev) && netif_carrier_ok(curr_netdev)) ?
1817 IB_PORT_ACTIVE : IB_PORT_DOWN;
1818 mlx4_ib_set_default_gid(ibdev, curr_netdev, port);
1819 } else {
1820 reset_gid_table(ibdev, port);
1821 }
1822 /* if using bonding/team and a slave port is down, we don't the bond IP
1823 * based gids in the table since flows that select port by gid may get
1824 * the down port.
1825 */
1826 if (curr_master && (port_state == IB_PORT_DOWN)) {
1827 reset_gid_table(ibdev, port);
1828 mlx4_ib_set_default_gid(ibdev, curr_netdev, port);
1829 }
d487ee77 1830 /* if bonding is used it is possible that we add it to masters
ad4885d2
MS		 1831 * only after IP address is assigned to the net bonding
1832 * interface.
1833 */
1834 if (curr_master && (old_master != curr_master)) {
1835 reset_gid_table(ibdev, port);
1836 mlx4_ib_set_default_gid(ibdev, curr_netdev, port);
d487ee77 1837 mlx4_ib_get_dev_addr(curr_master, ibdev, port);
ad4885d2
MS		 1838 }
1839
1840 if (!curr_master && (old_master != curr_master)) {
1841 reset_gid_table(ibdev, port);
1842 mlx4_ib_set_default_gid(ibdev, curr_netdev, port);
1843 mlx4_ib_get_dev_addr(curr_netdev, ibdev, port);
1844 }
d487ee77 1845 }
fa417f7b
EC		 1846
1847 spin_unlock(&iboe->lock);
9433c188
MB		 1848
1849 if (update_qps_port > 0)
1850 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
d487ee77
MS		 1851}
1852
1853static int mlx4_ib_netdev_event(struct notifier_block *this,
1854 unsigned long event, void *ptr)
1855{
1856 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1857 struct mlx4_ib_dev *ibdev;
1858
1859 if (!net_eq(dev_net(dev), &init_net))
1860 return NOTIFY_DONE;
1861
1862 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
9433c188 1863 mlx4_ib_scan_netdevs(ibdev, dev, event);
fa417f7b
EC		 1864
1865 return NOTIFY_DONE;
1866}
1867
54679e14
JM		 1868static void init_pkeys(struct mlx4_ib_dev *ibdev)
1869{
1870 int port;
1871 int slave;
1872 int i;
1873
1874 if (mlx4_is_master(ibdev->dev)) {
1875 for (slave = 0; slave <= ibdev->dev->num_vfs; ++slave) {
1876 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
1877 for (i = 0;
1878 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
1879 ++i) {
1880 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
1881 /* master has the identity virt2phys pkey mapping */
1882 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
1883 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
1884 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
1885 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
1886 }
1887 }
1888 }
1889 /* initialize pkey cache */
1890 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
1891 for (i = 0;
1892 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
1893 ++i)
1894 ibdev->pkeys.phys_pkey_cache[port-1][i] =
1895 (i) ? 0 : 0xFFFF;
1896 }
1897 }
1898}
1899
e605b743
SP		 1900static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
1901{
4661bd79 1902 char name[80];
e605b743
SP		 1903 int eq_per_port = 0;
1904 int added_eqs = 0;
1905 int total_eqs = 0;
1906 int i, j, eq;
1907
3aac6ff1
SP		 1908 /* Legacy mode or comp_pool is not large enough */
1909 if (dev->caps.comp_pool == 0 ||
1910 dev->caps.num_ports > dev->caps.comp_pool)
e605b743
SP		 1911 return;
1912
1913 eq_per_port = rounddown_pow_of_two(dev->caps.comp_pool/
1914 dev->caps.num_ports);
1915
1916 /* Init eq table */
1917 added_eqs = 0;
1918 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
1919 added_eqs += eq_per_port;
1920
1921 total_eqs = dev->caps.num_comp_vectors + added_eqs;
1922
1923 ibdev->eq_table = kzalloc(total_eqs * sizeof(int), GFP_KERNEL);
1924 if (!ibdev->eq_table)
1925 return;
1926
1927 ibdev->eq_added = added_eqs;
1928
1929 eq = 0;
1930 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) {
1931 for (j = 0; j < eq_per_port; j++) {
4661bd79
DC		 1932 snprintf(name, sizeof(name), "mlx4-ib-%d-%d@%s",
1933 i, j, dev->pdev->bus->name);
e605b743 1934 /* Set IRQ for specific name (per ring) */
d9236c3f
AV		 1935 if (mlx4_assign_eq(dev, name, NULL,
1936 &ibdev->eq_table[eq])) {
e605b743
SP		 1937 /* Use legacy (same as mlx4_en driver) */
1938 pr_warn("Can't allocate EQ %d; reverting to legacy\n", eq);
1939 ibdev->eq_table[eq] =
1940 (eq % dev->caps.num_comp_vectors);
1941 }
1942 eq++;
1943 }
1944 }
1945
1946 /* Fill the reset of the vector with legacy EQ */
1947 for (i = 0, eq = added_eqs; i < dev->caps.num_comp_vectors; i++)
1948 ibdev->eq_table[eq++] = i;
1949
1950 /* Advertise the new number of EQs to clients */
1951 ibdev->ib_dev.num_comp_vectors = total_eqs;
1952}
1953
1954static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
1955{
1956 int i;
3aac6ff1
SP		 1957
1958 /* no additional eqs were added */
1959 if (!ibdev->eq_table)
1960 return;
e605b743
SP		 1961
1962 /* Reset the advertised EQ number */
1963 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
1964
1965 /* Free only the added eqs */
1966 for (i = 0; i < ibdev->eq_added; i++) {
1967 /* Don't free legacy eqs if used */
1968 if (ibdev->eq_table[i] <= dev->caps.num_comp_vectors)
1969 continue;
1970 mlx4_release_eq(dev, ibdev->eq_table[i]);
1971 }
1972
e605b743 1973 kfree(ibdev->eq_table);
e605b743
SP		 1974}
1975
225c7b1f
RD		 1976static void *mlx4_ib_add(struct mlx4_dev *dev)
1977{
1978 struct mlx4_ib_dev *ibdev;
22e7ef9c 1979 int num_ports = 0;
035b1032 1980 int i, j;
fa417f7b
EC		 1981 int err;
1982 struct mlx4_ib_iboe *iboe;
4196670b 1983 int ib_num_ports = 0;
225c7b1f 1984
987c8f8f 1985 pr_info_once("%s", mlx4_ib_version);
68f3948d 1986
026149cb 1987 num_ports = 0;
fa417f7b 1988 mlx4_foreach_ib_transport_port(i, dev)
22e7ef9c
RD		 1989 num_ports++;
1990
1991 /* No point in registering a device with no ports... */
1992 if (num_ports == 0)
1993 return NULL;
1994
225c7b1f
RD		 1995 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
1996 if (!ibdev) {
1997 dev_err(&dev->pdev->dev, "Device struct alloc failed\n");
1998 return NULL;
1999 }
2000
fa417f7b
EC		 2001 iboe = &ibdev->iboe;
2002
225c7b1f
RD		 2003 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2004 goto err_dealloc;
2005
2006 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2007 goto err_pd;
2008
4979d18f
RD		 2009 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2010 PAGE_SIZE);
225c7b1f
RD		 2011 if (!ibdev->uar_map)
2012 goto err_uar;
26c6bc7b 2013 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
225c7b1f 2014
225c7b1f
RD		 2015 ibdev->dev = dev;
2016
2017 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2018 ibdev->ib_dev.owner = THIS_MODULE;
2019 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
95d04f07 2020 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
22e7ef9c 2021 ibdev->num_ports = num_ports;
7ff93f8b 2022 ibdev->ib_dev.phys_port_cnt = ibdev->num_ports;
b8dd786f 2023 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
225c7b1f
RD		 2024 ibdev->ib_dev.dma_device = &dev->pdev->dev;
2025
08ff3235
OG		 2026 if (dev->caps.userspace_caps)
2027 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2028 else
2029 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2030
225c7b1f
RD		 2031 ibdev->ib_dev.uverbs_cmd_mask =
2032 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2033 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2034 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2035 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2036 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2037 (1ull << IB_USER_VERBS_CMD_REG_MR) |
9376932d 2038 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
225c7b1f
RD		 2039 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2040 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2041 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
bbf8eed1 2042 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
225c7b1f
RD		 2043 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2044 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2045 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6a775e2b 2046 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
225c7b1f
RD		 2047 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2048 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2049 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2050 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2051 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
65541cb7 2052 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
18abd5ea 2053 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
42849b26
SH		 2054 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2055 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
225c7b1f
RD		 2056
2057 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2058 ibdev->ib_dev.query_port = mlx4_ib_query_port;
fa417f7b 2059 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
225c7b1f
RD		 2060 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2061 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2062 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2063 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2064 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2065 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2066 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2067 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2068 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2069 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2070 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2071 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2072 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2073 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
65541cb7 2074 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
225c7b1f
RD		 2075 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2076 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2077 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2078 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
6a775e2b 2079 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
225c7b1f
RD		 2080 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2081 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2082 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2083 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
3fdcb97f 2084 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
bbf8eed1 2085 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
225c7b1f
RD		 2086 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2087 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2088 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2089 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2090 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
9376932d 2091 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
225c7b1f 2092 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
95d04f07
RD		 2093 ibdev->ib_dev.alloc_fast_reg_mr = mlx4_ib_alloc_fast_reg_mr;
2094 ibdev->ib_dev.alloc_fast_reg_page_list = mlx4_ib_alloc_fast_reg_page_list;
2095 ibdev->ib_dev.free_fast_reg_page_list = mlx4_ib_free_fast_reg_page_list;
225c7b1f
RD		 2096 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2097 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2098 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2099
992e8e6e
JM		 2100 if (!mlx4_is_slave(ibdev->dev)) {
2101 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2102 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2103 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2104 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2105 }
8ad11fb6 2106
b425388d
SM		 2107 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2108 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2109 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2110 ibdev->ib_dev.bind_mw = mlx4_ib_bind_mw;
2111 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2112
2113 ibdev->ib_dev.uverbs_cmd_mask |=
2114 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2115 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2116 }
2117
012a8ff5
SH		 2118 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2119 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2120 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2121 ibdev->ib_dev.uverbs_cmd_mask |=
2122 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2123 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2124 }
2125
f77c0162 2126 if (check_flow_steering_support(dev)) {
0a9b7d59 2127 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
f77c0162
HHZ		 2128 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2129 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2130
f21519b2
YD		 2131 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2132 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2133 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
f77c0162
HHZ		 2134 }
2135
e605b743
SP		 2136 mlx4_ib_alloc_eqs(dev, ibdev);
2137
fa417f7b
EC		 2138 spin_lock_init(&iboe->lock);
2139
225c7b1f
RD		 2140 if (init_node_data(ibdev))
2141 goto err_map;
2142
cfcde11c 2143 for (i = 0; i < ibdev->num_ports; ++i) {
9433c188 2144 mutex_init(&ibdev->qp1_proxy_lock[i]);
cfcde11c
OG		 2145 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2146 IB_LINK_LAYER_ETHERNET) {
2147 err = mlx4_counter_alloc(ibdev->dev, &ibdev->counters[i]);
2148 if (err)
2149 ibdev->counters[i] = -1;
3839d8ac
DC		 2150 } else {
2151 ibdev->counters[i] = -1;
2152 }
cfcde11c
OG		 2153 }
2154
4196670b
MB		 2155 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2156 ib_num_ports++;
2157
225c7b1f
RD		 2158 spin_lock_init(&ibdev->sm_lock);
2159 mutex_init(&ibdev->cap_mask_mutex);
2160
4196670b
MB		 2161 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2162 ib_num_ports) {
c1c98501
MB		 2163 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2164 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2165 MLX4_IB_UC_STEER_QPN_ALIGN,
2166 &ibdev->steer_qpn_base);
2167 if (err)
2168 goto err_counter;
2169
2170 ibdev->ib_uc_qpns_bitmap =
2171 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2172 sizeof(long),
2173 GFP_KERNEL);
2174 if (!ibdev->ib_uc_qpns_bitmap) {
2175 dev_err(&dev->pdev->dev, "bit map alloc failed\n");
2176 goto err_steer_qp_release;
2177 }
2178
2179 bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
2180
2181 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2182 dev, ibdev->steer_qpn_base,
2183 ibdev->steer_qpn_base +
2184 ibdev->steer_qpn_count - 1);
2185 if (err)
2186 goto err_steer_free_bitmap;
2187 }
2188
9a6edb60 2189 if (ib_register_device(&ibdev->ib_dev, NULL))
c1c98501 2190 goto err_steer_free_bitmap;
225c7b1f
RD		 2191
2192 if (mlx4_ib_mad_init(ibdev))
2193 goto err_reg;
2194
fc06573d
JM		 2195 if (mlx4_ib_init_sriov(ibdev))
2196 goto err_mad;
2197
d487ee77
MS		 2198 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) {
2199 if (!iboe->nb.notifier_call) {
2200 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2201 err = register_netdevice_notifier(&iboe->nb);
2202 if (err) {
2203 iboe->nb.notifier_call = NULL;
2204 goto err_notif;
2205 }
2206 }
2207 if (!iboe->nb_inet.notifier_call) {
2208 iboe->nb_inet.notifier_call = mlx4_ib_inet_event;
2209 err = register_inetaddr_notifier(&iboe->nb_inet);
2210 if (err) {
2211 iboe->nb_inet.notifier_call = NULL;
2212 goto err_notif;
2213 }
2214 }
27cdef63 2215#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 2216 if (!iboe->nb_inet6.notifier_call) {
2217 iboe->nb_inet6.notifier_call = mlx4_ib_inet6_event;
2218 err = register_inet6addr_notifier(&iboe->nb_inet6);
2219 if (err) {
2220 iboe->nb_inet6.notifier_call = NULL;
2221 goto err_notif;
2222 }
2223 }
2224#endif
ad4885d2
MS		 2225 for (i = 1 ; i <= ibdev->num_ports ; ++i)
2226 reset_gid_table(ibdev, i);
4ce5a574 2227 rtnl_lock();
9433c188 2228 mlx4_ib_scan_netdevs(ibdev, NULL, 0);
4ce5a574 2229 rtnl_unlock();
d487ee77 2230 mlx4_ib_init_gid_table(ibdev);
fa417f7b
EC		 2231 }
2232
035b1032 2233 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
f4e91eb4 2234 if (device_create_file(&ibdev->ib_dev.dev,
035b1032 2235 mlx4_class_attributes[j]))
fa417f7b 2236 goto err_notif;
cd9281d8
JM		 2237 }
2238
3b4a8cd5
JM		 2239 ibdev->ib_active = true;
2240
54679e14
JM		 2241 if (mlx4_is_mfunc(ibdev->dev))
2242 init_pkeys(ibdev);
2243
3806d08c
JM		 2244 /* create paravirt contexts for any VFs which are active */
2245 if (mlx4_is_master(ibdev->dev)) {
2246 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2247 if (j == mlx4_master_func_num(ibdev->dev))
2248 continue;
2249 if (mlx4_is_slave_active(ibdev->dev, j))
2250 do_slave_init(ibdev, j, 1);
2251 }
2252 }
225c7b1f
RD		 2253 return ibdev;
2254
fa417f7b 2255err_notif:
d487ee77
MS		 2256 if (ibdev->iboe.nb.notifier_call) {
2257 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2258 pr_warn("failure unregistering notifier\n");
2259 ibdev->iboe.nb.notifier_call = NULL;
2260 }
2261 if (ibdev->iboe.nb_inet.notifier_call) {
2262 if (unregister_inetaddr_notifier(&ibdev->iboe.nb_inet))
2263 pr_warn("failure unregistering notifier\n");
2264 ibdev->iboe.nb_inet.notifier_call = NULL;
2265 }
27cdef63 2266#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 2267 if (ibdev->iboe.nb_inet6.notifier_call) {
2268 if (unregister_inet6addr_notifier(&ibdev->iboe.nb_inet6))
2269 pr_warn("failure unregistering notifier\n");
2270 ibdev->iboe.nb_inet6.notifier_call = NULL;
2271 }
2272#endif
fa417f7b
EC		 2273 flush_workqueue(wq);
2274
fc06573d
JM		 2275 mlx4_ib_close_sriov(ibdev);
2276
2277err_mad:
2278 mlx4_ib_mad_cleanup(ibdev);
2279
225c7b1f
RD		 2280err_reg:
2281 ib_unregister_device(&ibdev->ib_dev);
2282
c1c98501
MB		 2283err_steer_free_bitmap:
2284 kfree(ibdev->ib_uc_qpns_bitmap);
2285
2286err_steer_qp_release:
2287 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2288 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2289 ibdev->steer_qpn_count);
cfcde11c
OG		 2290err_counter:
2291 for (; i; --i)
4af3ce0d
RD		 2292 if (ibdev->counters[i - 1] != -1)
2293 mlx4_counter_free(ibdev->dev, ibdev->counters[i - 1]);
cfcde11c 2294
225c7b1f
RD		 2295err_map:
2296 iounmap(ibdev->uar_map);
2297
2298err_uar:
2299 mlx4_uar_free(dev, &ibdev->priv_uar);
2300
2301err_pd:
2302 mlx4_pd_free(dev, ibdev->priv_pdn);
2303
2304err_dealloc:
2305 ib_dealloc_device(&ibdev->ib_dev);
2306
2307 return NULL;
2308}
2309
c1c98501
MB		 2310int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2311{
2312 int offset;
2313
2314 WARN_ON(!dev->ib_uc_qpns_bitmap);
2315
2316 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2317 dev->steer_qpn_count,
2318 get_count_order(count));
2319 if (offset < 0)
2320 return offset;
2321
2322 *qpn = dev->steer_qpn_base + offset;
2323 return 0;
2324}
2325
2326void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2327{
2328 if (!qpn ||
2329 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2330 return;
2331
2332 BUG_ON(qpn < dev->steer_qpn_base);
2333
2334 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2335 qpn - dev->steer_qpn_base,
2336 get_count_order(count));
2337}
2338
2339int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2340 int is_attach)
2341{
2342 int err;
2343 size_t flow_size;
2344 struct ib_flow_attr *flow = NULL;
2345 struct ib_flow_spec_ib *ib_spec;
2346
2347 if (is_attach) {
2348 flow_size = sizeof(struct ib_flow_attr) +
2349 sizeof(struct ib_flow_spec_ib);
2350 flow = kzalloc(flow_size, GFP_KERNEL);
2351 if (!flow)
2352 return -ENOMEM;
2353 flow->port = mqp->port;
2354 flow->num_of_specs = 1;
2355 flow->size = flow_size;
2356 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2357 ib_spec->type = IB_FLOW_SPEC_IB;
2358 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2359 /* Add an empty rule for IB L2 */
2360 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2361
2362 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
2363 IB_FLOW_DOMAIN_NIC,
2364 MLX4_FS_REGULAR,
2365 &mqp->reg_id);
2366 } else {
2367 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
2368 }
2369 kfree(flow);
2370 return err;
2371}
2372
225c7b1f
RD		 2373static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
2374{
2375 struct mlx4_ib_dev *ibdev = ibdev_ptr;
2376 int p;
2377
fc06573d 2378 mlx4_ib_close_sriov(ibdev);
a6a47771
YP		 2379 mlx4_ib_mad_cleanup(ibdev);
2380 ib_unregister_device(&ibdev->ib_dev);
fa417f7b
EC		 2381 if (ibdev->iboe.nb.notifier_call) {
2382 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
987c8f8f 2383 pr_warn("failure unregistering notifier\n");
fa417f7b
EC		 2384 ibdev->iboe.nb.notifier_call = NULL;
2385 }
c1c98501
MB		 2386
2387 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
2388 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2389 ibdev->steer_qpn_count);
2390 kfree(ibdev->ib_uc_qpns_bitmap);
2391 }
2392
d487ee77
MS		 2393 if (ibdev->iboe.nb_inet.notifier_call) {
2394 if (unregister_inetaddr_notifier(&ibdev->iboe.nb_inet))
2395 pr_warn("failure unregistering notifier\n");
2396 ibdev->iboe.nb_inet.notifier_call = NULL;
2397 }
27cdef63 2398#if IS_ENABLED(CONFIG_IPV6)
d487ee77
MS		 2399 if (ibdev->iboe.nb_inet6.notifier_call) {
2400 if (unregister_inet6addr_notifier(&ibdev->iboe.nb_inet6))
2401 pr_warn("failure unregistering notifier\n");
2402 ibdev->iboe.nb_inet6.notifier_call = NULL;
2403 }
2404#endif
fb1b5034 2405
fa417f7b 2406 iounmap(ibdev->uar_map);
cfcde11c 2407 for (p = 0; p < ibdev->num_ports; ++p)
4af3ce0d
RD		 2408 if (ibdev->counters[p] != -1)
2409 mlx4_counter_free(ibdev->dev, ibdev->counters[p]);
fa417f7b 2410 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
225c7b1f
RD		 2411 mlx4_CLOSE_PORT(dev, p);
2412
e605b743
SP		 2413 mlx4_ib_free_eqs(dev, ibdev);
2414
225c7b1f
RD		 2415 mlx4_uar_free(dev, &ibdev->priv_uar);
2416 mlx4_pd_free(dev, ibdev->priv_pdn);
2417 ib_dealloc_device(&ibdev->ib_dev);
2418}
2419
fc06573d
JM		 2420static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
2421{
2422 struct mlx4_ib_demux_work **dm = NULL;
2423 struct mlx4_dev *dev = ibdev->dev;
2424 int i;
2425 unsigned long flags;
449fc488
MB		 2426 struct mlx4_active_ports actv_ports;
2427 unsigned int ports;
2428 unsigned int first_port;
fc06573d
JM		 2429
2430 if (!mlx4_is_master(dev))
2431 return;
2432
449fc488
MB		 2433 actv_ports = mlx4_get_active_ports(dev, slave);
2434 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2435 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2436
2437 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
fc06573d
JM		 2438 if (!dm) {
2439 pr_err("failed to allocate memory for tunneling qp update\n");
2440 goto out;
2441 }
2442
449fc488 2443 for (i = 0; i < ports; i++) {
fc06573d
JM		 2444 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
2445 if (!dm[i]) {
2446 pr_err("failed to allocate memory for tunneling qp update work struct\n");
2447 for (i = 0; i < dev->caps.num_ports; i++) {
2448 if (dm[i])
2449 kfree(dm[i]);
2450 }
2451 goto out;
2452 }
2453 }
2454 /* initialize or tear down tunnel QPs for the slave */
449fc488 2455 for (i = 0; i < ports; i++) {
fc06573d 2456 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
449fc488 2457 dm[i]->port = first_port + i + 1;
fc06573d
JM		 2458 dm[i]->slave = slave;
2459 dm[i]->do_init = do_init;
2460 dm[i]->dev = ibdev;
2461 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
2462 if (!ibdev->sriov.is_going_down)
2463 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
2464 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
2465 }
2466out:
c89d1271 2467 kfree(dm);
fc06573d
JM		 2468 return;
2469}
2470
225c7b1f 2471static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
00f5ce99 2472 enum mlx4_dev_event event, unsigned long param)
225c7b1f
RD		 2473{
2474 struct ib_event ibev;
7ff93f8b 2475 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
00f5ce99
JM		 2476 struct mlx4_eqe *eqe = NULL;
2477 struct ib_event_work *ew;
fc06573d 2478 int p = 0;
00f5ce99
JM		 2479
2480 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
2481 eqe = (struct mlx4_eqe *)param;
2482 else
fc06573d 2483 p = (int) param;
225c7b1f
RD		 2484
2485 switch (event) {
37608eea 2486 case MLX4_DEV_EVENT_PORT_UP:
fc06573d
JM		 2487 if (p > ibdev->num_ports)
2488 return;
a0c64a17
JM		 2489 if (mlx4_is_master(dev) &&
2490 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
2491 IB_LINK_LAYER_INFINIBAND) {
2492 mlx4_ib_invalidate_all_guid_record(ibdev, p);
2493 }
37608eea 2494 ibev.event = IB_EVENT_PORT_ACTIVE;
225c7b1f
RD		 2495 break;
2496
37608eea 2497 case MLX4_DEV_EVENT_PORT_DOWN:
fc06573d
JM		 2498 if (p > ibdev->num_ports)
2499 return;
37608eea
RD		 2500 ibev.event = IB_EVENT_PORT_ERR;
2501 break;
2502
2503 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3b4a8cd5 2504 ibdev->ib_active = false;
225c7b1f
RD		 2505 ibev.event = IB_EVENT_DEVICE_FATAL;
2506 break;
2507
00f5ce99
JM		 2508 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
2509 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
2510 if (!ew) {
2511 pr_err("failed to allocate memory for events work\n");
2512 break;
2513 }
2514
2515 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
2516 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
2517 ew->ib_dev = ibdev;
992e8e6e
JM		 2518 /* need to queue only for port owner, which uses GEN_EQE */
2519 if (mlx4_is_master(dev))
2520 queue_work(wq, &ew->work);
2521 else
2522 handle_port_mgmt_change_event(&ew->work);
00f5ce99
JM		 2523 return;
2524
fc06573d
JM		 2525 case MLX4_DEV_EVENT_SLAVE_INIT:
2526 /* here, p is the slave id */
2527 do_slave_init(ibdev, p, 1);
2528 return;
2529
2530 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
2531 /* here, p is the slave id */
2532 do_slave_init(ibdev, p, 0);
2533 return;
2534
225c7b1f
RD		 2535 default:
2536 return;
2537 }
2538
2539 ibev.device = ibdev_ptr;
fc06573d 2540 ibev.element.port_num = (u8) p;
225c7b1f
RD		 2541
2542 ib_dispatch_event(&ibev);
2543}
2544
2545static struct mlx4_interface mlx4_ib_interface = {
fa417f7b
EC		 2546 .add = mlx4_ib_add,
2547 .remove = mlx4_ib_remove,
2548 .event = mlx4_ib_event,
0345584e 2549 .protocol = MLX4_PROT_IB_IPV6
225c7b1f
RD		 2550};
2551
2552static int __init mlx4_ib_init(void)
2553{
fa417f7b
EC		 2554 int err;
2555
2556 wq = create_singlethread_workqueue("mlx4_ib");
2557 if (!wq)
2558 return -ENOMEM;
2559
b9c5d6a6
OD		 2560 err = mlx4_ib_mcg_init();
2561 if (err)
2562 goto clean_wq;
2563
fa417f7b 2564 err = mlx4_register_interface(&mlx4_ib_interface);
b9c5d6a6
OD		 2565 if (err)
2566 goto clean_mcg;
fa417f7b
EC		 2567
2568 return 0;
b9c5d6a6
OD		 2569
2570clean_mcg:
2571 mlx4_ib_mcg_destroy();
2572
2573clean_wq:
2574 destroy_workqueue(wq);
2575 return err;
225c7b1f
RD		 2576}
2577
2578static void __exit mlx4_ib_cleanup(void)
2579{
2580 mlx4_unregister_interface(&mlx4_ib_interface);
b9c5d6a6 2581 mlx4_ib_mcg_destroy();
fa417f7b 2582 destroy_workqueue(wq);
225c7b1f
RD		 2583}
2584
2585module_init(mlx4_ib_init);
2586module_exit(mlx4_ib_cleanup);
Linux kernel - Deliverables
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