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IB/mlx5: Implement callbacks for manipulating VFs
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
2811ba51 44#include <rdma/ib_cache.h>
1b5daf11 45#include <linux/mlx5/vport.h>
e126ba97
EC		 46#include <rdma/ib_smi.h>
47#include <rdma/ib_umem.h>
038d2ef8
MG		 48#include <linux/in.h>
49#include <linux/etherdevice.h>
50#include <linux/mlx5/fs.h>
e126ba97
EC		 51#include "user.h"
52#include "mlx5_ib.h"
53
54#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 55#define DRIVER_VERSION "2.2-1"
56#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 57
58MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
59MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
60MODULE_LICENSE("Dual BSD/GPL");
61MODULE_VERSION(DRIVER_VERSION);
62
9603b61d
JM		 63static int deprecated_prof_sel = 2;
64module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
65MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 66
67static char mlx5_version[] =
68 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
69 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
70
da7525d2
EBE		 71enum {
72 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
73};
74
1b5daf11 75static enum rdma_link_layer
ebd61f68 76mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 77{
ebd61f68 78 switch (port_type_cap) {
1b5daf11
MD		 79 case MLX5_CAP_PORT_TYPE_IB:
80 return IB_LINK_LAYER_INFINIBAND;
81 case MLX5_CAP_PORT_TYPE_ETH:
82 return IB_LINK_LAYER_ETHERNET;
83 default:
84 return IB_LINK_LAYER_UNSPECIFIED;
85 }
86}
87
ebd61f68
AS		 88static enum rdma_link_layer
89mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
90{
91 struct mlx5_ib_dev *dev = to_mdev(device);
92 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
93
94 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
95}
96
fc24fc5e
AS		 97static int mlx5_netdev_event(struct notifier_block *this,
98 unsigned long event, void *ptr)
99{
100 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
101 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
102 roce.nb);
103
104 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
105 return NOTIFY_DONE;
106
107 write_lock(&ibdev->roce.netdev_lock);
108 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
109 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
110 write_unlock(&ibdev->roce.netdev_lock);
111
112 return NOTIFY_DONE;
113}
114
115static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
116 u8 port_num)
117{
118 struct mlx5_ib_dev *ibdev = to_mdev(device);
119 struct net_device *ndev;
120
121 /* Ensure ndev does not disappear before we invoke dev_hold()
122 */
123 read_lock(&ibdev->roce.netdev_lock);
124 ndev = ibdev->roce.netdev;
125 if (ndev)
126 dev_hold(ndev);
127 read_unlock(&ibdev->roce.netdev_lock);
128
129 return ndev;
130}
131
3f89a643
AS		 132static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
133 struct ib_port_attr *props)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 struct net_device *ndev;
137 enum ib_mtu ndev_ib_mtu;
c876a1b7 138 u16 qkey_viol_cntr;
3f89a643
AS		 139
140 memset(props, 0, sizeof(*props));
141
142 props->port_cap_flags |= IB_PORT_CM_SUP;
143 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
144
145 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
146 roce_address_table_size);
147 props->max_mtu = IB_MTU_4096;
148 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
149 props->pkey_tbl_len = 1;
150 props->state = IB_PORT_DOWN;
151 props->phys_state = 3;
152
c876a1b7
LR		 153 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
154 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 155
156 ndev = mlx5_ib_get_netdev(device, port_num);
157 if (!ndev)
158 return 0;
159
160 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
161 props->state = IB_PORT_ACTIVE;
162 props->phys_state = 5;
163 }
164
165 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
166
167 dev_put(ndev);
168
169 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
170
171 props->active_width = IB_WIDTH_4X; /* TODO */
172 props->active_speed = IB_SPEED_QDR; /* TODO */
173
174 return 0;
175}
176
3cca2606
AS		 177static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
178 const struct ib_gid_attr *attr,
179 void *mlx5_addr)
180{
181#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
182 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
183 source_l3_address);
184 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
185 source_mac_47_32);
186
187 if (!gid)
188 return;
189
190 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
191
192 if (is_vlan_dev(attr->ndev)) {
193 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
194 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
195 }
196
197 switch (attr->gid_type) {
198 case IB_GID_TYPE_IB:
199 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
200 break;
201 case IB_GID_TYPE_ROCE_UDP_ENCAP:
202 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
203 break;
204
205 default:
206 WARN_ON(true);
207 }
208
209 if (attr->gid_type != IB_GID_TYPE_IB) {
210 if (ipv6_addr_v4mapped((void *)gid))
211 MLX5_SET_RA(mlx5_addr, roce_l3_type,
212 MLX5_ROCE_L3_TYPE_IPV4);
213 else
214 MLX5_SET_RA(mlx5_addr, roce_l3_type,
215 MLX5_ROCE_L3_TYPE_IPV6);
216 }
217
218 if ((attr->gid_type == IB_GID_TYPE_IB) ||
219 !ipv6_addr_v4mapped((void *)gid))
220 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
221 else
222 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
223}
224
225static int set_roce_addr(struct ib_device *device, u8 port_num,
226 unsigned int index,
227 const union ib_gid *gid,
228 const struct ib_gid_attr *attr)
229{
230 struct mlx5_ib_dev *dev = to_mdev(device);
231 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
232 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
233 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
234 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
235
236 if (ll != IB_LINK_LAYER_ETHERNET)
237 return -EINVAL;
238
239 memset(in, 0, sizeof(in));
240
241 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
242
243 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
244 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
245
246 memset(out, 0, sizeof(out));
247 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
248}
249
250static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
251 unsigned int index, const union ib_gid *gid,
252 const struct ib_gid_attr *attr,
253 __always_unused void **context)
254{
255 return set_roce_addr(device, port_num, index, gid, attr);
256}
257
258static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
259 unsigned int index, __always_unused void **context)
260{
261 return set_roce_addr(device, port_num, index, NULL, NULL);
262}
263
2811ba51
AS		 264__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
265 int index)
266{
267 struct ib_gid_attr attr;
268 union ib_gid gid;
269
270 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
271 return 0;
272
273 if (!attr.ndev)
274 return 0;
275
276 dev_put(attr.ndev);
277
278 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
279 return 0;
280
281 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
282}
283
1b5daf11
MD		 284static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
285{
d603c809 286 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
1b5daf11
MD		 287}
288
289enum {
290 MLX5_VPORT_ACCESS_METHOD_MAD,
291 MLX5_VPORT_ACCESS_METHOD_HCA,
292 MLX5_VPORT_ACCESS_METHOD_NIC,
293};
294
295static int mlx5_get_vport_access_method(struct ib_device *ibdev)
296{
297 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
298 return MLX5_VPORT_ACCESS_METHOD_MAD;
299
ebd61f68 300 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 301 IB_LINK_LAYER_ETHERNET)
302 return MLX5_VPORT_ACCESS_METHOD_NIC;
303
304 return MLX5_VPORT_ACCESS_METHOD_HCA;
305}
306
da7525d2
EBE		 307static void get_atomic_caps(struct mlx5_ib_dev *dev,
308 struct ib_device_attr *props)
309{
310 u8 tmp;
311 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
312 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
313 u8 atomic_req_8B_endianness_mode =
314 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
315
316 /* Check if HW supports 8 bytes standard atomic operations and capable
317 * of host endianness respond
318 */
319 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
320 if (((atomic_operations & tmp) == tmp) &&
321 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
322 (atomic_req_8B_endianness_mode)) {
323 props->atomic_cap = IB_ATOMIC_HCA;
324 } else {
325 props->atomic_cap = IB_ATOMIC_NONE;
326 }
327}
328
1b5daf11
MD		 329static int mlx5_query_system_image_guid(struct ib_device *ibdev,
330 __be64 *sys_image_guid)
331{
332 struct mlx5_ib_dev *dev = to_mdev(ibdev);
333 struct mlx5_core_dev *mdev = dev->mdev;
334 u64 tmp;
335 int err;
336
337 switch (mlx5_get_vport_access_method(ibdev)) {
338 case MLX5_VPORT_ACCESS_METHOD_MAD:
339 return mlx5_query_mad_ifc_system_image_guid(ibdev,
340 sys_image_guid);
341
342 case MLX5_VPORT_ACCESS_METHOD_HCA:
343 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 344 break;
345
346 case MLX5_VPORT_ACCESS_METHOD_NIC:
347 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
348 break;
1b5daf11
MD		 349
350 default:
351 return -EINVAL;
352 }
3f89a643
AS		 353
354 if (!err)
355 *sys_image_guid = cpu_to_be64(tmp);
356
357 return err;
358
1b5daf11
MD		 359}
360
361static int mlx5_query_max_pkeys(struct ib_device *ibdev,
362 u16 *max_pkeys)
363{
364 struct mlx5_ib_dev *dev = to_mdev(ibdev);
365 struct mlx5_core_dev *mdev = dev->mdev;
366
367 switch (mlx5_get_vport_access_method(ibdev)) {
368 case MLX5_VPORT_ACCESS_METHOD_MAD:
369 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
370
371 case MLX5_VPORT_ACCESS_METHOD_HCA:
372 case MLX5_VPORT_ACCESS_METHOD_NIC:
373 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
374 pkey_table_size));
375 return 0;
376
377 default:
378 return -EINVAL;
379 }
380}
381
382static int mlx5_query_vendor_id(struct ib_device *ibdev,
383 u32 *vendor_id)
384{
385 struct mlx5_ib_dev *dev = to_mdev(ibdev);
386
387 switch (mlx5_get_vport_access_method(ibdev)) {
388 case MLX5_VPORT_ACCESS_METHOD_MAD:
389 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
390
391 case MLX5_VPORT_ACCESS_METHOD_HCA:
392 case MLX5_VPORT_ACCESS_METHOD_NIC:
393 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
394
395 default:
396 return -EINVAL;
397 }
398}
399
400static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
401 __be64 *node_guid)
402{
403 u64 tmp;
404 int err;
405
406 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
407 case MLX5_VPORT_ACCESS_METHOD_MAD:
408 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
409
410 case MLX5_VPORT_ACCESS_METHOD_HCA:
411 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 412 break;
413
414 case MLX5_VPORT_ACCESS_METHOD_NIC:
415 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
416 break;
1b5daf11
MD		 417
418 default:
419 return -EINVAL;
420 }
3f89a643
AS		 421
422 if (!err)
423 *node_guid = cpu_to_be64(tmp);
424
425 return err;
1b5daf11
MD		 426}
427
428struct mlx5_reg_node_desc {
429 u8 desc[64];
430};
431
432static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
433{
434 struct mlx5_reg_node_desc in;
435
436 if (mlx5_use_mad_ifc(dev))
437 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
438
439 memset(&in, 0, sizeof(in));
440
441 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
442 sizeof(struct mlx5_reg_node_desc),
443 MLX5_REG_NODE_DESC, 0, 0);
444}
445
e126ba97 446static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 447 struct ib_device_attr *props,
448 struct ib_udata *uhw)
e126ba97
EC		 449{
450 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 451 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 452 int err = -ENOMEM;
453 int max_rq_sg;
454 int max_sq_sg;
e0238a6a 455 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 456
2528e33e
MB		 457 if (uhw->inlen || uhw->outlen)
458 return -EINVAL;
459
1b5daf11
MD		 460 memset(props, 0, sizeof(*props));
461 err = mlx5_query_system_image_guid(ibdev,
462 &props->sys_image_guid);
463 if (err)
464 return err;
e126ba97 465
1b5daf11 466 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 467 if (err)
1b5daf11 468 return err;
e126ba97 469
1b5daf11
MD		 470 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
471 if (err)
472 return err;
e126ba97 473
9603b61d
JM		 474 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
475 (fw_rev_min(dev->mdev) << 16) |
476 fw_rev_sub(dev->mdev);
e126ba97
EC		 477 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
478 IB_DEVICE_PORT_ACTIVE_EVENT |
479 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 480 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 481
482 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 483 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 484 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 485 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 486 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 487 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 488 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 489 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 490 if (MLX5_CAP_GEN(mdev, imaicl)) {
491 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
492 IB_DEVICE_MEM_WINDOW_TYPE_2B;
493 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 494 /* We support 'Gappy' memory registration too */
495 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 496 }
e126ba97 497 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 498 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 499 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
500 /* At this stage no support for signature handover */
501 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
502 IB_PROT_T10DIF_TYPE_2 |
503 IB_PROT_T10DIF_TYPE_3;
504 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
505 IB_GUARD_T10DIF_CSUM;
506 }
938fe83c 507 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 508 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 509
88115fe7
BW		 510 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
511 (MLX5_CAP_ETH(dev->mdev, csum_cap)))
512 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
513
f0313965
ES		 514 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
515 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
516 props->device_cap_flags |= IB_DEVICE_UD_TSO;
517 }
518
1b5daf11
MD		 519 props->vendor_part_id = mdev->pdev->device;
520 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 521
522 props->max_mr_size = ~0ull;
e0238a6a 523 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 524 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
525 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
526 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
527 sizeof(struct mlx5_wqe_data_seg);
528 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
529 sizeof(struct mlx5_wqe_ctrl_seg)) /
530 sizeof(struct mlx5_wqe_data_seg);
e126ba97 531 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 532 props->max_sge_rd = props->max_sge;
938fe83c 533 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 534 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 535 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
536 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
537 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
538 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
539 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
540 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
541 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 542 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 543 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 544 props->max_fast_reg_page_list_len =
545 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 546 get_atomic_caps(dev, props);
81bea28f 547 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 548 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
549 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 550 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
551 props->max_mcast_grp;
552 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 553 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
554 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 555
8cdd312c 556#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 557 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 558 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
559 props->odp_caps = dev->odp_caps;
560#endif
561
051f2630
LR		 562 if (MLX5_CAP_GEN(mdev, cd))
563 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
564
eff901d3
EC		 565 if (!mlx5_core_is_pf(mdev))
566 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
567
1b5daf11 568 return 0;
e126ba97
EC		 569}
570
1b5daf11
MD		 571enum mlx5_ib_width {
572 MLX5_IB_WIDTH_1X = 1 << 0,
573 MLX5_IB_WIDTH_2X = 1 << 1,
574 MLX5_IB_WIDTH_4X = 1 << 2,
575 MLX5_IB_WIDTH_8X = 1 << 3,
576 MLX5_IB_WIDTH_12X = 1 << 4
577};
578
579static int translate_active_width(struct ib_device *ibdev, u8 active_width,
580 u8 *ib_width)
e126ba97
EC		 581{
582 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 583 int err = 0;
584
585 if (active_width & MLX5_IB_WIDTH_1X) {
586 *ib_width = IB_WIDTH_1X;
587 } else if (active_width & MLX5_IB_WIDTH_2X) {
588 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
589 (int)active_width);
590 err = -EINVAL;
591 } else if (active_width & MLX5_IB_WIDTH_4X) {
592 *ib_width = IB_WIDTH_4X;
593 } else if (active_width & MLX5_IB_WIDTH_8X) {
594 *ib_width = IB_WIDTH_8X;
595 } else if (active_width & MLX5_IB_WIDTH_12X) {
596 *ib_width = IB_WIDTH_12X;
597 } else {
598 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
599 (int)active_width);
600 err = -EINVAL;
e126ba97
EC		 601 }
602
1b5daf11
MD		 603 return err;
604}
e126ba97 605
1b5daf11
MD		 606static int mlx5_mtu_to_ib_mtu(int mtu)
607{
608 switch (mtu) {
609 case 256: return 1;
610 case 512: return 2;
611 case 1024: return 3;
612 case 2048: return 4;
613 case 4096: return 5;
614 default:
615 pr_warn("invalid mtu\n");
616 return -1;
e126ba97 617 }
1b5daf11 618}
e126ba97 619
1b5daf11
MD		 620enum ib_max_vl_num {
621 __IB_MAX_VL_0 = 1,
622 __IB_MAX_VL_0_1 = 2,
623 __IB_MAX_VL_0_3 = 3,
624 __IB_MAX_VL_0_7 = 4,
625 __IB_MAX_VL_0_14 = 5,
626};
e126ba97 627
1b5daf11
MD		 628enum mlx5_vl_hw_cap {
629 MLX5_VL_HW_0 = 1,
630 MLX5_VL_HW_0_1 = 2,
631 MLX5_VL_HW_0_2 = 3,
632 MLX5_VL_HW_0_3 = 4,
633 MLX5_VL_HW_0_4 = 5,
634 MLX5_VL_HW_0_5 = 6,
635 MLX5_VL_HW_0_6 = 7,
636 MLX5_VL_HW_0_7 = 8,
637 MLX5_VL_HW_0_14 = 15
638};
e126ba97 639
1b5daf11
MD		 640static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
641 u8 *max_vl_num)
642{
643 switch (vl_hw_cap) {
644 case MLX5_VL_HW_0:
645 *max_vl_num = __IB_MAX_VL_0;
646 break;
647 case MLX5_VL_HW_0_1:
648 *max_vl_num = __IB_MAX_VL_0_1;
649 break;
650 case MLX5_VL_HW_0_3:
651 *max_vl_num = __IB_MAX_VL_0_3;
652 break;
653 case MLX5_VL_HW_0_7:
654 *max_vl_num = __IB_MAX_VL_0_7;
655 break;
656 case MLX5_VL_HW_0_14:
657 *max_vl_num = __IB_MAX_VL_0_14;
658 break;
e126ba97 659
1b5daf11
MD		 660 default:
661 return -EINVAL;
e126ba97 662 }
e126ba97 663
1b5daf11 664 return 0;
e126ba97
EC		 665}
666
1b5daf11
MD		 667static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
668 struct ib_port_attr *props)
e126ba97 669{
1b5daf11
MD		 670 struct mlx5_ib_dev *dev = to_mdev(ibdev);
671 struct mlx5_core_dev *mdev = dev->mdev;
672 struct mlx5_hca_vport_context *rep;
673 int max_mtu;
674 int oper_mtu;
675 int err;
676 u8 ib_link_width_oper;
677 u8 vl_hw_cap;
e126ba97 678
1b5daf11
MD		 679 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
680 if (!rep) {
681 err = -ENOMEM;
e126ba97 682 goto out;
e126ba97 683 }
e126ba97 684
1b5daf11 685 memset(props, 0, sizeof(*props));
e126ba97 686
1b5daf11 687 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 688 if (err)
689 goto out;
690
1b5daf11
MD		 691 props->lid = rep->lid;
692 props->lmc = rep->lmc;
693 props->sm_lid = rep->sm_lid;
694 props->sm_sl = rep->sm_sl;
695 props->state = rep->vport_state;
696 props->phys_state = rep->port_physical_state;
697 props->port_cap_flags = rep->cap_mask1;
698 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
699 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
700 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
701 props->bad_pkey_cntr = rep->pkey_violation_counter;
702 props->qkey_viol_cntr = rep->qkey_violation_counter;
703 props->subnet_timeout = rep->subnet_timeout;
704 props->init_type_reply = rep->init_type_reply;
eff901d3 705 props->grh_required = rep->grh_required;
e126ba97 706
1b5daf11
MD		 707 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
708 if (err)
e126ba97 709 goto out;
e126ba97 710
1b5daf11
MD		 711 err = translate_active_width(ibdev, ib_link_width_oper,
712 &props->active_width);
713 if (err)
714 goto out;
715 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
716 port);
e126ba97
EC		 717 if (err)
718 goto out;
719
facc9699 720 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 721
1b5daf11 722 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 723
facc9699 724 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 725
1b5daf11 726 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 727
1b5daf11
MD		 728 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
729 if (err)
730 goto out;
e126ba97 731
1b5daf11
MD		 732 err = translate_max_vl_num(ibdev, vl_hw_cap,
733 &props->max_vl_num);
e126ba97 734out:
1b5daf11 735 kfree(rep);
e126ba97
EC		 736 return err;
737}
738
1b5daf11
MD		 739int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
740 struct ib_port_attr *props)
e126ba97 741{
1b5daf11
MD		 742 switch (mlx5_get_vport_access_method(ibdev)) {
743 case MLX5_VPORT_ACCESS_METHOD_MAD:
744 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 745
1b5daf11
MD		 746 case MLX5_VPORT_ACCESS_METHOD_HCA:
747 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 748
3f89a643
AS		 749 case MLX5_VPORT_ACCESS_METHOD_NIC:
750 return mlx5_query_port_roce(ibdev, port, props);
751
1b5daf11
MD		 752 default:
753 return -EINVAL;
754 }
755}
e126ba97 756
1b5daf11
MD		 757static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
758 union ib_gid *gid)
759{
760 struct mlx5_ib_dev *dev = to_mdev(ibdev);
761 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 762
1b5daf11
MD		 763 switch (mlx5_get_vport_access_method(ibdev)) {
764 case MLX5_VPORT_ACCESS_METHOD_MAD:
765 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 766
1b5daf11
MD		 767 case MLX5_VPORT_ACCESS_METHOD_HCA:
768 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
769
770 default:
771 return -EINVAL;
772 }
e126ba97 773
e126ba97
EC		 774}
775
1b5daf11
MD		 776static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
777 u16 *pkey)
778{
779 struct mlx5_ib_dev *dev = to_mdev(ibdev);
780 struct mlx5_core_dev *mdev = dev->mdev;
781
782 switch (mlx5_get_vport_access_method(ibdev)) {
783 case MLX5_VPORT_ACCESS_METHOD_MAD:
784 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
785
786 case MLX5_VPORT_ACCESS_METHOD_HCA:
787 case MLX5_VPORT_ACCESS_METHOD_NIC:
788 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
789 pkey);
790 default:
791 return -EINVAL;
792 }
793}
e126ba97
EC		 794
795static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
796 struct ib_device_modify *props)
797{
798 struct mlx5_ib_dev *dev = to_mdev(ibdev);
799 struct mlx5_reg_node_desc in;
800 struct mlx5_reg_node_desc out;
801 int err;
802
803 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
804 return -EOPNOTSUPP;
805
806 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
807 return 0;
808
809 /*
810 * If possible, pass node desc to FW, so it can generate
811 * a 144 trap. If cmd fails, just ignore.
812 */
813 memcpy(&in, props->node_desc, 64);
9603b61d 814 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 815 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
816 if (err)
817 return err;
818
819 memcpy(ibdev->node_desc, props->node_desc, 64);
820
821 return err;
822}
823
824static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
825 struct ib_port_modify *props)
826{
827 struct mlx5_ib_dev *dev = to_mdev(ibdev);
828 struct ib_port_attr attr;
829 u32 tmp;
830 int err;
831
832 mutex_lock(&dev->cap_mask_mutex);
833
834 err = mlx5_ib_query_port(ibdev, port, &attr);
835 if (err)
836 goto out;
837
838 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
839 ~props->clr_port_cap_mask;
840
9603b61d 841 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 842
843out:
844 mutex_unlock(&dev->cap_mask_mutex);
845 return err;
846}
847
848static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
849 struct ib_udata *udata)
850{
851 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 852 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
853 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 854 struct mlx5_ib_ucontext *context;
855 struct mlx5_uuar_info *uuari;
856 struct mlx5_uar *uars;
c1be5232 857 int gross_uuars;
e126ba97 858 int num_uars;
78c0f98c 859 int ver;
e126ba97
EC		 860 int uuarn;
861 int err;
862 int i;
f241e749 863 size_t reqlen;
a168a41c
MD		 864 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
865 max_cqe_version);
e126ba97
EC		 866
867 if (!dev->ib_active)
868 return ERR_PTR(-EAGAIN);
869
dfbee859
HA		 870 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
871 return ERR_PTR(-EINVAL);
872
78c0f98c
EC		 873 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
874 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
875 ver = 0;
a168a41c 876 else if (reqlen >= min_req_v2)
78c0f98c
EC		 877 ver = 2;
878 else
879 return ERR_PTR(-EINVAL);
880
b368d7cb 881 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 882 if (err)
883 return ERR_PTR(err);
884
b368d7cb 885 if (req.flags)
78c0f98c
EC		 886 return ERR_PTR(-EINVAL);
887
e126ba97
EC		 888 if (req.total_num_uuars > MLX5_MAX_UUARS)
889 return ERR_PTR(-ENOMEM);
890
891 if (req.total_num_uuars == 0)
892 return ERR_PTR(-EINVAL);
893
f72300c5 894 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 895 return ERR_PTR(-EOPNOTSUPP);
896
897 if (reqlen > sizeof(req) &&
898 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 899 reqlen - sizeof(req)))
b368d7cb
MB		 900 return ERR_PTR(-EOPNOTSUPP);
901
c1be5232
EC		 902 req.total_num_uuars = ALIGN(req.total_num_uuars,
903 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 904 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
905 return ERR_PTR(-EINVAL);
906
c1be5232
EC		 907 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
908 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 909 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
910 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
911 resp.cache_line_size = L1_CACHE_BYTES;
912 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
913 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
914 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
915 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
916 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 917 resp.cqe_version = min_t(__u8,
918 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
919 req.max_cqe_version);
b368d7cb
MB		 920 resp.response_length = min(offsetof(typeof(resp), response_length) +
921 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 922
923 context = kzalloc(sizeof(*context), GFP_KERNEL);
924 if (!context)
925 return ERR_PTR(-ENOMEM);
926
927 uuari = &context->uuari;
928 mutex_init(&uuari->lock);
929 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
930 if (!uars) {
931 err = -ENOMEM;
932 goto out_ctx;
933 }
934
c1be5232 935 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 936 sizeof(*uuari->bitmap),
937 GFP_KERNEL);
938 if (!uuari->bitmap) {
939 err = -ENOMEM;
940 goto out_uar_ctx;
941 }
942 /*
943 * clear all fast path uuars
944 */
c1be5232 945 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 946 uuarn = i & 3;
947 if (uuarn == 2 || uuarn == 3)
948 set_bit(i, uuari->bitmap);
949 }
950
c1be5232 951 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 952 if (!uuari->count) {
953 err = -ENOMEM;
954 goto out_bitmap;
955 }
956
957 for (i = 0; i < num_uars; i++) {
9603b61d 958 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 959 if (err)
960 goto out_count;
961 }
962
b4cfe447
HE		 963#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
964 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
965#endif
966
146d2f1a 967 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
968 err = mlx5_core_alloc_transport_domain(dev->mdev,
969 &context->tdn);
970 if (err)
971 goto out_uars;
972 }
973
e126ba97
EC		 974 INIT_LIST_HEAD(&context->db_page_list);
975 mutex_init(&context->db_page_mutex);
976
977 resp.tot_uuars = req.total_num_uuars;
938fe83c 978 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 979
f72300c5
HA		 980 if (field_avail(typeof(resp), cqe_version, udata->outlen))
981 resp.response_length += sizeof(resp.cqe_version);
b368d7cb
MB		 982
983 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
984 resp.comp_mask |=
985 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
986 resp.hca_core_clock_offset =
987 offsetof(struct mlx5_init_seg, internal_timer_h) %
988 PAGE_SIZE;
f72300c5
HA		 989 resp.response_length += sizeof(resp.hca_core_clock_offset) +
990 sizeof(resp.reserved2) +
991 sizeof(resp.reserved3);
b368d7cb
MB		 992 }
993
994 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 995 if (err)
146d2f1a 996 goto out_td;
e126ba97 997
78c0f98c 998 uuari->ver = ver;
e126ba97
EC		 999 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1000 uuari->uars = uars;
1001 uuari->num_uars = num_uars;
f72300c5
HA		 1002 context->cqe_version = resp.cqe_version;
1003
e126ba97
EC		 1004 return &context->ibucontext;
1005
146d2f1a 1006out_td:
1007 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1008 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1009
e126ba97
EC		 1010out_uars:
1011 for (i--; i >= 0; i--)
9603b61d 1012 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1013out_count:
1014 kfree(uuari->count);
1015
1016out_bitmap:
1017 kfree(uuari->bitmap);
1018
1019out_uar_ctx:
1020 kfree(uars);
1021
1022out_ctx:
1023 kfree(context);
1024 return ERR_PTR(err);
1025}
1026
1027static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1028{
1029 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1030 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1031 struct mlx5_uuar_info *uuari = &context->uuari;
1032 int i;
1033
146d2f1a 1034 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1035 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1036
e126ba97 1037 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1038 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1039 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1040 }
1041
1042 kfree(uuari->count);
1043 kfree(uuari->bitmap);
1044 kfree(uuari->uars);
1045 kfree(context);
1046
1047 return 0;
1048}
1049
1050static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1051{
9603b61d 1052 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1053}
1054
1055static int get_command(unsigned long offset)
1056{
1057 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1058}
1059
1060static int get_arg(unsigned long offset)
1061{
1062 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1063}
1064
1065static int get_index(unsigned long offset)
1066{
1067 return get_arg(offset);
1068}
1069
1070static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1071{
1072 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1073 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1074 struct mlx5_uuar_info *uuari = &context->uuari;
1075 unsigned long command;
1076 unsigned long idx;
1077 phys_addr_t pfn;
1078
1079 command = get_command(vma->vm_pgoff);
1080 switch (command) {
1081 case MLX5_IB_MMAP_REGULAR_PAGE:
1082 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1083 return -EINVAL;
1084
1085 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 1086 if (idx >= uuari->num_uars)
1087 return -EINVAL;
1088
e126ba97
EC		 1089 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1090 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1091 (unsigned long long)pfn);
1092
e126ba97
EC		 1093 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1094 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1095 PAGE_SIZE, vma->vm_page_prot))
1096 return -EAGAIN;
1097
1098 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1099 vma->vm_start,
1100 (unsigned long long)pfn << PAGE_SHIFT);
1101 break;
1102
1103 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1104 return -ENOSYS;
1105
d69e3bcf 1106 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1107 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1108 return -EINVAL;
1109
1110 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1111 return -EPERM;
1112
1113 /* Don't expose to user-space information it shouldn't have */
1114 if (PAGE_SIZE > 4096)
1115 return -EOPNOTSUPP;
1116
1117 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1118 pfn = (dev->mdev->iseg_base +
1119 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1120 PAGE_SHIFT;
1121 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1122 PAGE_SIZE, vma->vm_page_prot))
1123 return -EAGAIN;
1124
1125 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1126 vma->vm_start,
1127 (unsigned long long)pfn << PAGE_SHIFT);
1128 break;
d69e3bcf 1129
e126ba97
EC		 1130 default:
1131 return -EINVAL;
1132 }
1133
1134 return 0;
1135}
1136
e126ba97
EC		 1137static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1138 struct ib_ucontext *context,
1139 struct ib_udata *udata)
1140{
1141 struct mlx5_ib_alloc_pd_resp resp;
1142 struct mlx5_ib_pd *pd;
1143 int err;
1144
1145 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1146 if (!pd)
1147 return ERR_PTR(-ENOMEM);
1148
9603b61d 1149 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1150 if (err) {
1151 kfree(pd);
1152 return ERR_PTR(err);
1153 }
1154
1155 if (context) {
1156 resp.pdn = pd->pdn;
1157 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1158 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1159 kfree(pd);
1160 return ERR_PTR(-EFAULT);
1161 }
e126ba97
EC		 1162 }
1163
1164 return &pd->ibpd;
1165}
1166
1167static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1168{
1169 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1170 struct mlx5_ib_pd *mpd = to_mpd(pd);
1171
9603b61d 1172 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1173 kfree(mpd);
1174
1175 return 0;
1176}
1177
038d2ef8
MG		 1178static bool outer_header_zero(u32 *match_criteria)
1179{
1180 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1181 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1182 outer_headers);
1183
1184 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1185 outer_headers_c + 1,
1186 size - 1);
1187}
1188
1189static int parse_flow_attr(u32 *match_c, u32 *match_v,
1190 union ib_flow_spec *ib_spec)
1191{
1192 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1193 outer_headers);
1194 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1195 outer_headers);
1196 switch (ib_spec->type) {
1197 case IB_FLOW_SPEC_ETH:
1198 if (ib_spec->size != sizeof(ib_spec->eth))
1199 return -EINVAL;
1200
1201 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1202 dmac_47_16),
1203 ib_spec->eth.mask.dst_mac);
1204 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1205 dmac_47_16),
1206 ib_spec->eth.val.dst_mac);
1207
1208 if (ib_spec->eth.mask.vlan_tag) {
1209 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1210 vlan_tag, 1);
1211 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1212 vlan_tag, 1);
1213
1214 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1215 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1216 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1217 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1218
1219 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1220 first_cfi,
1221 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1222 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1223 first_cfi,
1224 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1225
1226 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1227 first_prio,
1228 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1229 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1230 first_prio,
1231 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1232 }
1233 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1234 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1235 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1236 ethertype, ntohs(ib_spec->eth.val.ether_type));
1237 break;
1238 case IB_FLOW_SPEC_IPV4:
1239 if (ib_spec->size != sizeof(ib_spec->ipv4))
1240 return -EINVAL;
1241
1242 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1243 ethertype, 0xffff);
1244 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1245 ethertype, ETH_P_IP);
1246
1247 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1248 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1249 &ib_spec->ipv4.mask.src_ip,
1250 sizeof(ib_spec->ipv4.mask.src_ip));
1251 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1252 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1253 &ib_spec->ipv4.val.src_ip,
1254 sizeof(ib_spec->ipv4.val.src_ip));
1255 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1256 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1257 &ib_spec->ipv4.mask.dst_ip,
1258 sizeof(ib_spec->ipv4.mask.dst_ip));
1259 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1260 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1261 &ib_spec->ipv4.val.dst_ip,
1262 sizeof(ib_spec->ipv4.val.dst_ip));
1263 break;
1264 case IB_FLOW_SPEC_TCP:
1265 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1266 return -EINVAL;
1267
1268 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1269 0xff);
1270 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1271 IPPROTO_TCP);
1272
1273 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1274 ntohs(ib_spec->tcp_udp.mask.src_port));
1275 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1276 ntohs(ib_spec->tcp_udp.val.src_port));
1277
1278 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1279 ntohs(ib_spec->tcp_udp.mask.dst_port));
1280 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1281 ntohs(ib_spec->tcp_udp.val.dst_port));
1282 break;
1283 case IB_FLOW_SPEC_UDP:
1284 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1285 return -EINVAL;
1286
1287 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1288 0xff);
1289 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1290 IPPROTO_UDP);
1291
1292 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1293 ntohs(ib_spec->tcp_udp.mask.src_port));
1294 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1295 ntohs(ib_spec->tcp_udp.val.src_port));
1296
1297 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1298 ntohs(ib_spec->tcp_udp.mask.dst_port));
1299 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1300 ntohs(ib_spec->tcp_udp.val.dst_port));
1301 break;
1302 default:
1303 return -EINVAL;
1304 }
1305
1306 return 0;
1307}
1308
1309/* If a flow could catch both multicast and unicast packets,
1310 * it won't fall into the multicast flow steering table and this rule
1311 * could steal other multicast packets.
1312 */
1313static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1314{
1315 struct ib_flow_spec_eth *eth_spec;
1316
1317 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1318 ib_attr->size < sizeof(struct ib_flow_attr) +
1319 sizeof(struct ib_flow_spec_eth) ||
1320 ib_attr->num_of_specs < 1)
1321 return false;
1322
1323 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1324 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1325 eth_spec->size != sizeof(*eth_spec))
1326 return false;
1327
1328 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1329 is_multicast_ether_addr(eth_spec->val.dst_mac);
1330}
1331
1332static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1333{
1334 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1335 bool has_ipv4_spec = false;
1336 bool eth_type_ipv4 = true;
1337 unsigned int spec_index;
1338
1339 /* Validate that ethertype is correct */
1340 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1341 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1342 ib_spec->eth.mask.ether_type) {
1343 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1344 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1345 eth_type_ipv4 = false;
1346 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1347 has_ipv4_spec = true;
1348 }
1349 ib_spec = (void *)ib_spec + ib_spec->size;
1350 }
1351 return !has_ipv4_spec || eth_type_ipv4;
1352}
1353
1354static void put_flow_table(struct mlx5_ib_dev *dev,
1355 struct mlx5_ib_flow_prio *prio, bool ft_added)
1356{
1357 prio->refcount -= !!ft_added;
1358 if (!prio->refcount) {
1359 mlx5_destroy_flow_table(prio->flow_table);
1360 prio->flow_table = NULL;
1361 }
1362}
1363
1364static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1365{
1366 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1367 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1368 struct mlx5_ib_flow_handler,
1369 ibflow);
1370 struct mlx5_ib_flow_handler *iter, *tmp;
1371
1372 mutex_lock(&dev->flow_db.lock);
1373
1374 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1375 mlx5_del_flow_rule(iter->rule);
1376 list_del(&iter->list);
1377 kfree(iter);
1378 }
1379
1380 mlx5_del_flow_rule(handler->rule);
1381 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1382 mutex_unlock(&dev->flow_db.lock);
1383
1384 kfree(handler);
1385
1386 return 0;
1387}
1388
35d19011
MG		 1389static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1390{
1391 priority *= 2;
1392 if (!dont_trap)
1393 priority++;
1394 return priority;
1395}
1396
038d2ef8
MG		 1397#define MLX5_FS_MAX_TYPES 10
1398#define MLX5_FS_MAX_ENTRIES 32000UL
1399static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1400 struct ib_flow_attr *flow_attr)
1401{
35d19011 1402 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1403 struct mlx5_flow_namespace *ns = NULL;
1404 struct mlx5_ib_flow_prio *prio;
1405 struct mlx5_flow_table *ft;
1406 int num_entries;
1407 int num_groups;
1408 int priority;
1409 int err = 0;
1410
1411 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1412 if (flow_is_multicast_only(flow_attr) &&
1413 !dont_trap)
038d2ef8
MG		 1414 priority = MLX5_IB_FLOW_MCAST_PRIO;
1415 else
35d19011
MG		 1416 priority = ib_prio_to_core_prio(flow_attr->priority,
1417 dont_trap);
038d2ef8
MG		 1418 ns = mlx5_get_flow_namespace(dev->mdev,
1419 MLX5_FLOW_NAMESPACE_BYPASS);
1420 num_entries = MLX5_FS_MAX_ENTRIES;
1421 num_groups = MLX5_FS_MAX_TYPES;
1422 prio = &dev->flow_db.prios[priority];
1423 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1424 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1425 ns = mlx5_get_flow_namespace(dev->mdev,
1426 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1427 build_leftovers_ft_param(&priority,
1428 &num_entries,
1429 &num_groups);
1430 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1431 }
1432
1433 if (!ns)
1434 return ERR_PTR(-ENOTSUPP);
1435
1436 ft = prio->flow_table;
1437 if (!ft) {
1438 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1439 num_entries,
1440 num_groups);
1441
1442 if (!IS_ERR(ft)) {
1443 prio->refcount = 0;
1444 prio->flow_table = ft;
1445 } else {
1446 err = PTR_ERR(ft);
1447 }
1448 }
1449
1450 return err ? ERR_PTR(err) : prio;
1451}
1452
1453static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1454 struct mlx5_ib_flow_prio *ft_prio,
1455 struct ib_flow_attr *flow_attr,
1456 struct mlx5_flow_destination *dst)
1457{
1458 struct mlx5_flow_table *ft = ft_prio->flow_table;
1459 struct mlx5_ib_flow_handler *handler;
1460 void *ib_flow = flow_attr + 1;
1461 u8 match_criteria_enable = 0;
1462 unsigned int spec_index;
1463 u32 *match_c;
1464 u32 *match_v;
35d19011 1465 u32 action;
038d2ef8
MG		 1466 int err = 0;
1467
1468 if (!is_valid_attr(flow_attr))
1469 return ERR_PTR(-EINVAL);
1470
1471 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1472 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1473 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1474 if (!handler || !match_c || !match_v) {
1475 err = -ENOMEM;
1476 goto free;
1477 }
1478
1479 INIT_LIST_HEAD(&handler->list);
1480
1481 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1482 err = parse_flow_attr(match_c, match_v, ib_flow);
1483 if (err < 0)
1484 goto free;
1485
1486 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1487 }
1488
1489 /* Outer header support only */
1490 match_criteria_enable = (!outer_header_zero(match_c)) << 0;
35d19011
MG		 1491 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1492 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
038d2ef8
MG		 1493 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1494 match_c, match_v,
35d19011 1495 action,
038d2ef8
MG		 1496 MLX5_FS_DEFAULT_FLOW_TAG,
1497 dst);
1498
1499 if (IS_ERR(handler->rule)) {
1500 err = PTR_ERR(handler->rule);
1501 goto free;
1502 }
1503
1504 handler->prio = ft_prio - dev->flow_db.prios;
1505
1506 ft_prio->flow_table = ft;
1507free:
1508 if (err)
1509 kfree(handler);
1510 kfree(match_c);
1511 kfree(match_v);
1512 return err ? ERR_PTR(err) : handler;
1513}
1514
35d19011
MG		 1515static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1516 struct mlx5_ib_flow_prio *ft_prio,
1517 struct ib_flow_attr *flow_attr,
1518 struct mlx5_flow_destination *dst)
1519{
1520 struct mlx5_ib_flow_handler *handler_dst = NULL;
1521 struct mlx5_ib_flow_handler *handler = NULL;
1522
1523 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1524 if (!IS_ERR(handler)) {
1525 handler_dst = create_flow_rule(dev, ft_prio,
1526 flow_attr, dst);
1527 if (IS_ERR(handler_dst)) {
1528 mlx5_del_flow_rule(handler->rule);
1529 kfree(handler);
1530 handler = handler_dst;
1531 } else {
1532 list_add(&handler_dst->list, &handler->list);
1533 }
1534 }
1535
1536 return handler;
1537}
038d2ef8
MG		 1538enum {
1539 LEFTOVERS_MC,
1540 LEFTOVERS_UC,
1541};
1542
1543static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1544 struct mlx5_ib_flow_prio *ft_prio,
1545 struct ib_flow_attr *flow_attr,
1546 struct mlx5_flow_destination *dst)
1547{
1548 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1549 struct mlx5_ib_flow_handler *handler = NULL;
1550
1551 static struct {
1552 struct ib_flow_attr flow_attr;
1553 struct ib_flow_spec_eth eth_flow;
1554 } leftovers_specs[] = {
1555 [LEFTOVERS_MC] = {
1556 .flow_attr = {
1557 .num_of_specs = 1,
1558 .size = sizeof(leftovers_specs[0])
1559 },
1560 .eth_flow = {
1561 .type = IB_FLOW_SPEC_ETH,
1562 .size = sizeof(struct ib_flow_spec_eth),
1563 .mask = {.dst_mac = {0x1} },
1564 .val = {.dst_mac = {0x1} }
1565 }
1566 },
1567 [LEFTOVERS_UC] = {
1568 .flow_attr = {
1569 .num_of_specs = 1,
1570 .size = sizeof(leftovers_specs[0])
1571 },
1572 .eth_flow = {
1573 .type = IB_FLOW_SPEC_ETH,
1574 .size = sizeof(struct ib_flow_spec_eth),
1575 .mask = {.dst_mac = {0x1} },
1576 .val = {.dst_mac = {} }
1577 }
1578 }
1579 };
1580
1581 handler = create_flow_rule(dev, ft_prio,
1582 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1583 dst);
1584 if (!IS_ERR(handler) &&
1585 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1586 handler_ucast = create_flow_rule(dev, ft_prio,
1587 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1588 dst);
1589 if (IS_ERR(handler_ucast)) {
1590 kfree(handler);
1591 handler = handler_ucast;
1592 } else {
1593 list_add(&handler_ucast->list, &handler->list);
1594 }
1595 }
1596
1597 return handler;
1598}
1599
1600static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1601 struct ib_flow_attr *flow_attr,
1602 int domain)
1603{
1604 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1605 struct mlx5_ib_flow_handler *handler = NULL;
1606 struct mlx5_flow_destination *dst = NULL;
1607 struct mlx5_ib_flow_prio *ft_prio;
1608 int err;
1609
1610 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1611 return ERR_PTR(-ENOSPC);
1612
1613 if (domain != IB_FLOW_DOMAIN_USER ||
1614 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 1615 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 1616 return ERR_PTR(-EINVAL);
1617
1618 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1619 if (!dst)
1620 return ERR_PTR(-ENOMEM);
1621
1622 mutex_lock(&dev->flow_db.lock);
1623
1624 ft_prio = get_flow_table(dev, flow_attr);
1625 if (IS_ERR(ft_prio)) {
1626 err = PTR_ERR(ft_prio);
1627 goto unlock;
1628 }
1629
1630 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1631 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1632
1633 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1634 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1635 handler = create_dont_trap_rule(dev, ft_prio,
1636 flow_attr, dst);
1637 } else {
1638 handler = create_flow_rule(dev, ft_prio, flow_attr,
1639 dst);
1640 }
038d2ef8
MG		 1641 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1642 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1643 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1644 dst);
1645 } else {
1646 err = -EINVAL;
1647 goto destroy_ft;
1648 }
1649
1650 if (IS_ERR(handler)) {
1651 err = PTR_ERR(handler);
1652 handler = NULL;
1653 goto destroy_ft;
1654 }
1655
1656 ft_prio->refcount++;
1657 mutex_unlock(&dev->flow_db.lock);
1658 kfree(dst);
1659
1660 return &handler->ibflow;
1661
1662destroy_ft:
1663 put_flow_table(dev, ft_prio, false);
1664unlock:
1665 mutex_unlock(&dev->flow_db.lock);
1666 kfree(dst);
1667 kfree(handler);
1668 return ERR_PTR(err);
1669}
1670
e126ba97
EC		 1671static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1672{
1673 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1674 int err;
1675
9603b61d 1676 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1677 if (err)
1678 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1679 ibqp->qp_num, gid->raw);
1680
1681 return err;
1682}
1683
1684static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1685{
1686 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1687 int err;
1688
9603b61d 1689 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1690 if (err)
1691 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1692 ibqp->qp_num, gid->raw);
1693
1694 return err;
1695}
1696
1697static int init_node_data(struct mlx5_ib_dev *dev)
1698{
1b5daf11 1699 int err;
e126ba97 1700
1b5daf11 1701 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1702 if (err)
1b5daf11 1703 return err;
e126ba97 1704
1b5daf11 1705 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1706
1b5daf11 1707 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1708}
1709
1710static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1711 char *buf)
1712{
1713 struct mlx5_ib_dev *dev =
1714 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1715
9603b61d 1716 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1717}
1718
1719static ssize_t show_reg_pages(struct device *device,
1720 struct device_attribute *attr, char *buf)
1721{
1722 struct mlx5_ib_dev *dev =
1723 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1724
6aec21f6 1725 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1726}
1727
1728static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1729 char *buf)
1730{
1731 struct mlx5_ib_dev *dev =
1732 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1733 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1734}
1735
1736static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1737 char *buf)
1738{
1739 struct mlx5_ib_dev *dev =
1740 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1741 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1742 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1743}
1744
1745static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1746 char *buf)
1747{
1748 struct mlx5_ib_dev *dev =
1749 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1750 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1751}
1752
1753static ssize_t show_board(struct device *device, struct device_attribute *attr,
1754 char *buf)
1755{
1756 struct mlx5_ib_dev *dev =
1757 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1758 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1759 dev->mdev->board_id);
e126ba97
EC		 1760}
1761
1762static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1763static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1764static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1765static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1766static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1767static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1768
1769static struct device_attribute *mlx5_class_attributes[] = {
1770 &dev_attr_hw_rev,
1771 &dev_attr_fw_ver,
1772 &dev_attr_hca_type,
1773 &dev_attr_board_id,
1774 &dev_attr_fw_pages,
1775 &dev_attr_reg_pages,
1776};
1777
7722f47e
HE		 1778static void pkey_change_handler(struct work_struct *work)
1779{
1780 struct mlx5_ib_port_resources *ports =
1781 container_of(work, struct mlx5_ib_port_resources,
1782 pkey_change_work);
1783
1784 mutex_lock(&ports->devr->mutex);
1785 mlx5_ib_gsi_pkey_change(ports->gsi);
1786 mutex_unlock(&ports->devr->mutex);
1787}
1788
9603b61d 1789static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1790 enum mlx5_dev_event event, unsigned long param)
e126ba97 1791{
9603b61d 1792 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1793 struct ib_event ibev;
9603b61d 1794
e126ba97
EC		 1795 u8 port = 0;
1796
1797 switch (event) {
1798 case MLX5_DEV_EVENT_SYS_ERROR:
1799 ibdev->ib_active = false;
1800 ibev.event = IB_EVENT_DEVICE_FATAL;
1801 break;
1802
1803 case MLX5_DEV_EVENT_PORT_UP:
1804 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1805 port = (u8)param;
e126ba97
EC		 1806 break;
1807
1808 case MLX5_DEV_EVENT_PORT_DOWN:
1809 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1810 port = (u8)param;
e126ba97
EC		 1811 break;
1812
1813 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1814 /* not used by ULPs */
1815 return;
1816
1817 case MLX5_DEV_EVENT_LID_CHANGE:
1818 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1819 port = (u8)param;
e126ba97
EC		 1820 break;
1821
1822 case MLX5_DEV_EVENT_PKEY_CHANGE:
1823 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1824 port = (u8)param;
7722f47e
HE		 1825
1826 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 1827 break;
1828
1829 case MLX5_DEV_EVENT_GUID_CHANGE:
1830 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1831 port = (u8)param;
e126ba97
EC		 1832 break;
1833
1834 case MLX5_DEV_EVENT_CLIENT_REREG:
1835 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1836 port = (u8)param;
e126ba97
EC		 1837 break;
1838 }
1839
1840 ibev.device = &ibdev->ib_dev;
1841 ibev.element.port_num = port;
1842
a0c84c32
EC		 1843 if (port < 1 || port > ibdev->num_ports) {
1844 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1845 return;
1846 }
1847
e126ba97
EC		 1848 if (ibdev->ib_active)
1849 ib_dispatch_event(&ibev);
1850}
1851
1852static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1853{
1854 int port;
1855
938fe83c 1856 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1857 mlx5_query_ext_port_caps(dev, port);
1858}
1859
1860static int get_port_caps(struct mlx5_ib_dev *dev)
1861{
1862 struct ib_device_attr *dprops = NULL;
1863 struct ib_port_attr *pprops = NULL;
f614fc15 1864 int err = -ENOMEM;
e126ba97 1865 int port;
2528e33e 1866 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1867
1868 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1869 if (!pprops)
1870 goto out;
1871
1872 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1873 if (!dprops)
1874 goto out;
1875
2528e33e 1876 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1877 if (err) {
1878 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1879 goto out;
1880 }
1881
938fe83c 1882 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1883 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1884 if (err) {
938fe83c
SM		 1885 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1886 port, err);
e126ba97
EC		 1887 break;
1888 }
938fe83c
SM		 1889 dev->mdev->port_caps[port - 1].pkey_table_len =
1890 dprops->max_pkeys;
1891 dev->mdev->port_caps[port - 1].gid_table_len =
1892 pprops->gid_tbl_len;
e126ba97
EC		 1893 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1894 dprops->max_pkeys, pprops->gid_tbl_len);
1895 }
1896
1897out:
1898 kfree(pprops);
1899 kfree(dprops);
1900
1901 return err;
1902}
1903
1904static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1905{
1906 int err;
1907
1908 err = mlx5_mr_cache_cleanup(dev);
1909 if (err)
1910 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1911
1912 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 1913 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 1914 ib_dealloc_pd(dev->umrc.pd);
1915}
1916
1917enum {
1918 MAX_UMR_WR = 128,
1919};
1920
1921static int create_umr_res(struct mlx5_ib_dev *dev)
1922{
1923 struct ib_qp_init_attr *init_attr = NULL;
1924 struct ib_qp_attr *attr = NULL;
1925 struct ib_pd *pd;
1926 struct ib_cq *cq;
1927 struct ib_qp *qp;
e126ba97
EC		 1928 int ret;
1929
1930 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1931 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1932 if (!attr || !init_attr) {
1933 ret = -ENOMEM;
1934 goto error_0;
1935 }
1936
1937 pd = ib_alloc_pd(&dev->ib_dev);
1938 if (IS_ERR(pd)) {
1939 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1940 ret = PTR_ERR(pd);
1941 goto error_0;
1942 }
1943
add08d76 1944 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 1945 if (IS_ERR(cq)) {
1946 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1947 ret = PTR_ERR(cq);
1948 goto error_2;
1949 }
e126ba97
EC		 1950
1951 init_attr->send_cq = cq;
1952 init_attr->recv_cq = cq;
1953 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1954 init_attr->cap.max_send_wr = MAX_UMR_WR;
1955 init_attr->cap.max_send_sge = 1;
1956 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1957 init_attr->port_num = 1;
1958 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1959 if (IS_ERR(qp)) {
1960 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1961 ret = PTR_ERR(qp);
1962 goto error_3;
1963 }
1964 qp->device = &dev->ib_dev;
1965 qp->real_qp = qp;
1966 qp->uobject = NULL;
1967 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1968
1969 attr->qp_state = IB_QPS_INIT;
1970 attr->port_num = 1;
1971 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1972 IB_QP_PORT, NULL);
1973 if (ret) {
1974 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1975 goto error_4;
1976 }
1977
1978 memset(attr, 0, sizeof(*attr));
1979 attr->qp_state = IB_QPS_RTR;
1980 attr->path_mtu = IB_MTU_256;
1981
1982 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1983 if (ret) {
1984 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1985 goto error_4;
1986 }
1987
1988 memset(attr, 0, sizeof(*attr));
1989 attr->qp_state = IB_QPS_RTS;
1990 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1991 if (ret) {
1992 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1993 goto error_4;
1994 }
1995
1996 dev->umrc.qp = qp;
1997 dev->umrc.cq = cq;
e126ba97
EC		 1998 dev->umrc.pd = pd;
1999
2000 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2001 ret = mlx5_mr_cache_init(dev);
2002 if (ret) {
2003 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2004 goto error_4;
2005 }
2006
2007 kfree(attr);
2008 kfree(init_attr);
2009
2010 return 0;
2011
2012error_4:
2013 mlx5_ib_destroy_qp(qp);
2014
2015error_3:
add08d76 2016 ib_free_cq(cq);
e126ba97
EC		 2017
2018error_2:
e126ba97
EC		 2019 ib_dealloc_pd(pd);
2020
2021error_0:
2022 kfree(attr);
2023 kfree(init_attr);
2024 return ret;
2025}
2026
2027static int create_dev_resources(struct mlx5_ib_resources *devr)
2028{
2029 struct ib_srq_init_attr attr;
2030 struct mlx5_ib_dev *dev;
bcf4c1ea 2031 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2032 int port;
e126ba97
EC		 2033 int ret = 0;
2034
2035 dev = container_of(devr, struct mlx5_ib_dev, devr);
2036
d16e91da
HE		 2037 mutex_init(&devr->mutex);
2038
e126ba97
EC		 2039 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2040 if (IS_ERR(devr->p0)) {
2041 ret = PTR_ERR(devr->p0);
2042 goto error0;
2043 }
2044 devr->p0->device = &dev->ib_dev;
2045 devr->p0->uobject = NULL;
2046 atomic_set(&devr->p0->usecnt, 0);
2047
bcf4c1ea 2048 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2049 if (IS_ERR(devr->c0)) {
2050 ret = PTR_ERR(devr->c0);
2051 goto error1;
2052 }
2053 devr->c0->device = &dev->ib_dev;
2054 devr->c0->uobject = NULL;
2055 devr->c0->comp_handler = NULL;
2056 devr->c0->event_handler = NULL;
2057 devr->c0->cq_context = NULL;
2058 atomic_set(&devr->c0->usecnt, 0);
2059
2060 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2061 if (IS_ERR(devr->x0)) {
2062 ret = PTR_ERR(devr->x0);
2063 goto error2;
2064 }
2065 devr->x0->device = &dev->ib_dev;
2066 devr->x0->inode = NULL;
2067 atomic_set(&devr->x0->usecnt, 0);
2068 mutex_init(&devr->x0->tgt_qp_mutex);
2069 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2070
2071 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2072 if (IS_ERR(devr->x1)) {
2073 ret = PTR_ERR(devr->x1);
2074 goto error3;
2075 }
2076 devr->x1->device = &dev->ib_dev;
2077 devr->x1->inode = NULL;
2078 atomic_set(&devr->x1->usecnt, 0);
2079 mutex_init(&devr->x1->tgt_qp_mutex);
2080 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2081
2082 memset(&attr, 0, sizeof(attr));
2083 attr.attr.max_sge = 1;
2084 attr.attr.max_wr = 1;
2085 attr.srq_type = IB_SRQT_XRC;
2086 attr.ext.xrc.cq = devr->c0;
2087 attr.ext.xrc.xrcd = devr->x0;
2088
2089 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2090 if (IS_ERR(devr->s0)) {
2091 ret = PTR_ERR(devr->s0);
2092 goto error4;
2093 }
2094 devr->s0->device = &dev->ib_dev;
2095 devr->s0->pd = devr->p0;
2096 devr->s0->uobject = NULL;
2097 devr->s0->event_handler = NULL;
2098 devr->s0->srq_context = NULL;
2099 devr->s0->srq_type = IB_SRQT_XRC;
2100 devr->s0->ext.xrc.xrcd = devr->x0;
2101 devr->s0->ext.xrc.cq = devr->c0;
2102 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2103 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2104 atomic_inc(&devr->p0->usecnt);
2105 atomic_set(&devr->s0->usecnt, 0);
2106
4aa17b28
HA		 2107 memset(&attr, 0, sizeof(attr));
2108 attr.attr.max_sge = 1;
2109 attr.attr.max_wr = 1;
2110 attr.srq_type = IB_SRQT_BASIC;
2111 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2112 if (IS_ERR(devr->s1)) {
2113 ret = PTR_ERR(devr->s1);
2114 goto error5;
2115 }
2116 devr->s1->device = &dev->ib_dev;
2117 devr->s1->pd = devr->p0;
2118 devr->s1->uobject = NULL;
2119 devr->s1->event_handler = NULL;
2120 devr->s1->srq_context = NULL;
2121 devr->s1->srq_type = IB_SRQT_BASIC;
2122 devr->s1->ext.xrc.cq = devr->c0;
2123 atomic_inc(&devr->p0->usecnt);
2124 atomic_set(&devr->s0->usecnt, 0);
2125
7722f47e
HE		 2126 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2127 INIT_WORK(&devr->ports[port].pkey_change_work,
2128 pkey_change_handler);
2129 devr->ports[port].devr = devr;
2130 }
2131
e126ba97
EC		 2132 return 0;
2133
4aa17b28
HA		 2134error5:
2135 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2136error4:
2137 mlx5_ib_dealloc_xrcd(devr->x1);
2138error3:
2139 mlx5_ib_dealloc_xrcd(devr->x0);
2140error2:
2141 mlx5_ib_destroy_cq(devr->c0);
2142error1:
2143 mlx5_ib_dealloc_pd(devr->p0);
2144error0:
2145 return ret;
2146}
2147
2148static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2149{
7722f47e
HE		 2150 struct mlx5_ib_dev *dev =
2151 container_of(devr, struct mlx5_ib_dev, devr);
2152 int port;
2153
4aa17b28 2154 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2155 mlx5_ib_destroy_srq(devr->s0);
2156 mlx5_ib_dealloc_xrcd(devr->x0);
2157 mlx5_ib_dealloc_xrcd(devr->x1);
2158 mlx5_ib_destroy_cq(devr->c0);
2159 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2160
2161 /* Make sure no change P_Key work items are still executing */
2162 for (port = 0; port < dev->num_ports; ++port)
2163 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2164}
2165
e53505a8
AS		 2166static u32 get_core_cap_flags(struct ib_device *ibdev)
2167{
2168 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2169 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2170 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2171 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2172 u32 ret = 0;
2173
2174 if (ll == IB_LINK_LAYER_INFINIBAND)
2175 return RDMA_CORE_PORT_IBA_IB;
2176
2177 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2178 return 0;
2179
2180 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2181 return 0;
2182
2183 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2184 ret |= RDMA_CORE_PORT_IBA_ROCE;
2185
2186 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2187 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2188
2189 return ret;
2190}
2191
7738613e
IW		 2192static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2193 struct ib_port_immutable *immutable)
2194{
2195 struct ib_port_attr attr;
2196 int err;
2197
2198 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2199 if (err)
2200 return err;
2201
2202 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2203 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2204 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2205 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2206
2207 return 0;
2208}
2209
fc24fc5e
AS		 2210static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2211{
e53505a8
AS		 2212 int err;
2213
fc24fc5e 2214 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2215 err = register_netdevice_notifier(&dev->roce.nb);
2216 if (err)
2217 return err;
2218
2219 err = mlx5_nic_vport_enable_roce(dev->mdev);
2220 if (err)
2221 goto err_unregister_netdevice_notifier;
2222
2223 return 0;
2224
2225err_unregister_netdevice_notifier:
2226 unregister_netdevice_notifier(&dev->roce.nb);
2227 return err;
fc24fc5e
AS		 2228}
2229
2230static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2231{
e53505a8 2232 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2233 unregister_netdevice_notifier(&dev->roce.nb);
2234}
2235
9603b61d 2236static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2237{
e126ba97 2238 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2239 enum rdma_link_layer ll;
2240 int port_type_cap;
e126ba97
EC		 2241 int err;
2242 int i;
2243
ebd61f68
AS		 2244 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2245 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2246
e53505a8 2247 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2248 return NULL;
2249
e126ba97
EC		 2250 printk_once(KERN_INFO "%s", mlx5_version);
2251
2252 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2253 if (!dev)
9603b61d 2254 return NULL;
e126ba97 2255
9603b61d 2256 dev->mdev = mdev;
e126ba97 2257
fc24fc5e 2258 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2259 err = get_port_caps(dev);
2260 if (err)
9603b61d 2261 goto err_dealloc;
e126ba97 2262
1b5daf11
MD		 2263 if (mlx5_use_mad_ifc(dev))
2264 get_ext_port_caps(dev);
e126ba97 2265
e126ba97
EC		 2266 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2267
2268 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2269 dev->ib_dev.owner = THIS_MODULE;
2270 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2271 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2272 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2273 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2274 dev->ib_dev.num_comp_vectors =
2275 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2276 dev->ib_dev.dma_device = &mdev->pdev->dev;
2277
2278 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2279 dev->ib_dev.uverbs_cmd_mask =
2280 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2281 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2282 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2283 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2284 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2285 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2286 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2287 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2288 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2289 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2290 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2291 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2292 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2293 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2294 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2295 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2296 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2297 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2298 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2299 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2300 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2301 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2302 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2303 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2304 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2305 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2306 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2307 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2308
2309 dev->ib_dev.query_device = mlx5_ib_query_device;
2310 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2311 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2312 if (ll == IB_LINK_LAYER_ETHERNET)
2313 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2314 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2315 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2316 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2317 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2318 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2319 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2320 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2321 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2322 dev->ib_dev.mmap = mlx5_ib_mmap;
2323 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2324 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2325 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2326 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2327 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2328 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2329 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2330 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2331 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2332 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2333 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2334 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2335 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2336 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2337 dev->ib_dev.post_send = mlx5_ib_post_send;
2338 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2339 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2340 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2341 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2342 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2343 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2344 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2345 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2346 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2347 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2348 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2349 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2350 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2351 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2352 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2353 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2354 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2355 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
eff901d3
EC		 2356 if (mlx5_core_is_pf(mdev)) {
2357 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2358 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2359 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2360 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2361 }
e126ba97 2362
938fe83c 2363 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2364
d2370e0a
MB		 2365 if (MLX5_CAP_GEN(mdev, imaicl)) {
2366 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2367 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2368 dev->ib_dev.uverbs_cmd_mask |=
2369 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2370 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2371 }
2372
938fe83c 2373 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2374 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2375 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2376 dev->ib_dev.uverbs_cmd_mask |=
2377 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2378 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2379 }
2380
048ccca8 2381 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2382 IB_LINK_LAYER_ETHERNET) {
2383 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2384 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2385 dev->ib_dev.uverbs_ex_cmd_mask |=
2386 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2387 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2388 }
e126ba97
EC		 2389 err = init_node_data(dev);
2390 if (err)
233d05d2 2391 goto err_dealloc;
e126ba97 2392
038d2ef8 2393 mutex_init(&dev->flow_db.lock);
e126ba97 2394 mutex_init(&dev->cap_mask_mutex);
e126ba97 2395
fc24fc5e
AS		 2396 if (ll == IB_LINK_LAYER_ETHERNET) {
2397 err = mlx5_enable_roce(dev);
2398 if (err)
2399 goto err_dealloc;
2400 }
2401
e126ba97
EC		 2402 err = create_dev_resources(&dev->devr);
2403 if (err)
fc24fc5e 2404 goto err_disable_roce;
e126ba97 2405
6aec21f6 2406 err = mlx5_ib_odp_init_one(dev);
281d1a92 2407 if (err)
e126ba97
EC		 2408 goto err_rsrc;
2409
6aec21f6
HE		 2410 err = ib_register_device(&dev->ib_dev, NULL);
2411 if (err)
2412 goto err_odp;
2413
e126ba97
EC		 2414 err = create_umr_res(dev);
2415 if (err)
2416 goto err_dev;
2417
2418 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2419 err = device_create_file(&dev->ib_dev.dev,
2420 mlx5_class_attributes[i]);
2421 if (err)
e126ba97
EC		 2422 goto err_umrc;
2423 }
2424
2425 dev->ib_active = true;
2426
9603b61d 2427 return dev;
e126ba97
EC		 2428
2429err_umrc:
2430 destroy_umrc_res(dev);
2431
2432err_dev:
2433 ib_unregister_device(&dev->ib_dev);
2434
6aec21f6
HE		 2435err_odp:
2436 mlx5_ib_odp_remove_one(dev);
2437
e126ba97
EC		 2438err_rsrc:
2439 destroy_dev_resources(&dev->devr);
2440
fc24fc5e
AS		 2441err_disable_roce:
2442 if (ll == IB_LINK_LAYER_ETHERNET)
2443 mlx5_disable_roce(dev);
2444
9603b61d 2445err_dealloc:
e126ba97
EC		 2446 ib_dealloc_device((struct ib_device *)dev);
2447
9603b61d 2448 return NULL;
e126ba97
EC		 2449}
2450
9603b61d 2451static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 2452{
9603b61d 2453 struct mlx5_ib_dev *dev = context;
fc24fc5e 2454 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 2455
e126ba97 2456 ib_unregister_device(&dev->ib_dev);
eefd56e5 2457 destroy_umrc_res(dev);
6aec21f6 2458 mlx5_ib_odp_remove_one(dev);
e126ba97 2459 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 2460 if (ll == IB_LINK_LAYER_ETHERNET)
2461 mlx5_disable_roce(dev);
e126ba97
EC		 2462 ib_dealloc_device(&dev->ib_dev);
2463}
2464
9603b61d
JM		 2465static struct mlx5_interface mlx5_ib_interface = {
2466 .add = mlx5_ib_add,
2467 .remove = mlx5_ib_remove,
2468 .event = mlx5_ib_event,
64613d94 2469 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 2470};
2471
2472static int __init mlx5_ib_init(void)
2473{
6aec21f6
HE		 2474 int err;
2475
9603b61d
JM		 2476 if (deprecated_prof_sel != 2)
2477 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2478
6aec21f6
HE		 2479 err = mlx5_ib_odp_init();
2480 if (err)
2481 return err;
2482
2483 err = mlx5_register_interface(&mlx5_ib_interface);
2484 if (err)
2485 goto clean_odp;
2486
2487 return err;
2488
2489clean_odp:
2490 mlx5_ib_odp_cleanup();
2491 return err;
e126ba97
EC		 2492}
2493
2494static void __exit mlx5_ib_cleanup(void)
2495{
9603b61d 2496 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 2497 mlx5_ib_odp_cleanup();
e126ba97
EC		 2498}
2499
2500module_init(mlx5_ib_init);
2501module_exit(mlx5_ib_cleanup);
Linux kernel - Deliverables
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