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IB/mlx5: Support the new memory registration API
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
35#include "mlx5_ib.h"
36#include "user.h"
37
38/* not supported currently */
39static int wq_signature;
40
41enum {
42 MLX5_IB_ACK_REQ_FREQ = 8,
43};
44
45enum {
46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
48 MLX5_IB_LINK_TYPE_IB = 0,
49 MLX5_IB_LINK_TYPE_ETH = 1
50};
51
52enum {
53 MLX5_IB_SQ_STRIDE = 6,
54 MLX5_IB_CACHE_LINE_SIZE = 64,
55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR,
8a187ee5 68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
72};
73
e126ba97
EC		 74
75static int is_qp0(enum ib_qp_type qp_type)
76{
77 return qp_type == IB_QPT_SMI;
78}
79
e126ba97
EC		 80static int is_sqp(enum ib_qp_type qp_type)
81{
82 return is_qp0(qp_type) || is_qp1(qp_type);
83}
84
85static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
86{
87 return mlx5_buf_offset(&qp->buf, offset);
88}
89
90static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
91{
92 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
93}
94
95void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
96{
97 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
98}
99
c1395a2a
HE		 100/**
101 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
102 *
103 * @qp: QP to copy from.
104 * @send: copy from the send queue when non-zero, use the receive queue
105 * otherwise.
106 * @wqe_index: index to start copying from. For send work queues, the
107 * wqe_index is in units of MLX5_SEND_WQE_BB.
108 * For receive work queue, it is the number of work queue
109 * element in the queue.
110 * @buffer: destination buffer.
111 * @length: maximum number of bytes to copy.
112 *
113 * Copies at least a single WQE, but may copy more data.
114 *
115 * Return: the number of bytes copied, or an error code.
116 */
117int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
118 void *buffer, u32 length)
119{
120 struct ib_device *ibdev = qp->ibqp.device;
121 struct mlx5_ib_dev *dev = to_mdev(ibdev);
122 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
123 size_t offset;
124 size_t wq_end;
125 struct ib_umem *umem = qp->umem;
126 u32 first_copy_length;
127 int wqe_length;
128 int ret;
129
130 if (wq->wqe_cnt == 0) {
131 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
132 qp->ibqp.qp_type);
133 return -EINVAL;
134 }
135
136 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
137 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
138
139 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
140 return -EINVAL;
141
142 if (offset > umem->length ||
143 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
144 return -EINVAL;
145
146 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
147 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
148 if (ret)
149 return ret;
150
151 if (send) {
152 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
153 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
154
155 wqe_length = ds * MLX5_WQE_DS_UNITS;
156 } else {
157 wqe_length = 1 << wq->wqe_shift;
158 }
159
160 if (wqe_length <= first_copy_length)
161 return first_copy_length;
162
163 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
164 wqe_length - first_copy_length);
165 if (ret)
166 return ret;
167
168 return wqe_length;
169}
170
e126ba97
EC		 171static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
172{
173 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
174 struct ib_event event;
175
176 if (type == MLX5_EVENT_TYPE_PATH_MIG)
177 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
178
179 if (ibqp->event_handler) {
180 event.device = ibqp->device;
181 event.element.qp = ibqp;
182 switch (type) {
183 case MLX5_EVENT_TYPE_PATH_MIG:
184 event.event = IB_EVENT_PATH_MIG;
185 break;
186 case MLX5_EVENT_TYPE_COMM_EST:
187 event.event = IB_EVENT_COMM_EST;
188 break;
189 case MLX5_EVENT_TYPE_SQ_DRAINED:
190 event.event = IB_EVENT_SQ_DRAINED;
191 break;
192 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
193 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
194 break;
195 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
196 event.event = IB_EVENT_QP_FATAL;
197 break;
198 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
199 event.event = IB_EVENT_PATH_MIG_ERR;
200 break;
201 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
202 event.event = IB_EVENT_QP_REQ_ERR;
203 break;
204 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
205 event.event = IB_EVENT_QP_ACCESS_ERR;
206 break;
207 default:
208 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
209 return;
210 }
211
212 ibqp->event_handler(&event, ibqp->qp_context);
213 }
214}
215
216static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
217 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
218{
219 int wqe_size;
220 int wq_size;
221
222 /* Sanity check RQ size before proceeding */
938fe83c 223 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 224 return -EINVAL;
225
226 if (!has_rq) {
227 qp->rq.max_gs = 0;
228 qp->rq.wqe_cnt = 0;
229 qp->rq.wqe_shift = 0;
230 } else {
231 if (ucmd) {
232 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
233 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
234 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
235 qp->rq.max_post = qp->rq.wqe_cnt;
236 } else {
237 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
238 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
239 wqe_size = roundup_pow_of_two(wqe_size);
240 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
241 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
242 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 243 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 244 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
245 wqe_size,
938fe83c
SM		 246 MLX5_CAP_GEN(dev->mdev,
247 max_wqe_sz_rq));
e126ba97
EC		 248 return -EINVAL;
249 }
250 qp->rq.wqe_shift = ilog2(wqe_size);
251 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
252 qp->rq.max_post = qp->rq.wqe_cnt;
253 }
254 }
255
256 return 0;
257}
258
259static int sq_overhead(enum ib_qp_type qp_type)
260{
618af384 261 int size = 0;
e126ba97
EC		 262
263 switch (qp_type) {
264 case IB_QPT_XRC_INI:
b125a54b 265 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 266 /* fall through */
267 case IB_QPT_RC:
268 size += sizeof(struct mlx5_wqe_ctrl_seg) +
269 sizeof(struct mlx5_wqe_atomic_seg) +
270 sizeof(struct mlx5_wqe_raddr_seg);
271 break;
272
b125a54b
EC		 273 case IB_QPT_XRC_TGT:
274 return 0;
275
e126ba97 276 case IB_QPT_UC:
b125a54b 277 size += sizeof(struct mlx5_wqe_ctrl_seg) +
9e65dc37
EC		 278 sizeof(struct mlx5_wqe_raddr_seg) +
279 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
280 sizeof(struct mlx5_mkey_seg);
e126ba97
EC		 281 break;
282
283 case IB_QPT_UD:
284 case IB_QPT_SMI:
285 case IB_QPT_GSI:
b125a54b 286 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 287 sizeof(struct mlx5_wqe_datagram_seg);
288 break;
289
290 case MLX5_IB_QPT_REG_UMR:
b125a54b 291 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 292 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
293 sizeof(struct mlx5_mkey_seg);
294 break;
295
296 default:
297 return -EINVAL;
298 }
299
300 return size;
301}
302
303static int calc_send_wqe(struct ib_qp_init_attr *attr)
304{
305 int inl_size = 0;
306 int size;
307
308 size = sq_overhead(attr->qp_type);
309 if (size < 0)
310 return size;
311
312 if (attr->cap.max_inline_data) {
313 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
314 attr->cap.max_inline_data;
315 }
316
317 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 318 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
319 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
320 return MLX5_SIG_WQE_SIZE;
321 else
322 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 323}
324
325static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
326 struct mlx5_ib_qp *qp)
327{
328 int wqe_size;
329 int wq_size;
330
331 if (!attr->cap.max_send_wr)
332 return 0;
333
334 wqe_size = calc_send_wqe(attr);
335 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
336 if (wqe_size < 0)
337 return wqe_size;
338
938fe83c 339 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 340 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 341 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 342 return -EINVAL;
343 }
344
345 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
346 sizeof(struct mlx5_wqe_inline_seg);
347 attr->cap.max_inline_data = qp->max_inline_data;
348
e1e66cc2
SG		 349 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
350 qp->signature_en = true;
351
e126ba97
EC		 352 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
353 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 354 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 355 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 356 qp->sq.wqe_cnt,
357 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 358 return -ENOMEM;
359 }
e126ba97
EC		 360 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
361 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 362 qp->sq.max_post = wq_size / wqe_size;
363 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 364
365 return wq_size;
366}
367
368static int set_user_buf_size(struct mlx5_ib_dev *dev,
369 struct mlx5_ib_qp *qp,
370 struct mlx5_ib_create_qp *ucmd)
371{
372 int desc_sz = 1 << qp->sq.wqe_shift;
373
938fe83c 374 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 375 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 376 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 377 return -EINVAL;
378 }
379
380 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
381 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
382 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
383 return -EINVAL;
384 }
385
386 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
387
938fe83c 388 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 389 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 390 qp->sq.wqe_cnt,
391 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 392 return -EINVAL;
393 }
394
395 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
396 (qp->sq.wqe_cnt << 6);
397
398 return 0;
399}
400
401static int qp_has_rq(struct ib_qp_init_attr *attr)
402{
403 if (attr->qp_type == IB_QPT_XRC_INI ||
404 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
405 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
406 !attr->cap.max_recv_wr)
407 return 0;
408
409 return 1;
410}
411
c1be5232
EC		 412static int first_med_uuar(void)
413{
414 return 1;
415}
416
417static int next_uuar(int n)
418{
419 n++;
420
421 while (((n % 4) & 2))
422 n++;
423
424 return n;
425}
426
427static int num_med_uuar(struct mlx5_uuar_info *uuari)
428{
429 int n;
430
431 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
432 uuari->num_low_latency_uuars - 1;
433
434 return n >= 0 ? n : 0;
435}
436
437static int max_uuari(struct mlx5_uuar_info *uuari)
438{
439 return uuari->num_uars * 4;
440}
441
442static int first_hi_uuar(struct mlx5_uuar_info *uuari)
443{
444 int med;
445 int i;
446 int t;
447
448 med = num_med_uuar(uuari);
449 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
450 t++;
451 if (t == med)
452 return next_uuar(i);
453 }
454
455 return 0;
456}
457
e126ba97
EC		 458static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
459{
e126ba97
EC		 460 int i;
461
c1be5232 462 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 463 if (!test_bit(i, uuari->bitmap)) {
464 set_bit(i, uuari->bitmap);
465 uuari->count[i]++;
466 return i;
467 }
468 }
469
470 return -ENOMEM;
471}
472
473static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
474{
c1be5232 475 int minidx = first_med_uuar();
e126ba97
EC		 476 int i;
477
c1be5232 478 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 479 if (uuari->count[i] < uuari->count[minidx])
480 minidx = i;
481 }
482
483 uuari->count[minidx]++;
484 return minidx;
485}
486
487static int alloc_uuar(struct mlx5_uuar_info *uuari,
488 enum mlx5_ib_latency_class lat)
489{
490 int uuarn = -EINVAL;
491
492 mutex_lock(&uuari->lock);
493 switch (lat) {
494 case MLX5_IB_LATENCY_CLASS_LOW:
495 uuarn = 0;
496 uuari->count[uuarn]++;
497 break;
498
499 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 500 if (uuari->ver < 2)
501 uuarn = -ENOMEM;
502 else
503 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 504 break;
505
506 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 507 if (uuari->ver < 2)
508 uuarn = -ENOMEM;
509 else
510 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 511 break;
512
513 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
514 uuarn = 2;
515 break;
516 }
517 mutex_unlock(&uuari->lock);
518
519 return uuarn;
520}
521
522static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
523{
524 clear_bit(uuarn, uuari->bitmap);
525 --uuari->count[uuarn];
526}
527
528static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
529{
530 clear_bit(uuarn, uuari->bitmap);
531 --uuari->count[uuarn];
532}
533
534static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
535{
536 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
537 int high_uuar = nuuars - uuari->num_low_latency_uuars;
538
539 mutex_lock(&uuari->lock);
540 if (uuarn == 0) {
541 --uuari->count[uuarn];
542 goto out;
543 }
544
545 if (uuarn < high_uuar) {
546 free_med_class_uuar(uuari, uuarn);
547 goto out;
548 }
549
550 free_high_class_uuar(uuari, uuarn);
551
552out:
553 mutex_unlock(&uuari->lock);
554}
555
556static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
557{
558 switch (state) {
559 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
560 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
561 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
562 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
563 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
564 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
565 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
566 default: return -1;
567 }
568}
569
570static int to_mlx5_st(enum ib_qp_type type)
571{
572 switch (type) {
573 case IB_QPT_RC: return MLX5_QP_ST_RC;
574 case IB_QPT_UC: return MLX5_QP_ST_UC;
575 case IB_QPT_UD: return MLX5_QP_ST_UD;
576 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
577 case IB_QPT_XRC_INI:
578 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
579 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
580 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
581 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
582 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
583 case IB_QPT_RAW_PACKET:
584 case IB_QPT_MAX:
585 default: return -EINVAL;
586 }
587}
588
589static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
590{
591 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
592}
593
594static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
595 struct mlx5_ib_qp *qp, struct ib_udata *udata,
596 struct mlx5_create_qp_mbox_in **in,
597 struct mlx5_ib_create_qp_resp *resp, int *inlen)
598{
599 struct mlx5_ib_ucontext *context;
600 struct mlx5_ib_create_qp ucmd;
9e9c47d0 601 int page_shift = 0;
e126ba97
EC		 602 int uar_index;
603 int npages;
9e9c47d0 604 u32 offset = 0;
e126ba97 605 int uuarn;
9e9c47d0 606 int ncont = 0;
e126ba97
EC		 607 int err;
608
609 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
610 if (err) {
611 mlx5_ib_dbg(dev, "copy failed\n");
612 return err;
613 }
614
615 context = to_mucontext(pd->uobject->context);
616 /*
617 * TBD: should come from the verbs when we have the API
618 */
619 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
620 if (uuarn < 0) {
621 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
c1be5232
EC		 622 mlx5_ib_dbg(dev, "reverting to medium latency\n");
623 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
e126ba97 624 if (uuarn < 0) {
c1be5232
EC		 625 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
626 mlx5_ib_dbg(dev, "reverting to high latency\n");
627 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
628 if (uuarn < 0) {
629 mlx5_ib_warn(dev, "uuar allocation failed\n");
630 return uuarn;
631 }
e126ba97
EC		 632 }
633 }
634
635 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
636 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
637
48fea837
HE		 638 qp->rq.offset = 0;
639 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
640 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
641
e126ba97
EC		 642 err = set_user_buf_size(dev, qp, &ucmd);
643 if (err)
644 goto err_uuar;
645
9e9c47d0
EC		 646 if (ucmd.buf_addr && qp->buf_size) {
647 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
648 qp->buf_size, 0, 0);
649 if (IS_ERR(qp->umem)) {
650 mlx5_ib_dbg(dev, "umem_get failed\n");
651 err = PTR_ERR(qp->umem);
652 goto err_uuar;
653 }
654 } else {
655 qp->umem = NULL;
e126ba97
EC		 656 }
657
9e9c47d0
EC		 658 if (qp->umem) {
659 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
660 &ncont, NULL);
661 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
662 if (err) {
663 mlx5_ib_warn(dev, "bad offset\n");
664 goto err_umem;
665 }
666 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
667 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
e126ba97 668 }
e126ba97
EC		 669
670 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
671 *in = mlx5_vzalloc(*inlen);
672 if (!*in) {
673 err = -ENOMEM;
674 goto err_umem;
675 }
9e9c47d0
EC		 676 if (qp->umem)
677 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
e126ba97 678 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 679 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 680 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
681
682 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
683 resp->uuar_index = uuarn;
684 qp->uuarn = uuarn;
685
686 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
687 if (err) {
688 mlx5_ib_dbg(dev, "map failed\n");
689 goto err_free;
690 }
691
692 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
693 if (err) {
694 mlx5_ib_dbg(dev, "copy failed\n");
695 goto err_unmap;
696 }
697 qp->create_type = MLX5_QP_USER;
698
699 return 0;
700
701err_unmap:
702 mlx5_ib_db_unmap_user(context, &qp->db);
703
704err_free:
479163f4 705 kvfree(*in);
e126ba97
EC		 706
707err_umem:
9e9c47d0
EC		 708 if (qp->umem)
709 ib_umem_release(qp->umem);
e126ba97
EC		 710
711err_uuar:
712 free_uuar(&context->uuari, uuarn);
713 return err;
714}
715
716static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
717{
718 struct mlx5_ib_ucontext *context;
719
720 context = to_mucontext(pd->uobject->context);
721 mlx5_ib_db_unmap_user(context, &qp->db);
9e9c47d0
EC		 722 if (qp->umem)
723 ib_umem_release(qp->umem);
e126ba97
EC		 724 free_uuar(&context->uuari, qp->uuarn);
725}
726
727static int create_kernel_qp(struct mlx5_ib_dev *dev,
728 struct ib_qp_init_attr *init_attr,
729 struct mlx5_ib_qp *qp,
730 struct mlx5_create_qp_mbox_in **in, int *inlen)
731{
732 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
733 struct mlx5_uuar_info *uuari;
734 int uar_index;
735 int uuarn;
736 int err;
737
9603b61d 738 uuari = &dev->mdev->priv.uuari;
652c1a05 739 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
1a4c3a3d 740 return -EINVAL;
e126ba97
EC		 741
742 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
743 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
744
745 uuarn = alloc_uuar(uuari, lc);
746 if (uuarn < 0) {
747 mlx5_ib_dbg(dev, "\n");
748 return -ENOMEM;
749 }
750
751 qp->bf = &uuari->bfs[uuarn];
752 uar_index = qp->bf->uar->index;
753
754 err = calc_sq_size(dev, init_attr, qp);
755 if (err < 0) {
756 mlx5_ib_dbg(dev, "err %d\n", err);
757 goto err_uuar;
758 }
759
760 qp->rq.offset = 0;
761 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
762 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
763
64ffaa21 764 err = mlx5_buf_alloc(dev->mdev, qp->buf_size, &qp->buf);
e126ba97
EC		 765 if (err) {
766 mlx5_ib_dbg(dev, "err %d\n", err);
767 goto err_uuar;
768 }
769
770 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
771 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
772 *in = mlx5_vzalloc(*inlen);
773 if (!*in) {
774 err = -ENOMEM;
775 goto err_buf;
776 }
777 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 778 (*in)->ctx.log_pg_sz_remote_qpn =
779 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 780 /* Set "fast registration enabled" for all kernel QPs */
781 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
782 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
783
784 mlx5_fill_page_array(&qp->buf, (*in)->pas);
785
9603b61d 786 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 787 if (err) {
788 mlx5_ib_dbg(dev, "err %d\n", err);
789 goto err_free;
790 }
791
e126ba97
EC		 792 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
793 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
794 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
795 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
796 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
797
798 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
799 !qp->sq.w_list || !qp->sq.wqe_head) {
800 err = -ENOMEM;
801 goto err_wrid;
802 }
803 qp->create_type = MLX5_QP_KERNEL;
804
805 return 0;
806
807err_wrid:
9603b61d 808 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 809 kfree(qp->sq.wqe_head);
810 kfree(qp->sq.w_list);
811 kfree(qp->sq.wrid);
812 kfree(qp->sq.wr_data);
813 kfree(qp->rq.wrid);
814
815err_free:
479163f4 816 kvfree(*in);
e126ba97
EC		 817
818err_buf:
9603b61d 819 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 820
821err_uuar:
9603b61d 822 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 823 return err;
824}
825
826static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
827{
9603b61d 828 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 829 kfree(qp->sq.wqe_head);
830 kfree(qp->sq.w_list);
831 kfree(qp->sq.wrid);
832 kfree(qp->sq.wr_data);
833 kfree(qp->rq.wrid);
9603b61d
JM		 834 mlx5_buf_free(dev->mdev, &qp->buf);
835 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 836}
837
838static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
839{
840 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
841 (attr->qp_type == IB_QPT_XRC_INI))
842 return cpu_to_be32(MLX5_SRQ_RQ);
843 else if (!qp->has_rq)
844 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
845 else
846 return cpu_to_be32(MLX5_NON_ZERO_RQ);
847}
848
849static int is_connected(enum ib_qp_type qp_type)
850{
851 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
852 return 1;
853
854 return 0;
855}
856
857static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
858 struct ib_qp_init_attr *init_attr,
859 struct ib_udata *udata, struct mlx5_ib_qp *qp)
860{
861 struct mlx5_ib_resources *devr = &dev->devr;
938fe83c 862 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 863 struct mlx5_ib_create_qp_resp resp;
864 struct mlx5_create_qp_mbox_in *in;
865 struct mlx5_ib_create_qp ucmd;
866 int inlen = sizeof(*in);
867 int err;
868
6aec21f6
HE		 869 mlx5_ib_odp_create_qp(qp);
870
e126ba97
EC		 871 mutex_init(&qp->mutex);
872 spin_lock_init(&qp->sq.lock);
873 spin_lock_init(&qp->rq.lock);
874
f360d88a 875 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 876 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 877 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
878 return -EINVAL;
879 } else {
880 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
881 }
882 }
883
e126ba97
EC		 884 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
885 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
886
887 if (pd && pd->uobject) {
888 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
889 mlx5_ib_dbg(dev, "copy failed\n");
890 return -EFAULT;
891 }
892
893 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
894 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
895 } else {
896 qp->wq_sig = !!wq_signature;
897 }
898
899 qp->has_rq = qp_has_rq(init_attr);
900 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
901 qp, (pd && pd->uobject) ? &ucmd : NULL);
902 if (err) {
903 mlx5_ib_dbg(dev, "err %d\n", err);
904 return err;
905 }
906
907 if (pd) {
908 if (pd->uobject) {
938fe83c
SM		 909 __u32 max_wqes =
910 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 911 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
912 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
913 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
914 mlx5_ib_dbg(dev, "invalid rq params\n");
915 return -EINVAL;
916 }
938fe83c 917 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 918 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 919 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 920 return -EINVAL;
921 }
922 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
923 if (err)
924 mlx5_ib_dbg(dev, "err %d\n", err);
925 } else {
926 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
927 if (err)
928 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 929 }
930
931 if (err)
932 return err;
933 } else {
934 in = mlx5_vzalloc(sizeof(*in));
935 if (!in)
936 return -ENOMEM;
937
938 qp->create_type = MLX5_QP_EMPTY;
939 }
940
941 if (is_sqp(init_attr->qp_type))
942 qp->port = init_attr->port_num;
943
944 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
945 MLX5_QP_PM_MIGRATED << 11);
946
947 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
948 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
949 else
950 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
951
952 if (qp->wq_sig)
953 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
954
f360d88a
EC		 955 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
956 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
957
e126ba97
EC		 958 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
959 int rcqe_sz;
960 int scqe_sz;
961
962 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
963 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
964
965 if (rcqe_sz == 128)
966 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
967 else
968 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
969
970 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
971 if (scqe_sz == 128)
972 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
973 else
974 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
975 }
976 }
977
978 if (qp->rq.wqe_cnt) {
979 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
980 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
981 }
982
983 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
984
985 if (qp->sq.wqe_cnt)
986 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
987 else
988 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
989
990 /* Set default resources */
991 switch (init_attr->qp_type) {
992 case IB_QPT_XRC_TGT:
993 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
994 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
995 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
996 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
997 break;
998 case IB_QPT_XRC_INI:
999 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1000 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1001 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1002 break;
1003 default:
1004 if (init_attr->srq) {
1005 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1006 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1007 } else {
1008 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
4aa17b28
HA		 1009 in->ctx.rq_type_srqn |=
1010 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1011 }
1012 }
1013
1014 if (init_attr->send_cq)
1015 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1016
1017 if (init_attr->recv_cq)
1018 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1019
1020 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1021
9603b61d 1022 err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen);
e126ba97
EC		 1023 if (err) {
1024 mlx5_ib_dbg(dev, "create qp failed\n");
1025 goto err_create;
1026 }
1027
479163f4 1028 kvfree(in);
e126ba97
EC		 1029 /* Hardware wants QPN written in big-endian order (after
1030 * shifting) for send doorbell. Precompute this value to save
1031 * a little bit when posting sends.
1032 */
1033 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1034
1035 qp->mqp.event = mlx5_ib_qp_event;
1036
1037 return 0;
1038
1039err_create:
1040 if (qp->create_type == MLX5_QP_USER)
1041 destroy_qp_user(pd, qp);
1042 else if (qp->create_type == MLX5_QP_KERNEL)
1043 destroy_qp_kernel(dev, qp);
1044
479163f4 1045 kvfree(in);
e126ba97
EC		 1046 return err;
1047}
1048
1049static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1050 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1051{
1052 if (send_cq) {
1053 if (recv_cq) {
1054 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1055 spin_lock_irq(&send_cq->lock);
1056 spin_lock_nested(&recv_cq->lock,
1057 SINGLE_DEPTH_NESTING);
1058 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1059 spin_lock_irq(&send_cq->lock);
1060 __acquire(&recv_cq->lock);
1061 } else {
1062 spin_lock_irq(&recv_cq->lock);
1063 spin_lock_nested(&send_cq->lock,
1064 SINGLE_DEPTH_NESTING);
1065 }
1066 } else {
1067 spin_lock_irq(&send_cq->lock);
6a4f139a 1068 __acquire(&recv_cq->lock);
e126ba97
EC		 1069 }
1070 } else if (recv_cq) {
1071 spin_lock_irq(&recv_cq->lock);
6a4f139a
EC		 1072 __acquire(&send_cq->lock);
1073 } else {
1074 __acquire(&send_cq->lock);
1075 __acquire(&recv_cq->lock);
e126ba97
EC		 1076 }
1077}
1078
1079static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1080 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1081{
1082 if (send_cq) {
1083 if (recv_cq) {
1084 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1085 spin_unlock(&recv_cq->lock);
1086 spin_unlock_irq(&send_cq->lock);
1087 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1088 __release(&recv_cq->lock);
1089 spin_unlock_irq(&send_cq->lock);
1090 } else {
1091 spin_unlock(&send_cq->lock);
1092 spin_unlock_irq(&recv_cq->lock);
1093 }
1094 } else {
6a4f139a 1095 __release(&recv_cq->lock);
e126ba97
EC		 1096 spin_unlock_irq(&send_cq->lock);
1097 }
1098 } else if (recv_cq) {
6a4f139a 1099 __release(&send_cq->lock);
e126ba97 1100 spin_unlock_irq(&recv_cq->lock);
6a4f139a
EC		 1101 } else {
1102 __release(&recv_cq->lock);
1103 __release(&send_cq->lock);
e126ba97
EC		 1104 }
1105}
1106
1107static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1108{
1109 return to_mpd(qp->ibqp.pd);
1110}
1111
1112static void get_cqs(struct mlx5_ib_qp *qp,
1113 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1114{
1115 switch (qp->ibqp.qp_type) {
1116 case IB_QPT_XRC_TGT:
1117 *send_cq = NULL;
1118 *recv_cq = NULL;
1119 break;
1120 case MLX5_IB_QPT_REG_UMR:
1121 case IB_QPT_XRC_INI:
1122 *send_cq = to_mcq(qp->ibqp.send_cq);
1123 *recv_cq = NULL;
1124 break;
1125
1126 case IB_QPT_SMI:
1127 case IB_QPT_GSI:
1128 case IB_QPT_RC:
1129 case IB_QPT_UC:
1130 case IB_QPT_UD:
1131 case IB_QPT_RAW_IPV6:
1132 case IB_QPT_RAW_ETHERTYPE:
1133 *send_cq = to_mcq(qp->ibqp.send_cq);
1134 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1135 break;
1136
1137 case IB_QPT_RAW_PACKET:
1138 case IB_QPT_MAX:
1139 default:
1140 *send_cq = NULL;
1141 *recv_cq = NULL;
1142 break;
1143 }
1144}
1145
1146static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1147{
1148 struct mlx5_ib_cq *send_cq, *recv_cq;
1149 struct mlx5_modify_qp_mbox_in *in;
1150 int err;
1151
1152 in = kzalloc(sizeof(*in), GFP_KERNEL);
1153 if (!in)
1154 return;
7bef7ad2 1155
6aec21f6
HE		 1156 if (qp->state != IB_QPS_RESET) {
1157 mlx5_ib_qp_disable_pagefaults(qp);
9603b61d 1158 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state),
c3c6c9c8 1159 MLX5_QP_STATE_RST, in, 0, &qp->mqp))
e126ba97
EC		 1160 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1161 qp->mqp.qpn);
6aec21f6 1162 }
e126ba97
EC		 1163
1164 get_cqs(qp, &send_cq, &recv_cq);
1165
1166 if (qp->create_type == MLX5_QP_KERNEL) {
1167 mlx5_ib_lock_cqs(send_cq, recv_cq);
1168 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1169 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1170 if (send_cq != recv_cq)
1171 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1172 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1173 }
1174
9603b61d 1175 err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp);
e126ba97
EC		 1176 if (err)
1177 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1178 kfree(in);
1179
1180
1181 if (qp->create_type == MLX5_QP_KERNEL)
1182 destroy_qp_kernel(dev, qp);
1183 else if (qp->create_type == MLX5_QP_USER)
1184 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1185}
1186
1187static const char *ib_qp_type_str(enum ib_qp_type type)
1188{
1189 switch (type) {
1190 case IB_QPT_SMI:
1191 return "IB_QPT_SMI";
1192 case IB_QPT_GSI:
1193 return "IB_QPT_GSI";
1194 case IB_QPT_RC:
1195 return "IB_QPT_RC";
1196 case IB_QPT_UC:
1197 return "IB_QPT_UC";
1198 case IB_QPT_UD:
1199 return "IB_QPT_UD";
1200 case IB_QPT_RAW_IPV6:
1201 return "IB_QPT_RAW_IPV6";
1202 case IB_QPT_RAW_ETHERTYPE:
1203 return "IB_QPT_RAW_ETHERTYPE";
1204 case IB_QPT_XRC_INI:
1205 return "IB_QPT_XRC_INI";
1206 case IB_QPT_XRC_TGT:
1207 return "IB_QPT_XRC_TGT";
1208 case IB_QPT_RAW_PACKET:
1209 return "IB_QPT_RAW_PACKET";
1210 case MLX5_IB_QPT_REG_UMR:
1211 return "MLX5_IB_QPT_REG_UMR";
1212 case IB_QPT_MAX:
1213 default:
1214 return "Invalid QP type";
1215 }
1216}
1217
1218struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1219 struct ib_qp_init_attr *init_attr,
1220 struct ib_udata *udata)
1221{
1222 struct mlx5_ib_dev *dev;
1223 struct mlx5_ib_qp *qp;
1224 u16 xrcdn = 0;
1225 int err;
1226
1227 if (pd) {
1228 dev = to_mdev(pd->device);
1229 } else {
1230 /* being cautious here */
1231 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1232 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1233 pr_warn("%s: no PD for transport %s\n", __func__,
1234 ib_qp_type_str(init_attr->qp_type));
1235 return ERR_PTR(-EINVAL);
1236 }
1237 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1238 }
1239
1240 switch (init_attr->qp_type) {
1241 case IB_QPT_XRC_TGT:
1242 case IB_QPT_XRC_INI:
938fe83c 1243 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 1244 mlx5_ib_dbg(dev, "XRC not supported\n");
1245 return ERR_PTR(-ENOSYS);
1246 }
1247 init_attr->recv_cq = NULL;
1248 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1249 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1250 init_attr->send_cq = NULL;
1251 }
1252
1253 /* fall through */
1254 case IB_QPT_RC:
1255 case IB_QPT_UC:
1256 case IB_QPT_UD:
1257 case IB_QPT_SMI:
1258 case IB_QPT_GSI:
1259 case MLX5_IB_QPT_REG_UMR:
1260 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1261 if (!qp)
1262 return ERR_PTR(-ENOMEM);
1263
1264 err = create_qp_common(dev, pd, init_attr, udata, qp);
1265 if (err) {
1266 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1267 kfree(qp);
1268 return ERR_PTR(err);
1269 }
1270
1271 if (is_qp0(init_attr->qp_type))
1272 qp->ibqp.qp_num = 0;
1273 else if (is_qp1(init_attr->qp_type))
1274 qp->ibqp.qp_num = 1;
1275 else
1276 qp->ibqp.qp_num = qp->mqp.qpn;
1277
1278 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1279 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1280 to_mcq(init_attr->send_cq)->mcq.cqn);
1281
1282 qp->xrcdn = xrcdn;
1283
1284 break;
1285
1286 case IB_QPT_RAW_IPV6:
1287 case IB_QPT_RAW_ETHERTYPE:
1288 case IB_QPT_RAW_PACKET:
1289 case IB_QPT_MAX:
1290 default:
1291 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1292 init_attr->qp_type);
1293 /* Don't support raw QPs */
1294 return ERR_PTR(-EINVAL);
1295 }
1296
1297 return &qp->ibqp;
1298}
1299
1300int mlx5_ib_destroy_qp(struct ib_qp *qp)
1301{
1302 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1303 struct mlx5_ib_qp *mqp = to_mqp(qp);
1304
1305 destroy_qp_common(dev, mqp);
1306
1307 kfree(mqp);
1308
1309 return 0;
1310}
1311
1312static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1313 int attr_mask)
1314{
1315 u32 hw_access_flags = 0;
1316 u8 dest_rd_atomic;
1317 u32 access_flags;
1318
1319 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1320 dest_rd_atomic = attr->max_dest_rd_atomic;
1321 else
1322 dest_rd_atomic = qp->resp_depth;
1323
1324 if (attr_mask & IB_QP_ACCESS_FLAGS)
1325 access_flags = attr->qp_access_flags;
1326 else
1327 access_flags = qp->atomic_rd_en;
1328
1329 if (!dest_rd_atomic)
1330 access_flags &= IB_ACCESS_REMOTE_WRITE;
1331
1332 if (access_flags & IB_ACCESS_REMOTE_READ)
1333 hw_access_flags |= MLX5_QP_BIT_RRE;
1334 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1335 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1336 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1337 hw_access_flags |= MLX5_QP_BIT_RWE;
1338
1339 return cpu_to_be32(hw_access_flags);
1340}
1341
1342enum {
1343 MLX5_PATH_FLAG_FL = 1 << 0,
1344 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1345 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1346};
1347
1348static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1349{
1350 if (rate == IB_RATE_PORT_CURRENT) {
1351 return 0;
1352 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1353 return -EINVAL;
1354 } else {
1355 while (rate != IB_RATE_2_5_GBPS &&
1356 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 1357 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 1358 --rate;
1359 }
1360
1361 return rate + MLX5_STAT_RATE_OFFSET;
1362}
1363
1364static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1365 struct mlx5_qp_path *path, u8 port, int attr_mask,
1366 u32 path_flags, const struct ib_qp_attr *attr)
1367{
1368 int err;
1369
1370 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1371 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1372
1373 if (attr_mask & IB_QP_PKEY_INDEX)
1374 path->pkey_index = attr->pkey_index;
1375
1376 path->grh_mlid = ah->src_path_bits & 0x7f;
1377 path->rlid = cpu_to_be16(ah->dlid);
1378
1379 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 1380 if (ah->grh.sgid_index >=
1381 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 1382 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 1383 ah->grh.sgid_index,
1384 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 1385 return -EINVAL;
1386 }
e126ba97
EC		 1387 path->grh_mlid |= 1 << 7;
1388 path->mgid_index = ah->grh.sgid_index;
1389 path->hop_limit = ah->grh.hop_limit;
1390 path->tclass_flowlabel =
1391 cpu_to_be32((ah->grh.traffic_class << 20) |
1392 (ah->grh.flow_label));
1393 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1394 }
1395
1396 err = ib_rate_to_mlx5(dev, ah->static_rate);
1397 if (err < 0)
1398 return err;
1399 path->static_rate = err;
1400 path->port = port;
1401
e126ba97
EC		 1402 if (attr_mask & IB_QP_TIMEOUT)
1403 path->ackto_lt = attr->timeout << 3;
1404
1405 path->sl = ah->sl & 0xf;
1406
1407 return 0;
1408}
1409
1410static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1411 [MLX5_QP_STATE_INIT] = {
1412 [MLX5_QP_STATE_INIT] = {
1413 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1414 MLX5_QP_OPTPAR_RAE |
1415 MLX5_QP_OPTPAR_RWE |
1416 MLX5_QP_OPTPAR_PKEY_INDEX |
1417 MLX5_QP_OPTPAR_PRI_PORT,
1418 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1419 MLX5_QP_OPTPAR_PKEY_INDEX |
1420 MLX5_QP_OPTPAR_PRI_PORT,
1421 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1422 MLX5_QP_OPTPAR_Q_KEY |
1423 MLX5_QP_OPTPAR_PRI_PORT,
1424 },
1425 [MLX5_QP_STATE_RTR] = {
1426 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1427 MLX5_QP_OPTPAR_RRE |
1428 MLX5_QP_OPTPAR_RAE |
1429 MLX5_QP_OPTPAR_RWE |
1430 MLX5_QP_OPTPAR_PKEY_INDEX,
1431 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1432 MLX5_QP_OPTPAR_RWE |
1433 MLX5_QP_OPTPAR_PKEY_INDEX,
1434 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1435 MLX5_QP_OPTPAR_Q_KEY,
1436 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1437 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 1438 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1439 MLX5_QP_OPTPAR_RRE |
1440 MLX5_QP_OPTPAR_RAE |
1441 MLX5_QP_OPTPAR_RWE |
1442 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 1443 },
1444 },
1445 [MLX5_QP_STATE_RTR] = {
1446 [MLX5_QP_STATE_RTS] = {
1447 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1448 MLX5_QP_OPTPAR_RRE |
1449 MLX5_QP_OPTPAR_RAE |
1450 MLX5_QP_OPTPAR_RWE |
1451 MLX5_QP_OPTPAR_PM_STATE |
1452 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1453 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1454 MLX5_QP_OPTPAR_RWE |
1455 MLX5_QP_OPTPAR_PM_STATE,
1456 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1457 },
1458 },
1459 [MLX5_QP_STATE_RTS] = {
1460 [MLX5_QP_STATE_RTS] = {
1461 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1462 MLX5_QP_OPTPAR_RAE |
1463 MLX5_QP_OPTPAR_RWE |
1464 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 1465 MLX5_QP_OPTPAR_PM_STATE |
1466 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 1467 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 1468 MLX5_QP_OPTPAR_PM_STATE |
1469 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 1470 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1471 MLX5_QP_OPTPAR_SRQN |
1472 MLX5_QP_OPTPAR_CQN_RCV,
1473 },
1474 },
1475 [MLX5_QP_STATE_SQER] = {
1476 [MLX5_QP_STATE_RTS] = {
1477 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1478 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 1479 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 1480 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1481 MLX5_QP_OPTPAR_RWE |
1482 MLX5_QP_OPTPAR_RAE |
1483 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 1484 },
1485 },
1486};
1487
1488static int ib_nr_to_mlx5_nr(int ib_mask)
1489{
1490 switch (ib_mask) {
1491 case IB_QP_STATE:
1492 return 0;
1493 case IB_QP_CUR_STATE:
1494 return 0;
1495 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1496 return 0;
1497 case IB_QP_ACCESS_FLAGS:
1498 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1499 MLX5_QP_OPTPAR_RAE;
1500 case IB_QP_PKEY_INDEX:
1501 return MLX5_QP_OPTPAR_PKEY_INDEX;
1502 case IB_QP_PORT:
1503 return MLX5_QP_OPTPAR_PRI_PORT;
1504 case IB_QP_QKEY:
1505 return MLX5_QP_OPTPAR_Q_KEY;
1506 case IB_QP_AV:
1507 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1508 MLX5_QP_OPTPAR_PRI_PORT;
1509 case IB_QP_PATH_MTU:
1510 return 0;
1511 case IB_QP_TIMEOUT:
1512 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1513 case IB_QP_RETRY_CNT:
1514 return MLX5_QP_OPTPAR_RETRY_COUNT;
1515 case IB_QP_RNR_RETRY:
1516 return MLX5_QP_OPTPAR_RNR_RETRY;
1517 case IB_QP_RQ_PSN:
1518 return 0;
1519 case IB_QP_MAX_QP_RD_ATOMIC:
1520 return MLX5_QP_OPTPAR_SRA_MAX;
1521 case IB_QP_ALT_PATH:
1522 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1523 case IB_QP_MIN_RNR_TIMER:
1524 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1525 case IB_QP_SQ_PSN:
1526 return 0;
1527 case IB_QP_MAX_DEST_RD_ATOMIC:
1528 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1529 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1530 case IB_QP_PATH_MIG_STATE:
1531 return MLX5_QP_OPTPAR_PM_STATE;
1532 case IB_QP_CAP:
1533 return 0;
1534 case IB_QP_DEST_QPN:
1535 return 0;
1536 }
1537 return 0;
1538}
1539
1540static int ib_mask_to_mlx5_opt(int ib_mask)
1541{
1542 int result = 0;
1543 int i;
1544
1545 for (i = 0; i < 8 * sizeof(int); i++) {
1546 if ((1 << i) & ib_mask)
1547 result |= ib_nr_to_mlx5_nr(1 << i);
1548 }
1549
1550 return result;
1551}
1552
1553static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1554 const struct ib_qp_attr *attr, int attr_mask,
1555 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1556{
1557 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1558 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1559 struct mlx5_ib_cq *send_cq, *recv_cq;
1560 struct mlx5_qp_context *context;
1561 struct mlx5_modify_qp_mbox_in *in;
1562 struct mlx5_ib_pd *pd;
1563 enum mlx5_qp_state mlx5_cur, mlx5_new;
1564 enum mlx5_qp_optpar optpar;
1565 int sqd_event;
1566 int mlx5_st;
1567 int err;
1568
1569 in = kzalloc(sizeof(*in), GFP_KERNEL);
1570 if (!in)
1571 return -ENOMEM;
1572
1573 context = &in->ctx;
1574 err = to_mlx5_st(ibqp->qp_type);
1575 if (err < 0)
1576 goto out;
1577
1578 context->flags = cpu_to_be32(err << 16);
1579
1580 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1581 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1582 } else {
1583 switch (attr->path_mig_state) {
1584 case IB_MIG_MIGRATED:
1585 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1586 break;
1587 case IB_MIG_REARM:
1588 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1589 break;
1590 case IB_MIG_ARMED:
1591 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1592 break;
1593 }
1594 }
1595
1596 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1597 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1598 } else if (ibqp->qp_type == IB_QPT_UD ||
1599 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1600 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1601 } else if (attr_mask & IB_QP_PATH_MTU) {
1602 if (attr->path_mtu < IB_MTU_256 ||
1603 attr->path_mtu > IB_MTU_4096) {
1604 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1605 err = -EINVAL;
1606 goto out;
1607 }
938fe83c
SM		 1608 context->mtu_msgmax = (attr->path_mtu << 5) |
1609 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 1610 }
1611
1612 if (attr_mask & IB_QP_DEST_QPN)
1613 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1614
1615 if (attr_mask & IB_QP_PKEY_INDEX)
1616 context->pri_path.pkey_index = attr->pkey_index;
1617
1618 /* todo implement counter_index functionality */
1619
1620 if (is_sqp(ibqp->qp_type))
1621 context->pri_path.port = qp->port;
1622
1623 if (attr_mask & IB_QP_PORT)
1624 context->pri_path.port = attr->port_num;
1625
1626 if (attr_mask & IB_QP_AV) {
1627 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1628 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1629 attr_mask, 0, attr);
1630 if (err)
1631 goto out;
1632 }
1633
1634 if (attr_mask & IB_QP_TIMEOUT)
1635 context->pri_path.ackto_lt |= attr->timeout << 3;
1636
1637 if (attr_mask & IB_QP_ALT_PATH) {
1638 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1639 attr->alt_port_num, attr_mask, 0, attr);
1640 if (err)
1641 goto out;
1642 }
1643
1644 pd = get_pd(qp);
1645 get_cqs(qp, &send_cq, &recv_cq);
1646
1647 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1648 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1649 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1650 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1651
1652 if (attr_mask & IB_QP_RNR_RETRY)
1653 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1654
1655 if (attr_mask & IB_QP_RETRY_CNT)
1656 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1657
1658 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1659 if (attr->max_rd_atomic)
1660 context->params1 |=
1661 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1662 }
1663
1664 if (attr_mask & IB_QP_SQ_PSN)
1665 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1666
1667 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1668 if (attr->max_dest_rd_atomic)
1669 context->params2 |=
1670 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1671 }
1672
1673 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1674 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1675
1676 if (attr_mask & IB_QP_MIN_RNR_TIMER)
1677 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1678
1679 if (attr_mask & IB_QP_RQ_PSN)
1680 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1681
1682 if (attr_mask & IB_QP_QKEY)
1683 context->qkey = cpu_to_be32(attr->qkey);
1684
1685 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1686 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1687
1688 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1689 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1690 sqd_event = 1;
1691 else
1692 sqd_event = 0;
1693
1694 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1695 context->sq_crq_size |= cpu_to_be16(1 << 4);
1696
1697
1698 mlx5_cur = to_mlx5_state(cur_state);
1699 mlx5_new = to_mlx5_state(new_state);
1700 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 1701 if (mlx5_st < 0)
e126ba97
EC		 1702 goto out;
1703
6aec21f6
HE		 1704 /* If moving to a reset or error state, we must disable page faults on
1705 * this QP and flush all current page faults. Otherwise a stale page
1706 * fault may attempt to work on this QP after it is reset and moved
1707 * again to RTS, and may cause the driver and the device to get out of
1708 * sync. */
1709 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1710 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1711 mlx5_ib_qp_disable_pagefaults(qp);
1712
e126ba97
EC		 1713 optpar = ib_mask_to_mlx5_opt(attr_mask);
1714 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1715 in->optparam = cpu_to_be32(optpar);
9603b61d 1716 err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state),
e126ba97
EC		 1717 to_mlx5_state(new_state), in, sqd_event,
1718 &qp->mqp);
1719 if (err)
1720 goto out;
1721
6aec21f6
HE		 1722 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1723 mlx5_ib_qp_enable_pagefaults(qp);
1724
e126ba97
EC		 1725 qp->state = new_state;
1726
1727 if (attr_mask & IB_QP_ACCESS_FLAGS)
1728 qp->atomic_rd_en = attr->qp_access_flags;
1729 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1730 qp->resp_depth = attr->max_dest_rd_atomic;
1731 if (attr_mask & IB_QP_PORT)
1732 qp->port = attr->port_num;
1733 if (attr_mask & IB_QP_ALT_PATH)
1734 qp->alt_port = attr->alt_port_num;
1735
1736 /*
1737 * If we moved a kernel QP to RESET, clean up all old CQ
1738 * entries and reinitialize the QP.
1739 */
1740 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1741 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1742 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1743 if (send_cq != recv_cq)
1744 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1745
1746 qp->rq.head = 0;
1747 qp->rq.tail = 0;
1748 qp->sq.head = 0;
1749 qp->sq.tail = 0;
1750 qp->sq.cur_post = 0;
1751 qp->sq.last_poll = 0;
1752 qp->db.db[MLX5_RCV_DBR] = 0;
1753 qp->db.db[MLX5_SND_DBR] = 0;
1754 }
1755
1756out:
1757 kfree(in);
1758 return err;
1759}
1760
1761int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1762 int attr_mask, struct ib_udata *udata)
1763{
1764 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1765 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1766 enum ib_qp_state cur_state, new_state;
1767 int err = -EINVAL;
1768 int port;
1769
1770 mutex_lock(&qp->mutex);
1771
1772 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1773 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1774
1775 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
dd5f03be
MB		 1776 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1777 IB_LINK_LAYER_UNSPECIFIED))
e126ba97
EC		 1778 goto out;
1779
1780 if ((attr_mask & IB_QP_PORT) &&
938fe83c
SM		 1781 (attr->port_num == 0 ||
1782 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)))
e126ba97
EC		 1783 goto out;
1784
1785 if (attr_mask & IB_QP_PKEY_INDEX) {
1786 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c
SM		 1787 if (attr->pkey_index >=
1788 dev->mdev->port_caps[port - 1].pkey_table_len)
e126ba97
EC		 1789 goto out;
1790 }
1791
1792 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c
SM		 1793 attr->max_rd_atomic >
1794 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp)))
e126ba97
EC		 1795 goto out;
1796
1797 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c
SM		 1798 attr->max_dest_rd_atomic >
1799 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp)))
e126ba97
EC		 1800 goto out;
1801
1802 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1803 err = 0;
1804 goto out;
1805 }
1806
1807 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1808
1809out:
1810 mutex_unlock(&qp->mutex);
1811 return err;
1812}
1813
1814static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1815{
1816 struct mlx5_ib_cq *cq;
1817 unsigned cur;
1818
1819 cur = wq->head - wq->tail;
1820 if (likely(cur + nreq < wq->max_post))
1821 return 0;
1822
1823 cq = to_mcq(ib_cq);
1824 spin_lock(&cq->lock);
1825 cur = wq->head - wq->tail;
1826 spin_unlock(&cq->lock);
1827
1828 return cur + nreq >= wq->max_post;
1829}
1830
1831static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1832 u64 remote_addr, u32 rkey)
1833{
1834 rseg->raddr = cpu_to_be64(remote_addr);
1835 rseg->rkey = cpu_to_be32(rkey);
1836 rseg->reserved = 0;
1837}
1838
e126ba97
EC		 1839static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1840 struct ib_send_wr *wr)
1841{
e622f2f4
CH		 1842 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
1843 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
1844 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 1845}
1846
1847static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1848{
1849 dseg->byte_count = cpu_to_be32(sg->length);
1850 dseg->lkey = cpu_to_be32(sg->lkey);
1851 dseg->addr = cpu_to_be64(sg->addr);
1852}
1853
1854static __be16 get_klm_octo(int npages)
1855{
1856 return cpu_to_be16(ALIGN(npages, 8) / 2);
1857}
1858
1859static __be64 frwr_mkey_mask(void)
1860{
1861 u64 result;
1862
1863 result = MLX5_MKEY_MASK_LEN |
1864 MLX5_MKEY_MASK_PAGE_SIZE |
1865 MLX5_MKEY_MASK_START_ADDR |
1866 MLX5_MKEY_MASK_EN_RINVAL |
1867 MLX5_MKEY_MASK_KEY |
1868 MLX5_MKEY_MASK_LR |
1869 MLX5_MKEY_MASK_LW |
1870 MLX5_MKEY_MASK_RR |
1871 MLX5_MKEY_MASK_RW |
1872 MLX5_MKEY_MASK_A |
1873 MLX5_MKEY_MASK_SMALL_FENCE |
1874 MLX5_MKEY_MASK_FREE;
1875
1876 return cpu_to_be64(result);
1877}
1878
e6631814
SG		 1879static __be64 sig_mkey_mask(void)
1880{
1881 u64 result;
1882
1883 result = MLX5_MKEY_MASK_LEN |
1884 MLX5_MKEY_MASK_PAGE_SIZE |
1885 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 1886 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 1887 MLX5_MKEY_MASK_EN_RINVAL |
1888 MLX5_MKEY_MASK_KEY |
1889 MLX5_MKEY_MASK_LR |
1890 MLX5_MKEY_MASK_LW |
1891 MLX5_MKEY_MASK_RR |
1892 MLX5_MKEY_MASK_RW |
1893 MLX5_MKEY_MASK_SMALL_FENCE |
1894 MLX5_MKEY_MASK_FREE |
1895 MLX5_MKEY_MASK_BSF_EN;
1896
1897 return cpu_to_be64(result);
1898}
1899
8a187ee5
SG		 1900static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
1901 struct mlx5_ib_mr *mr)
1902{
1903 int ndescs = mr->ndescs;
1904
1905 memset(umr, 0, sizeof(*umr));
1906 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
1907 umr->klm_octowords = get_klm_octo(ndescs);
1908 umr->mkey_mask = frwr_mkey_mask();
1909}
1910
e126ba97
EC		 1911static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1912 struct ib_send_wr *wr, int li)
1913{
1914 memset(umr, 0, sizeof(*umr));
1915
1916 if (li) {
1917 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1918 umr->flags = 1 << 7;
1919 return;
1920 }
1921
1922 umr->flags = (1 << 5); /* fail if not free */
e622f2f4 1923 umr->klm_octowords = get_klm_octo(fast_reg_wr(wr)->page_list_len);
e126ba97
EC		 1924 umr->mkey_mask = frwr_mkey_mask();
1925}
1926
968e78dd
HE		 1927static __be64 get_umr_reg_mr_mask(void)
1928{
1929 u64 result;
1930
1931 result = MLX5_MKEY_MASK_LEN |
1932 MLX5_MKEY_MASK_PAGE_SIZE |
1933 MLX5_MKEY_MASK_START_ADDR |
1934 MLX5_MKEY_MASK_PD |
1935 MLX5_MKEY_MASK_LR |
1936 MLX5_MKEY_MASK_LW |
1937 MLX5_MKEY_MASK_KEY |
1938 MLX5_MKEY_MASK_RR |
1939 MLX5_MKEY_MASK_RW |
1940 MLX5_MKEY_MASK_A |
1941 MLX5_MKEY_MASK_FREE;
1942
1943 return cpu_to_be64(result);
1944}
1945
1946static __be64 get_umr_unreg_mr_mask(void)
1947{
1948 u64 result;
1949
1950 result = MLX5_MKEY_MASK_FREE;
1951
1952 return cpu_to_be64(result);
1953}
1954
1955static __be64 get_umr_update_mtt_mask(void)
1956{
1957 u64 result;
1958
1959 result = MLX5_MKEY_MASK_FREE;
1960
1961 return cpu_to_be64(result);
1962}
1963
e126ba97
EC		 1964static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1965 struct ib_send_wr *wr)
1966{
e622f2f4 1967 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 1968
1969 memset(umr, 0, sizeof(*umr));
1970
968e78dd
HE		 1971 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
1972 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
1973 else
1974 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
1975
e126ba97 1976 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 1977 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 1978 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
1979 umr->mkey_mask = get_umr_update_mtt_mask();
1980 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
1981 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
1982 } else {
1983 umr->mkey_mask = get_umr_reg_mr_mask();
1984 }
e126ba97 1985 } else {
968e78dd 1986 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 1987 }
1988
1989 if (!wr->num_sge)
968e78dd 1990 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 1991}
1992
1993static u8 get_umr_flags(int acc)
1994{
1995 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1996 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1997 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1998 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 1999 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 2000}
2001
8a187ee5
SG		 2002static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2003 struct mlx5_ib_mr *mr,
2004 u32 key, int access)
2005{
2006 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2007
2008 memset(seg, 0, sizeof(*seg));
2009 seg->flags = get_umr_flags(access) | MLX5_ACCESS_MODE_MTT;
2010 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2011 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2012 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2013 seg->len = cpu_to_be64(mr->ibmr.length);
2014 seg->xlt_oct_size = cpu_to_be32(ndescs);
2015 seg->log2_page_size = ilog2(mr->ibmr.page_size);
2016}
2017
e126ba97
EC		 2018static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
2019 int li, int *writ)
2020{
2021 memset(seg, 0, sizeof(*seg));
2022 if (li) {
968e78dd 2023 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2024 return;
2025 }
2026
e622f2f4 2027 seg->flags = get_umr_flags(fast_reg_wr(wr)->access_flags) |
2ac45934 2028 MLX5_ACCESS_MODE_MTT;
e126ba97 2029 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
e622f2f4 2030 seg->qpn_mkey7_0 = cpu_to_be32((fast_reg_wr(wr)->rkey & 0xff) | 0xffffff00);
e126ba97 2031 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
e622f2f4
CH		 2032 seg->start_addr = cpu_to_be64(fast_reg_wr(wr)->iova_start);
2033 seg->len = cpu_to_be64(fast_reg_wr(wr)->length);
2034 seg->xlt_oct_size = cpu_to_be32((fast_reg_wr(wr)->page_list_len + 1) / 2);
2035 seg->log2_page_size = fast_reg_wr(wr)->page_shift;
e126ba97
EC		 2036}
2037
2038static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2039{
e622f2f4 2040 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 2041
e126ba97
EC		 2042 memset(seg, 0, sizeof(*seg));
2043 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 2044 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2045 return;
2046 }
2047
968e78dd
HE		 2048 seg->flags = convert_access(umrwr->access_flags);
2049 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
2050 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
2051 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2052 }
2053 seg->len = cpu_to_be64(umrwr->length);
2054 seg->log2_page_size = umrwr->page_shift;
746b5583 2055 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 2056 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 2057}
2058
8a187ee5
SG		 2059static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2060 struct mlx5_ib_mr *mr,
2061 struct mlx5_ib_pd *pd)
2062{
2063 int bcount = mr->desc_size * mr->ndescs;
2064
2065 dseg->addr = cpu_to_be64(mr->desc_map);
2066 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2067 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2068}
2069
e126ba97
EC		 2070static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
2071 struct ib_send_wr *wr,
2072 struct mlx5_core_dev *mdev,
2073 struct mlx5_ib_pd *pd,
2074 int writ)
2075{
e622f2f4
CH		 2076 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(fast_reg_wr(wr)->page_list);
2077 u64 *page_list = fast_reg_wr(wr)->page_list->page_list;
e126ba97
EC		 2078 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
2079 int i;
2080
e622f2f4 2081 for (i = 0; i < fast_reg_wr(wr)->page_list_len; i++)
e126ba97
EC		 2082 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
2083 dseg->addr = cpu_to_be64(mfrpl->map);
e622f2f4 2084 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * fast_reg_wr(wr)->page_list_len, 64));
81fb5e26 2085 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
e126ba97
EC		 2086}
2087
2088static __be32 send_ieth(struct ib_send_wr *wr)
2089{
2090 switch (wr->opcode) {
2091 case IB_WR_SEND_WITH_IMM:
2092 case IB_WR_RDMA_WRITE_WITH_IMM:
2093 return wr->ex.imm_data;
2094
2095 case IB_WR_SEND_WITH_INV:
2096 return cpu_to_be32(wr->ex.invalidate_rkey);
2097
2098 default:
2099 return 0;
2100 }
2101}
2102
2103static u8 calc_sig(void *wqe, int size)
2104{
2105 u8 *p = wqe;
2106 u8 res = 0;
2107 int i;
2108
2109 for (i = 0; i < size; i++)
2110 res ^= p[i];
2111
2112 return ~res;
2113}
2114
2115static u8 wq_sig(void *wqe)
2116{
2117 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2118}
2119
2120static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2121 void *wqe, int *sz)
2122{
2123 struct mlx5_wqe_inline_seg *seg;
2124 void *qend = qp->sq.qend;
2125 void *addr;
2126 int inl = 0;
2127 int copy;
2128 int len;
2129 int i;
2130
2131 seg = wqe;
2132 wqe += sizeof(*seg);
2133 for (i = 0; i < wr->num_sge; i++) {
2134 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2135 len = wr->sg_list[i].length;
2136 inl += len;
2137
2138 if (unlikely(inl > qp->max_inline_data))
2139 return -ENOMEM;
2140
2141 if (unlikely(wqe + len > qend)) {
2142 copy = qend - wqe;
2143 memcpy(wqe, addr, copy);
2144 addr += copy;
2145 len -= copy;
2146 wqe = mlx5_get_send_wqe(qp, 0);
2147 }
2148 memcpy(wqe, addr, len);
2149 wqe += len;
2150 }
2151
2152 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2153
2154 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2155
2156 return 0;
2157}
2158
e6631814
SG		 2159static u16 prot_field_size(enum ib_signature_type type)
2160{
2161 switch (type) {
2162 case IB_SIG_TYPE_T10_DIF:
2163 return MLX5_DIF_SIZE;
2164 default:
2165 return 0;
2166 }
2167}
2168
2169static u8 bs_selector(int block_size)
2170{
2171 switch (block_size) {
2172 case 512: return 0x1;
2173 case 520: return 0x2;
2174 case 4096: return 0x3;
2175 case 4160: return 0x4;
2176 case 1073741824: return 0x5;
2177 default: return 0;
2178 }
2179}
2180
78eda2bb
SG		 2181static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2182 struct mlx5_bsf_inl *inl)
e6631814 2183{
142537f4
SG		 2184 /* Valid inline section and allow BSF refresh */
2185 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2186 MLX5_BSF_REFRESH_DIF);
2187 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2188 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 2189 /* repeating block */
2190 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2191 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2192 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 2193
78eda2bb
SG		 2194 if (domain->sig.dif.ref_remap)
2195 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 2196
78eda2bb
SG		 2197 if (domain->sig.dif.app_escape) {
2198 if (domain->sig.dif.ref_escape)
2199 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2200 else
2201 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 2202 }
2203
78eda2bb
SG		 2204 inl->dif_app_bitmask_check =
2205 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 2206}
2207
2208static int mlx5_set_bsf(struct ib_mr *sig_mr,
2209 struct ib_sig_attrs *sig_attrs,
2210 struct mlx5_bsf *bsf, u32 data_size)
2211{
2212 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2213 struct mlx5_bsf_basic *basic = &bsf->basic;
2214 struct ib_sig_domain *mem = &sig_attrs->mem;
2215 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 2216
c7f44fbd 2217 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 2218
2219 /* Basic + Extended + Inline */
2220 basic->bsf_size_sbs = 1 << 7;
2221 /* Input domain check byte mask */
2222 basic->check_byte_mask = sig_attrs->check_mask;
2223 basic->raw_data_size = cpu_to_be32(data_size);
2224
2225 /* Memory domain */
e6631814 2226 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 2227 case IB_SIG_TYPE_NONE:
2228 break;
e6631814 2229 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 2230 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2231 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2232 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2233 break;
2234 default:
2235 return -EINVAL;
2236 }
e6631814 2237
78eda2bb
SG		 2238 /* Wire domain */
2239 switch (sig_attrs->wire.sig_type) {
2240 case IB_SIG_TYPE_NONE:
2241 break;
2242 case IB_SIG_TYPE_T10_DIF:
e6631814 2243 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 2244 mem->sig_type == wire->sig_type) {
e6631814 2245 /* Same block structure */
142537f4 2246 basic->bsf_size_sbs |= 1 << 4;
e6631814 2247 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 2248 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 2249 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 2250 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 2251 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 2252 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 2253 } else
2254 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2255
142537f4 2256 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 2257 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 2258 break;
e6631814
SG		 2259 default:
2260 return -EINVAL;
2261 }
2262
2263 return 0;
2264}
2265
e622f2f4
CH		 2266static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
2267 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 2268{
e622f2f4
CH		 2269 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
2270 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 2271 struct mlx5_bsf *bsf;
e622f2f4
CH		 2272 u32 data_len = wr->wr.sg_list->length;
2273 u32 data_key = wr->wr.sg_list->lkey;
2274 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 2275 int ret;
2276 int wqe_size;
2277
e622f2f4
CH		 2278 if (!wr->prot ||
2279 (data_key == wr->prot->lkey &&
2280 data_va == wr->prot->addr &&
2281 data_len == wr->prot->length)) {
e6631814
SG		 2282 /**
2283 * Source domain doesn't contain signature information
5c273b16 2284 * or data and protection are interleaved in memory.
e6631814
SG		 2285 * So need construct:
2286 * ------------------
2287 * | data_klm |
2288 * ------------------
2289 * | BSF |
2290 * ------------------
2291 **/
2292 struct mlx5_klm *data_klm = *seg;
2293
2294 data_klm->bcount = cpu_to_be32(data_len);
2295 data_klm->key = cpu_to_be32(data_key);
2296 data_klm->va = cpu_to_be64(data_va);
2297 wqe_size = ALIGN(sizeof(*data_klm), 64);
2298 } else {
2299 /**
2300 * Source domain contains signature information
2301 * So need construct a strided block format:
2302 * ---------------------------
2303 * | stride_block_ctrl |
2304 * ---------------------------
2305 * | data_klm |
2306 * ---------------------------
2307 * | prot_klm |
2308 * ---------------------------
2309 * | BSF |
2310 * ---------------------------
2311 **/
2312 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2313 struct mlx5_stride_block_entry *data_sentry;
2314 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 2315 u32 prot_key = wr->prot->lkey;
2316 u64 prot_va = wr->prot->addr;
e6631814
SG		 2317 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2318 int prot_size;
2319
2320 sblock_ctrl = *seg;
2321 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2322 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2323
2324 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2325 if (!prot_size) {
2326 pr_err("Bad block size given: %u\n", block_size);
2327 return -EINVAL;
2328 }
2329 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2330 prot_size);
2331 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2332 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2333 sblock_ctrl->num_entries = cpu_to_be16(2);
2334
2335 data_sentry->bcount = cpu_to_be16(block_size);
2336 data_sentry->key = cpu_to_be32(data_key);
2337 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 2338 data_sentry->stride = cpu_to_be16(block_size);
2339
e6631814
SG		 2340 prot_sentry->bcount = cpu_to_be16(prot_size);
2341 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 2342 prot_sentry->va = cpu_to_be64(prot_va);
2343 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 2344
e6631814
SG		 2345 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2346 sizeof(*prot_sentry), 64);
2347 }
2348
2349 *seg += wqe_size;
2350 *size += wqe_size / 16;
2351 if (unlikely((*seg == qp->sq.qend)))
2352 *seg = mlx5_get_send_wqe(qp, 0);
2353
2354 bsf = *seg;
2355 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2356 if (ret)
2357 return -EINVAL;
2358
2359 *seg += sizeof(*bsf);
2360 *size += sizeof(*bsf) / 16;
2361 if (unlikely((*seg == qp->sq.qend)))
2362 *seg = mlx5_get_send_wqe(qp, 0);
2363
2364 return 0;
2365}
2366
2367static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 2368 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 2369 u32 length, u32 pdn)
2370{
e622f2f4 2371 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 2372 u32 sig_key = sig_mr->rkey;
d5436ba0 2373 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 2374
2375 memset(seg, 0, sizeof(*seg));
2376
e622f2f4 2377 seg->flags = get_umr_flags(wr->access_flags) |
e6631814
SG		 2378 MLX5_ACCESS_MODE_KLM;
2379 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 2380 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 2381 MLX5_MKEY_BSF_EN | pdn);
2382 seg->len = cpu_to_be64(length);
2383 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2384 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2385}
2386
2387static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 2388 u32 nelements)
e6631814
SG		 2389{
2390 memset(umr, 0, sizeof(*umr));
2391
2392 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2393 umr->klm_octowords = get_klm_octo(nelements);
2394 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2395 umr->mkey_mask = sig_mkey_mask();
2396}
2397
2398
e622f2f4 2399static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 2400 void **seg, int *size)
2401{
e622f2f4
CH		 2402 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
2403 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 2404 u32 pdn = get_pd(qp)->pdn;
2405 u32 klm_oct_size;
2406 int region_len, ret;
2407
e622f2f4
CH		 2408 if (unlikely(wr->wr.num_sge != 1) ||
2409 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 2410 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2411 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 2412 return -EINVAL;
2413
2414 /* length of the protected region, data + protection */
e622f2f4
CH		 2415 region_len = wr->wr.sg_list->length;
2416 if (wr->prot &&
2417 (wr->prot->lkey != wr->wr.sg_list->lkey ||
2418 wr->prot->addr != wr->wr.sg_list->addr ||
2419 wr->prot->length != wr->wr.sg_list->length))
2420 region_len += wr->prot->length;
e6631814
SG		 2421
2422 /**
2423 * KLM octoword size - if protection was provided
2424 * then we use strided block format (3 octowords),
2425 * else we use single KLM (1 octoword)
2426 **/
e622f2f4 2427 klm_oct_size = wr->prot ? 3 : 1;
e6631814 2428
e622f2f4 2429 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 2430 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2431 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2432 if (unlikely((*seg == qp->sq.qend)))
2433 *seg = mlx5_get_send_wqe(qp, 0);
2434
2435 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
2436 *seg += sizeof(struct mlx5_mkey_seg);
2437 *size += sizeof(struct mlx5_mkey_seg) / 16;
2438 if (unlikely((*seg == qp->sq.qend)))
2439 *seg = mlx5_get_send_wqe(qp, 0);
2440
2441 ret = set_sig_data_segment(wr, qp, seg, size);
2442 if (ret)
2443 return ret;
2444
d5436ba0 2445 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 2446 return 0;
2447}
2448
2449static int set_psv_wr(struct ib_sig_domain *domain,
2450 u32 psv_idx, void **seg, int *size)
2451{
2452 struct mlx5_seg_set_psv *psv_seg = *seg;
2453
2454 memset(psv_seg, 0, sizeof(*psv_seg));
2455 psv_seg->psv_num = cpu_to_be32(psv_idx);
2456 switch (domain->sig_type) {
78eda2bb
SG		 2457 case IB_SIG_TYPE_NONE:
2458 break;
e6631814
SG		 2459 case IB_SIG_TYPE_T10_DIF:
2460 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
2461 domain->sig.dif.app_tag);
2462 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 2463 break;
e6631814
SG		 2464 default:
2465 pr_err("Bad signature type given.\n");
2466 return 1;
2467 }
2468
78eda2bb
SG		 2469 *seg += sizeof(*psv_seg);
2470 *size += sizeof(*psv_seg) / 16;
2471
e6631814
SG		 2472 return 0;
2473}
2474
8a187ee5
SG		 2475static int set_reg_wr(struct mlx5_ib_qp *qp,
2476 struct ib_reg_wr *wr,
2477 void **seg, int *size)
2478{
2479 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
2480 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
2481
2482 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
2483 mlx5_ib_warn(to_mdev(qp->ibqp.device),
2484 "Invalid IB_SEND_INLINE send flag\n");
2485 return -EINVAL;
2486 }
2487
2488 set_reg_umr_seg(*seg, mr);
2489 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2490 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2491 if (unlikely((*seg == qp->sq.qend)))
2492 *seg = mlx5_get_send_wqe(qp, 0);
2493
2494 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
2495 *seg += sizeof(struct mlx5_mkey_seg);
2496 *size += sizeof(struct mlx5_mkey_seg) / 16;
2497 if (unlikely((*seg == qp->sq.qend)))
2498 *seg = mlx5_get_send_wqe(qp, 0);
2499
2500 set_reg_data_seg(*seg, mr, pd);
2501 *seg += sizeof(struct mlx5_wqe_data_seg);
2502 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2503
2504 return 0;
2505}
2506
e126ba97
EC		 2507static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
2508 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
2509{
2510 int writ = 0;
2511 int li;
2512
2513 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
2514 if (unlikely(wr->send_flags & IB_SEND_INLINE))
2515 return -EINVAL;
2516
2517 set_frwr_umr_segment(*seg, wr, li);
2518 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2519 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2520 if (unlikely((*seg == qp->sq.qend)))
2521 *seg = mlx5_get_send_wqe(qp, 0);
2522 set_mkey_segment(*seg, wr, li, &writ);
2523 *seg += sizeof(struct mlx5_mkey_seg);
2524 *size += sizeof(struct mlx5_mkey_seg) / 16;
2525 if (unlikely((*seg == qp->sq.qend)))
2526 *seg = mlx5_get_send_wqe(qp, 0);
2527 if (!li) {
e622f2f4
CH		 2528 if (unlikely(fast_reg_wr(wr)->page_list_len >
2529 fast_reg_wr(wr)->page_list->max_page_list_len))
9641b74e
EC		 2530 return -ENOMEM;
2531
e126ba97
EC		 2532 set_frwr_pages(*seg, wr, mdev, pd, writ);
2533 *seg += sizeof(struct mlx5_wqe_data_seg);
2534 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2535 }
2536 return 0;
2537}
2538
2539static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
2540{
2541 __be32 *p = NULL;
2542 int tidx = idx;
2543 int i, j;
2544
2545 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2546 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2547 if ((i & 0xf) == 0) {
2548 void *buf = mlx5_get_send_wqe(qp, tidx);
2549 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2550 p = buf;
2551 j = 0;
2552 }
2553 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2554 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2555 be32_to_cpu(p[j + 3]));
2556 }
2557}
2558
2559static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2560 unsigned bytecnt, struct mlx5_ib_qp *qp)
2561{
2562 while (bytecnt > 0) {
2563 __iowrite64_copy(dst++, src++, 8);
2564 __iowrite64_copy(dst++, src++, 8);
2565 __iowrite64_copy(dst++, src++, 8);
2566 __iowrite64_copy(dst++, src++, 8);
2567 __iowrite64_copy(dst++, src++, 8);
2568 __iowrite64_copy(dst++, src++, 8);
2569 __iowrite64_copy(dst++, src++, 8);
2570 __iowrite64_copy(dst++, src++, 8);
2571 bytecnt -= 64;
2572 if (unlikely(src == qp->sq.qend))
2573 src = mlx5_get_send_wqe(qp, 0);
2574 }
2575}
2576
2577static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2578{
2579 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2580 wr->send_flags & IB_SEND_FENCE))
2581 return MLX5_FENCE_MODE_STRONG_ORDERING;
2582
2583 if (unlikely(fence)) {
2584 if (wr->send_flags & IB_SEND_FENCE)
2585 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2586 else
2587 return fence;
2588
2589 } else {
2590 return 0;
2591 }
2592}
2593
6e5eadac
SG		 2594static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
2595 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 2596 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 2597 int *size, int nreq)
2598{
2599 int err = 0;
2600
2601 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2602 err = -ENOMEM;
2603 return err;
2604 }
2605
2606 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2607 *seg = mlx5_get_send_wqe(qp, *idx);
2608 *ctrl = *seg;
2609 *(uint32_t *)(*seg + 8) = 0;
2610 (*ctrl)->imm = send_ieth(wr);
2611 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
2612 (wr->send_flags & IB_SEND_SIGNALED ?
2613 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2614 (wr->send_flags & IB_SEND_SOLICITED ?
2615 MLX5_WQE_CTRL_SOLICITED : 0);
2616
2617 *seg += sizeof(**ctrl);
2618 *size = sizeof(**ctrl) / 16;
2619
2620 return err;
2621}
2622
2623static void finish_wqe(struct mlx5_ib_qp *qp,
2624 struct mlx5_wqe_ctrl_seg *ctrl,
2625 u8 size, unsigned idx, u64 wr_id,
2626 int nreq, u8 fence, u8 next_fence,
2627 u32 mlx5_opcode)
2628{
2629 u8 opmod = 0;
2630
2631 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2632 mlx5_opcode | ((u32)opmod << 24));
2633 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2634 ctrl->fm_ce_se |= fence;
2635 qp->fm_cache = next_fence;
2636 if (unlikely(qp->wq_sig))
2637 ctrl->signature = wq_sig(ctrl);
2638
2639 qp->sq.wrid[idx] = wr_id;
2640 qp->sq.w_list[idx].opcode = mlx5_opcode;
2641 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2642 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2643 qp->sq.w_list[idx].next = qp->sq.cur_post;
2644}
2645
2646
e126ba97
EC		 2647int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2648 struct ib_send_wr **bad_wr)
2649{
2650 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
2651 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
9603b61d 2652 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 2653 struct mlx5_ib_qp *qp = to_mqp(ibqp);
e6631814 2654 struct mlx5_ib_mr *mr;
e126ba97
EC		 2655 struct mlx5_wqe_data_seg *dpseg;
2656 struct mlx5_wqe_xrc_seg *xrc;
2657 struct mlx5_bf *bf = qp->bf;
2658 int uninitialized_var(size);
2659 void *qend = qp->sq.qend;
2660 unsigned long flags;
e126ba97
EC		 2661 unsigned idx;
2662 int err = 0;
2663 int inl = 0;
2664 int num_sge;
2665 void *seg;
2666 int nreq;
2667 int i;
2668 u8 next_fence = 0;
e126ba97
EC		 2669 u8 fence;
2670
2671 spin_lock_irqsave(&qp->sq.lock, flags);
2672
2673 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 2674 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 2675 mlx5_ib_warn(dev, "\n");
2676 err = -EINVAL;
2677 *bad_wr = wr;
2678 goto out;
2679 }
2680
6e5eadac
SG		 2681 fence = qp->fm_cache;
2682 num_sge = wr->num_sge;
2683 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 2684 mlx5_ib_warn(dev, "\n");
2685 err = -ENOMEM;
2686 *bad_wr = wr;
2687 goto out;
2688 }
2689
6e5eadac
SG		 2690 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
2691 if (err) {
e126ba97
EC		 2692 mlx5_ib_warn(dev, "\n");
2693 err = -ENOMEM;
2694 *bad_wr = wr;
2695 goto out;
2696 }
2697
e126ba97
EC		 2698 switch (ibqp->qp_type) {
2699 case IB_QPT_XRC_INI:
2700 xrc = seg;
e126ba97
EC		 2701 seg += sizeof(*xrc);
2702 size += sizeof(*xrc) / 16;
2703 /* fall through */
2704 case IB_QPT_RC:
2705 switch (wr->opcode) {
2706 case IB_WR_RDMA_READ:
2707 case IB_WR_RDMA_WRITE:
2708 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 2709 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
2710 rdma_wr(wr)->rkey);
f241e749 2711 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 2712 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2713 break;
2714
2715 case IB_WR_ATOMIC_CMP_AND_SWP:
2716 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 2717 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 2718 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2719 err = -ENOSYS;
2720 *bad_wr = wr;
2721 goto out;
e126ba97
EC		 2722
2723 case IB_WR_LOCAL_INV:
2724 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2725 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2726 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2727 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2728 if (err) {
2729 mlx5_ib_warn(dev, "\n");
2730 *bad_wr = wr;
2731 goto out;
2732 }
2733 num_sge = 0;
2734 break;
2735
2736 case IB_WR_FAST_REG_MR:
2737 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2738 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
e622f2f4 2739 ctrl->imm = cpu_to_be32(fast_reg_wr(wr)->rkey);
e126ba97
EC		 2740 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2741 if (err) {
2742 mlx5_ib_warn(dev, "\n");
2743 *bad_wr = wr;
2744 goto out;
2745 }
2746 num_sge = 0;
2747 break;
2748
8a187ee5
SG		 2749 case IB_WR_REG_MR:
2750 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2751 qp->sq.wr_data[idx] = IB_WR_REG_MR;
2752 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
2753 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
2754 if (err) {
2755 *bad_wr = wr;
2756 goto out;
2757 }
2758 num_sge = 0;
2759 break;
2760
e6631814
SG		 2761 case IB_WR_REG_SIG_MR:
2762 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 2763 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 2764
2765 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
2766 err = set_sig_umr_wr(wr, qp, &seg, &size);
2767 if (err) {
2768 mlx5_ib_warn(dev, "\n");
2769 *bad_wr = wr;
2770 goto out;
2771 }
2772
2773 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2774 nreq, get_fence(fence, wr),
2775 next_fence, MLX5_OPCODE_UMR);
2776 /*
2777 * SET_PSV WQEs are not signaled and solicited
2778 * on error
2779 */
2780 wr->send_flags &= ~IB_SEND_SIGNALED;
2781 wr->send_flags |= IB_SEND_SOLICITED;
2782 err = begin_wqe(qp, &seg, &ctrl, wr,
2783 &idx, &size, nreq);
2784 if (err) {
2785 mlx5_ib_warn(dev, "\n");
2786 err = -ENOMEM;
2787 *bad_wr = wr;
2788 goto out;
2789 }
2790
e622f2f4 2791 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 2792 mr->sig->psv_memory.psv_idx, &seg,
2793 &size);
2794 if (err) {
2795 mlx5_ib_warn(dev, "\n");
2796 *bad_wr = wr;
2797 goto out;
2798 }
2799
2800 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2801 nreq, get_fence(fence, wr),
2802 next_fence, MLX5_OPCODE_SET_PSV);
2803 err = begin_wqe(qp, &seg, &ctrl, wr,
2804 &idx, &size, nreq);
2805 if (err) {
2806 mlx5_ib_warn(dev, "\n");
2807 err = -ENOMEM;
2808 *bad_wr = wr;
2809 goto out;
2810 }
2811
2812 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 2813 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 2814 mr->sig->psv_wire.psv_idx, &seg,
2815 &size);
2816 if (err) {
2817 mlx5_ib_warn(dev, "\n");
2818 *bad_wr = wr;
2819 goto out;
2820 }
2821
2822 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2823 nreq, get_fence(fence, wr),
2824 next_fence, MLX5_OPCODE_SET_PSV);
2825 num_sge = 0;
2826 goto skip_psv;
2827
e126ba97
EC		 2828 default:
2829 break;
2830 }
2831 break;
2832
2833 case IB_QPT_UC:
2834 switch (wr->opcode) {
2835 case IB_WR_RDMA_WRITE:
2836 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 2837 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
2838 rdma_wr(wr)->rkey);
e126ba97
EC		 2839 seg += sizeof(struct mlx5_wqe_raddr_seg);
2840 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2841 break;
2842
2843 default:
2844 break;
2845 }
2846 break;
2847
2848 case IB_QPT_UD:
2849 case IB_QPT_SMI:
2850 case IB_QPT_GSI:
2851 set_datagram_seg(seg, wr);
f241e749 2852 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 2853 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2854 if (unlikely((seg == qend)))
2855 seg = mlx5_get_send_wqe(qp, 0);
2856 break;
2857
2858 case MLX5_IB_QPT_REG_UMR:
2859 if (wr->opcode != MLX5_IB_WR_UMR) {
2860 err = -EINVAL;
2861 mlx5_ib_warn(dev, "bad opcode\n");
2862 goto out;
2863 }
2864 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 2865 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 2866 set_reg_umr_segment(seg, wr);
2867 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2868 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2869 if (unlikely((seg == qend)))
2870 seg = mlx5_get_send_wqe(qp, 0);
2871 set_reg_mkey_segment(seg, wr);
2872 seg += sizeof(struct mlx5_mkey_seg);
2873 size += sizeof(struct mlx5_mkey_seg) / 16;
2874 if (unlikely((seg == qend)))
2875 seg = mlx5_get_send_wqe(qp, 0);
2876 break;
2877
2878 default:
2879 break;
2880 }
2881
2882 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2883 int uninitialized_var(sz);
2884
2885 err = set_data_inl_seg(qp, wr, seg, &sz);
2886 if (unlikely(err)) {
2887 mlx5_ib_warn(dev, "\n");
2888 *bad_wr = wr;
2889 goto out;
2890 }
2891 inl = 1;
2892 size += sz;
2893 } else {
2894 dpseg = seg;
2895 for (i = 0; i < num_sge; i++) {
2896 if (unlikely(dpseg == qend)) {
2897 seg = mlx5_get_send_wqe(qp, 0);
2898 dpseg = seg;
2899 }
2900 if (likely(wr->sg_list[i].length)) {
2901 set_data_ptr_seg(dpseg, wr->sg_list + i);
2902 size += sizeof(struct mlx5_wqe_data_seg) / 16;
2903 dpseg++;
2904 }
2905 }
2906 }
2907
6e5eadac
SG		 2908 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
2909 get_fence(fence, wr), next_fence,
2910 mlx5_ib_opcode[wr->opcode]);
e6631814 2911skip_psv:
e126ba97
EC		 2912 if (0)
2913 dump_wqe(qp, idx, size);
2914 }
2915
2916out:
2917 if (likely(nreq)) {
2918 qp->sq.head += nreq;
2919
2920 /* Make sure that descriptors are written before
2921 * updating doorbell record and ringing the doorbell
2922 */
2923 wmb();
2924
2925 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2926
ada388f7
EC		 2927 /* Make sure doorbell record is visible to the HCA before
2928 * we hit doorbell */
2929 wmb();
2930
e126ba97
EC		 2931 if (bf->need_lock)
2932 spin_lock(&bf->lock);
6a4f139a
EC		 2933 else
2934 __acquire(&bf->lock);
e126ba97
EC		 2935
2936 /* TBD enable WC */
2937 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2938 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2939 /* wc_wmb(); */
2940 } else {
2941 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2942 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2943 /* Make sure doorbells don't leak out of SQ spinlock
2944 * and reach the HCA out of order.
2945 */
2946 mmiowb();
2947 }
2948 bf->offset ^= bf->buf_size;
2949 if (bf->need_lock)
2950 spin_unlock(&bf->lock);
6a4f139a
EC		 2951 else
2952 __release(&bf->lock);
e126ba97
EC		 2953 }
2954
2955 spin_unlock_irqrestore(&qp->sq.lock, flags);
2956
2957 return err;
2958}
2959
2960static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2961{
2962 sig->signature = calc_sig(sig, size);
2963}
2964
2965int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2966 struct ib_recv_wr **bad_wr)
2967{
2968 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2969 struct mlx5_wqe_data_seg *scat;
2970 struct mlx5_rwqe_sig *sig;
2971 unsigned long flags;
2972 int err = 0;
2973 int nreq;
2974 int ind;
2975 int i;
2976
2977 spin_lock_irqsave(&qp->rq.lock, flags);
2978
2979 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2980
2981 for (nreq = 0; wr; nreq++, wr = wr->next) {
2982 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2983 err = -ENOMEM;
2984 *bad_wr = wr;
2985 goto out;
2986 }
2987
2988 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2989 err = -EINVAL;
2990 *bad_wr = wr;
2991 goto out;
2992 }
2993
2994 scat = get_recv_wqe(qp, ind);
2995 if (qp->wq_sig)
2996 scat++;
2997
2998 for (i = 0; i < wr->num_sge; i++)
2999 set_data_ptr_seg(scat + i, wr->sg_list + i);
3000
3001 if (i < qp->rq.max_gs) {
3002 scat[i].byte_count = 0;
3003 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
3004 scat[i].addr = 0;
3005 }
3006
3007 if (qp->wq_sig) {
3008 sig = (struct mlx5_rwqe_sig *)scat;
3009 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
3010 }
3011
3012 qp->rq.wrid[ind] = wr->wr_id;
3013
3014 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3015 }
3016
3017out:
3018 if (likely(nreq)) {
3019 qp->rq.head += nreq;
3020
3021 /* Make sure that descriptors are written before
3022 * doorbell record.
3023 */
3024 wmb();
3025
3026 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3027 }
3028
3029 spin_unlock_irqrestore(&qp->rq.lock, flags);
3030
3031 return err;
3032}
3033
3034static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
3035{
3036 switch (mlx5_state) {
3037 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
3038 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
3039 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
3040 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
3041 case MLX5_QP_STATE_SQ_DRAINING:
3042 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
3043 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
3044 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
3045 default: return -1;
3046 }
3047}
3048
3049static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3050{
3051 switch (mlx5_mig_state) {
3052 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
3053 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
3054 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3055 default: return -1;
3056 }
3057}
3058
3059static int to_ib_qp_access_flags(int mlx5_flags)
3060{
3061 int ib_flags = 0;
3062
3063 if (mlx5_flags & MLX5_QP_BIT_RRE)
3064 ib_flags |= IB_ACCESS_REMOTE_READ;
3065 if (mlx5_flags & MLX5_QP_BIT_RWE)
3066 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3067 if (mlx5_flags & MLX5_QP_BIT_RAE)
3068 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3069
3070 return ib_flags;
3071}
3072
3073static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3074 struct mlx5_qp_path *path)
3075{
9603b61d 3076 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 3077
3078 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3079 ib_ah_attr->port_num = path->port;
3080
c7a08ac7 3081 if (ib_ah_attr->port_num == 0 ||
938fe83c 3082 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 3083 return;
3084
3085 ib_ah_attr->sl = path->sl & 0xf;
3086
3087 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3088 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3089 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3090 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3091 if (ib_ah_attr->ah_flags) {
3092 ib_ah_attr->grh.sgid_index = path->mgid_index;
3093 ib_ah_attr->grh.hop_limit = path->hop_limit;
3094 ib_ah_attr->grh.traffic_class =
3095 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3096 ib_ah_attr->grh.flow_label =
3097 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3098 memcpy(ib_ah_attr->grh.dgid.raw,
3099 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3100 }
3101}
3102
3103int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3104 struct ib_qp_init_attr *qp_init_attr)
3105{
3106 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3107 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3108 struct mlx5_query_qp_mbox_out *outb;
3109 struct mlx5_qp_context *context;
3110 int mlx5_state;
3111 int err = 0;
3112
6aec21f6
HE		 3113#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3114 /*
3115 * Wait for any outstanding page faults, in case the user frees memory
3116 * based upon this query's result.
3117 */
3118 flush_workqueue(mlx5_ib_page_fault_wq);
3119#endif
3120
e126ba97
EC		 3121 mutex_lock(&qp->mutex);
3122 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
3123 if (!outb) {
3124 err = -ENOMEM;
3125 goto out;
3126 }
3127 context = &outb->ctx;
9603b61d 3128 err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb));
e126ba97
EC		 3129 if (err)
3130 goto out_free;
3131
3132 mlx5_state = be32_to_cpu(context->flags) >> 28;
3133
3134 qp->state = to_ib_qp_state(mlx5_state);
3135 qp_attr->qp_state = qp->state;
3136 qp_attr->path_mtu = context->mtu_msgmax >> 5;
3137 qp_attr->path_mig_state =
3138 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
3139 qp_attr->qkey = be32_to_cpu(context->qkey);
3140 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
3141 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
3142 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
3143 qp_attr->qp_access_flags =
3144 to_ib_qp_access_flags(be32_to_cpu(context->params2));
3145
3146 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3147 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
3148 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
3149 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
3150 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3151 }
3152
3153 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
3154 qp_attr->port_num = context->pri_path.port;
3155
3156 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3157 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
3158
3159 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
3160
3161 qp_attr->max_dest_rd_atomic =
3162 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
3163 qp_attr->min_rnr_timer =
3164 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
3165 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
3166 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
3167 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
3168 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
3169 qp_attr->cur_qp_state = qp_attr->qp_state;
3170 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3171 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3172
3173 if (!ibqp->uobject) {
3174 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3175 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3176 } else {
3177 qp_attr->cap.max_send_wr = 0;
3178 qp_attr->cap.max_send_sge = 0;
3179 }
3180
3181 /* We don't support inline sends for kernel QPs (yet), and we
3182 * don't know what userspace's value should be.
3183 */
3184 qp_attr->cap.max_inline_data = 0;
3185
3186 qp_init_attr->cap = qp_attr->cap;
3187
3188 qp_init_attr->create_flags = 0;
3189 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3190 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3191
3192 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
3193 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3194
3195out_free:
3196 kfree(outb);
3197
3198out:
3199 mutex_unlock(&qp->mutex);
3200 return err;
3201}
3202
3203struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
3204 struct ib_ucontext *context,
3205 struct ib_udata *udata)
3206{
3207 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3208 struct mlx5_ib_xrcd *xrcd;
3209 int err;
3210
938fe83c 3211 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 3212 return ERR_PTR(-ENOSYS);
3213
3214 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3215 if (!xrcd)
3216 return ERR_PTR(-ENOMEM);
3217
9603b61d 3218 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 3219 if (err) {
3220 kfree(xrcd);
3221 return ERR_PTR(-ENOMEM);
3222 }
3223
3224 return &xrcd->ibxrcd;
3225}
3226
3227int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3228{
3229 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3230 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3231 int err;
3232
9603b61d 3233 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 3234 if (err) {
3235 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3236 return err;
3237 }
3238
3239 kfree(xrcd);
3240
3241 return 0;
3242}
Linux kernel - Deliverables
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