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[deliverable/linux.git] / drivers / infiniband / hw / mthca / mthca_dev.h
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1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
99264c1e 4 * Copyright (c) 2005 Cisco Systems. All rights reserved.
2a1d9b7f
RD		 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
37 */
38
39#ifndef MTHCA_DEV_H
40#define MTHCA_DEV_H
41
42#include <linux/spinlock.h>
43#include <linux/kernel.h>
44#include <linux/pci.h>
45#include <linux/dma-mapping.h>
de25968c 46#include <linux/timer.h>
fd9cfdd1
RD		 47#include <linux/mutex.h>
48
1da177e4
LT		 49#include <asm/semaphore.h>
50
51#include "mthca_provider.h"
52#include "mthca_doorbell.h"
53
54#define DRV_NAME "ib_mthca"
55#define PFX DRV_NAME ": "
7d2babc4
RD		 56#define DRV_VERSION "0.07"
57#define DRV_RELDATE "February 13, 2006"
1da177e4 58
1da177e4
LT		 59enum {
60 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
61 MTHCA_FLAG_SRQ = 1 << 2,
62 MTHCA_FLAG_MSI = 1 << 3,
63 MTHCA_FLAG_MSI_X = 1 << 4,
e0f5fdca 64 MTHCA_FLAG_NO_LAM = 1 << 5,
68a3c212
RD		 65 MTHCA_FLAG_FMR = 1 << 6,
66 MTHCA_FLAG_MEMFREE = 1 << 7,
67 MTHCA_FLAG_PCIE = 1 << 8
1da177e4
LT		 68};
69
70enum {
71 MTHCA_MAX_PORTS = 2
72};
73
2e8b981c
MT		 74enum {
75 MTHCA_BOARD_ID_LEN = 64
76};
77
1da177e4
LT		 78enum {
79 MTHCA_EQ_CONTEXT_SIZE = 0x40,
80 MTHCA_CQ_CONTEXT_SIZE = 0x40,
81 MTHCA_QP_CONTEXT_SIZE = 0x200,
82 MTHCA_RDB_ENTRY_SIZE = 0x20,
83 MTHCA_AV_SIZE = 0x20,
84 MTHCA_MGM_ENTRY_SIZE = 0x40,
85
86 /* Arbel FW gives us these, but we need them for Tavor */
87 MTHCA_MPT_ENTRY_SIZE = 0x40,
88 MTHCA_MTT_SEG_SIZE = 0x40,
efaae8f7
JM		 89
90 MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
1da177e4
LT		 91};
92
93enum {
94 MTHCA_EQ_CMD,
95 MTHCA_EQ_ASYNC,
96 MTHCA_EQ_COMP,
97 MTHCA_NUM_EQ
98};
99
2a4443a6
MT		 100enum {
101 MTHCA_OPCODE_NOP = 0x00,
102 MTHCA_OPCODE_RDMA_WRITE = 0x08,
103 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
104 MTHCA_OPCODE_SEND = 0x0a,
105 MTHCA_OPCODE_SEND_IMM = 0x0b,
106 MTHCA_OPCODE_RDMA_READ = 0x10,
107 MTHCA_OPCODE_ATOMIC_CS = 0x11,
108 MTHCA_OPCODE_ATOMIC_FA = 0x12,
109 MTHCA_OPCODE_BIND_MW = 0x18,
110 MTHCA_OPCODE_INVALID = 0xff
111};
112
1da177e4 113struct mthca_cmd {
ed878458 114 struct pci_pool *pool;
1da177e4 115 int use_events;
fd9cfdd1 116 struct mutex hcr_mutex;
1da177e4
LT		 117 struct semaphore poll_sem;
118 struct semaphore event_sem;
119 int max_cmds;
120 spinlock_t context_lock;
121 int free_head;
122 struct mthca_cmd_context *context;
123 u16 token_mask;
124};
125
126struct mthca_limits {
127 int num_ports;
128 int vl_cap;
129 int mtu_cap;
130 int gid_table_len;
131 int pkey_table_len;
132 int local_ca_ack_delay;
133 int num_uars;
134 int max_sg;
135 int num_qps;
efaae8f7 136 int max_wqes;
77369ed3 137 int max_desc_sz;
efaae8f7 138 int max_qp_init_rdma;
1da177e4
LT		 139 int reserved_qps;
140 int num_srqs;
efaae8f7 141 int max_srq_wqes;
1da177e4
LT		 142 int reserved_srqs;
143 int num_eecs;
144 int reserved_eecs;
145 int num_cqs;
efaae8f7 146 int max_cqes;
1da177e4
LT		 147 int reserved_cqs;
148 int num_eqs;
149 int reserved_eqs;
150 int num_mpts;
151 int num_mtt_segs;
e0f5fdca 152 int fmr_reserved_mtts;
1da177e4
LT		 153 int reserved_mtts;
154 int reserved_mrws;
155 int reserved_uars;
156 int num_mgms;
157 int num_amgms;
158 int reserved_mcgs;
159 int num_pds;
160 int reserved_pds;
0f69ce1e 161 u32 page_size_cap;
33033b79 162 u32 flags;
da6561c2 163 u8 port_width_cap;
1da177e4
LT		 164};
165
166struct mthca_alloc {
167 u32 last;
168 u32 top;
169 u32 max;
170 u32 mask;
171 spinlock_t lock;
172 unsigned long *table;
173};
174
175struct mthca_array {
176 struct {
177 void **page;
178 int used;
179 } *page_list;
180};
181
182struct mthca_uar_table {
183 struct mthca_alloc alloc;
184 u64 uarc_base;
185 int uarc_size;
186};
187
188struct mthca_pd_table {
189 struct mthca_alloc alloc;
190};
191
9095e208
MT		 192struct mthca_buddy {
193 unsigned long **bits;
194 int max_order;
195 spinlock_t lock;
196};
197
1da177e4
LT		 198struct mthca_mr_table {
199 struct mthca_alloc mpt_alloc;
e0f5fdca
MT		 200 struct mthca_buddy mtt_buddy;
201 struct mthca_buddy *fmr_mtt_buddy;
1da177e4 202 u64 mtt_base;
e0f5fdca 203 u64 mpt_base;
1da177e4
LT		 204 struct mthca_icm_table *mtt_table;
205 struct mthca_icm_table *mpt_table;
e0f5fdca
MT		 206 struct {
207 void __iomem *mpt_base;
208 void __iomem *mtt_base;
209 struct mthca_buddy mtt_buddy;
210 } tavor_fmr;
1da177e4
LT		 211};
212
213struct mthca_eq_table {
214 struct mthca_alloc alloc;
215 void __iomem *clr_int;
216 u32 clr_mask;
217 u32 arm_mask;
218 struct mthca_eq eq[MTHCA_NUM_EQ];
219 u64 icm_virt;
220 struct page *icm_page;
221 dma_addr_t icm_dma;
222 int have_irq;
223 u8 inta_pin;
224};
225
226struct mthca_cq_table {
227 struct mthca_alloc alloc;
228 spinlock_t lock;
229 struct mthca_array cq;
230 struct mthca_icm_table *table;
231};
232
ec34a922
RD		 233struct mthca_srq_table {
234 struct mthca_alloc alloc;
235 spinlock_t lock;
236 struct mthca_array srq;
237 struct mthca_icm_table *table;
238};
239
1da177e4
LT		 240struct mthca_qp_table {
241 struct mthca_alloc alloc;
242 u32 rdb_base;
243 int rdb_shift;
244 int sqp_start;
245 spinlock_t lock;
246 struct mthca_array qp;
247 struct mthca_icm_table *qp_table;
248 struct mthca_icm_table *eqp_table;
08aeb14e 249 struct mthca_icm_table *rdb_table;
1da177e4
LT		 250};
251
252struct mthca_av_table {
253 struct pci_pool *pool;
254 int num_ddr_avs;
255 u64 ddr_av_base;
256 void __iomem *av_map;
257 struct mthca_alloc alloc;
258};
259
260struct mthca_mcg_table {
fd9cfdd1 261 struct mutex mutex;
1da177e4
LT		 262 struct mthca_alloc alloc;
263 struct mthca_icm_table *table;
264};
265
3d155f8c
RD		 266struct mthca_catas_err {
267 u64 addr;
268 u32 __iomem *map;
269 unsigned long stop;
270 u32 size;
271 struct timer_list timer;
272};
273
1da177e4
LT		 274struct mthca_dev {
275 struct ib_device ib_dev;
276 struct pci_dev *pdev;
277
278 int hca_type;
279 unsigned long mthca_flags;
280 unsigned long device_cap_flags;
281
282 u32 rev_id;
2e8b981c 283 char board_id[MTHCA_BOARD_ID_LEN];
1da177e4
LT		 284
285 /* firmware info */
286 u64 fw_ver;
287 union {
288 struct {
289 u64 fw_start;
290 u64 fw_end;
291 } tavor;
292 struct {
293 u64 clr_int_base;
294 u64 eq_arm_base;
295 u64 eq_set_ci_base;
296 struct mthca_icm *fw_icm;
297 struct mthca_icm *aux_icm;
298 u16 fw_pages;
299 } arbel;
300 } fw;
301
302 u64 ddr_start;
303 u64 ddr_end;
304
305 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
fd9cfdd1 306 struct mutex cap_mask_mutex;
1da177e4
LT		 307
308 void __iomem *hcr;
309 void __iomem *kar;
310 void __iomem *clr_base;
311 union {
312 struct {
313 void __iomem *ecr_base;
314 } tavor;
315 struct {
316 void __iomem *eq_arm;
317 void __iomem *eq_set_ci_base;
318 } arbel;
319 } eq_regs;
320
321 struct mthca_cmd cmd;
322 struct mthca_limits limits;
323
324 struct mthca_uar_table uar_table;
325 struct mthca_pd_table pd_table;
326 struct mthca_mr_table mr_table;
327 struct mthca_eq_table eq_table;
328 struct mthca_cq_table cq_table;
ec34a922 329 struct mthca_srq_table srq_table;
1da177e4
LT		 330 struct mthca_qp_table qp_table;
331 struct mthca_av_table av_table;
332 struct mthca_mcg_table mcg_table;
333
3d155f8c
RD		 334 struct mthca_catas_err catas_err;
335
1da177e4
LT		 336 struct mthca_uar driver_uar;
337 struct mthca_db_table *db_tab;
338 struct mthca_pd driver_pd;
339 struct mthca_mr driver_mr;
340
341 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
342 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
343 spinlock_t sm_lock;
344};
345
346#define mthca_dbg(mdev, format, arg...) \
347 dev_dbg(&mdev->pdev->dev, format, ## arg)
348#define mthca_err(mdev, format, arg...) \
349 dev_err(&mdev->pdev->dev, format, ## arg)
350#define mthca_info(mdev, format, arg...) \
351 dev_info(&mdev->pdev->dev, format, ## arg)
352#define mthca_warn(mdev, format, arg...) \
353 dev_warn(&mdev->pdev->dev, format, ## arg)
354
355extern void __buggy_use_of_MTHCA_GET(void);
356extern void __buggy_use_of_MTHCA_PUT(void);
357
358#define MTHCA_GET(dest, source, offset) \
359 do { \
360 void *__p = (char *) (source) + (offset); \
361 switch (sizeof (dest)) { \
362 case 1: (dest) = *(u8 *) __p; break; \
363 case 2: (dest) = be16_to_cpup(__p); break; \
364 case 4: (dest) = be32_to_cpup(__p); break; \
365 case 8: (dest) = be64_to_cpup(__p); break; \
366 default: __buggy_use_of_MTHCA_GET(); \
367 } \
368 } while (0)
369
370#define MTHCA_PUT(dest, source, offset) \
371 do { \
97f52eb4 372 void *__d = ((char *) (dest) + (offset)); \
1da177e4 373 switch (sizeof(source)) { \
97f52eb4
SH		 374 case 1: *(u8 *) __d = (source); break; \
375 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
376 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
377 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
378 default: __buggy_use_of_MTHCA_PUT(); \
1da177e4
LT		 379 } \
380 } while (0)
381
382int mthca_reset(struct mthca_dev *mdev);
383
384u32 mthca_alloc(struct mthca_alloc *alloc);
385void mthca_free(struct mthca_alloc *alloc, u32 obj);
386int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
387 u32 reserved);
388void mthca_alloc_cleanup(struct mthca_alloc *alloc);
389void *mthca_array_get(struct mthca_array *array, int index);
390int mthca_array_set(struct mthca_array *array, int index, void *value);
391void mthca_array_clear(struct mthca_array *array, int index);
392int mthca_array_init(struct mthca_array *array, int nent);
393void mthca_array_cleanup(struct mthca_array *array, int nent);
87b81670
RD		 394int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
395 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
396 int hca_write, struct mthca_mr *mr);
397void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
398 int is_direct, struct mthca_mr *mr);
1da177e4
LT		 399
400int mthca_init_uar_table(struct mthca_dev *dev);
401int mthca_init_pd_table(struct mthca_dev *dev);
402int mthca_init_mr_table(struct mthca_dev *dev);
403int mthca_init_eq_table(struct mthca_dev *dev);
404int mthca_init_cq_table(struct mthca_dev *dev);
ec34a922 405int mthca_init_srq_table(struct mthca_dev *dev);
1da177e4
LT		 406int mthca_init_qp_table(struct mthca_dev *dev);
407int mthca_init_av_table(struct mthca_dev *dev);
408int mthca_init_mcg_table(struct mthca_dev *dev);
409
410void mthca_cleanup_uar_table(struct mthca_dev *dev);
411void mthca_cleanup_pd_table(struct mthca_dev *dev);
412void mthca_cleanup_mr_table(struct mthca_dev *dev);
413void mthca_cleanup_eq_table(struct mthca_dev *dev);
414void mthca_cleanup_cq_table(struct mthca_dev *dev);
ec34a922 415void mthca_cleanup_srq_table(struct mthca_dev *dev);
1da177e4
LT		 416void mthca_cleanup_qp_table(struct mthca_dev *dev);
417void mthca_cleanup_av_table(struct mthca_dev *dev);
418void mthca_cleanup_mcg_table(struct mthca_dev *dev);
419
420int mthca_register_device(struct mthca_dev *dev);
421void mthca_unregister_device(struct mthca_dev *dev);
422
3d155f8c
RD		 423void mthca_start_catas_poll(struct mthca_dev *dev);
424void mthca_stop_catas_poll(struct mthca_dev *dev);
425
1da177e4
LT		 426int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
427void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
428
99264c1e 429int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
1da177e4
LT		 430void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
431
d56d6f95
RD		 432struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
433void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
434int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
435 int start_index, u64 *buffer_list, int list_len);
436int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
437 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
1da177e4
LT		 438int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
439 u32 access, struct mthca_mr *mr);
440int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
441 u64 *buffer_list, int buffer_size_shift,
442 int list_len, u64 iova, u64 total_size,
443 u32 access, struct mthca_mr *mr);
e0f5fdca
MT		 444void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
445
446int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
447 u32 access, struct mthca_fmr *fmr);
448int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
449 int list_len, u64 iova);
450void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
451int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
452 int list_len, u64 iova);
453void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
454int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
1da177e4
LT		 455
456int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
457void mthca_unmap_eq_icm(struct mthca_dev *dev);
458
459int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
460 struct ib_wc *entry);
461int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
462int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
463int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e 464 struct mthca_ucontext *ctx, u32 pdn,
1da177e4
LT		 465 struct mthca_cq *cq);
466void mthca_free_cq(struct mthca_dev *dev,
467 struct mthca_cq *cq);
affcd505
MT		 468void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
469void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
470 enum ib_event_type event_type);
ec34a922
RD		 471void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
472 struct mthca_srq *srq);
473
474int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
475 struct ib_srq_attr *attr, struct mthca_srq *srq);
476void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
90f104da
RD		 477int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
478 enum ib_srq_attr_mask attr_mask);
ec34a922
RD		 479void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
480 enum ib_event_type event_type);
481void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
482int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
483 struct ib_recv_wr **bad_wr);
484int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
485 struct ib_recv_wr **bad_wr);
1da177e4
LT		 486
487void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
488 enum ib_event_type event_type);
489int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
490int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
491 struct ib_send_wr **bad_wr);
492int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
493 struct ib_recv_wr **bad_wr);
494int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
495 struct ib_send_wr **bad_wr);
496int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
497 struct ib_recv_wr **bad_wr);
498int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
97f52eb4 499 int index, int *dbd, __be32 *new_wqe);
1da177e4
LT		 500int mthca_alloc_qp(struct mthca_dev *dev,
501 struct mthca_pd *pd,
502 struct mthca_cq *send_cq,
503 struct mthca_cq *recv_cq,
504 enum ib_qp_type type,
505 enum ib_sig_type send_policy,
80c8ec2c 506 struct ib_qp_cap *cap,
1da177e4
LT		 507 struct mthca_qp *qp);
508int mthca_alloc_sqp(struct mthca_dev *dev,
509 struct mthca_pd *pd,
510 struct mthca_cq *send_cq,
511 struct mthca_cq *recv_cq,
512 enum ib_sig_type send_policy,
80c8ec2c 513 struct ib_qp_cap *cap,
1da177e4
LT		 514 int qpn,
515 int port,
516 struct mthca_sqp *sqp);
517void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
518int mthca_create_ah(struct mthca_dev *dev,
519 struct mthca_pd *pd,
520 struct ib_ah_attr *ah_attr,
521 struct mthca_ah *ah);
522int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
523int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
524 struct ib_ud_header *header);
9eacee2a 525int mthca_ah_grh_present(struct mthca_ah *ah);
1da177e4
LT		 526
527int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
528int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
529
530int mthca_process_mad(struct ib_device *ibdev,
531 int mad_flags,
532 u8 port_num,
533 struct ib_wc *in_wc,
534 struct ib_grh *in_grh,
535 struct ib_mad *in_mad,
536 struct ib_mad *out_mad);
537int mthca_create_agents(struct mthca_dev *dev);
538void mthca_free_agents(struct mthca_dev *dev);
539
540static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
541{
542 return container_of(ibdev, struct mthca_dev, ib_dev);
543}
544
d10ddbf6
RD		 545static inline int mthca_is_memfree(struct mthca_dev *dev)
546{
68a3c212 547 return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
d10ddbf6
RD		 548}
549
1da177e4 550#endif /* MTHCA_DEV_H */
Linux kernel - Deliverables
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