Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
cd4e8fb4 | 3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. |
2a1d9b7f | 4 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
1da177e4 LT |
33 | */ |
34 | ||
1da177e4 LT |
35 | #include <linux/module.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/interrupt.h> | |
5a0e3ad6 | 40 | #include <linux/gfp.h> |
1da177e4 LT |
41 | |
42 | #include "mthca_dev.h" | |
43 | #include "mthca_config_reg.h" | |
44 | #include "mthca_cmd.h" | |
45 | #include "mthca_profile.h" | |
46 | #include "mthca_memfree.h" | |
12103dca | 47 | #include "mthca_wqe.h" |
1da177e4 LT |
48 | |
49 | MODULE_AUTHOR("Roland Dreier"); | |
50 | MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver"); | |
51 | MODULE_LICENSE("Dual BSD/GPL"); | |
52 | MODULE_VERSION(DRV_VERSION); | |
53 | ||
227c939b RD |
54 | #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG |
55 | ||
56 | int mthca_debug_level = 0; | |
57 | module_param_named(debug_level, mthca_debug_level, int, 0644); | |
58 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
59 | ||
60 | #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */ | |
61 | ||
1da177e4 LT |
62 | #ifdef CONFIG_PCI_MSI |
63 | ||
017aadc4 | 64 | static int msi_x = 1; |
1da177e4 LT |
65 | module_param(msi_x, int, 0444); |
66 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
67 | ||
1da177e4 LT |
68 | #else /* CONFIG_PCI_MSI */ |
69 | ||
70 | #define msi_x (0) | |
1da177e4 LT |
71 | |
72 | #endif /* CONFIG_PCI_MSI */ | |
73 | ||
abf45dbb MT |
74 | static int tune_pci = 0; |
75 | module_param(tune_pci, int, 0444); | |
76 | MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero"); | |
77 | ||
0b0df6f2 | 78 | DEFINE_MUTEX(mthca_device_mutex); |
b3b30f5e | 79 | |
82da703e LA |
80 | #define MTHCA_DEFAULT_NUM_QP (1 << 16) |
81 | #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2) | |
82 | #define MTHCA_DEFAULT_NUM_CQ (1 << 16) | |
83 | #define MTHCA_DEFAULT_NUM_MCG (1 << 13) | |
84 | #define MTHCA_DEFAULT_NUM_MPT (1 << 17) | |
85 | #define MTHCA_DEFAULT_NUM_MTT (1 << 20) | |
86 | #define MTHCA_DEFAULT_NUM_UDAV (1 << 15) | |
87 | #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18) | |
88 | #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18) | |
89 | ||
90 | static struct mthca_profile hca_profile = { | |
91 | .num_qp = MTHCA_DEFAULT_NUM_QP, | |
92 | .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP, | |
93 | .num_cq = MTHCA_DEFAULT_NUM_CQ, | |
94 | .num_mcg = MTHCA_DEFAULT_NUM_MCG, | |
95 | .num_mpt = MTHCA_DEFAULT_NUM_MPT, | |
96 | .num_mtt = MTHCA_DEFAULT_NUM_MTT, | |
97 | .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */ | |
98 | .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */ | |
99 | .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */ | |
100 | }; | |
101 | ||
102 | module_param_named(num_qp, hca_profile.num_qp, int, 0444); | |
103 | MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA"); | |
104 | ||
105 | module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444); | |
106 | MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP"); | |
107 | ||
108 | module_param_named(num_cq, hca_profile.num_cq, int, 0444); | |
109 | MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA"); | |
110 | ||
111 | module_param_named(num_mcg, hca_profile.num_mcg, int, 0444); | |
112 | MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA"); | |
113 | ||
114 | module_param_named(num_mpt, hca_profile.num_mpt, int, 0444); | |
115 | MODULE_PARM_DESC(num_mpt, | |
116 | "maximum number of memory protection table entries per HCA"); | |
117 | ||
118 | module_param_named(num_mtt, hca_profile.num_mtt, int, 0444); | |
119 | MODULE_PARM_DESC(num_mtt, | |
120 | "maximum number of memory translation table segments per HCA"); | |
121 | ||
122 | module_param_named(num_udav, hca_profile.num_udav, int, 0444); | |
123 | MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA"); | |
124 | ||
125 | module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444); | |
126 | MODULE_PARM_DESC(fmr_reserved_mtts, | |
127 | "number of memory translation table segments reserved for FMR"); | |
128 | ||
c1f67a88 EC |
129 | static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8); |
130 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); | |
131 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)"); | |
132 | ||
1e6d9abe | 133 | static char mthca_version[] = |
177214af | 134 | DRV_NAME ": Mellanox InfiniBand HCA driver v" |
1da177e4 LT |
135 | DRV_VERSION " (" DRV_RELDATE ")\n"; |
136 | ||
f4f3d0f0 | 137 | static int mthca_tune_pci(struct mthca_dev *mdev) |
1da177e4 | 138 | { |
abf45dbb MT |
139 | if (!tune_pci) |
140 | return 0; | |
141 | ||
1da177e4 | 142 | /* First try to max out Read Byte Count */ |
a855b1a7 PO |
143 | if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) { |
144 | if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) { | |
145 | mthca_err(mdev, "Couldn't set PCI-X max read count, " | |
146 | "aborting.\n"); | |
1da177e4 LT |
147 | return -ENODEV; |
148 | } | |
68a3c212 | 149 | } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE)) |
1da177e4 LT |
150 | mthca_info(mdev, "No PCI-X capability, not setting RBC.\n"); |
151 | ||
9b89925c | 152 | if (pci_is_pcie(mdev->pdev)) { |
a855b1a7 PO |
153 | if (pcie_set_readrq(mdev->pdev, 4096)) { |
154 | mthca_err(mdev, "Couldn't write PCI Express read request, " | |
155 | "aborting.\n"); | |
1da177e4 LT |
156 | return -ENODEV; |
157 | } | |
68a3c212 | 158 | } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE) |
1da177e4 LT |
159 | mthca_info(mdev, "No PCI Express capability, " |
160 | "not setting Max Read Request Size.\n"); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
f4f3d0f0 | 165 | static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim) |
1da177e4 LT |
166 | { |
167 | int err; | |
1da177e4 | 168 | |
c1f67a88 | 169 | mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8; |
cdb73db0 | 170 | err = mthca_QUERY_DEV_LIM(mdev, dev_lim); |
1da177e4 | 171 | if (err) { |
cdb73db0 GR |
172 | mthca_err(mdev, "QUERY_DEV_LIM command returned %d" |
173 | ", aborting.\n", err); | |
1da177e4 LT |
174 | return err; |
175 | } | |
1da177e4 LT |
176 | if (dev_lim->min_page_sz > PAGE_SIZE) { |
177 | mthca_err(mdev, "HCA minimum page size of %d bigger than " | |
178 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
179 | dev_lim->min_page_sz, PAGE_SIZE); | |
180 | return -ENODEV; | |
181 | } | |
182 | if (dev_lim->num_ports > MTHCA_MAX_PORTS) { | |
183 | mthca_err(mdev, "HCA has %d ports, but we only support %d, " | |
184 | "aborting.\n", | |
185 | dev_lim->num_ports, MTHCA_MAX_PORTS); | |
186 | return -ENODEV; | |
187 | } | |
188 | ||
cbd2981a MT |
189 | if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) { |
190 | mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than " | |
e29419ff GKH |
191 | "PCI resource 2 size of 0x%llx, aborting.\n", |
192 | dev_lim->uar_size, | |
193 | (unsigned long long)pci_resource_len(mdev->pdev, 2)); | |
cbd2981a MT |
194 | return -ENODEV; |
195 | } | |
196 | ||
1da177e4 LT |
197 | mdev->limits.num_ports = dev_lim->num_ports; |
198 | mdev->limits.vl_cap = dev_lim->max_vl; | |
199 | mdev->limits.mtu_cap = dev_lim->max_mtu; | |
200 | mdev->limits.gid_table_len = dev_lim->max_gids; | |
201 | mdev->limits.pkey_table_len = dev_lim->max_pkeys; | |
202 | mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay; | |
12103dca RD |
203 | /* |
204 | * Need to allow for worst case send WQE overhead and check | |
205 | * whether max_desc_sz imposes a lower limit than max_sg; UD | |
206 | * send has the biggest overhead. | |
207 | */ | |
208 | mdev->limits.max_sg = min_t(int, dev_lim->max_sg, | |
209 | (dev_lim->max_desc_sz - | |
210 | sizeof (struct mthca_next_seg) - | |
211 | (mthca_is_memfree(mdev) ? | |
212 | sizeof (struct mthca_arbel_ud_seg) : | |
213 | sizeof (struct mthca_tavor_ud_seg))) / | |
214 | sizeof (struct mthca_data_seg)); | |
efaae8f7 JM |
215 | mdev->limits.max_wqes = dev_lim->max_qp_sz; |
216 | mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp; | |
1da177e4 | 217 | mdev->limits.reserved_qps = dev_lim->reserved_qps; |
efaae8f7 | 218 | mdev->limits.max_srq_wqes = dev_lim->max_srq_sz; |
1da177e4 LT |
219 | mdev->limits.reserved_srqs = dev_lim->reserved_srqs; |
220 | mdev->limits.reserved_eecs = dev_lim->reserved_eecs; | |
77369ed3 | 221 | mdev->limits.max_desc_sz = dev_lim->max_desc_sz; |
59fef3b1 | 222 | mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev); |
efaae8f7 JM |
223 | /* |
224 | * Subtract 1 from the limit because we need to allocate a | |
225 | * spare CQE so the HCA HW can tell the difference between an | |
226 | * empty CQ and a full CQ. | |
227 | */ | |
228 | mdev->limits.max_cqes = dev_lim->max_cq_sz - 1; | |
1da177e4 LT |
229 | mdev->limits.reserved_cqs = dev_lim->reserved_cqs; |
230 | mdev->limits.reserved_eqs = dev_lim->reserved_eqs; | |
231 | mdev->limits.reserved_mtts = dev_lim->reserved_mtts; | |
232 | mdev->limits.reserved_mrws = dev_lim->reserved_mrws; | |
233 | mdev->limits.reserved_uars = dev_lim->reserved_uars; | |
234 | mdev->limits.reserved_pds = dev_lim->reserved_pds; | |
da6561c2 | 235 | mdev->limits.port_width_cap = dev_lim->max_port_width; |
0f69ce1e | 236 | mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1); |
33033b79 | 237 | mdev->limits.flags = dev_lim->flags; |
bf6a9e31 JM |
238 | /* |
239 | * For old FW that doesn't return static rate support, use a | |
240 | * value of 0x3 (only static rate values of 0 or 1 are handled), | |
241 | * except on Sinai, where even old FW can handle static rate | |
242 | * values of 2 and 3. | |
243 | */ | |
244 | if (dev_lim->stat_rate_support) | |
245 | mdev->limits.stat_rate_support = dev_lim->stat_rate_support; | |
246 | else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT) | |
247 | mdev->limits.stat_rate_support = 0xf; | |
248 | else | |
249 | mdev->limits.stat_rate_support = 0x3; | |
1da177e4 LT |
250 | |
251 | /* IB_DEVICE_RESIZE_MAX_WR not supported by driver. | |
252 | May be doable since hardware supports it for SRQ. | |
253 | ||
254 | IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver. | |
255 | ||
256 | IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not | |
257 | supported by driver. */ | |
258 | mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | | |
259 | IB_DEVICE_PORT_ACTIVE_EVENT | | |
260 | IB_DEVICE_SYS_IMAGE_GUID | | |
261 | IB_DEVICE_RC_RNR_NAK_GEN; | |
262 | ||
263 | if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR) | |
264 | mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; | |
265 | ||
266 | if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR) | |
267 | mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; | |
268 | ||
269 | if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI) | |
270 | mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI; | |
271 | ||
272 | if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG) | |
273 | mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; | |
274 | ||
275 | if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE) | |
276 | mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; | |
277 | ||
278 | if (dev_lim->flags & DEV_LIM_FLAG_SRQ) | |
279 | mdev->mthca_flags |= MTHCA_FLAG_SRQ; | |
280 | ||
680b575f EC |
281 | if (mthca_is_memfree(mdev)) |
282 | if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM) | |
283 | mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; | |
284 | ||
1da177e4 LT |
285 | return 0; |
286 | } | |
287 | ||
f4f3d0f0 | 288 | static int mthca_init_tavor(struct mthca_dev *mdev) |
1da177e4 | 289 | { |
19773539 | 290 | s64 size; |
1da177e4 LT |
291 | int err; |
292 | struct mthca_dev_lim dev_lim; | |
293 | struct mthca_profile profile; | |
294 | struct mthca_init_hca_param init_hca; | |
1da177e4 | 295 | |
cdb73db0 | 296 | err = mthca_SYS_EN(mdev); |
1da177e4 | 297 | if (err) { |
cdb73db0 | 298 | mthca_err(mdev, "SYS_EN command returned %d, aborting.\n", err); |
1da177e4 LT |
299 | return err; |
300 | } | |
1da177e4 | 301 | |
cdb73db0 | 302 | err = mthca_QUERY_FW(mdev); |
1da177e4 | 303 | if (err) { |
cdb73db0 GR |
304 | mthca_err(mdev, "QUERY_FW command returned %d," |
305 | " aborting.\n", err); | |
1da177e4 LT |
306 | goto err_disable; |
307 | } | |
cdb73db0 | 308 | err = mthca_QUERY_DDR(mdev); |
1da177e4 | 309 | if (err) { |
cdb73db0 | 310 | mthca_err(mdev, "QUERY_DDR command returned %d, aborting.\n", err); |
1da177e4 LT |
311 | goto err_disable; |
312 | } | |
313 | ||
314 | err = mthca_dev_lim(mdev, &dev_lim); | |
aa2f9367 | 315 | if (err) { |
cdb73db0 | 316 | mthca_err(mdev, "QUERY_DEV_LIM command returned %d, aborting.\n", err); |
aa2f9367 JM |
317 | goto err_disable; |
318 | } | |
1da177e4 | 319 | |
82da703e | 320 | profile = hca_profile; |
1da177e4 LT |
321 | profile.num_uar = dev_lim.uar_size / PAGE_SIZE; |
322 | profile.uarc_size = 0; | |
ec34a922 RD |
323 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) |
324 | profile.num_srq = dev_lim.max_srqs; | |
1da177e4 | 325 | |
19773539 RD |
326 | size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca); |
327 | if (size < 0) { | |
328 | err = size; | |
1da177e4 | 329 | goto err_disable; |
19773539 | 330 | } |
1da177e4 | 331 | |
cdb73db0 | 332 | err = mthca_INIT_HCA(mdev, &init_hca); |
1da177e4 | 333 | if (err) { |
cdb73db0 | 334 | mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err); |
1da177e4 LT |
335 | goto err_disable; |
336 | } | |
337 | ||
1da177e4 LT |
338 | return 0; |
339 | ||
1da177e4 | 340 | err_disable: |
cdb73db0 | 341 | mthca_SYS_DIS(mdev); |
1da177e4 LT |
342 | |
343 | return err; | |
344 | } | |
345 | ||
f4f3d0f0 | 346 | static int mthca_load_fw(struct mthca_dev *mdev) |
1da177e4 | 347 | { |
1da177e4 LT |
348 | int err; |
349 | ||
350 | /* FIXME: use HCA-attached memory for FW if present */ | |
351 | ||
352 | mdev->fw.arbel.fw_icm = | |
353 | mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages, | |
391e4dea | 354 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
1da177e4 LT |
355 | if (!mdev->fw.arbel.fw_icm) { |
356 | mthca_err(mdev, "Couldn't allocate FW area, aborting.\n"); | |
357 | return -ENOMEM; | |
358 | } | |
359 | ||
cdb73db0 | 360 | err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm); |
1da177e4 | 361 | if (err) { |
cdb73db0 | 362 | mthca_err(mdev, "MAP_FA command returned %d, aborting.\n", err); |
1da177e4 LT |
363 | goto err_free; |
364 | } | |
cdb73db0 | 365 | err = mthca_RUN_FW(mdev); |
1da177e4 | 366 | if (err) { |
cdb73db0 | 367 | mthca_err(mdev, "RUN_FW command returned %d, aborting.\n", err); |
1da177e4 LT |
368 | goto err_unmap_fa; |
369 | } | |
370 | ||
371 | return 0; | |
372 | ||
373 | err_unmap_fa: | |
cdb73db0 | 374 | mthca_UNMAP_FA(mdev); |
1da177e4 LT |
375 | |
376 | err_free: | |
391e4dea | 377 | mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0); |
1da177e4 LT |
378 | return err; |
379 | } | |
380 | ||
f4f3d0f0 RD |
381 | static int mthca_init_icm(struct mthca_dev *mdev, |
382 | struct mthca_dev_lim *dev_lim, | |
383 | struct mthca_init_hca_param *init_hca, | |
384 | u64 icm_size) | |
1da177e4 LT |
385 | { |
386 | u64 aux_pages; | |
1da177e4 LT |
387 | int err; |
388 | ||
cdb73db0 | 389 | err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages); |
1da177e4 | 390 | if (err) { |
cdb73db0 | 391 | mthca_err(mdev, "SET_ICM_SIZE command returned %d, aborting.\n", err); |
1da177e4 LT |
392 | return err; |
393 | } | |
1da177e4 LT |
394 | |
395 | mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n", | |
396 | (unsigned long long) icm_size >> 10, | |
397 | (unsigned long long) aux_pages << 2); | |
398 | ||
399 | mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages, | |
391e4dea | 400 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
1da177e4 LT |
401 | if (!mdev->fw.arbel.aux_icm) { |
402 | mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n"); | |
403 | return -ENOMEM; | |
404 | } | |
405 | ||
cdb73db0 | 406 | err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm); |
1da177e4 | 407 | if (err) { |
cdb73db0 | 408 | mthca_err(mdev, "MAP_ICM_AUX returned %d, aborting.\n", err); |
1da177e4 LT |
409 | goto err_free_aux; |
410 | } | |
411 | ||
412 | err = mthca_map_eq_icm(mdev, init_hca->eqc_base); | |
413 | if (err) { | |
414 | mthca_err(mdev, "Failed to map EQ context memory, aborting.\n"); | |
415 | goto err_unmap_aux; | |
416 | } | |
417 | ||
1d1f19cf | 418 | /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */ |
c1f67a88 EC |
419 | mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size, |
420 | dma_get_cache_alignment()) / mdev->limits.mtt_seg_size; | |
1d1f19cf | 421 | |
1da177e4 | 422 | mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base, |
c1f67a88 | 423 | mdev->limits.mtt_seg_size, |
1da177e4 | 424 | mdev->limits.num_mtt_segs, |
391e4dea MT |
425 | mdev->limits.reserved_mtts, |
426 | 1, 0); | |
1da177e4 LT |
427 | if (!mdev->mr_table.mtt_table) { |
428 | mthca_err(mdev, "Failed to map MTT context memory, aborting.\n"); | |
429 | err = -ENOMEM; | |
430 | goto err_unmap_eq; | |
431 | } | |
432 | ||
433 | mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base, | |
434 | dev_lim->mpt_entry_sz, | |
435 | mdev->limits.num_mpts, | |
391e4dea MT |
436 | mdev->limits.reserved_mrws, |
437 | 1, 1); | |
1da177e4 LT |
438 | if (!mdev->mr_table.mpt_table) { |
439 | mthca_err(mdev, "Failed to map MPT context memory, aborting.\n"); | |
440 | err = -ENOMEM; | |
441 | goto err_unmap_mtt; | |
442 | } | |
443 | ||
444 | mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base, | |
445 | dev_lim->qpc_entry_sz, | |
446 | mdev->limits.num_qps, | |
391e4dea MT |
447 | mdev->limits.reserved_qps, |
448 | 0, 0); | |
1da177e4 LT |
449 | if (!mdev->qp_table.qp_table) { |
450 | mthca_err(mdev, "Failed to map QP context memory, aborting.\n"); | |
451 | err = -ENOMEM; | |
452 | goto err_unmap_mpt; | |
453 | } | |
454 | ||
455 | mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base, | |
456 | dev_lim->eqpc_entry_sz, | |
457 | mdev->limits.num_qps, | |
391e4dea MT |
458 | mdev->limits.reserved_qps, |
459 | 0, 0); | |
1da177e4 LT |
460 | if (!mdev->qp_table.eqp_table) { |
461 | mthca_err(mdev, "Failed to map EQP context memory, aborting.\n"); | |
462 | err = -ENOMEM; | |
463 | goto err_unmap_qp; | |
464 | } | |
465 | ||
08aeb14e RD |
466 | mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base, |
467 | MTHCA_RDB_ENTRY_SIZE, | |
468 | mdev->limits.num_qps << | |
391e4dea | 469 | mdev->qp_table.rdb_shift, 0, |
08aeb14e RD |
470 | 0, 0); |
471 | if (!mdev->qp_table.rdb_table) { | |
472 | mthca_err(mdev, "Failed to map RDB context memory, aborting\n"); | |
473 | err = -ENOMEM; | |
19272d43 | 474 | goto err_unmap_eqp; |
08aeb14e RD |
475 | } |
476 | ||
477 | mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base, | |
ec34a922 RD |
478 | dev_lim->cqc_entry_sz, |
479 | mdev->limits.num_cqs, | |
391e4dea MT |
480 | mdev->limits.reserved_cqs, |
481 | 0, 0); | |
1da177e4 LT |
482 | if (!mdev->cq_table.table) { |
483 | mthca_err(mdev, "Failed to map CQ context memory, aborting.\n"); | |
484 | err = -ENOMEM; | |
08aeb14e | 485 | goto err_unmap_rdb; |
1da177e4 LT |
486 | } |
487 | ||
ec34a922 RD |
488 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) { |
489 | mdev->srq_table.table = | |
490 | mthca_alloc_icm_table(mdev, init_hca->srqc_base, | |
491 | dev_lim->srq_entry_sz, | |
492 | mdev->limits.num_srqs, | |
391e4dea MT |
493 | mdev->limits.reserved_srqs, |
494 | 0, 0); | |
ec34a922 RD |
495 | if (!mdev->srq_table.table) { |
496 | mthca_err(mdev, "Failed to map SRQ context memory, " | |
497 | "aborting.\n"); | |
498 | err = -ENOMEM; | |
499 | goto err_unmap_cq; | |
500 | } | |
501 | } | |
502 | ||
1da177e4 LT |
503 | /* |
504 | * It's not strictly required, but for simplicity just map the | |
505 | * whole multicast group table now. The table isn't very big | |
506 | * and it's a lot easier than trying to track ref counts. | |
507 | */ | |
508 | mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base, | |
509 | MTHCA_MGM_ENTRY_SIZE, | |
510 | mdev->limits.num_mgms + | |
511 | mdev->limits.num_amgms, | |
512 | mdev->limits.num_mgms + | |
513 | mdev->limits.num_amgms, | |
391e4dea | 514 | 0, 0); |
1da177e4 LT |
515 | if (!mdev->mcg_table.table) { |
516 | mthca_err(mdev, "Failed to map MCG context memory, aborting.\n"); | |
517 | err = -ENOMEM; | |
ec34a922 | 518 | goto err_unmap_srq; |
1da177e4 LT |
519 | } |
520 | ||
521 | return 0; | |
522 | ||
ec34a922 RD |
523 | err_unmap_srq: |
524 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) | |
525 | mthca_free_icm_table(mdev, mdev->srq_table.table); | |
526 | ||
1da177e4 LT |
527 | err_unmap_cq: |
528 | mthca_free_icm_table(mdev, mdev->cq_table.table); | |
529 | ||
08aeb14e RD |
530 | err_unmap_rdb: |
531 | mthca_free_icm_table(mdev, mdev->qp_table.rdb_table); | |
532 | ||
1da177e4 LT |
533 | err_unmap_eqp: |
534 | mthca_free_icm_table(mdev, mdev->qp_table.eqp_table); | |
535 | ||
536 | err_unmap_qp: | |
537 | mthca_free_icm_table(mdev, mdev->qp_table.qp_table); | |
538 | ||
539 | err_unmap_mpt: | |
540 | mthca_free_icm_table(mdev, mdev->mr_table.mpt_table); | |
541 | ||
542 | err_unmap_mtt: | |
543 | mthca_free_icm_table(mdev, mdev->mr_table.mtt_table); | |
544 | ||
545 | err_unmap_eq: | |
546 | mthca_unmap_eq_icm(mdev); | |
547 | ||
548 | err_unmap_aux: | |
cdb73db0 | 549 | mthca_UNMAP_ICM_AUX(mdev); |
1da177e4 LT |
550 | |
551 | err_free_aux: | |
391e4dea | 552 | mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0); |
1da177e4 LT |
553 | |
554 | return err; | |
555 | } | |
556 | ||
aba7a22f MT |
557 | static void mthca_free_icms(struct mthca_dev *mdev) |
558 | { | |
aba7a22f MT |
559 | |
560 | mthca_free_icm_table(mdev, mdev->mcg_table.table); | |
561 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) | |
562 | mthca_free_icm_table(mdev, mdev->srq_table.table); | |
563 | mthca_free_icm_table(mdev, mdev->cq_table.table); | |
564 | mthca_free_icm_table(mdev, mdev->qp_table.rdb_table); | |
565 | mthca_free_icm_table(mdev, mdev->qp_table.eqp_table); | |
566 | mthca_free_icm_table(mdev, mdev->qp_table.qp_table); | |
567 | mthca_free_icm_table(mdev, mdev->mr_table.mpt_table); | |
568 | mthca_free_icm_table(mdev, mdev->mr_table.mtt_table); | |
569 | mthca_unmap_eq_icm(mdev); | |
570 | ||
cdb73db0 | 571 | mthca_UNMAP_ICM_AUX(mdev); |
391e4dea | 572 | mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0); |
aba7a22f MT |
573 | } |
574 | ||
f4f3d0f0 | 575 | static int mthca_init_arbel(struct mthca_dev *mdev) |
1da177e4 LT |
576 | { |
577 | struct mthca_dev_lim dev_lim; | |
578 | struct mthca_profile profile; | |
579 | struct mthca_init_hca_param init_hca; | |
19773539 | 580 | s64 icm_size; |
1da177e4 LT |
581 | int err; |
582 | ||
cdb73db0 | 583 | err = mthca_QUERY_FW(mdev); |
1da177e4 | 584 | if (err) { |
cdb73db0 | 585 | mthca_err(mdev, "QUERY_FW command failed %d, aborting.\n", err); |
1da177e4 LT |
586 | return err; |
587 | } | |
1da177e4 | 588 | |
cdb73db0 GR |
589 | err = mthca_ENABLE_LAM(mdev); |
590 | if (err == -EAGAIN) { | |
1da177e4 LT |
591 | mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n"); |
592 | mdev->mthca_flags |= MTHCA_FLAG_NO_LAM; | |
cdb73db0 GR |
593 | } else if (err) { |
594 | mthca_err(mdev, "ENABLE_LAM returned %d, aborting.\n", err); | |
595 | return err; | |
1da177e4 LT |
596 | } |
597 | ||
598 | err = mthca_load_fw(mdev); | |
599 | if (err) { | |
cdb73db0 | 600 | mthca_err(mdev, "Loading FW returned %d, aborting.\n", err); |
1da177e4 LT |
601 | goto err_disable; |
602 | } | |
603 | ||
604 | err = mthca_dev_lim(mdev, &dev_lim); | |
605 | if (err) { | |
cdb73db0 | 606 | mthca_err(mdev, "QUERY_DEV_LIM returned %d, aborting.\n", err); |
1da177e4 LT |
607 | goto err_stop_fw; |
608 | } | |
609 | ||
82da703e | 610 | profile = hca_profile; |
1da177e4 LT |
611 | profile.num_uar = dev_lim.uar_size / PAGE_SIZE; |
612 | profile.num_udav = 0; | |
ec34a922 RD |
613 | if (mdev->mthca_flags & MTHCA_FLAG_SRQ) |
614 | profile.num_srq = dev_lim.max_srqs; | |
1da177e4 LT |
615 | |
616 | icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca); | |
19773539 | 617 | if (icm_size < 0) { |
1da177e4 LT |
618 | err = icm_size; |
619 | goto err_stop_fw; | |
620 | } | |
621 | ||
622 | err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size); | |
623 | if (err) | |
624 | goto err_stop_fw; | |
625 | ||
cdb73db0 | 626 | err = mthca_INIT_HCA(mdev, &init_hca); |
1da177e4 | 627 | if (err) { |
cdb73db0 | 628 | mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err); |
1da177e4 LT |
629 | goto err_free_icm; |
630 | } | |
631 | ||
1da177e4 LT |
632 | return 0; |
633 | ||
634 | err_free_icm: | |
aba7a22f | 635 | mthca_free_icms(mdev); |
1da177e4 LT |
636 | |
637 | err_stop_fw: | |
cdb73db0 | 638 | mthca_UNMAP_FA(mdev); |
391e4dea | 639 | mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0); |
1da177e4 LT |
640 | |
641 | err_disable: | |
642 | if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM)) | |
cdb73db0 | 643 | mthca_DISABLE_LAM(mdev); |
1da177e4 LT |
644 | |
645 | return err; | |
646 | } | |
647 | ||
2e8b981c MT |
648 | static void mthca_close_hca(struct mthca_dev *mdev) |
649 | { | |
cdb73db0 | 650 | mthca_CLOSE_HCA(mdev, 0); |
2e8b981c MT |
651 | |
652 | if (mthca_is_memfree(mdev)) { | |
aba7a22f | 653 | mthca_free_icms(mdev); |
2e8b981c | 654 | |
cdb73db0 | 655 | mthca_UNMAP_FA(mdev); |
391e4dea | 656 | mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0); |
2e8b981c MT |
657 | |
658 | if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM)) | |
cdb73db0 | 659 | mthca_DISABLE_LAM(mdev); |
2e8b981c | 660 | } else |
cdb73db0 | 661 | mthca_SYS_DIS(mdev); |
2e8b981c MT |
662 | } |
663 | ||
f4f3d0f0 | 664 | static int mthca_init_hca(struct mthca_dev *mdev) |
1da177e4 | 665 | { |
2e8b981c MT |
666 | int err; |
667 | struct mthca_adapter adapter; | |
668 | ||
d10ddbf6 | 669 | if (mthca_is_memfree(mdev)) |
2e8b981c | 670 | err = mthca_init_arbel(mdev); |
1da177e4 | 671 | else |
2e8b981c MT |
672 | err = mthca_init_tavor(mdev); |
673 | ||
674 | if (err) | |
675 | return err; | |
676 | ||
cdb73db0 | 677 | err = mthca_QUERY_ADAPTER(mdev, &adapter); |
2e8b981c | 678 | if (err) { |
cdb73db0 | 679 | mthca_err(mdev, "QUERY_ADAPTER command returned %d, aborting.\n", err); |
2e8b981c MT |
680 | goto err_close; |
681 | } | |
682 | ||
683 | mdev->eq_table.inta_pin = adapter.inta_pin; | |
6ccef1de JM |
684 | if (!mthca_is_memfree(mdev)) |
685 | mdev->rev_id = adapter.revision_id; | |
2e8b981c MT |
686 | memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id); |
687 | ||
688 | return 0; | |
689 | ||
690 | err_close: | |
691 | mthca_close_hca(mdev); | |
692 | return err; | |
1da177e4 LT |
693 | } |
694 | ||
f4f3d0f0 | 695 | static int mthca_setup_hca(struct mthca_dev *dev) |
1da177e4 LT |
696 | { |
697 | int err; | |
1da177e4 LT |
698 | |
699 | MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock); | |
700 | ||
701 | err = mthca_init_uar_table(dev); | |
702 | if (err) { | |
703 | mthca_err(dev, "Failed to initialize " | |
704 | "user access region table, aborting.\n"); | |
705 | return err; | |
706 | } | |
707 | ||
708 | err = mthca_uar_alloc(dev, &dev->driver_uar); | |
709 | if (err) { | |
710 | mthca_err(dev, "Failed to allocate driver access region, " | |
711 | "aborting.\n"); | |
712 | goto err_uar_table_free; | |
713 | } | |
714 | ||
eb4a7cbf | 715 | dev->kar = ioremap((phys_addr_t) dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); |
1da177e4 LT |
716 | if (!dev->kar) { |
717 | mthca_err(dev, "Couldn't map kernel access region, " | |
718 | "aborting.\n"); | |
719 | err = -ENOMEM; | |
720 | goto err_uar_free; | |
721 | } | |
722 | ||
723 | err = mthca_init_pd_table(dev); | |
724 | if (err) { | |
725 | mthca_err(dev, "Failed to initialize " | |
726 | "protection domain table, aborting.\n"); | |
727 | goto err_kar_unmap; | |
728 | } | |
729 | ||
730 | err = mthca_init_mr_table(dev); | |
731 | if (err) { | |
732 | mthca_err(dev, "Failed to initialize " | |
733 | "memory region table, aborting.\n"); | |
734 | goto err_pd_table_free; | |
735 | } | |
736 | ||
99264c1e | 737 | err = mthca_pd_alloc(dev, 1, &dev->driver_pd); |
1da177e4 LT |
738 | if (err) { |
739 | mthca_err(dev, "Failed to create driver PD, " | |
740 | "aborting.\n"); | |
741 | goto err_mr_table_free; | |
742 | } | |
743 | ||
744 | err = mthca_init_eq_table(dev); | |
745 | if (err) { | |
746 | mthca_err(dev, "Failed to initialize " | |
747 | "event queue table, aborting.\n"); | |
748 | goto err_pd_free; | |
749 | } | |
750 | ||
751 | err = mthca_cmd_use_events(dev); | |
752 | if (err) { | |
753 | mthca_err(dev, "Failed to switch to event-driven " | |
754 | "firmware commands, aborting.\n"); | |
755 | goto err_eq_table_free; | |
756 | } | |
757 | ||
cdb73db0 GR |
758 | err = mthca_NOP(dev); |
759 | if (err) { | |
e57895d3 | 760 | if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { |
017aadc4 MT |
761 | mthca_warn(dev, "NOP command failed to generate interrupt " |
762 | "(IRQ %d).\n", | |
e57895d3 AB |
763 | dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector); |
764 | mthca_warn(dev, "Trying again with MSI-X disabled.\n"); | |
017aadc4 MT |
765 | } else { |
766 | mthca_err(dev, "NOP command failed to generate interrupt " | |
767 | "(IRQ %d), aborting.\n", | |
768 | dev->pdev->irq); | |
1da177e4 | 769 | mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
017aadc4 | 770 | } |
1da177e4 LT |
771 | |
772 | goto err_cmd_poll; | |
773 | } | |
774 | ||
775 | mthca_dbg(dev, "NOP command IRQ test passed\n"); | |
776 | ||
777 | err = mthca_init_cq_table(dev); | |
778 | if (err) { | |
779 | mthca_err(dev, "Failed to initialize " | |
780 | "completion queue table, aborting.\n"); | |
781 | goto err_cmd_poll; | |
782 | } | |
783 | ||
ec34a922 RD |
784 | err = mthca_init_srq_table(dev); |
785 | if (err) { | |
786 | mthca_err(dev, "Failed to initialize " | |
787 | "shared receive queue table, aborting.\n"); | |
788 | goto err_cq_table_free; | |
789 | } | |
790 | ||
1da177e4 LT |
791 | err = mthca_init_qp_table(dev); |
792 | if (err) { | |
793 | mthca_err(dev, "Failed to initialize " | |
794 | "queue pair table, aborting.\n"); | |
ec34a922 | 795 | goto err_srq_table_free; |
1da177e4 LT |
796 | } |
797 | ||
798 | err = mthca_init_av_table(dev); | |
799 | if (err) { | |
800 | mthca_err(dev, "Failed to initialize " | |
801 | "address vector table, aborting.\n"); | |
802 | goto err_qp_table_free; | |
803 | } | |
804 | ||
805 | err = mthca_init_mcg_table(dev); | |
806 | if (err) { | |
807 | mthca_err(dev, "Failed to initialize " | |
808 | "multicast group table, aborting.\n"); | |
809 | goto err_av_table_free; | |
810 | } | |
811 | ||
812 | return 0; | |
813 | ||
814 | err_av_table_free: | |
815 | mthca_cleanup_av_table(dev); | |
816 | ||
817 | err_qp_table_free: | |
818 | mthca_cleanup_qp_table(dev); | |
819 | ||
ec34a922 RD |
820 | err_srq_table_free: |
821 | mthca_cleanup_srq_table(dev); | |
822 | ||
1da177e4 LT |
823 | err_cq_table_free: |
824 | mthca_cleanup_cq_table(dev); | |
825 | ||
826 | err_cmd_poll: | |
827 | mthca_cmd_use_polling(dev); | |
828 | ||
829 | err_eq_table_free: | |
830 | mthca_cleanup_eq_table(dev); | |
831 | ||
832 | err_pd_free: | |
833 | mthca_pd_free(dev, &dev->driver_pd); | |
834 | ||
835 | err_mr_table_free: | |
836 | mthca_cleanup_mr_table(dev); | |
837 | ||
838 | err_pd_table_free: | |
839 | mthca_cleanup_pd_table(dev); | |
840 | ||
841 | err_kar_unmap: | |
842 | iounmap(dev->kar); | |
843 | ||
844 | err_uar_free: | |
845 | mthca_uar_free(dev, &dev->driver_uar); | |
846 | ||
847 | err_uar_table_free: | |
848 | mthca_cleanup_uar_table(dev); | |
849 | return err; | |
850 | } | |
851 | ||
f4f3d0f0 | 852 | static int mthca_enable_msi_x(struct mthca_dev *mdev) |
1da177e4 LT |
853 | { |
854 | struct msix_entry entries[3]; | |
855 | int err; | |
856 | ||
857 | entries[0].entry = 0; | |
858 | entries[1].entry = 1; | |
859 | entries[2].entry = 2; | |
860 | ||
9684c2ea AG |
861 | err = pci_enable_msix_exact(mdev->pdev, entries, ARRAY_SIZE(entries)); |
862 | if (err) | |
1da177e4 | 863 | return err; |
1da177e4 LT |
864 | |
865 | mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector; | |
866 | mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector; | |
867 | mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
68a3c212 RD |
872 | /* Types of supported HCA */ |
873 | enum { | |
874 | TAVOR, /* MT23108 */ | |
875 | ARBEL_COMPAT, /* MT25208 in Tavor compat mode */ | |
876 | ARBEL_NATIVE, /* MT25208 with extended features */ | |
877 | SINAI /* MT25204 */ | |
878 | }; | |
879 | ||
880 | #define MTHCA_FW_VER(major, minor, subminor) \ | |
881 | (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor)) | |
882 | ||
883 | static struct { | |
884 | u64 latest_fw; | |
651eaac9 | 885 | u32 flags; |
68a3c212 | 886 | } mthca_hca_table[] = { |
3f114853 | 887 | [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0), |
651eaac9 | 888 | .flags = 0 }, |
3f114853 | 889 | [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200), |
651eaac9 | 890 | .flags = MTHCA_FLAG_PCIE }, |
950529e5 | 891 | [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0), |
651eaac9 EC |
892 | .flags = MTHCA_FLAG_MEMFREE | |
893 | MTHCA_FLAG_PCIE }, | |
3f114853 | 894 | [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0), |
651eaac9 EC |
895 | .flags = MTHCA_FLAG_MEMFREE | |
896 | MTHCA_FLAG_PCIE | | |
897 | MTHCA_FLAG_SINAI_OPT } | |
68a3c212 RD |
898 | }; |
899 | ||
b3b30f5e | 900 | static int __mthca_init_one(struct pci_dev *pdev, int hca_type) |
1da177e4 | 901 | { |
1da177e4 LT |
902 | int ddr_hidden = 0; |
903 | int err; | |
904 | struct mthca_dev *mdev; | |
905 | ||
982245f0 AB |
906 | printk(KERN_INFO PFX "Initializing %s\n", |
907 | pci_name(pdev)); | |
1da177e4 LT |
908 | |
909 | err = pci_enable_device(pdev); | |
910 | if (err) { | |
911 | dev_err(&pdev->dev, "Cannot enable PCI device, " | |
912 | "aborting.\n"); | |
913 | return err; | |
914 | } | |
915 | ||
916 | /* | |
917 | * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not | |
918 | * be present) | |
919 | */ | |
920 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || | |
921 | pci_resource_len(pdev, 0) != 1 << 20) { | |
177214af | 922 | dev_err(&pdev->dev, "Missing DCS, aborting.\n"); |
1da177e4 LT |
923 | err = -ENODEV; |
924 | goto err_disable_pdev; | |
925 | } | |
cbd2981a | 926 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
177214af | 927 | dev_err(&pdev->dev, "Missing UAR, aborting.\n"); |
1da177e4 LT |
928 | err = -ENODEV; |
929 | goto err_disable_pdev; | |
930 | } | |
931 | if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM)) | |
932 | ddr_hidden = 1; | |
933 | ||
208dde28 | 934 | err = pci_request_regions(pdev, DRV_NAME); |
1da177e4 LT |
935 | if (err) { |
936 | dev_err(&pdev->dev, "Cannot obtain PCI resources, " | |
937 | "aborting.\n"); | |
938 | goto err_disable_pdev; | |
939 | } | |
940 | ||
941 | pci_set_master(pdev); | |
942 | ||
6a35528a | 943 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
1da177e4 LT |
944 | if (err) { |
945 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); | |
284901a9 | 946 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 LT |
947 | if (err) { |
948 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); | |
949 | goto err_free_res; | |
950 | } | |
951 | } | |
6a35528a | 952 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
1da177e4 LT |
953 | if (err) { |
954 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " | |
955 | "consistent PCI DMA mask.\n"); | |
284901a9 | 956 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 LT |
957 | if (err) { |
958 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " | |
959 | "aborting.\n"); | |
960 | goto err_free_res; | |
961 | } | |
962 | } | |
963 | ||
7f9e5c48 DD |
964 | /* We can handle large RDMA requests, so allow larger segments. */ |
965 | dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); | |
966 | ||
1da177e4 LT |
967 | mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev); |
968 | if (!mdev) { | |
969 | dev_err(&pdev->dev, "Device struct alloc failed, " | |
970 | "aborting.\n"); | |
971 | err = -ENOMEM; | |
972 | goto err_free_res; | |
973 | } | |
974 | ||
68a3c212 | 975 | mdev->pdev = pdev; |
1da177e4 | 976 | |
b3b30f5e | 977 | mdev->mthca_flags = mthca_hca_table[hca_type].flags; |
1da177e4 LT |
978 | if (ddr_hidden) |
979 | mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN; | |
980 | ||
981 | /* | |
982 | * Now reset the HCA before we touch the PCI capabilities or | |
983 | * attempt a firmware command, since a boot ROM may have left | |
984 | * the HCA in an undefined state. | |
985 | */ | |
986 | err = mthca_reset(mdev); | |
987 | if (err) { | |
988 | mthca_err(mdev, "Failed to reset HCA, aborting.\n"); | |
989 | goto err_free_dev; | |
990 | } | |
991 | ||
80fd8238 RD |
992 | if (mthca_cmd_init(mdev)) { |
993 | mthca_err(mdev, "Failed to init command interface, aborting.\n"); | |
1da177e4 LT |
994 | goto err_free_dev; |
995 | } | |
996 | ||
997 | err = mthca_tune_pci(mdev); | |
998 | if (err) | |
80fd8238 | 999 | goto err_cmd; |
1da177e4 LT |
1000 | |
1001 | err = mthca_init_hca(mdev); | |
1002 | if (err) | |
80fd8238 | 1003 | goto err_cmd; |
1da177e4 | 1004 | |
b3b30f5e | 1005 | if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) { |
e4daf738 | 1006 | mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n", |
68a3c212 RD |
1007 | (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff, |
1008 | (int) (mdev->fw_ver & 0xffff), | |
b3b30f5e JM |
1009 | (int) (mthca_hca_table[hca_type].latest_fw >> 32), |
1010 | (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff, | |
1011 | (int) (mthca_hca_table[hca_type].latest_fw & 0xffff)); | |
68a3c212 RD |
1012 | mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n"); |
1013 | } | |
1014 | ||
017aadc4 MT |
1015 | if (msi_x && !mthca_enable_msi_x(mdev)) |
1016 | mdev->mthca_flags |= MTHCA_FLAG_MSI_X; | |
017aadc4 | 1017 | |
1da177e4 | 1018 | err = mthca_setup_hca(mdev); |
e57895d3 | 1019 | if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) { |
017aadc4 MT |
1020 | if (mdev->mthca_flags & MTHCA_FLAG_MSI_X) |
1021 | pci_disable_msix(pdev); | |
e57895d3 | 1022 | mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X; |
017aadc4 MT |
1023 | |
1024 | err = mthca_setup_hca(mdev); | |
1025 | } | |
1026 | ||
1da177e4 LT |
1027 | if (err) |
1028 | goto err_close; | |
1029 | ||
1030 | err = mthca_register_device(mdev); | |
1031 | if (err) | |
1032 | goto err_cleanup; | |
1033 | ||
1034 | err = mthca_create_agents(mdev); | |
1035 | if (err) | |
1036 | goto err_unregister; | |
1037 | ||
1038 | pci_set_drvdata(pdev, mdev); | |
b3b30f5e | 1039 | mdev->hca_type = hca_type; |
1da177e4 | 1040 | |
d8410647 JM |
1041 | mdev->active = true; |
1042 | ||
1da177e4 LT |
1043 | return 0; |
1044 | ||
1045 | err_unregister: | |
1046 | mthca_unregister_device(mdev); | |
1047 | ||
1048 | err_cleanup: | |
1049 | mthca_cleanup_mcg_table(mdev); | |
1050 | mthca_cleanup_av_table(mdev); | |
1051 | mthca_cleanup_qp_table(mdev); | |
ec34a922 | 1052 | mthca_cleanup_srq_table(mdev); |
1da177e4 LT |
1053 | mthca_cleanup_cq_table(mdev); |
1054 | mthca_cmd_use_polling(mdev); | |
1055 | mthca_cleanup_eq_table(mdev); | |
1056 | ||
1057 | mthca_pd_free(mdev, &mdev->driver_pd); | |
1058 | ||
1059 | mthca_cleanup_mr_table(mdev); | |
1060 | mthca_cleanup_pd_table(mdev); | |
1061 | mthca_cleanup_uar_table(mdev); | |
1062 | ||
1063 | err_close: | |
017aadc4 MT |
1064 | if (mdev->mthca_flags & MTHCA_FLAG_MSI_X) |
1065 | pci_disable_msix(pdev); | |
017aadc4 | 1066 | |
1da177e4 LT |
1067 | mthca_close_hca(mdev); |
1068 | ||
80fd8238 RD |
1069 | err_cmd: |
1070 | mthca_cmd_cleanup(mdev); | |
1da177e4 LT |
1071 | |
1072 | err_free_dev: | |
1da177e4 LT |
1073 | ib_dealloc_device(&mdev->ib_dev); |
1074 | ||
1075 | err_free_res: | |
208dde28 | 1076 | pci_release_regions(pdev); |
1da177e4 LT |
1077 | |
1078 | err_disable_pdev: | |
1079 | pci_disable_device(pdev); | |
1080 | pci_set_drvdata(pdev, NULL); | |
1081 | return err; | |
1082 | } | |
1083 | ||
b3b30f5e | 1084 | static void __mthca_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1085 | { |
1086 | struct mthca_dev *mdev = pci_get_drvdata(pdev); | |
1da177e4 LT |
1087 | int p; |
1088 | ||
1089 | if (mdev) { | |
1090 | mthca_free_agents(mdev); | |
1091 | mthca_unregister_device(mdev); | |
1092 | ||
1093 | for (p = 1; p <= mdev->limits.num_ports; ++p) | |
cdb73db0 | 1094 | mthca_CLOSE_IB(mdev, p); |
1da177e4 LT |
1095 | |
1096 | mthca_cleanup_mcg_table(mdev); | |
1097 | mthca_cleanup_av_table(mdev); | |
1098 | mthca_cleanup_qp_table(mdev); | |
ec34a922 | 1099 | mthca_cleanup_srq_table(mdev); |
1da177e4 LT |
1100 | mthca_cleanup_cq_table(mdev); |
1101 | mthca_cmd_use_polling(mdev); | |
1102 | mthca_cleanup_eq_table(mdev); | |
1103 | ||
1104 | mthca_pd_free(mdev, &mdev->driver_pd); | |
1105 | ||
1106 | mthca_cleanup_mr_table(mdev); | |
1107 | mthca_cleanup_pd_table(mdev); | |
1108 | ||
1109 | iounmap(mdev->kar); | |
1110 | mthca_uar_free(mdev, &mdev->driver_uar); | |
1111 | mthca_cleanup_uar_table(mdev); | |
1da177e4 | 1112 | mthca_close_hca(mdev); |
80fd8238 | 1113 | mthca_cmd_cleanup(mdev); |
1da177e4 LT |
1114 | |
1115 | if (mdev->mthca_flags & MTHCA_FLAG_MSI_X) | |
1116 | pci_disable_msix(pdev); | |
1da177e4 LT |
1117 | |
1118 | ib_dealloc_device(&mdev->ib_dev); | |
208dde28 | 1119 | pci_release_regions(pdev); |
1da177e4 LT |
1120 | pci_disable_device(pdev); |
1121 | pci_set_drvdata(pdev, NULL); | |
1122 | } | |
1123 | } | |
1124 | ||
b3b30f5e JM |
1125 | int __mthca_restart_one(struct pci_dev *pdev) |
1126 | { | |
1127 | struct mthca_dev *mdev; | |
de57c9f1 | 1128 | int hca_type; |
b3b30f5e JM |
1129 | |
1130 | mdev = pci_get_drvdata(pdev); | |
1131 | if (!mdev) | |
1132 | return -ENODEV; | |
de57c9f1 | 1133 | hca_type = mdev->hca_type; |
b3b30f5e | 1134 | __mthca_remove_one(pdev); |
de57c9f1 | 1135 | return __mthca_init_one(pdev, hca_type); |
b3b30f5e JM |
1136 | } |
1137 | ||
1e6d9abe | 1138 | static int mthca_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
b3b30f5e | 1139 | { |
b3b30f5e JM |
1140 | int ret; |
1141 | ||
1142 | mutex_lock(&mthca_device_mutex); | |
1143 | ||
f1aa78b2 | 1144 | printk_once(KERN_INFO "%s", mthca_version); |
b3b30f5e JM |
1145 | |
1146 | if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) { | |
1147 | printk(KERN_ERR PFX "%s has invalid driver data %lx\n", | |
1148 | pci_name(pdev), id->driver_data); | |
1149 | mutex_unlock(&mthca_device_mutex); | |
1150 | return -ENODEV; | |
1151 | } | |
1152 | ||
1153 | ret = __mthca_init_one(pdev, id->driver_data); | |
1154 | ||
1155 | mutex_unlock(&mthca_device_mutex); | |
1156 | ||
1157 | return ret; | |
1158 | } | |
1159 | ||
1e6d9abe | 1160 | static void mthca_remove_one(struct pci_dev *pdev) |
b3b30f5e JM |
1161 | { |
1162 | mutex_lock(&mthca_device_mutex); | |
1163 | __mthca_remove_one(pdev); | |
1164 | mutex_unlock(&mthca_device_mutex); | |
1165 | } | |
1166 | ||
1da177e4 LT |
1167 | static struct pci_device_id mthca_pci_table[] = { |
1168 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR), | |
1169 | .driver_data = TAVOR }, | |
1170 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR), | |
1171 | .driver_data = TAVOR }, | |
1172 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT), | |
1173 | .driver_data = ARBEL_COMPAT }, | |
1174 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT), | |
1175 | .driver_data = ARBEL_COMPAT }, | |
1176 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL), | |
1177 | .driver_data = ARBEL_NATIVE }, | |
1178 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL), | |
1179 | .driver_data = ARBEL_NATIVE }, | |
68a3c212 RD |
1180 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI), |
1181 | .driver_data = SINAI }, | |
1182 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI), | |
1183 | .driver_data = SINAI }, | |
1184 | { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD), | |
1185 | .driver_data = SINAI }, | |
1186 | { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD), | |
1187 | .driver_data = SINAI }, | |
1da177e4 LT |
1188 | { 0, } |
1189 | }; | |
1190 | ||
1191 | MODULE_DEVICE_TABLE(pci, mthca_pci_table); | |
1192 | ||
1193 | static struct pci_driver mthca_driver = { | |
177214af | 1194 | .name = DRV_NAME, |
1da177e4 LT |
1195 | .id_table = mthca_pci_table, |
1196 | .probe = mthca_init_one, | |
1e6d9abe | 1197 | .remove = mthca_remove_one, |
1da177e4 LT |
1198 | }; |
1199 | ||
82da703e LA |
1200 | static void __init __mthca_check_profile_val(const char *name, int *pval, |
1201 | int pval_default) | |
1202 | { | |
1203 | /* value must be positive and power of 2 */ | |
1204 | int old_pval = *pval; | |
1205 | ||
1206 | if (old_pval <= 0) | |
1207 | *pval = pval_default; | |
1208 | else | |
1209 | *pval = roundup_pow_of_two(old_pval); | |
1210 | ||
1211 | if (old_pval != *pval) { | |
1212 | printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n", | |
1213 | old_pval, name); | |
1214 | printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval); | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | #define mthca_check_profile_val(name, default) \ | |
1219 | __mthca_check_profile_val(#name, &hca_profile.name, default) | |
1220 | ||
1221 | static void __init mthca_validate_profile(void) | |
1222 | { | |
1223 | mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP); | |
1224 | mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP); | |
1225 | mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ); | |
1226 | mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG); | |
1227 | mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT); | |
1228 | mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT); | |
1229 | mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV); | |
1230 | mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS); | |
1231 | ||
1232 | if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) { | |
1233 | printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n", | |
1234 | hca_profile.fmr_reserved_mtts); | |
1235 | printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n", | |
1236 | hca_profile.num_mtt); | |
1237 | hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2; | |
1238 | printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n", | |
1239 | hca_profile.fmr_reserved_mtts); | |
1240 | } | |
c1f67a88 EC |
1241 | |
1242 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) { | |
1243 | printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n", | |
1244 | log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8)); | |
1245 | log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8); | |
1246 | } | |
82da703e LA |
1247 | } |
1248 | ||
1da177e4 LT |
1249 | static int __init mthca_init(void) |
1250 | { | |
1251 | int ret; | |
1252 | ||
82da703e LA |
1253 | mthca_validate_profile(); |
1254 | ||
b3b30f5e JM |
1255 | ret = mthca_catas_init(); |
1256 | if (ret) | |
1257 | return ret; | |
1258 | ||
1da177e4 | 1259 | ret = pci_register_driver(&mthca_driver); |
b3b30f5e JM |
1260 | if (ret < 0) { |
1261 | mthca_catas_cleanup(); | |
1262 | return ret; | |
1263 | } | |
1264 | ||
1265 | return 0; | |
1da177e4 LT |
1266 | } |
1267 | ||
1268 | static void __exit mthca_cleanup(void) | |
1269 | { | |
1270 | pci_unregister_driver(&mthca_driver); | |
b3b30f5e | 1271 | mthca_catas_cleanup(); |
1da177e4 LT |
1272 | } |
1273 | ||
1274 | module_init(mthca_init); | |
1275 | module_exit(mthca_cleanup); |