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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. | |
4885bf64 | 3 | * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. |
2a1d9b7f | 4 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | * | |
34 | * $Id: mthca_provider.h 1349 2004-12-16 21:09:43Z roland $ | |
35 | */ | |
36 | ||
37 | #ifndef MTHCA_PROVIDER_H | |
38 | #define MTHCA_PROVIDER_H | |
39 | ||
a4d61e84 RD |
40 | #include <rdma/ib_verbs.h> |
41 | #include <rdma/ib_pack.h> | |
1da177e4 LT |
42 | |
43 | #define MTHCA_MPT_FLAG_ATOMIC (1 << 14) | |
44 | #define MTHCA_MPT_FLAG_REMOTE_WRITE (1 << 13) | |
45 | #define MTHCA_MPT_FLAG_REMOTE_READ (1 << 12) | |
46 | #define MTHCA_MPT_FLAG_LOCAL_WRITE (1 << 11) | |
47 | #define MTHCA_MPT_FLAG_LOCAL_READ (1 << 10) | |
48 | ||
49 | struct mthca_buf_list { | |
50 | void *buf; | |
51 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
52 | }; | |
53 | ||
87b81670 RD |
54 | union mthca_buf { |
55 | struct mthca_buf_list direct; | |
56 | struct mthca_buf_list *page_list; | |
57 | }; | |
58 | ||
1da177e4 LT |
59 | struct mthca_uar { |
60 | unsigned long pfn; | |
61 | int index; | |
62 | }; | |
63 | ||
5e0b537c RD |
64 | struct mthca_user_db_table; |
65 | ||
66 | struct mthca_ucontext { | |
67 | struct ib_ucontext ibucontext; | |
68 | struct mthca_uar uar; | |
69 | struct mthca_user_db_table *db_tab; | |
70 | }; | |
71 | ||
d56d6f95 RD |
72 | struct mthca_mtt; |
73 | ||
1da177e4 | 74 | struct mthca_mr { |
d56d6f95 RD |
75 | struct ib_mr ibmr; |
76 | struct mthca_mtt *mtt; | |
1da177e4 LT |
77 | }; |
78 | ||
e0f5fdca | 79 | struct mthca_fmr { |
d56d6f95 | 80 | struct ib_fmr ibmr; |
e0f5fdca | 81 | struct ib_fmr_attr attr; |
d56d6f95 RD |
82 | struct mthca_mtt *mtt; |
83 | int maps; | |
e0f5fdca MT |
84 | union { |
85 | struct { | |
86 | struct mthca_mpt_entry __iomem *mpt; | |
87 | u64 __iomem *mtts; | |
88 | } tavor; | |
89 | struct { | |
90 | struct mthca_mpt_entry *mpt; | |
91 | __be64 *mtts; | |
92 | } arbel; | |
93 | } mem; | |
94 | }; | |
95 | ||
1da177e4 LT |
96 | struct mthca_pd { |
97 | struct ib_pd ibpd; | |
98 | u32 pd_num; | |
99 | atomic_t sqp_count; | |
100 | struct mthca_mr ntmr; | |
99264c1e | 101 | int privileged; |
1da177e4 LT |
102 | }; |
103 | ||
104 | struct mthca_eq { | |
105 | struct mthca_dev *dev; | |
106 | int eqn; | |
107 | u32 eqn_mask; | |
108 | u32 cons_index; | |
109 | u16 msi_x_vector; | |
110 | u16 msi_x_entry; | |
111 | int have_irq; | |
112 | int nent; | |
113 | struct mthca_buf_list *page_list; | |
114 | struct mthca_mr mr; | |
115 | }; | |
116 | ||
117 | struct mthca_av; | |
118 | ||
119 | enum mthca_ah_type { | |
120 | MTHCA_AH_ON_HCA, | |
121 | MTHCA_AH_PCI_POOL, | |
122 | MTHCA_AH_KMALLOC | |
123 | }; | |
124 | ||
125 | struct mthca_ah { | |
126 | struct ib_ah ibah; | |
127 | enum mthca_ah_type type; | |
128 | u32 key; | |
129 | struct mthca_av *av; | |
130 | dma_addr_t avdma; | |
131 | }; | |
132 | ||
133 | /* | |
134 | * Quick description of our CQ/QP locking scheme: | |
135 | * | |
136 | * We have one global lock that protects dev->cq/qp_table. Each | |
137 | * struct mthca_cq/qp also has its own lock. An individual qp lock | |
138 | * may be taken inside of an individual cq lock. Both cqs attached to | |
139 | * a qp may be locked, with the send cq locked first. No other | |
140 | * nesting should be done. | |
141 | * | |
a3285aa4 RD |
142 | * Each struct mthca_cq/qp also has an ref count, protected by the |
143 | * corresponding table lock. The pointer from the cq/qp_table to the | |
144 | * struct counts as one reference. This reference also is good for | |
145 | * access through the consumer API, so modifying the CQ/QP etc doesn't | |
146 | * need to take another reference. Access to a QP because of a | |
147 | * completion being polled does not need a reference either. | |
1da177e4 LT |
148 | * |
149 | * Finally, each struct mthca_cq/qp has a wait_queue_head_t for the | |
150 | * destroy function to sleep on. | |
151 | * | |
152 | * This means that access from the consumer API requires nothing but | |
153 | * taking the struct's lock. | |
154 | * | |
155 | * Access because of a completion event should go as follows: | |
156 | * - lock cq/qp_table and look up struct | |
157 | * - increment ref count in struct | |
158 | * - drop cq/qp_table lock | |
159 | * - lock struct, do your thing, and unlock struct | |
160 | * - decrement ref count; if zero, wake up waiters | |
161 | * | |
162 | * To destroy a CQ/QP, we can do the following: | |
a3285aa4 RD |
163 | * - lock cq/qp_table |
164 | * - remove pointer and decrement ref count | |
165 | * - unlock cq/qp_table lock | |
1da177e4 LT |
166 | * - wait_event until ref count is zero |
167 | * | |
168 | * It is the consumer's responsibilty to make sure that no QP | |
4885bf64 | 169 | * operations (WQE posting or state modification) are pending when a |
1da177e4 | 170 | * QP is destroyed. Also, the consumer must make sure that calls to |
4885bf64 RD |
171 | * qp_modify are serialized. Similarly, the consumer is responsible |
172 | * for ensuring that no CQ resize operations are pending when a CQ | |
173 | * is destroyed. | |
1da177e4 LT |
174 | * |
175 | * Possible optimizations (wait for profile data to see if/where we | |
176 | * have locks bouncing between CPUs): | |
177 | * - split cq/qp table lock into n separate (cache-aligned) locks, | |
178 | * indexed (say) by the page in the table | |
179 | * - split QP struct lock into three (one for common info, one for the | |
180 | * send queue and one for the receive queue) | |
181 | */ | |
182 | ||
4885bf64 RD |
183 | struct mthca_cq_buf { |
184 | union mthca_buf queue; | |
185 | struct mthca_mr mr; | |
186 | int is_direct; | |
187 | }; | |
188 | ||
189 | struct mthca_cq_resize { | |
190 | struct mthca_cq_buf buf; | |
191 | int cqe; | |
192 | enum { | |
193 | CQ_RESIZE_ALLOC, | |
194 | CQ_RESIZE_READY, | |
195 | CQ_RESIZE_SWAPPED | |
196 | } state; | |
197 | }; | |
198 | ||
1da177e4 | 199 | struct mthca_cq { |
4885bf64 RD |
200 | struct ib_cq ibcq; |
201 | spinlock_t lock; | |
a3285aa4 | 202 | int refcount; |
4885bf64 RD |
203 | int cqn; |
204 | u32 cons_index; | |
205 | struct mthca_cq_buf buf; | |
206 | struct mthca_cq_resize *resize_buf; | |
207 | int is_kernel; | |
1da177e4 LT |
208 | |
209 | /* Next fields are Arbel only */ | |
4885bf64 RD |
210 | int set_ci_db_index; |
211 | __be32 *set_ci_db; | |
212 | int arm_db_index; | |
213 | __be32 *arm_db; | |
214 | int arm_sn; | |
1da177e4 | 215 | |
4885bf64 | 216 | wait_queue_head_t wait; |
c93b6fba | 217 | struct mutex mutex; |
1da177e4 LT |
218 | }; |
219 | ||
ec34a922 RD |
220 | struct mthca_srq { |
221 | struct ib_srq ibsrq; | |
222 | spinlock_t lock; | |
a3285aa4 | 223 | int refcount; |
ec34a922 RD |
224 | int srqn; |
225 | int max; | |
226 | int max_gs; | |
227 | int wqe_shift; | |
228 | int first_free; | |
229 | int last_free; | |
230 | u16 counter; /* Arbel only */ | |
231 | int db_index; /* Arbel only */ | |
232 | __be32 *db; /* Arbel only */ | |
233 | void *last; | |
234 | ||
235 | int is_direct; | |
236 | u64 *wrid; | |
237 | union mthca_buf queue; | |
238 | struct mthca_mr mr; | |
239 | ||
240 | wait_queue_head_t wait; | |
c93b6fba | 241 | struct mutex mutex; |
ec34a922 RD |
242 | }; |
243 | ||
1da177e4 LT |
244 | struct mthca_wq { |
245 | spinlock_t lock; | |
246 | int max; | |
247 | unsigned next_ind; | |
248 | unsigned last_comp; | |
249 | unsigned head; | |
250 | unsigned tail; | |
251 | void *last; | |
252 | int max_gs; | |
253 | int wqe_shift; | |
254 | ||
255 | int db_index; /* Arbel only */ | |
97f52eb4 | 256 | __be32 *db; |
1da177e4 LT |
257 | }; |
258 | ||
259 | struct mthca_qp { | |
260 | struct ib_qp ibqp; | |
a3285aa4 | 261 | int refcount; |
1da177e4 LT |
262 | u32 qpn; |
263 | int is_direct; | |
bf6a9e31 JM |
264 | u8 port; /* for SQP and memfree use only */ |
265 | u8 alt_port; /* for memfree use only */ | |
1da177e4 LT |
266 | u8 transport; |
267 | u8 state; | |
268 | u8 atomic_rd_en; | |
269 | u8 resp_depth; | |
270 | ||
271 | struct mthca_mr mr; | |
272 | ||
273 | struct mthca_wq rq; | |
274 | struct mthca_wq sq; | |
275 | enum ib_sig_type sq_policy; | |
276 | int send_wqe_offset; | |
77369ed3 | 277 | int max_inline_data; |
1da177e4 LT |
278 | |
279 | u64 *wrid; | |
87b81670 | 280 | union mthca_buf queue; |
1da177e4 LT |
281 | |
282 | wait_queue_head_t wait; | |
c93b6fba | 283 | struct mutex mutex; |
1da177e4 LT |
284 | }; |
285 | ||
286 | struct mthca_sqp { | |
287 | struct mthca_qp qp; | |
1da177e4 LT |
288 | int pkey_index; |
289 | u32 qkey; | |
290 | u32 send_psn; | |
291 | struct ib_ud_header ud_header; | |
292 | int header_buf_size; | |
293 | void *header_buf; | |
294 | dma_addr_t header_dma; | |
295 | }; | |
296 | ||
5e0b537c RD |
297 | static inline struct mthca_ucontext *to_mucontext(struct ib_ucontext *ibucontext) |
298 | { | |
299 | return container_of(ibucontext, struct mthca_ucontext, ibucontext); | |
300 | } | |
301 | ||
e0f5fdca MT |
302 | static inline struct mthca_fmr *to_mfmr(struct ib_fmr *ibmr) |
303 | { | |
304 | return container_of(ibmr, struct mthca_fmr, ibmr); | |
305 | } | |
306 | ||
1da177e4 LT |
307 | static inline struct mthca_mr *to_mmr(struct ib_mr *ibmr) |
308 | { | |
309 | return container_of(ibmr, struct mthca_mr, ibmr); | |
310 | } | |
311 | ||
312 | static inline struct mthca_pd *to_mpd(struct ib_pd *ibpd) | |
313 | { | |
314 | return container_of(ibpd, struct mthca_pd, ibpd); | |
315 | } | |
316 | ||
317 | static inline struct mthca_ah *to_mah(struct ib_ah *ibah) | |
318 | { | |
319 | return container_of(ibah, struct mthca_ah, ibah); | |
320 | } | |
321 | ||
322 | static inline struct mthca_cq *to_mcq(struct ib_cq *ibcq) | |
323 | { | |
324 | return container_of(ibcq, struct mthca_cq, ibcq); | |
325 | } | |
326 | ||
ec34a922 RD |
327 | static inline struct mthca_srq *to_msrq(struct ib_srq *ibsrq) |
328 | { | |
329 | return container_of(ibsrq, struct mthca_srq, ibsrq); | |
330 | } | |
331 | ||
1da177e4 LT |
332 | static inline struct mthca_qp *to_mqp(struct ib_qp *ibqp) |
333 | { | |
334 | return container_of(ibqp, struct mthca_qp, ibqp); | |
335 | } | |
336 | ||
337 | static inline struct mthca_sqp *to_msqp(struct mthca_qp *qp) | |
338 | { | |
339 | return container_of(qp, struct mthca_sqp, qp); | |
340 | } | |
341 | ||
342 | #endif /* MTHCA_PROVIDER_H */ |