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[IB] uverbs: have kernel return QP capabilities
[deliverable/linux.git] / drivers / infiniband / hw / mthca / mthca_qp.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
80c8ec2c 3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
2a1d9b7f
RD		 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 *
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */
37
38#include <linux/init.h>
4e57b681
TS		 39#include <linux/string.h>
40#include <linux/slab.h>
1da177e4 41
a4d61e84
RD		 42#include <rdma/ib_verbs.h>
43#include <rdma/ib_cache.h>
44#include <rdma/ib_pack.h>
1da177e4
LT		 45
46#include "mthca_dev.h"
47#include "mthca_cmd.h"
48#include "mthca_memfree.h"
c04bc3d1 49#include "mthca_wqe.h"
1da177e4
LT		 50
51enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
80c8ec2c
RD		 55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
1da177e4
LT		 58};
59
60enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69};
70
71enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77};
78
79enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83};
84
85enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100};
101
102struct mthca_qp_path {
97f52eb4
SH		 103 __be32 port_pkey;
104 u8 rnr_retry;
105 u8 g_mylmc;
106 __be16 rlid;
107 u8 ackto;
108 u8 mgid_index;
109 u8 static_rate;
110 u8 hop_limit;
111 __be32 sl_tclass_flowlabel;
112 u8 rgid[16];
1da177e4
LT		 113} __attribute__((packed));
114
115struct mthca_qp_context {
97f52eb4
SH		 116 __be32 flags;
117 __be32 tavor_sched_queue; /* Reserved on Arbel */
118 u8 mtu_msgmax;
119 u8 rq_size_stride; /* Reserved on Tavor */
120 u8 sq_size_stride; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
122 __be32 usr_page;
123 __be32 local_qpn;
124 __be32 remote_qpn;
125 u32 reserved1[2];
1da177e4
LT		 126 struct mthca_qp_path pri_path;
127 struct mthca_qp_path alt_path;
97f52eb4
SH		 128 __be32 rdd;
129 __be32 pd;
130 __be32 wqe_base;
131 __be32 wqe_lkey;
132 __be32 params1;
133 __be32 reserved2;
134 __be32 next_send_psn;
135 __be32 cqn_snd;
136 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
137 __be32 snd_db_index; /* (debugging only entries) */
138 __be32 last_acked_psn;
139 __be32 ssn;
140 __be32 params2;
141 __be32 rnr_nextrecvpsn;
142 __be32 ra_buff_indx;
143 __be32 cqn_rcv;
144 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index; /* (debugging only entries) */
146 __be32 qkey;
147 __be32 srqn;
148 __be32 rmsn;
149 __be16 rq_wqe_counter; /* reserved on Tavor */
150 __be16 sq_wqe_counter; /* reserved on Tavor */
151 u32 reserved3[18];
1da177e4
LT		 152} __attribute__((packed));
153
154struct mthca_qp_param {
97f52eb4
SH		 155 __be32 opt_param_mask;
156 u32 reserved1;
1da177e4 157 struct mthca_qp_context context;
97f52eb4 158 u32 reserved2[62];
1da177e4
LT		 159} __attribute__((packed));
160
161enum {
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
163 MTHCA_QP_OPTPAR_RRE = 1 << 1,
164 MTHCA_QP_OPTPAR_RAE = 1 << 2,
165 MTHCA_QP_OPTPAR_RWE = 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
179};
180
1da177e4
LT		 181static const u8 mthca_opcode[] = {
182 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
183 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
184 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
185 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
186 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
187 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
188 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
189};
190
191static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
192{
193 return qp->qpn >= dev->qp_table.sqp_start &&
194 qp->qpn <= dev->qp_table.sqp_start + 3;
195}
196
197static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
198{
199 return qp->qpn >= dev->qp_table.sqp_start &&
200 qp->qpn <= dev->qp_table.sqp_start + 1;
201}
202
203static void *get_recv_wqe(struct mthca_qp *qp, int n)
204{
205 if (qp->is_direct)
206 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
207 else
208 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
209 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
210}
211
212static void *get_send_wqe(struct mthca_qp *qp, int n)
213{
214 if (qp->is_direct)
215 return qp->queue.direct.buf + qp->send_wqe_offset +
216 (n << qp->sq.wqe_shift);
217 else
218 return qp->queue.page_list[(qp->send_wqe_offset +
219 (n << qp->sq.wqe_shift)) >>
220 PAGE_SHIFT].buf +
221 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
222 (PAGE_SIZE - 1));
223}
224
c9fe2b32
RD		 225static void mthca_wq_init(struct mthca_wq *wq)
226{
227 spin_lock_init(&wq->lock);
228 wq->next_ind = 0;
229 wq->last_comp = wq->max - 1;
230 wq->head = 0;
231 wq->tail = 0;
c9fe2b32
RD		 232}
233
1da177e4
LT		 234void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
235 enum ib_event_type event_type)
236{
237 struct mthca_qp *qp;
238 struct ib_event event;
239
240 spin_lock(&dev->qp_table.lock);
241 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
242 if (qp)
243 atomic_inc(&qp->refcount);
244 spin_unlock(&dev->qp_table.lock);
245
246 if (!qp) {
247 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
248 return;
249 }
250
251 event.device = &dev->ib_dev;
252 event.event = event_type;
253 event.element.qp = &qp->ibqp;
254 if (qp->ibqp.event_handler)
255 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
256
257 if (atomic_dec_and_test(&qp->refcount))
258 wake_up(&qp->wait);
259}
260
261static int to_mthca_state(enum ib_qp_state ib_state)
262{
263 switch (ib_state) {
264 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
265 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
266 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
267 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
268 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
269 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
270 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
271 default: return -1;
272 }
273}
274
275enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
276
277static int to_mthca_st(int transport)
278{
279 switch (transport) {
280 case RC: return MTHCA_QP_ST_RC;
281 case UC: return MTHCA_QP_ST_UC;
282 case UD: return MTHCA_QP_ST_UD;
283 case RD: return MTHCA_QP_ST_RD;
284 case MLX: return MTHCA_QP_ST_MLX;
285 default: return -1;
286 }
287}
288
289static const struct {
290 int trans;
291 u32 req_param[NUM_TRANS];
292 u32 opt_param[NUM_TRANS];
293} state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
294 [IB_QPS_RESET] = {
295 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
296 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
297 [IB_QPS_INIT] = {
298 .trans = MTHCA_TRANS_RST2INIT,
299 .req_param = {
300 [UD] = (IB_QP_PKEY_INDEX |
301 IB_QP_PORT |
302 IB_QP_QKEY),
9e6970b5
RD		 303 [UC] = (IB_QP_PKEY_INDEX |
304 IB_QP_PORT |
305 IB_QP_ACCESS_FLAGS),
1da177e4
LT		 306 [RC] = (IB_QP_PKEY_INDEX |
307 IB_QP_PORT |
308 IB_QP_ACCESS_FLAGS),
309 [MLX] = (IB_QP_PKEY_INDEX |
310 IB_QP_QKEY),
311 },
312 /* bug-for-bug compatibility with VAPI: */
313 .opt_param = {
314 [MLX] = IB_QP_PORT
315 }
316 },
317 },
318 [IB_QPS_INIT] = {
319 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
320 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
321 [IB_QPS_INIT] = {
322 .trans = MTHCA_TRANS_INIT2INIT,
323 .opt_param = {
324 [UD] = (IB_QP_PKEY_INDEX |
325 IB_QP_PORT |
326 IB_QP_QKEY),
9e6970b5
RD		 327 [UC] = (IB_QP_PKEY_INDEX |
328 IB_QP_PORT |
329 IB_QP_ACCESS_FLAGS),
1da177e4
LT		 330 [RC] = (IB_QP_PKEY_INDEX |
331 IB_QP_PORT |
332 IB_QP_ACCESS_FLAGS),
333 [MLX] = (IB_QP_PKEY_INDEX |
334 IB_QP_QKEY),
335 }
336 },
337 [IB_QPS_RTR] = {
338 .trans = MTHCA_TRANS_INIT2RTR,
339 .req_param = {
9e6970b5
RD		 340 [UC] = (IB_QP_AV |
341 IB_QP_PATH_MTU |
342 IB_QP_DEST_QPN |
547e3090 343 IB_QP_RQ_PSN),
1da177e4
LT		 344 [RC] = (IB_QP_AV |
345 IB_QP_PATH_MTU |
346 IB_QP_DEST_QPN |
347 IB_QP_RQ_PSN |
348 IB_QP_MAX_DEST_RD_ATOMIC |
349 IB_QP_MIN_RNR_TIMER),
350 },
351 .opt_param = {
352 [UD] = (IB_QP_PKEY_INDEX |
353 IB_QP_QKEY),
9e6970b5
RD		 354 [UC] = (IB_QP_ALT_PATH |
355 IB_QP_ACCESS_FLAGS |
356 IB_QP_PKEY_INDEX),
1da177e4
LT		 357 [RC] = (IB_QP_ALT_PATH |
358 IB_QP_ACCESS_FLAGS |
359 IB_QP_PKEY_INDEX),
360 [MLX] = (IB_QP_PKEY_INDEX |
361 IB_QP_QKEY),
362 }
363 }
364 },
365 [IB_QPS_RTR] = {
366 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
367 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
368 [IB_QPS_RTS] = {
369 .trans = MTHCA_TRANS_RTR2RTS,
370 .req_param = {
371 [UD] = IB_QP_SQ_PSN,
547e3090 372 [UC] = IB_QP_SQ_PSN,
1da177e4
LT		 373 [RC] = (IB_QP_TIMEOUT |
374 IB_QP_RETRY_CNT |
375 IB_QP_RNR_RETRY |
376 IB_QP_SQ_PSN |
377 IB_QP_MAX_QP_RD_ATOMIC),
378 [MLX] = IB_QP_SQ_PSN,
379 },
380 .opt_param = {
381 [UD] = (IB_QP_CUR_STATE |
382 IB_QP_QKEY),
9e6970b5
RD		 383 [UC] = (IB_QP_CUR_STATE |
384 IB_QP_ALT_PATH |
385 IB_QP_ACCESS_FLAGS |
386 IB_QP_PKEY_INDEX |
387 IB_QP_PATH_MIG_STATE),
1da177e4
LT		 388 [RC] = (IB_QP_CUR_STATE |
389 IB_QP_ALT_PATH |
390 IB_QP_ACCESS_FLAGS |
391 IB_QP_PKEY_INDEX |
392 IB_QP_MIN_RNR_TIMER |
393 IB_QP_PATH_MIG_STATE),
394 [MLX] = (IB_QP_CUR_STATE |
395 IB_QP_QKEY),
396 }
397 }
398 },
399 [IB_QPS_RTS] = {
400 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
401 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
402 [IB_QPS_RTS] = {
403 .trans = MTHCA_TRANS_RTS2RTS,
404 .opt_param = {
405 [UD] = (IB_QP_CUR_STATE |
406 IB_QP_QKEY),
9e6970b5
RD		 407 [UC] = (IB_QP_ACCESS_FLAGS |
408 IB_QP_ALT_PATH |
409 IB_QP_PATH_MIG_STATE),
1da177e4
LT		 410 [RC] = (IB_QP_ACCESS_FLAGS |
411 IB_QP_ALT_PATH |
412 IB_QP_PATH_MIG_STATE |
413 IB_QP_MIN_RNR_TIMER),
414 [MLX] = (IB_QP_CUR_STATE |
415 IB_QP_QKEY),
416 }
417 },
418 [IB_QPS_SQD] = {
419 .trans = MTHCA_TRANS_RTS2SQD,
420 },
421 },
422 [IB_QPS_SQD] = {
423 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
424 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
425 [IB_QPS_RTS] = {
426 .trans = MTHCA_TRANS_SQD2RTS,
427 .opt_param = {
428 [UD] = (IB_QP_CUR_STATE |
429 IB_QP_QKEY),
9e6970b5
RD		 430 [UC] = (IB_QP_CUR_STATE |
431 IB_QP_ALT_PATH |
432 IB_QP_ACCESS_FLAGS |
433 IB_QP_PATH_MIG_STATE),
1da177e4
LT		 434 [RC] = (IB_QP_CUR_STATE |
435 IB_QP_ALT_PATH |
436 IB_QP_ACCESS_FLAGS |
437 IB_QP_MIN_RNR_TIMER |
438 IB_QP_PATH_MIG_STATE),
439 [MLX] = (IB_QP_CUR_STATE |
440 IB_QP_QKEY),
441 }
442 },
443 [IB_QPS_SQD] = {
444 .trans = MTHCA_TRANS_SQD2SQD,
445 .opt_param = {
446 [UD] = (IB_QP_PKEY_INDEX |
447 IB_QP_QKEY),
9e6970b5 448 [UC] = (IB_QP_AV |
9e6970b5
RD		 449 IB_QP_CUR_STATE |
450 IB_QP_ALT_PATH |
451 IB_QP_ACCESS_FLAGS |
452 IB_QP_PKEY_INDEX |
453 IB_QP_PATH_MIG_STATE),
1da177e4
LT		 454 [RC] = (IB_QP_AV |
455 IB_QP_TIMEOUT |
456 IB_QP_RETRY_CNT |
457 IB_QP_RNR_RETRY |
458 IB_QP_MAX_QP_RD_ATOMIC |
459 IB_QP_MAX_DEST_RD_ATOMIC |
460 IB_QP_CUR_STATE |
461 IB_QP_ALT_PATH |
462 IB_QP_ACCESS_FLAGS |
463 IB_QP_PKEY_INDEX |
464 IB_QP_MIN_RNR_TIMER |
465 IB_QP_PATH_MIG_STATE),
466 [MLX] = (IB_QP_PKEY_INDEX |
467 IB_QP_QKEY),
468 }
469 }
470 },
471 [IB_QPS_SQE] = {
472 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
473 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
474 [IB_QPS_RTS] = {
475 .trans = MTHCA_TRANS_SQERR2RTS,
476 .opt_param = {
477 [UD] = (IB_QP_CUR_STATE |
478 IB_QP_QKEY),
547e3090 479 [UC] = IB_QP_CUR_STATE,
1da177e4
LT		 480 [RC] = (IB_QP_CUR_STATE |
481 IB_QP_MIN_RNR_TIMER),
482 [MLX] = (IB_QP_CUR_STATE |
483 IB_QP_QKEY),
484 }
485 }
486 },
487 [IB_QPS_ERR] = {
488 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
489 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
490 }
491};
492
493static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
494 int attr_mask)
495{
496 if (attr_mask & IB_QP_PKEY_INDEX)
497 sqp->pkey_index = attr->pkey_index;
498 if (attr_mask & IB_QP_QKEY)
499 sqp->qkey = attr->qkey;
500 if (attr_mask & IB_QP_SQ_PSN)
501 sqp->send_psn = attr->sq_psn;
502}
503
504static void init_port(struct mthca_dev *dev, int port)
505{
506 int err;
507 u8 status;
508 struct mthca_init_ib_param param;
509
510 memset(&param, 0, sizeof param);
511
da6561c2
RD		 512 param.port_width = dev->limits.port_width_cap;
513 param.vl_cap = dev->limits.vl_cap;
514 param.mtu_cap = dev->limits.mtu_cap;
515 param.gid_cap = dev->limits.gid_table_len;
516 param.pkey_cap = dev->limits.pkey_table_len;
1da177e4
LT		 517
518 err = mthca_INIT_IB(dev, &param, port, &status);
519 if (err)
520 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
521 if (status)
522 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
523}
524
525int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
526{
527 struct mthca_dev *dev = to_mdev(ibqp->device);
528 struct mthca_qp *qp = to_mqp(ibqp);
529 enum ib_qp_state cur_state, new_state;
ed878458 530 struct mthca_mailbox *mailbox;
1da177e4
LT		 531 struct mthca_qp_param *qp_param;
532 struct mthca_qp_context *qp_context;
533 u32 req_param, opt_param;
534 u8 status;
535 int err;
536
537 if (attr_mask & IB_QP_CUR_STATE) {
538 if (attr->cur_qp_state != IB_QPS_RTR &&
539 attr->cur_qp_state != IB_QPS_RTS &&
540 attr->cur_qp_state != IB_QPS_SQD &&
541 attr->cur_qp_state != IB_QPS_SQE)
542 return -EINVAL;
543 else
544 cur_state = attr->cur_qp_state;
545 } else {
546 spin_lock_irq(&qp->sq.lock);
547 spin_lock(&qp->rq.lock);
548 cur_state = qp->state;
549 spin_unlock(&qp->rq.lock);
550 spin_unlock_irq(&qp->sq.lock);
551 }
552
553 if (attr_mask & IB_QP_STATE) {
554 if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
555 return -EINVAL;
556 new_state = attr->qp_state;
557 } else
558 new_state = cur_state;
559
560 if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
561 mthca_dbg(dev, "Illegal QP transition "
562 "%d->%d\n", cur_state, new_state);
563 return -EINVAL;
564 }
565
566 req_param = state_table[cur_state][new_state].req_param[qp->transport];
567 opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
568
569 if ((req_param & attr_mask) != req_param) {
570 mthca_dbg(dev, "QP transition "
571 "%d->%d missing req attr 0x%08x\n",
572 cur_state, new_state,
573 req_param & ~attr_mask);
574 return -EINVAL;
575 }
576
577 if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
578 mthca_dbg(dev, "QP transition (transport %d) "
579 "%d->%d has extra attr 0x%08x\n",
580 qp->transport,
581 cur_state, new_state,
582 attr_mask & ~(req_param | opt_param |
583 IB_QP_STATE));
584 return -EINVAL;
585 }
586
d09e3276
JM		 587 if ((attr_mask & IB_QP_PKEY_INDEX) &&
588 attr->pkey_index >= dev->limits.pkey_table_len) {
589 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
590 attr->pkey_index,dev->limits.pkey_table_len-1);
591 return -EINVAL;
592 }
593
ed878458
RD		 594 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
595 if (IS_ERR(mailbox))
596 return PTR_ERR(mailbox);
597 qp_param = mailbox->buf;
1da177e4
LT		 598 qp_context = &qp_param->context;
599 memset(qp_param, 0, sizeof *qp_param);
600
601 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
602 (to_mthca_st(qp->transport) << 16));
603 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
604 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
605 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
606 else {
607 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
608 switch (attr->path_mig_state) {
609 case IB_MIG_MIGRATED:
610 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
611 break;
612 case IB_MIG_REARM:
613 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
614 break;
615 case IB_MIG_ARMED:
616 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
617 break;
618 }
619 }
620
621 /* leave tavor_sched_queue as 0 */
622
623 if (qp->transport == MLX || qp->transport == UD)
624 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
625 else if (attr_mask & IB_QP_PATH_MTU)
626 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
627
d10ddbf6 628 if (mthca_is_memfree(dev)) {
ec34a922
RD		 629 if (qp->rq.max)
630 qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
631 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
632
633 if (qp->sq.max)
634 qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
635 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
1da177e4
LT		 636 }
637
638 /* leave arbel_sched_queue as 0 */
639
80c8ec2c
RD		 640 if (qp->ibqp.uobject)
641 qp_context->usr_page =
642 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
643 else
644 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
1da177e4
LT		 645 qp_context->local_qpn = cpu_to_be32(qp->qpn);
646 if (attr_mask & IB_QP_DEST_QPN) {
647 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
648 }
649
650 if (qp->transport == MLX)
651 qp_context->pri_path.port_pkey |=
652 cpu_to_be32(to_msqp(qp)->port << 24);
653 else {
654 if (attr_mask & IB_QP_PORT) {
655 qp_context->pri_path.port_pkey |=
656 cpu_to_be32(attr->port_num << 24);
657 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
658 }
659 }
660
661 if (attr_mask & IB_QP_PKEY_INDEX) {
662 qp_context->pri_path.port_pkey |=
663 cpu_to_be32(attr->pkey_index);
664 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
665 }
666
667 if (attr_mask & IB_QP_RNR_RETRY) {
668 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
669 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
670 }
671
672 if (attr_mask & IB_QP_AV) {
673 qp_context->pri_path.g_mylmc = attr->ah_attr.src_path_bits & 0x7f;
674 qp_context->pri_path.rlid = cpu_to_be16(attr->ah_attr.dlid);
cd123d7f 675 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
1da177e4
LT		 676 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
677 qp_context->pri_path.g_mylmc |= 1 << 7;
678 qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
679 qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
680 qp_context->pri_path.sl_tclass_flowlabel =
681 cpu_to_be32((attr->ah_attr.sl << 28) |
682 (attr->ah_attr.grh.traffic_class << 20) |
683 (attr->ah_attr.grh.flow_label));
684 memcpy(qp_context->pri_path.rgid,
685 attr->ah_attr.grh.dgid.raw, 16);
686 } else {
687 qp_context->pri_path.sl_tclass_flowlabel =
688 cpu_to_be32(attr->ah_attr.sl << 28);
689 }
690 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
691 }
692
693 if (attr_mask & IB_QP_TIMEOUT) {
bb4a7f0d 694 qp_context->pri_path.ackto = attr->timeout << 3;
1da177e4
LT		 695 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
696 }
697
698 /* XXX alt_path */
699
700 /* leave rdd as 0 */
701 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
702 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
703 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
704 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
705 (MTHCA_FLIGHT_LIMIT << 24) |
706 MTHCA_QP_BIT_SRE |
707 MTHCA_QP_BIT_SWE |
708 MTHCA_QP_BIT_SAE);
709 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
710 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
711 if (attr_mask & IB_QP_RETRY_CNT) {
712 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
713 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
714 }
715
34a4a753
RD		 716 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
717 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
718 ffs(attr->max_rd_atomic) - 1 : 0,
1da177e4
LT		 719 7) << 21);
720 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
721 }
722
723 if (attr_mask & IB_QP_SQ_PSN)
724 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
725 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
726
d10ddbf6 727 if (mthca_is_memfree(dev)) {
1da177e4
LT		 728 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
729 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
730 }
731
732 if (attr_mask & IB_QP_ACCESS_FLAGS) {
733 /*
734 * Only enable RDMA/atomics if we have responder
735 * resources set to a non-zero value.
736 */
737 if (qp->resp_depth) {
738 qp_context->params2 |=
739 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
740 MTHCA_QP_BIT_RWE : 0);
741 qp_context->params2 |=
742 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
743 MTHCA_QP_BIT_RRE : 0);
744 qp_context->params2 |=
745 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
746 MTHCA_QP_BIT_RAE : 0);
747 }
748
749 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
750 MTHCA_QP_OPTPAR_RRE |
751 MTHCA_QP_OPTPAR_RAE);
752
753 qp->atomic_rd_en = attr->qp_access_flags;
754 }
755
34a4a753 756 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1da177e4
LT		 757 u8 rra_max;
758
34a4a753 759 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
1da177e4
LT		 760 /*
761 * Lowering our responder resources to zero.
762 * Turn off RDMA/atomics as responder.
763 * (RWE/RRE/RAE in params2 already zero)
764 */
765 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
766 MTHCA_QP_OPTPAR_RRE |
767 MTHCA_QP_OPTPAR_RAE);
768 }
769
34a4a753 770 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
1da177e4
LT		 771 /*
772 * Increasing our responder resources from
773 * zero. Turn on RDMA/atomics as appropriate.
774 */
775 qp_context->params2 |=
776 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
777 MTHCA_QP_BIT_RWE : 0);
778 qp_context->params2 |=
779 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
780 MTHCA_QP_BIT_RRE : 0);
781 qp_context->params2 |=
782 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
783 MTHCA_QP_BIT_RAE : 0);
784
785 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
786 MTHCA_QP_OPTPAR_RRE |
787 MTHCA_QP_OPTPAR_RAE);
788 }
789
790 for (rra_max = 0;
34a4a753 791 1 << rra_max < attr->max_dest_rd_atomic &&
1da177e4
LT		 792 rra_max < dev->qp_table.rdb_shift;
793 ++rra_max)
794 ; /* nothing */
795
796 qp_context->params2 |= cpu_to_be32(rra_max << 21);
797 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
798
34a4a753 799 qp->resp_depth = attr->max_dest_rd_atomic;
1da177e4
LT		 800 }
801
802 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
803
ec34a922
RD		 804 if (ibqp->srq)
805 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
806
1da177e4
LT		 807 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
808 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
809 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
810 }
811 if (attr_mask & IB_QP_RQ_PSN)
812 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
813
814 qp_context->ra_buff_indx =
815 cpu_to_be32(dev->qp_table.rdb_base +
816 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
817 dev->qp_table.rdb_shift));
818
819 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
820
d10ddbf6 821 if (mthca_is_memfree(dev))
1da177e4
LT		 822 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
823
824 if (attr_mask & IB_QP_QKEY) {
825 qp_context->qkey = cpu_to_be32(attr->qkey);
826 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
827 }
828
ec34a922
RD		 829 if (ibqp->srq)
830 qp_context->srqn = cpu_to_be32(1 << 24 |
831 to_msrq(ibqp->srq)->srqn);
832
1da177e4 833 err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
ed878458 834 qp->qpn, 0, mailbox, 0, &status);
1da177e4
LT		 835 if (status) {
836 mthca_warn(dev, "modify QP %d returned status %02x.\n",
837 state_table[cur_state][new_state].trans, status);
838 err = -EINVAL;
839 }
840
841 if (!err)
842 qp->state = new_state;
843
ed878458 844 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 845
846 if (is_sqp(dev, qp))
847 store_attrs(to_msqp(qp), attr, attr_mask);
848
849 /*
c9fe2b32
RD		 850 * If we moved QP0 to RTR, bring the IB link up; if we moved
851 * QP0 to RESET or ERROR, bring the link back down.
1da177e4
LT		 852 */
853 if (is_qp0(dev, qp)) {
854 if (cur_state != IB_QPS_RTR &&
855 new_state == IB_QPS_RTR)
856 init_port(dev, to_msqp(qp)->port);
857
858 if (cur_state != IB_QPS_RESET &&
859 cur_state != IB_QPS_ERR &&
860 (new_state == IB_QPS_RESET ||
861 new_state == IB_QPS_ERR))
862 mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
863 }
864
c9fe2b32
RD		 865 /*
866 * If we moved a kernel QP to RESET, clean up all old CQ
867 * entries and reinitialize the QP.
868 */
869 if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
870 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
871 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
872 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
873 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
874 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
875
876 mthca_wq_init(&qp->sq);
877 mthca_wq_init(&qp->rq);
878
879 if (mthca_is_memfree(dev)) {
880 *qp->sq.db = 0;
881 *qp->rq.db = 0;
882 }
883 }
884
1da177e4
LT		 885 return err;
886}
887
77369ed3
JM		 888static void mthca_adjust_qp_caps(struct mthca_dev *dev,
889 struct mthca_pd *pd,
890 struct mthca_qp *qp)
891{
892 int max_data_size;
893
894 /*
895 * Calculate the maximum size of WQE s/g segments, excluding
896 * the next segment and other non-data segments.
897 */
898 max_data_size = min(dev->limits.max_desc_sz, 1 << qp->sq.wqe_shift) -
899 sizeof (struct mthca_next_seg);
900
901 switch (qp->transport) {
902 case MLX:
903 max_data_size -= 2 * sizeof (struct mthca_data_seg);
904 break;
905
906 case UD:
907 if (mthca_is_memfree(dev))
908 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
909 else
910 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
911 break;
912
913 default:
914 max_data_size -= sizeof (struct mthca_raddr_seg);
915 break;
916 }
917
918 /* We don't support inline data for kernel QPs (yet). */
919 if (!pd->ibpd.uobject)
920 qp->max_inline_data = 0;
921 else
922 qp->max_inline_data = max_data_size - MTHCA_INLINE_HEADER_SIZE;
923
924 qp->sq.max_gs = max_data_size / sizeof (struct mthca_data_seg);
925 qp->rq.max_gs = (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
926 sizeof (struct mthca_next_seg)) /
927 sizeof (struct mthca_data_seg);
928}
929
1da177e4
LT		 930/*
931 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
932 * rq.max_gs and sq.max_gs must all be assigned.
933 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
934 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
935 * queue)
936 */
937static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
938 struct mthca_pd *pd,
939 struct mthca_qp *qp)
940{
941 int size;
1da177e4
LT		 942 int err = -ENOMEM;
943
944 size = sizeof (struct mthca_next_seg) +
945 qp->rq.max_gs * sizeof (struct mthca_data_seg);
946
77369ed3
JM		 947 if (size > dev->limits.max_desc_sz)
948 return -EINVAL;
949
1da177e4
LT		 950 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
951 qp->rq.wqe_shift++)
952 ; /* nothing */
953
77369ed3 954 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1da177e4
LT		 955 switch (qp->transport) {
956 case MLX:
957 size += 2 * sizeof (struct mthca_data_seg);
958 break;
77369ed3 959
1da177e4 960 case UD:
77369ed3
JM		 961 size += mthca_is_memfree(dev) ?
962 sizeof (struct mthca_arbel_ud_seg) :
963 sizeof (struct mthca_tavor_ud_seg);
1da177e4 964 break;
77369ed3
JM		 965
966 case UC:
967 size += sizeof (struct mthca_raddr_seg);
968 break;
969
970 case RC:
971 size += sizeof (struct mthca_raddr_seg);
972 /*
973 * An atomic op will require an atomic segment, a
974 * remote address segment and one scatter entry.
975 */
976 size = max_t(int, size,
977 sizeof (struct mthca_atomic_seg) +
978 sizeof (struct mthca_raddr_seg) +
979 sizeof (struct mthca_data_seg));
980 break;
981
1da177e4 982 default:
77369ed3 983 break;
1da177e4
LT		 984 }
985
77369ed3
JM		 986 /* Make sure that we have enough space for a bind request */
987 size = max_t(int, size, sizeof (struct mthca_bind_seg));
988
989 size += sizeof (struct mthca_next_seg);
990
991 if (size > dev->limits.max_desc_sz)
992 return -EINVAL;
993
1da177e4
LT		 994 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
995 qp->sq.wqe_shift++)
996 ; /* nothing */
997
998 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
999 1 << qp->sq.wqe_shift);
80c8ec2c
RD		 1000
1001 /*
1002 * If this is a userspace QP, we don't actually have to
1003 * allocate anything. All we need is to calculate the WQE
1004 * sizes and the send_wqe_offset, so we're done now.
1005 */
1006 if (pd->ibpd.uobject)
1007 return 0;
1008
1da177e4
LT		 1009 size = PAGE_ALIGN(qp->send_wqe_offset +
1010 (qp->sq.max << qp->sq.wqe_shift));
1011
1012 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1013 GFP_KERNEL);
1014 if (!qp->wrid)
1015 goto err_out;
1016
87b81670
RD		 1017 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1018 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1da177e4 1019 if (err)
87b81670 1020 goto err_out;
1da177e4 1021
1da177e4
LT		 1022 return 0;
1023
87b81670 1024err_out:
1da177e4 1025 kfree(qp->wrid);
1da177e4
LT		 1026 return err;
1027}
1028
80c8ec2c 1029static void mthca_free_wqe_buf(struct mthca_dev *dev,
1da177e4
LT		 1030 struct mthca_qp *qp)
1031{
87b81670
RD		 1032 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1033 (qp->sq.max << qp->sq.wqe_shift)),
1034 &qp->queue, qp->is_direct, &qp->mr);
80c8ec2c
RD		 1035 kfree(qp->wrid);
1036}
1037
1038static int mthca_map_memfree(struct mthca_dev *dev,
1039 struct mthca_qp *qp)
1040{
1041 int ret;
1da177e4 1042
d10ddbf6 1043 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1044 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1045 if (ret)
1046 return ret;
1047
1048 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1049 if (ret)
1050 goto err_qpc;
1051
80c8ec2c
RD		 1052 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1053 qp->qpn << dev->qp_table.rdb_shift);
1054 if (ret)
1055 goto err_eqpc;
1da177e4 1056
1da177e4
LT		 1057 }
1058
1059 return 0;
1060
1da177e4
LT		 1061err_eqpc:
1062 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1063
1064err_qpc:
1065 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1066
1067 return ret;
1068}
1069
80c8ec2c
RD		 1070static void mthca_unmap_memfree(struct mthca_dev *dev,
1071 struct mthca_qp *qp)
1072{
1073 mthca_table_put(dev, dev->qp_table.rdb_table,
1074 qp->qpn << dev->qp_table.rdb_shift);
1075 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1076 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1077}
1078
1079static int mthca_alloc_memfree(struct mthca_dev *dev,
1080 struct mthca_qp *qp)
1081{
1082 int ret = 0;
1083
1084 if (mthca_is_memfree(dev)) {
1085 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1086 qp->qpn, &qp->rq.db);
1087 if (qp->rq.db_index < 0)
1088 return ret;
1089
1090 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1091 qp->qpn, &qp->sq.db);
1092 if (qp->sq.db_index < 0)
1093 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1094 }
1095
1096 return ret;
1097}
1098
1da177e4
LT		 1099static void mthca_free_memfree(struct mthca_dev *dev,
1100 struct mthca_qp *qp)
1101{
d10ddbf6 1102 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1103 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1104 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1da177e4
LT		 1105 }
1106}
1107
1da177e4
LT		 1108static int mthca_alloc_qp_common(struct mthca_dev *dev,
1109 struct mthca_pd *pd,
1110 struct mthca_cq *send_cq,
1111 struct mthca_cq *recv_cq,
1112 enum ib_sig_type send_policy,
1113 struct mthca_qp *qp)
1114{
1da177e4
LT		 1115 int ret;
1116 int i;
1117
1118 atomic_set(&qp->refcount, 1);
30a7e8ef 1119 init_waitqueue_head(&qp->wait);
1da177e4
LT		 1120 qp->state = IB_QPS_RESET;
1121 qp->atomic_rd_en = 0;
1122 qp->resp_depth = 0;
1123 qp->sq_policy = send_policy;
1124 mthca_wq_init(&qp->sq);
1125 mthca_wq_init(&qp->rq);
1126
80c8ec2c 1127 ret = mthca_map_memfree(dev, qp);
1da177e4
LT		 1128 if (ret)
1129 return ret;
1130
1131 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1132 if (ret) {
80c8ec2c
RD		 1133 mthca_unmap_memfree(dev, qp);
1134 return ret;
1135 }
1136
77369ed3
JM		 1137 mthca_adjust_qp_caps(dev, pd, qp);
1138
80c8ec2c
RD		 1139 /*
1140 * If this is a userspace QP, we're done now. The doorbells
1141 * will be allocated and buffers will be initialized in
1142 * userspace.
1143 */
1144 if (pd->ibpd.uobject)
1145 return 0;
1146
1147 ret = mthca_alloc_memfree(dev, qp);
1148 if (ret) {
1149 mthca_free_wqe_buf(dev, qp);
1150 mthca_unmap_memfree(dev, qp);
1da177e4
LT		 1151 return ret;
1152 }
1153
d10ddbf6 1154 if (mthca_is_memfree(dev)) {
ddf841f0
RD		 1155 struct mthca_next_seg *next;
1156 struct mthca_data_seg *scatter;
1157 int size = (sizeof (struct mthca_next_seg) +
1158 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1159
1da177e4 1160 for (i = 0; i < qp->rq.max; ++i) {
ddf841f0
RD		 1161 next = get_recv_wqe(qp, i);
1162 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1163 qp->rq.wqe_shift);
1164 next->ee_nds = cpu_to_be32(size);
1165
1166 for (scatter = (void *) (next + 1);
1167 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1168 ++scatter)
1169 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1da177e4
LT		 1170 }
1171
1172 for (i = 0; i < qp->sq.max; ++i) {
ddf841f0
RD		 1173 next = get_send_wqe(qp, i);
1174 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1175 qp->sq.wqe_shift) +
1176 qp->send_wqe_offset);
1da177e4
LT		 1177 }
1178 }
1179
d6cff021
RD		 1180 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1181 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1182
1da177e4
LT		 1183 return 0;
1184}
1185
80c8ec2c
RD		 1186static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1187 struct mthca_qp *qp)
1da177e4 1188{
80c8ec2c 1189 /* Sanity check QP size before proceeding */
efaae8f7
JM		 1190 if (cap->max_send_wr > dev->limits.max_wqes ||
1191 cap->max_recv_wr > dev->limits.max_wqes ||
1192 cap->max_send_sge > dev->limits.max_sg ||
1193 cap->max_recv_sge > dev->limits.max_sg)
80c8ec2c 1194 return -EINVAL;
1da177e4 1195
80c8ec2c
RD		 1196 if (mthca_is_memfree(dev)) {
1197 qp->rq.max = cap->max_recv_wr ?
1198 roundup_pow_of_two(cap->max_recv_wr) : 0;
1199 qp->sq.max = cap->max_send_wr ?
1200 roundup_pow_of_two(cap->max_send_wr) : 0;
1201 } else {
1202 qp->rq.max = cap->max_recv_wr;
1203 qp->sq.max = cap->max_send_wr;
1204 }
1da177e4 1205
80c8ec2c
RD		 1206 qp->rq.max_gs = cap->max_recv_sge;
1207 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1208 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1209 MTHCA_INLINE_CHUNK_SIZE) /
1210 sizeof (struct mthca_data_seg));
1da177e4 1211
80c8ec2c
RD		 1212 /*
1213 * For MLX transport we need 2 extra S/G entries:
1214 * one for the header and one for the checksum at the end
1215 */
1216 if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1217 qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1218 return -EINVAL;
1da177e4 1219
80c8ec2c 1220 return 0;
1da177e4
LT		 1221}
1222
1223int mthca_alloc_qp(struct mthca_dev *dev,
1224 struct mthca_pd *pd,
1225 struct mthca_cq *send_cq,
1226 struct mthca_cq *recv_cq,
1227 enum ib_qp_type type,
1228 enum ib_sig_type send_policy,
80c8ec2c 1229 struct ib_qp_cap *cap,
1da177e4
LT		 1230 struct mthca_qp *qp)
1231{
1232 int err;
1233
80c8ec2c
RD		 1234 err = mthca_set_qp_size(dev, cap, qp);
1235 if (err)
1236 return err;
1da177e4
LT		 1237
1238 switch (type) {
1239 case IB_QPT_RC: qp->transport = RC; break;
1240 case IB_QPT_UC: qp->transport = UC; break;
1241 case IB_QPT_UD: qp->transport = UD; break;
1242 default: return -EINVAL;
1243 }
1244
1245 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1246 if (qp->qpn == -1)
1247 return -ENOMEM;
1248
1249 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1250 send_policy, qp);
1251 if (err) {
1252 mthca_free(&dev->qp_table.alloc, qp->qpn);
1253 return err;
1254 }
1255
1256 spin_lock_irq(&dev->qp_table.lock);
1257 mthca_array_set(&dev->qp_table.qp,
1258 qp->qpn & (dev->limits.num_qps - 1), qp);
1259 spin_unlock_irq(&dev->qp_table.lock);
1260
1261 return 0;
1262}
1263
1264int mthca_alloc_sqp(struct mthca_dev *dev,
1265 struct mthca_pd *pd,
1266 struct mthca_cq *send_cq,
1267 struct mthca_cq *recv_cq,
1268 enum ib_sig_type send_policy,
80c8ec2c 1269 struct ib_qp_cap *cap,
1da177e4
LT		 1270 int qpn,
1271 int port,
1272 struct mthca_sqp *sqp)
1273{
1da177e4 1274 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
80c8ec2c 1275 int err;
1da177e4 1276
80c8ec2c
RD		 1277 err = mthca_set_qp_size(dev, cap, &sqp->qp);
1278 if (err)
1279 return err;
1da177e4
LT		 1280
1281 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1282 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1283 &sqp->header_dma, GFP_KERNEL);
1284 if (!sqp->header_buf)
1285 return -ENOMEM;
1286
1287 spin_lock_irq(&dev->qp_table.lock);
1288 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1289 err = -EBUSY;
1290 else
1291 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1292 spin_unlock_irq(&dev->qp_table.lock);
1293
1294 if (err)
1295 goto err_out;
1296
1297 sqp->port = port;
1298 sqp->qp.qpn = mqpn;
1299 sqp->qp.transport = MLX;
1300
1301 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1302 send_policy, &sqp->qp);
1303 if (err)
1304 goto err_out_free;
1305
1306 atomic_inc(&pd->sqp_count);
1307
1308 return 0;
1309
1310 err_out_free:
1311 /*
1312 * Lock CQs here, so that CQ polling code can do QP lookup
1313 * without taking a lock.
1314 */
1315 spin_lock_irq(&send_cq->lock);
1316 if (send_cq != recv_cq)
1317 spin_lock(&recv_cq->lock);
1318
1319 spin_lock(&dev->qp_table.lock);
1320 mthca_array_clear(&dev->qp_table.qp, mqpn);
1321 spin_unlock(&dev->qp_table.lock);
1322
1323 if (send_cq != recv_cq)
1324 spin_unlock(&recv_cq->lock);
1325 spin_unlock_irq(&send_cq->lock);
1326
1327 err_out:
1328 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1329 sqp->header_buf, sqp->header_dma);
1330
1331 return err;
1332}
1333
1334void mthca_free_qp(struct mthca_dev *dev,
1335 struct mthca_qp *qp)
1336{
1337 u8 status;
1da177e4
LT		 1338 struct mthca_cq *send_cq;
1339 struct mthca_cq *recv_cq;
1340
1341 send_cq = to_mcq(qp->ibqp.send_cq);
1342 recv_cq = to_mcq(qp->ibqp.recv_cq);
1343
1344 /*
1345 * Lock CQs here, so that CQ polling code can do QP lookup
1346 * without taking a lock.
1347 */
1348 spin_lock_irq(&send_cq->lock);
1349 if (send_cq != recv_cq)
1350 spin_lock(&recv_cq->lock);
1351
1352 spin_lock(&dev->qp_table.lock);
1353 mthca_array_clear(&dev->qp_table.qp,
1354 qp->qpn & (dev->limits.num_qps - 1));
1355 spin_unlock(&dev->qp_table.lock);
1356
1357 if (send_cq != recv_cq)
1358 spin_unlock(&recv_cq->lock);
1359 spin_unlock_irq(&send_cq->lock);
1360
1361 atomic_dec(&qp->refcount);
1362 wait_event(qp->wait, !atomic_read(&qp->refcount));
1363
1364 if (qp->state != IB_QPS_RESET)
1365 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1366
80c8ec2c
RD		 1367 /*
1368 * If this is a userspace QP, the buffers, MR, CQs and so on
1369 * will be cleaned up in userspace, so all we have to do is
1370 * unref the mem-free tables and free the QPN in our table.
1371 */
1372 if (!qp->ibqp.uobject) {
ec34a922
RD		 1373 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1374 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
80c8ec2c 1375 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
ec34a922
RD		 1376 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1377 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1da177e4 1378
80c8ec2c
RD		 1379 mthca_free_memfree(dev, qp);
1380 mthca_free_wqe_buf(dev, qp);
1da177e4
LT		 1381 }
1382
80c8ec2c 1383 mthca_unmap_memfree(dev, qp);
1da177e4
LT		 1384
1385 if (is_sqp(dev, qp)) {
1386 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1387 dma_free_coherent(&dev->pdev->dev,
1388 to_msqp(qp)->header_buf_size,
1389 to_msqp(qp)->header_buf,
1390 to_msqp(qp)->header_dma);
1391 } else
1392 mthca_free(&dev->qp_table.alloc, qp->qpn);
1393}
1394
1395/* Create UD header for an MLX send and build a data segment for it */
1396static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1397 int ind, struct ib_send_wr *wr,
1398 struct mthca_mlx_seg *mlx,
1399 struct mthca_data_seg *data)
1400{
1401 int header_size;
1402 int err;
97f52eb4 1403 u16 pkey;
1da177e4
LT		 1404
1405 ib_ud_header_init(256, /* assume a MAD */
1406 sqp->ud_header.grh_present,
1407 &sqp->ud_header);
1408
1409 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1410 if (err)
1411 return err;
1412 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1413 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
97f52eb4
SH		 1414 (sqp->ud_header.lrh.destination_lid ==
1415 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1da177e4
LT		 1416 (sqp->ud_header.lrh.service_level << 8));
1417 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1418 mlx->vcrc = 0;
1419
1420 switch (wr->opcode) {
1421 case IB_WR_SEND:
1422 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1423 sqp->ud_header.immediate_present = 0;
1424 break;
1425 case IB_WR_SEND_WITH_IMM:
1426 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1427 sqp->ud_header.immediate_present = 1;
1428 sqp->ud_header.immediate_data = wr->imm_data;
1429 break;
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
97f52eb4
SH		 1435 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1436 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1da177e4
LT		 1437 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1438 if (!sqp->qp.ibqp.qp_num)
1439 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
97f52eb4 1440 sqp->pkey_index, &pkey);
1da177e4
LT		 1441 else
1442 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
97f52eb4
SH		 1443 wr->wr.ud.pkey_index, &pkey);
1444 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1da177e4
LT		 1445 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1446 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1447 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1448 sqp->qkey : wr->wr.ud.remote_qkey);
1449 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1450
1451 header_size = ib_ud_header_pack(&sqp->ud_header,
1452 sqp->header_buf +
1453 ind * MTHCA_UD_HEADER_SIZE);
1454
1455 data->byte_count = cpu_to_be32(header_size);
1456 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1457 data->addr = cpu_to_be64(sqp->header_dma +
1458 ind * MTHCA_UD_HEADER_SIZE);
1459
1460 return 0;
1461}
1462
1463static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1464 struct ib_cq *ib_cq)
1465{
1466 unsigned cur;
1467 struct mthca_cq *cq;
1468
1469 cur = wq->head - wq->tail;
1470 if (likely(cur + nreq < wq->max))
1471 return 0;
1472
1473 cq = to_mcq(ib_cq);
1474 spin_lock(&cq->lock);
1475 cur = wq->head - wq->tail;
1476 spin_unlock(&cq->lock);
1477
1478 return cur + nreq >= wq->max;
1479}
1480
1481int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1482 struct ib_send_wr **bad_wr)
1483{
1484 struct mthca_dev *dev = to_mdev(ibqp->device);
1485 struct mthca_qp *qp = to_mqp(ibqp);
1486 void *wqe;
1487 void *prev_wqe;
1488 unsigned long flags;
1489 int err = 0;
1490 int nreq;
1491 int i;
1492 int size;
1493 int size0 = 0;
1494 u32 f0 = 0;
1495 int ind;
1496 u8 op0 = 0;
1497
1498 spin_lock_irqsave(&qp->sq.lock, flags);
1499
1500 /* XXX check that state is OK to post send */
1501
1502 ind = qp->sq.next_ind;
1503
1504 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1505 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1506 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1507 " %d max, %d nreq)\n", qp->qpn,
1508 qp->sq.head, qp->sq.tail,
1509 qp->sq.max, nreq);
1510 err = -ENOMEM;
1511 *bad_wr = wr;
1512 goto out;
1513 }
1514
1515 wqe = get_send_wqe(qp, ind);
1516 prev_wqe = qp->sq.last;
1517 qp->sq.last = wqe;
1518
1519 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1520 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1521 ((struct mthca_next_seg *) wqe)->flags =
1522 ((wr->send_flags & IB_SEND_SIGNALED) ?
1523 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1524 ((wr->send_flags & IB_SEND_SOLICITED) ?
1525 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1526 cpu_to_be32(1);
1527 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1528 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
3fba2317 1529 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1da177e4
LT		 1530
1531 wqe += sizeof (struct mthca_next_seg);
1532 size = sizeof (struct mthca_next_seg) / 16;
1533
1534 switch (qp->transport) {
1535 case RC:
1536 switch (wr->opcode) {
1537 case IB_WR_ATOMIC_CMP_AND_SWP:
1538 case IB_WR_ATOMIC_FETCH_AND_ADD:
1539 ((struct mthca_raddr_seg *) wqe)->raddr =
1540 cpu_to_be64(wr->wr.atomic.remote_addr);
1541 ((struct mthca_raddr_seg *) wqe)->rkey =
1542 cpu_to_be32(wr->wr.atomic.rkey);
1543 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1544
1545 wqe += sizeof (struct mthca_raddr_seg);
1546
1547 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1548 ((struct mthca_atomic_seg *) wqe)->swap_add =
1549 cpu_to_be64(wr->wr.atomic.swap);
1550 ((struct mthca_atomic_seg *) wqe)->compare =
1551 cpu_to_be64(wr->wr.atomic.compare_add);
1552 } else {
1553 ((struct mthca_atomic_seg *) wqe)->swap_add =
1554 cpu_to_be64(wr->wr.atomic.compare_add);
1555 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1556 }
1557
1558 wqe += sizeof (struct mthca_atomic_seg);
1559 size += sizeof (struct mthca_raddr_seg) / 16 +
1560 sizeof (struct mthca_atomic_seg);
1561 break;
1562
1563 case IB_WR_RDMA_WRITE:
1564 case IB_WR_RDMA_WRITE_WITH_IMM:
1565 case IB_WR_RDMA_READ:
1566 ((struct mthca_raddr_seg *) wqe)->raddr =
1567 cpu_to_be64(wr->wr.rdma.remote_addr);
1568 ((struct mthca_raddr_seg *) wqe)->rkey =
1569 cpu_to_be32(wr->wr.rdma.rkey);
1570 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1571 wqe += sizeof (struct mthca_raddr_seg);
1572 size += sizeof (struct mthca_raddr_seg) / 16;
1573 break;
1574
1575 default:
1576 /* No extra segments required for sends */
1577 break;
1578 }
1579
1580 break;
1581
9e6970b5
RD		 1582 case UC:
1583 switch (wr->opcode) {
1584 case IB_WR_RDMA_WRITE:
1585 case IB_WR_RDMA_WRITE_WITH_IMM:
1586 ((struct mthca_raddr_seg *) wqe)->raddr =
1587 cpu_to_be64(wr->wr.rdma.remote_addr);
1588 ((struct mthca_raddr_seg *) wqe)->rkey =
1589 cpu_to_be32(wr->wr.rdma.rkey);
1590 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1591 wqe += sizeof (struct mthca_raddr_seg);
1592 size += sizeof (struct mthca_raddr_seg) / 16;
1593 break;
1594
1595 default:
1596 /* No extra segments required for sends */
1597 break;
1598 }
1599
1600 break;
1601
1da177e4
LT		 1602 case UD:
1603 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1604 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1605 ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1606 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1607 ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1608 cpu_to_be32(wr->wr.ud.remote_qpn);
1609 ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1610 cpu_to_be32(wr->wr.ud.remote_qkey);
1611
1612 wqe += sizeof (struct mthca_tavor_ud_seg);
1613 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1614 break;
1615
1616 case MLX:
1617 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1618 wqe - sizeof (struct mthca_next_seg),
1619 wqe);
1620 if (err) {
1621 *bad_wr = wr;
1622 goto out;
1623 }
1624 wqe += sizeof (struct mthca_data_seg);
1625 size += sizeof (struct mthca_data_seg) / 16;
1626 break;
1627 }
1628
1629 if (wr->num_sge > qp->sq.max_gs) {
1630 mthca_err(dev, "too many gathers\n");
1631 err = -EINVAL;
1632 *bad_wr = wr;
1633 goto out;
1634 }
1635
1636 for (i = 0; i < wr->num_sge; ++i) {
1637 ((struct mthca_data_seg *) wqe)->byte_count =
1638 cpu_to_be32(wr->sg_list[i].length);
1639 ((struct mthca_data_seg *) wqe)->lkey =
1640 cpu_to_be32(wr->sg_list[i].lkey);
1641 ((struct mthca_data_seg *) wqe)->addr =
1642 cpu_to_be64(wr->sg_list[i].addr);
1643 wqe += sizeof (struct mthca_data_seg);
1644 size += sizeof (struct mthca_data_seg) / 16;
1645 }
1646
1647 /* Add one more inline data segment for ICRC */
1648 if (qp->transport == MLX) {
1649 ((struct mthca_data_seg *) wqe)->byte_count =
1650 cpu_to_be32((1 << 31) | 4);
1651 ((u32 *) wqe)[1] = 0;
1652 wqe += sizeof (struct mthca_data_seg);
1653 size += sizeof (struct mthca_data_seg) / 16;
1654 }
1655
1656 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1657
1658 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1659 mthca_err(dev, "opcode invalid\n");
1660 err = -EINVAL;
1661 *bad_wr = wr;
1662 goto out;
1663 }
1664
d6cff021
RD		 1665 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1666 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1667 qp->send_wqe_offset) |
1668 mthca_opcode[wr->opcode]);
1669 wmb();
1670 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1671 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1da177e4
LT		 1672
1673 if (!size0) {
1674 size0 = size;
1675 op0 = mthca_opcode[wr->opcode];
1676 }
1677
1678 ++ind;
1679 if (unlikely(ind >= qp->sq.max))
1680 ind -= qp->sq.max;
1681 }
1682
1683out:
1684 if (likely(nreq)) {
97f52eb4 1685 __be32 doorbell[2];
1da177e4
LT		 1686
1687 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1688 qp->send_wqe_offset) | f0 | op0);
1689 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1690
1691 wmb();
1692
1693 mthca_write64(doorbell,
1694 dev->kar + MTHCA_SEND_DOORBELL,
1695 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1696 }
1697
1698 qp->sq.next_ind = ind;
1699 qp->sq.head += nreq;
1700
1701 spin_unlock_irqrestore(&qp->sq.lock, flags);
1702 return err;
1703}
1704
1705int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1706 struct ib_recv_wr **bad_wr)
1707{
1708 struct mthca_dev *dev = to_mdev(ibqp->device);
1709 struct mthca_qp *qp = to_mqp(ibqp);
1710 unsigned long flags;
1711 int err = 0;
1712 int nreq;
1713 int i;
1714 int size;
1715 int size0 = 0;
1716 int ind;
1717 void *wqe;
1718 void *prev_wqe;
1719
1720 spin_lock_irqsave(&qp->rq.lock, flags);
1721
1722 /* XXX check that state is OK to post receive */
1723
1724 ind = qp->rq.next_ind;
1725
1726 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1727 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1728 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1729 " %d max, %d nreq)\n", qp->qpn,
1730 qp->rq.head, qp->rq.tail,
1731 qp->rq.max, nreq);
1732 err = -ENOMEM;
1733 *bad_wr = wr;
1734 goto out;
1735 }
1736
1737 wqe = get_recv_wqe(qp, ind);
1738 prev_wqe = qp->rq.last;
1739 qp->rq.last = wqe;
1740
1741 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1742 ((struct mthca_next_seg *) wqe)->ee_nds =
1743 cpu_to_be32(MTHCA_NEXT_DBD);
1744 ((struct mthca_next_seg *) wqe)->flags = 0;
1745
1746 wqe += sizeof (struct mthca_next_seg);
1747 size = sizeof (struct mthca_next_seg) / 16;
1748
1749 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1750 err = -EINVAL;
1751 *bad_wr = wr;
1752 goto out;
1753 }
1754
1755 for (i = 0; i < wr->num_sge; ++i) {
1756 ((struct mthca_data_seg *) wqe)->byte_count =
1757 cpu_to_be32(wr->sg_list[i].length);
1758 ((struct mthca_data_seg *) wqe)->lkey =
1759 cpu_to_be32(wr->sg_list[i].lkey);
1760 ((struct mthca_data_seg *) wqe)->addr =
1761 cpu_to_be64(wr->sg_list[i].addr);
1762 wqe += sizeof (struct mthca_data_seg);
1763 size += sizeof (struct mthca_data_seg) / 16;
1764 }
1765
1766 qp->wrid[ind] = wr->wr_id;
1767
d6cff021
RD		 1768 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1769 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1770 wmb();
1771 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1772 cpu_to_be32(MTHCA_NEXT_DBD | size);
1da177e4
LT		 1773
1774 if (!size0)
1775 size0 = size;
1776
1777 ++ind;
1778 if (unlikely(ind >= qp->rq.max))
1779 ind -= qp->rq.max;
1780 }
1781
1782out:
1783 if (likely(nreq)) {
97f52eb4 1784 __be32 doorbell[2];
1da177e4
LT		 1785
1786 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1787 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1788
1789 wmb();
1790
1791 mthca_write64(doorbell,
1792 dev->kar + MTHCA_RECEIVE_DOORBELL,
1793 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1794 }
1795
1796 qp->rq.next_ind = ind;
1797 qp->rq.head += nreq;
1798
1799 spin_unlock_irqrestore(&qp->rq.lock, flags);
1800 return err;
1801}
1802
1803int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1804 struct ib_send_wr **bad_wr)
1805{
1806 struct mthca_dev *dev = to_mdev(ibqp->device);
1807 struct mthca_qp *qp = to_mqp(ibqp);
1808 void *wqe;
1809 void *prev_wqe;
1810 unsigned long flags;
1811 int err = 0;
1812 int nreq;
1813 int i;
1814 int size;
1815 int size0 = 0;
1816 u32 f0 = 0;
1817 int ind;
1818 u8 op0 = 0;
1819
1820 spin_lock_irqsave(&qp->sq.lock, flags);
1821
1822 /* XXX check that state is OK to post send */
1823
1824 ind = qp->sq.head & (qp->sq.max - 1);
1825
1826 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1827 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1828 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1829 " %d max, %d nreq)\n", qp->qpn,
1830 qp->sq.head, qp->sq.tail,
1831 qp->sq.max, nreq);
1832 err = -ENOMEM;
1833 *bad_wr = wr;
1834 goto out;
1835 }
1836
1837 wqe = get_send_wqe(qp, ind);
1838 prev_wqe = qp->sq.last;
1839 qp->sq.last = wqe;
1840
1841 ((struct mthca_next_seg *) wqe)->flags =
1842 ((wr->send_flags & IB_SEND_SIGNALED) ?
1843 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1844 ((wr->send_flags & IB_SEND_SOLICITED) ?
1845 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1846 cpu_to_be32(1);
1847 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1848 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
3fba2317 1849 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1da177e4
LT		 1850
1851 wqe += sizeof (struct mthca_next_seg);
1852 size = sizeof (struct mthca_next_seg) / 16;
1853
1854 switch (qp->transport) {
ddb934e0
RD		 1855 case RC:
1856 switch (wr->opcode) {
1857 case IB_WR_ATOMIC_CMP_AND_SWP:
1858 case IB_WR_ATOMIC_FETCH_AND_ADD:
1859 ((struct mthca_raddr_seg *) wqe)->raddr =
1860 cpu_to_be64(wr->wr.atomic.remote_addr);
1861 ((struct mthca_raddr_seg *) wqe)->rkey =
1862 cpu_to_be32(wr->wr.atomic.rkey);
1863 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1864
1865 wqe += sizeof (struct mthca_raddr_seg);
1866
1867 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1868 ((struct mthca_atomic_seg *) wqe)->swap_add =
1869 cpu_to_be64(wr->wr.atomic.swap);
1870 ((struct mthca_atomic_seg *) wqe)->compare =
1871 cpu_to_be64(wr->wr.atomic.compare_add);
1872 } else {
1873 ((struct mthca_atomic_seg *) wqe)->swap_add =
1874 cpu_to_be64(wr->wr.atomic.compare_add);
1875 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1876 }
1877
1878 wqe += sizeof (struct mthca_atomic_seg);
1879 size += sizeof (struct mthca_raddr_seg) / 16 +
1880 sizeof (struct mthca_atomic_seg);
1881 break;
1882
9e6970b5
RD		 1883 case IB_WR_RDMA_READ:
1884 case IB_WR_RDMA_WRITE:
1885 case IB_WR_RDMA_WRITE_WITH_IMM:
1886 ((struct mthca_raddr_seg *) wqe)->raddr =
1887 cpu_to_be64(wr->wr.rdma.remote_addr);
1888 ((struct mthca_raddr_seg *) wqe)->rkey =
1889 cpu_to_be32(wr->wr.rdma.rkey);
1890 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1891 wqe += sizeof (struct mthca_raddr_seg);
1892 size += sizeof (struct mthca_raddr_seg) / 16;
1893 break;
1894
1895 default:
1896 /* No extra segments required for sends */
1897 break;
1898 }
1899
1900 break;
1901
1902 case UC:
1903 switch (wr->opcode) {
ddb934e0
RD		 1904 case IB_WR_RDMA_WRITE:
1905 case IB_WR_RDMA_WRITE_WITH_IMM:
ddb934e0
RD		 1906 ((struct mthca_raddr_seg *) wqe)->raddr =
1907 cpu_to_be64(wr->wr.rdma.remote_addr);
1908 ((struct mthca_raddr_seg *) wqe)->rkey =
1909 cpu_to_be32(wr->wr.rdma.rkey);
1910 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1911 wqe += sizeof (struct mthca_raddr_seg);
1912 size += sizeof (struct mthca_raddr_seg) / 16;
1913 break;
1914
1915 default:
1916 /* No extra segments required for sends */
1917 break;
1918 }
1919
1920 break;
1921
1da177e4
LT		 1922 case UD:
1923 memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1924 to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1925 ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1926 cpu_to_be32(wr->wr.ud.remote_qpn);
1927 ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1928 cpu_to_be32(wr->wr.ud.remote_qkey);
1929
1930 wqe += sizeof (struct mthca_arbel_ud_seg);
1931 size += sizeof (struct mthca_arbel_ud_seg) / 16;
1932 break;
1933
1934 case MLX:
1935 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1936 wqe - sizeof (struct mthca_next_seg),
1937 wqe);
1938 if (err) {
1939 *bad_wr = wr;
1940 goto out;
1941 }
1942 wqe += sizeof (struct mthca_data_seg);
1943 size += sizeof (struct mthca_data_seg) / 16;
1944 break;
1945 }
1946
1947 if (wr->num_sge > qp->sq.max_gs) {
1948 mthca_err(dev, "too many gathers\n");
1949 err = -EINVAL;
1950 *bad_wr = wr;
1951 goto out;
1952 }
1953
1954 for (i = 0; i < wr->num_sge; ++i) {
1955 ((struct mthca_data_seg *) wqe)->byte_count =
1956 cpu_to_be32(wr->sg_list[i].length);
1957 ((struct mthca_data_seg *) wqe)->lkey =
1958 cpu_to_be32(wr->sg_list[i].lkey);
1959 ((struct mthca_data_seg *) wqe)->addr =
1960 cpu_to_be64(wr->sg_list[i].addr);
1961 wqe += sizeof (struct mthca_data_seg);
1962 size += sizeof (struct mthca_data_seg) / 16;
1963 }
1964
1965 /* Add one more inline data segment for ICRC */
1966 if (qp->transport == MLX) {
1967 ((struct mthca_data_seg *) wqe)->byte_count =
1968 cpu_to_be32((1 << 31) | 4);
1969 ((u32 *) wqe)[1] = 0;
1970 wqe += sizeof (struct mthca_data_seg);
1971 size += sizeof (struct mthca_data_seg) / 16;
1972 }
1973
1974 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1975
1976 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1977 mthca_err(dev, "opcode invalid\n");
1978 err = -EINVAL;
1979 *bad_wr = wr;
1980 goto out;
1981 }
1982
d6cff021
RD		 1983 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1984 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1985 qp->send_wqe_offset) |
1986 mthca_opcode[wr->opcode]);
1987 wmb();
1988 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1989 cpu_to_be32(MTHCA_NEXT_DBD | size);
1da177e4
LT		 1990
1991 if (!size0) {
1992 size0 = size;
1993 op0 = mthca_opcode[wr->opcode];
1994 }
1995
1996 ++ind;
1997 if (unlikely(ind >= qp->sq.max))
1998 ind -= qp->sq.max;
1999 }
2000
2001out:
2002 if (likely(nreq)) {
97f52eb4 2003 __be32 doorbell[2];
1da177e4
LT		 2004
2005 doorbell[0] = cpu_to_be32((nreq << 24) |
2006 ((qp->sq.head & 0xffff) << 8) |
2007 f0 | op0);
2008 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2009
2010 qp->sq.head += nreq;
2011
2012 /*
2013 * Make sure that descriptors are written before
2014 * doorbell record.
2015 */
2016 wmb();
2017 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2018
2019 /*
2020 * Make sure doorbell record is written before we
2021 * write MMIO send doorbell.
2022 */
2023 wmb();
2024 mthca_write64(doorbell,
2025 dev->kar + MTHCA_SEND_DOORBELL,
2026 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2027 }
2028
2029 spin_unlock_irqrestore(&qp->sq.lock, flags);
2030 return err;
2031}
2032
2033int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2034 struct ib_recv_wr **bad_wr)
2035{
2036 struct mthca_dev *dev = to_mdev(ibqp->device);
2037 struct mthca_qp *qp = to_mqp(ibqp);
2038 unsigned long flags;
2039 int err = 0;
2040 int nreq;
2041 int ind;
2042 int i;
2043 void *wqe;
2044
2045 spin_lock_irqsave(&qp->rq.lock, flags);
2046
2047 /* XXX check that state is OK to post receive */
2048
2049 ind = qp->rq.head & (qp->rq.max - 1);
2050
2051 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2052 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2053 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2054 " %d max, %d nreq)\n", qp->qpn,
2055 qp->rq.head, qp->rq.tail,
2056 qp->rq.max, nreq);
2057 err = -ENOMEM;
2058 *bad_wr = wr;
2059 goto out;
2060 }
2061
2062 wqe = get_recv_wqe(qp, ind);
2063
2064 ((struct mthca_next_seg *) wqe)->flags = 0;
2065
2066 wqe += sizeof (struct mthca_next_seg);
2067
2068 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2069 err = -EINVAL;
2070 *bad_wr = wr;
2071 goto out;
2072 }
2073
2074 for (i = 0; i < wr->num_sge; ++i) {
2075 ((struct mthca_data_seg *) wqe)->byte_count =
2076 cpu_to_be32(wr->sg_list[i].length);
2077 ((struct mthca_data_seg *) wqe)->lkey =
2078 cpu_to_be32(wr->sg_list[i].lkey);
2079 ((struct mthca_data_seg *) wqe)->addr =
2080 cpu_to_be64(wr->sg_list[i].addr);
2081 wqe += sizeof (struct mthca_data_seg);
2082 }
2083
2084 if (i < qp->rq.max_gs) {
2085 ((struct mthca_data_seg *) wqe)->byte_count = 0;
ddf841f0 2086 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1da177e4
LT		 2087 ((struct mthca_data_seg *) wqe)->addr = 0;
2088 }
2089
2090 qp->wrid[ind] = wr->wr_id;
2091
2092 ++ind;
2093 if (unlikely(ind >= qp->rq.max))
2094 ind -= qp->rq.max;
2095 }
2096out:
2097 if (likely(nreq)) {
2098 qp->rq.head += nreq;
2099
2100 /*
2101 * Make sure that descriptors are written before
2102 * doorbell record.
2103 */
2104 wmb();
2105 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2106 }
2107
2108 spin_unlock_irqrestore(&qp->rq.lock, flags);
2109 return err;
2110}
2111
2112int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
97f52eb4 2113 int index, int *dbd, __be32 *new_wqe)
1da177e4
LT		 2114{
2115 struct mthca_next_seg *next;
2116
ec34a922
RD		 2117 /*
2118 * For SRQs, all WQEs generate a CQE, so we're always at the
2119 * end of the doorbell chain.
2120 */
2121 if (qp->ibqp.srq) {
2122 *new_wqe = 0;
2123 return 0;
2124 }
2125
1da177e4
LT		 2126 if (is_send)
2127 next = get_send_wqe(qp, index);
2128 else
2129 next = get_recv_wqe(qp, index);
2130
288bdeb4 2131 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
1da177e4
LT		 2132 if (next->ee_nds & cpu_to_be32(0x3f))
2133 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2134 (next->ee_nds & cpu_to_be32(0x3f));
2135 else
2136 *new_wqe = 0;
2137
2138 return 0;
2139}
2140
2141int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2142{
2143 int err;
2144 u8 status;
2145 int i;
2146
2147 spin_lock_init(&dev->qp_table.lock);
2148
2149 /*
2150 * We reserve 2 extra QPs per port for the special QPs. The
2151 * special QP for port 1 has to be even, so round up.
2152 */
2153 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2154 err = mthca_alloc_init(&dev->qp_table.alloc,
2155 dev->limits.num_qps,
2156 (1 << 24) - 1,
2157 dev->qp_table.sqp_start +
2158 MTHCA_MAX_PORTS * 2);
2159 if (err)
2160 return err;
2161
2162 err = mthca_array_init(&dev->qp_table.qp,
2163 dev->limits.num_qps);
2164 if (err) {
2165 mthca_alloc_cleanup(&dev->qp_table.alloc);
2166 return err;
2167 }
2168
2169 for (i = 0; i < 2; ++i) {
2170 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2171 dev->qp_table.sqp_start + i * 2,
2172 &status);
2173 if (err)
2174 goto err_out;
2175 if (status) {
2176 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2177 "status %02x, aborting.\n",
2178 status);
2179 err = -EINVAL;
2180 goto err_out;
2181 }
2182 }
2183 return 0;
2184
2185 err_out:
2186 for (i = 0; i < 2; ++i)
2187 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2188
2189 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2190 mthca_alloc_cleanup(&dev->qp_table.alloc);
2191
2192 return err;
2193}
2194
2195void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2196{
2197 int i;
2198 u8 status;
2199
2200 for (i = 0; i < 2; ++i)
2201 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2202
71eea47d 2203 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
1da177e4
LT		 2204 mthca_alloc_cleanup(&dev->qp_table.alloc);
2205}
Linux kernel - Deliverables
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