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IB/uverbs: Pass userspace data to modify_srq and modify_qp methods
[deliverable/linux.git] / drivers / infiniband / hw / mthca / mthca_qp.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
80c8ec2c 3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
2a1d9b7f 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
2fa5e2eb 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 *
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */
37
38#include <linux/init.h>
4e57b681
TS		 39#include <linux/string.h>
40#include <linux/slab.h>
1da177e4 41
a4d61e84
RD		 42#include <rdma/ib_verbs.h>
43#include <rdma/ib_cache.h>
44#include <rdma/ib_pack.h>
1da177e4
LT		 45
46#include "mthca_dev.h"
47#include "mthca_cmd.h"
48#include "mthca_memfree.h"
c04bc3d1 49#include "mthca_wqe.h"
1da177e4
LT		 50
51enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
80c8ec2c
RD		 55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
1da177e4
LT		 58};
59
60enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69};
70
71enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77};
78
79enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83};
84
85enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100};
101
e54b82d7
MT		 102enum {
103 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
104};
105
1da177e4 106struct mthca_qp_path {
97f52eb4
SH		 107 __be32 port_pkey;
108 u8 rnr_retry;
109 u8 g_mylmc;
110 __be16 rlid;
111 u8 ackto;
112 u8 mgid_index;
113 u8 static_rate;
114 u8 hop_limit;
115 __be32 sl_tclass_flowlabel;
116 u8 rgid[16];
1da177e4
LT		 117} __attribute__((packed));
118
119struct mthca_qp_context {
97f52eb4
SH		 120 __be32 flags;
121 __be32 tavor_sched_queue; /* Reserved on Arbel */
122 u8 mtu_msgmax;
123 u8 rq_size_stride; /* Reserved on Tavor */
124 u8 sq_size_stride; /* Reserved on Tavor */
125 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
126 __be32 usr_page;
127 __be32 local_qpn;
128 __be32 remote_qpn;
129 u32 reserved1[2];
1da177e4
LT		 130 struct mthca_qp_path pri_path;
131 struct mthca_qp_path alt_path;
97f52eb4
SH		 132 __be32 rdd;
133 __be32 pd;
134 __be32 wqe_base;
135 __be32 wqe_lkey;
136 __be32 params1;
137 __be32 reserved2;
138 __be32 next_send_psn;
139 __be32 cqn_snd;
140 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
141 __be32 snd_db_index; /* (debugging only entries) */
142 __be32 last_acked_psn;
143 __be32 ssn;
144 __be32 params2;
145 __be32 rnr_nextrecvpsn;
146 __be32 ra_buff_indx;
147 __be32 cqn_rcv;
148 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
149 __be32 rcv_db_index; /* (debugging only entries) */
150 __be32 qkey;
151 __be32 srqn;
152 __be32 rmsn;
153 __be16 rq_wqe_counter; /* reserved on Tavor */
154 __be16 sq_wqe_counter; /* reserved on Tavor */
155 u32 reserved3[18];
1da177e4
LT		 156} __attribute__((packed));
157
158struct mthca_qp_param {
97f52eb4
SH		 159 __be32 opt_param_mask;
160 u32 reserved1;
1da177e4 161 struct mthca_qp_context context;
97f52eb4 162 u32 reserved2[62];
1da177e4
LT		 163} __attribute__((packed));
164
165enum {
166 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
167 MTHCA_QP_OPTPAR_RRE = 1 << 1,
168 MTHCA_QP_OPTPAR_RAE = 1 << 2,
169 MTHCA_QP_OPTPAR_RWE = 1 << 3,
170 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
171 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
172 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
173 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
174 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
175 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
176 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
177 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
178 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
179 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
180 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
181 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
182 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
183};
184
1da177e4
LT		 185static const u8 mthca_opcode[] = {
186 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
187 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
188 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
189 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
190 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
191 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
192 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
193};
194
195static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
196{
197 return qp->qpn >= dev->qp_table.sqp_start &&
198 qp->qpn <= dev->qp_table.sqp_start + 3;
199}
200
201static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
202{
203 return qp->qpn >= dev->qp_table.sqp_start &&
204 qp->qpn <= dev->qp_table.sqp_start + 1;
205}
206
207static void *get_recv_wqe(struct mthca_qp *qp, int n)
208{
209 if (qp->is_direct)
210 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
211 else
212 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
213 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
214}
215
216static void *get_send_wqe(struct mthca_qp *qp, int n)
217{
218 if (qp->is_direct)
219 return qp->queue.direct.buf + qp->send_wqe_offset +
220 (n << qp->sq.wqe_shift);
221 else
222 return qp->queue.page_list[(qp->send_wqe_offset +
223 (n << qp->sq.wqe_shift)) >>
224 PAGE_SHIFT].buf +
225 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
226 (PAGE_SIZE - 1));
227}
228
0964d916 229static void mthca_wq_reset(struct mthca_wq *wq)
c9fe2b32 230{
c9fe2b32
RD		 231 wq->next_ind = 0;
232 wq->last_comp = wq->max - 1;
233 wq->head = 0;
234 wq->tail = 0;
c9fe2b32
RD		 235}
236
1da177e4
LT		 237void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
238 enum ib_event_type event_type)
239{
240 struct mthca_qp *qp;
241 struct ib_event event;
242
243 spin_lock(&dev->qp_table.lock);
244 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
245 if (qp)
a3285aa4 246 ++qp->refcount;
1da177e4
LT		 247 spin_unlock(&dev->qp_table.lock);
248
249 if (!qp) {
250 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
251 return;
252 }
253
bf6a9e31
JM		 254 if (event_type == IB_EVENT_PATH_MIG)
255 qp->port = qp->alt_port;
256
1da177e4
LT		 257 event.device = &dev->ib_dev;
258 event.event = event_type;
259 event.element.qp = &qp->ibqp;
260 if (qp->ibqp.event_handler)
261 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
262
a3285aa4
RD		 263 spin_lock(&dev->qp_table.lock);
264 if (!--qp->refcount)
1da177e4 265 wake_up(&qp->wait);
a3285aa4 266 spin_unlock(&dev->qp_table.lock);
1da177e4
LT		 267}
268
269static int to_mthca_state(enum ib_qp_state ib_state)
270{
271 switch (ib_state) {
272 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
273 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
274 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
275 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
276 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
277 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
278 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
279 default: return -1;
280 }
281}
282
283enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
284
285static int to_mthca_st(int transport)
286{
287 switch (transport) {
288 case RC: return MTHCA_QP_ST_RC;
289 case UC: return MTHCA_QP_ST_UC;
290 case UD: return MTHCA_QP_ST_UD;
291 case RD: return MTHCA_QP_ST_RD;
292 case MLX: return MTHCA_QP_ST_MLX;
293 default: return -1;
294 }
295}
296
1da177e4
LT		 297static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
298 int attr_mask)
299{
300 if (attr_mask & IB_QP_PKEY_INDEX)
301 sqp->pkey_index = attr->pkey_index;
302 if (attr_mask & IB_QP_QKEY)
303 sqp->qkey = attr->qkey;
304 if (attr_mask & IB_QP_SQ_PSN)
305 sqp->send_psn = attr->sq_psn;
306}
307
308static void init_port(struct mthca_dev *dev, int port)
309{
310 int err;
311 u8 status;
312 struct mthca_init_ib_param param;
313
314 memset(&param, 0, sizeof param);
315
da6561c2
RD		 316 param.port_width = dev->limits.port_width_cap;
317 param.vl_cap = dev->limits.vl_cap;
318 param.mtu_cap = dev->limits.mtu_cap;
319 param.gid_cap = dev->limits.gid_table_len;
320 param.pkey_cap = dev->limits.pkey_table_len;
1da177e4
LT		 321
322 err = mthca_INIT_IB(dev, &param, port, &status);
323 if (err)
324 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
325 if (status)
326 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
327}
328
d1646f86
JM		 329static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
330 int attr_mask)
331{
332 u8 dest_rd_atomic;
333 u32 access_flags;
334 u32 hw_access_flags = 0;
335
336 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
337 dest_rd_atomic = attr->max_dest_rd_atomic;
338 else
339 dest_rd_atomic = qp->resp_depth;
340
341 if (attr_mask & IB_QP_ACCESS_FLAGS)
342 access_flags = attr->qp_access_flags;
343 else
344 access_flags = qp->atomic_rd_en;
345
346 if (!dest_rd_atomic)
347 access_flags &= IB_ACCESS_REMOTE_WRITE;
348
349 if (access_flags & IB_ACCESS_REMOTE_READ)
350 hw_access_flags |= MTHCA_QP_BIT_RRE;
351 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
352 hw_access_flags |= MTHCA_QP_BIT_RAE;
353 if (access_flags & IB_ACCESS_REMOTE_WRITE)
354 hw_access_flags |= MTHCA_QP_BIT_RWE;
355
356 return cpu_to_be32(hw_access_flags);
357}
358
8ebe5077
EC		 359static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
360{
361 switch (mthca_state) {
362 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
363 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
364 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
365 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
366 case MTHCA_QP_STATE_DRAINING:
367 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
368 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
369 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
370 default: return -1;
371 }
372}
373
374static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
375{
376 switch (mthca_mig_state) {
377 case 0: return IB_MIG_ARMED;
378 case 1: return IB_MIG_REARM;
379 case 3: return IB_MIG_MIGRATED;
380 default: return -1;
381 }
382}
383
384static int to_ib_qp_access_flags(int mthca_flags)
385{
386 int ib_flags = 0;
387
388 if (mthca_flags & MTHCA_QP_BIT_RRE)
389 ib_flags |= IB_ACCESS_REMOTE_READ;
390 if (mthca_flags & MTHCA_QP_BIT_RWE)
391 ib_flags |= IB_ACCESS_REMOTE_WRITE;
392 if (mthca_flags & MTHCA_QP_BIT_RAE)
393 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
394
395 return ib_flags;
396}
397
398static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
399 struct mthca_qp_path *path)
400{
401 memset(ib_ah_attr, 0, sizeof *path);
402 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
bf6a9e31
JM		 403
404 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
405 return;
406
8ebe5077
EC		 407 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
408 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
409 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
bf6a9e31
JM		 410 ib_ah_attr->static_rate = mthca_rate_to_ib(dev,
411 path->static_rate & 0x7,
412 ib_ah_attr->port_num);
8ebe5077
EC		 413 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
414 if (ib_ah_attr->ah_flags) {
415 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
416 ib_ah_attr->grh.hop_limit = path->hop_limit;
417 ib_ah_attr->grh.traffic_class =
418 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
419 ib_ah_attr->grh.flow_label =
420 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
421 memcpy(ib_ah_attr->grh.dgid.raw,
422 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
423 }
424}
425
426int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
427 struct ib_qp_init_attr *qp_init_attr)
428{
429 struct mthca_dev *dev = to_mdev(ibqp->device);
430 struct mthca_qp *qp = to_mqp(ibqp);
431 int err;
432 struct mthca_mailbox *mailbox;
433 struct mthca_qp_param *qp_param;
434 struct mthca_qp_context *context;
435 int mthca_state;
436 u8 status;
437
438 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
439 if (IS_ERR(mailbox))
440 return PTR_ERR(mailbox);
441
442 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
443 if (err)
444 goto out;
445 if (status) {
446 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
447 err = -EINVAL;
448 goto out;
449 }
450
451 qp_param = mailbox->buf;
452 context = &qp_param->context;
453 mthca_state = be32_to_cpu(context->flags) >> 28;
454
455 qp_attr->qp_state = to_ib_qp_state(mthca_state);
456 qp_attr->cur_qp_state = qp_attr->qp_state;
457 qp_attr->path_mtu = context->mtu_msgmax >> 5;
458 qp_attr->path_mig_state =
459 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
460 qp_attr->qkey = be32_to_cpu(context->qkey);
461 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
462 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
463 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
464 qp_attr->qp_access_flags =
465 to_ib_qp_access_flags(be32_to_cpu(context->params2));
466 qp_attr->cap.max_send_wr = qp->sq.max;
467 qp_attr->cap.max_recv_wr = qp->rq.max;
468 qp_attr->cap.max_send_sge = qp->sq.max_gs;
469 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
470 qp_attr->cap.max_inline_data = qp->max_inline_data;
471
bf6a9e31
JM		 472 if (qp->transport == RC || qp->transport == UC) {
473 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
474 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
475 }
8ebe5077
EC		 476
477 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
478 qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
479
480 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
481 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
482
483 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
484
485 qp_attr->max_dest_rd_atomic =
486 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
487 qp_attr->min_rnr_timer =
488 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
489 qp_attr->port_num = qp_attr->ah_attr.port_num;
490 qp_attr->timeout = context->pri_path.ackto >> 3;
491 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
492 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
493 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
494 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
495 qp_init_attr->cap = qp_attr->cap;
496
497out:
498 mthca_free_mailbox(dev, mailbox);
499 return err;
500}
501
0ef61db8 502static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
bf6a9e31 503 struct mthca_qp_path *path, u8 port)
4de144bf
DB		 504{
505 path->g_mylmc = ah->src_path_bits & 0x7f;
506 path->rlid = cpu_to_be16(ah->dlid);
bf6a9e31 507 path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
4de144bf
DB		 508
509 if (ah->ah_flags & IB_AH_GRH) {
0ef61db8
DB		 510 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
511 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
512 ah->grh.sgid_index, dev->limits.gid_table_len-1);
513 return -1;
514 }
515
4de144bf
DB		 516 path->g_mylmc |= 1 << 7;
517 path->mgid_index = ah->grh.sgid_index;
518 path->hop_limit = ah->grh.hop_limit;
2fa5e2eb 519 path->sl_tclass_flowlabel =
4de144bf 520 cpu_to_be32((ah->sl << 28) |
2fa5e2eb 521 (ah->grh.traffic_class << 20) |
4de144bf
DB		 522 (ah->grh.flow_label));
523 memcpy(path->rgid, ah->grh.dgid.raw, 16);
524 } else
525 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
0ef61db8
DB		 526
527 return 0;
4de144bf
DB		 528}
529
9bc57e2d
RC		 530int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
531 struct ib_udata *udata)
1da177e4
LT		 532{
533 struct mthca_dev *dev = to_mdev(ibqp->device);
534 struct mthca_qp *qp = to_mqp(ibqp);
535 enum ib_qp_state cur_state, new_state;
ed878458 536 struct mthca_mailbox *mailbox;
1da177e4
LT		 537 struct mthca_qp_param *qp_param;
538 struct mthca_qp_context *qp_context;
3fa1fa3e 539 u32 sqd_event = 0;
1da177e4 540 u8 status;
c9c5d9fe 541 int err = -EINVAL;
1da177e4 542
c93b6fba
RD		 543 mutex_lock(&qp->mutex);
544
1da177e4 545 if (attr_mask & IB_QP_CUR_STATE) {
d844183d 546 cur_state = attr->cur_qp_state;
1da177e4
LT		 547 } else {
548 spin_lock_irq(&qp->sq.lock);
549 spin_lock(&qp->rq.lock);
550 cur_state = qp->state;
551 spin_unlock(&qp->rq.lock);
552 spin_unlock_irq(&qp->sq.lock);
553 }
554
d844183d 555 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1da177e4 556
d844183d
RD		 557 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
558 mthca_dbg(dev, "Bad QP transition (transport %d) "
559 "%d->%d with attr 0x%08x\n",
560 qp->transport, cur_state, new_state,
561 attr_mask);
c93b6fba 562 goto out;
1da177e4
LT		 563 }
564
2fa5e2eb 565 if ((attr_mask & IB_QP_PKEY_INDEX) &&
d09e3276 566 attr->pkey_index >= dev->limits.pkey_table_len) {
67e73776
DB		 567 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
568 attr->pkey_index, dev->limits.pkey_table_len-1);
c93b6fba 569 goto out;
d09e3276
JM		 570 }
571
38d1e793
JM		 572 if ((attr_mask & IB_QP_PORT) &&
573 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
574 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
c93b6fba 575 goto out;
38d1e793
JM		 576 }
577
94361cf7
JM		 578 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
579 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
580 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
581 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
c93b6fba 582 goto out;
94361cf7
JM		 583 }
584
585 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
586 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
587 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
588 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
c93b6fba 589 goto out;
94361cf7
JM		 590 }
591
ed878458 592 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
c93b6fba
RD		 593 if (IS_ERR(mailbox)) {
594 err = PTR_ERR(mailbox);
595 goto out;
596 }
ed878458 597 qp_param = mailbox->buf;
1da177e4
LT		 598 qp_context = &qp_param->context;
599 memset(qp_param, 0, sizeof *qp_param);
600
601 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
602 (to_mthca_st(qp->transport) << 16));
603 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
604 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
605 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
606 else {
607 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
608 switch (attr->path_mig_state) {
609 case IB_MIG_MIGRATED:
610 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
611 break;
612 case IB_MIG_REARM:
613 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
614 break;
615 case IB_MIG_ARMED:
616 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
617 break;
618 }
619 }
620
621 /* leave tavor_sched_queue as 0 */
622
623 if (qp->transport == MLX || qp->transport == UD)
624 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
0ef61db8
DB		 625 else if (attr_mask & IB_QP_PATH_MTU) {
626 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
627 mthca_dbg(dev, "path MTU (%u) is invalid\n",
628 attr->path_mtu);
c93b6fba 629 goto out_mailbox;
0ef61db8 630 }
1da177e4 631 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
0ef61db8 632 }
1da177e4 633
d10ddbf6 634 if (mthca_is_memfree(dev)) {
ec34a922
RD		 635 if (qp->rq.max)
636 qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
637 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
638
639 if (qp->sq.max)
640 qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
641 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
1da177e4
LT		 642 }
643
644 /* leave arbel_sched_queue as 0 */
645
80c8ec2c
RD		 646 if (qp->ibqp.uobject)
647 qp_context->usr_page =
648 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
649 else
650 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
1da177e4
LT		 651 qp_context->local_qpn = cpu_to_be32(qp->qpn);
652 if (attr_mask & IB_QP_DEST_QPN) {
653 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
654 }
655
656 if (qp->transport == MLX)
657 qp_context->pri_path.port_pkey |=
bf6a9e31 658 cpu_to_be32(qp->port << 24);
1da177e4
LT		 659 else {
660 if (attr_mask & IB_QP_PORT) {
661 qp_context->pri_path.port_pkey |=
662 cpu_to_be32(attr->port_num << 24);
663 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
664 }
665 }
666
667 if (attr_mask & IB_QP_PKEY_INDEX) {
668 qp_context->pri_path.port_pkey |=
669 cpu_to_be32(attr->pkey_index);
670 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
671 }
672
673 if (attr_mask & IB_QP_RNR_RETRY) {
4de144bf
DB		 674 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
675 attr->rnr_retry << 5;
2fa5e2eb 676 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
4de144bf 677 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
1da177e4
LT		 678 }
679
680 if (attr_mask & IB_QP_AV) {
bf6a9e31
JM		 681 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
682 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
c93b6fba 683 goto out_mailbox;
0ef61db8 684
1da177e4
LT		 685 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
686 }
687
688 if (attr_mask & IB_QP_TIMEOUT) {
bb4a7f0d 689 qp_context->pri_path.ackto = attr->timeout << 3;
1da177e4
LT		 690 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
691 }
692
4de144bf 693 if (attr_mask & IB_QP_ALT_PATH) {
67e73776
DB		 694 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
695 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
696 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
c93b6fba 697 goto out_mailbox;
67e73776
DB		 698 }
699
4de144bf 700 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
2fa5e2eb 701 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
4de144bf 702 attr->alt_port_num);
c93b6fba 703 goto out_mailbox;
4de144bf
DB		 704 }
705
bf6a9e31
JM		 706 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
707 attr->alt_ah_attr.port_num))
c93b6fba 708 goto out_mailbox;
0ef61db8 709
2fa5e2eb 710 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
4de144bf
DB		 711 attr->alt_port_num << 24);
712 qp_context->alt_path.ackto = attr->alt_timeout << 3;
713 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
714 }
1da177e4
LT		 715
716 /* leave rdd as 0 */
717 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
718 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
719 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
720 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
721 (MTHCA_FLIGHT_LIMIT << 24) |
c4342d8a 722 MTHCA_QP_BIT_SWE);
1da177e4
LT		 723 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
724 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
725 if (attr_mask & IB_QP_RETRY_CNT) {
726 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
727 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
728 }
729
34a4a753 730 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
c4342d8a
JM		 731 if (attr->max_rd_atomic) {
732 qp_context->params1 |=
733 cpu_to_be32(MTHCA_QP_BIT_SRE |
734 MTHCA_QP_BIT_SAE);
6aa2e4e8
JM		 735 qp_context->params1 |=
736 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
c4342d8a 737 }
1da177e4
LT		 738 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
739 }
740
741 if (attr_mask & IB_QP_SQ_PSN)
742 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
743 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
744
d10ddbf6 745 if (mthca_is_memfree(dev)) {
1da177e4
LT		 746 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
747 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
748 }
749
34a4a753 750 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
6aa2e4e8
JM		 751 if (attr->max_dest_rd_atomic)
752 qp_context->params2 |=
753 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1da177e4 754
1da177e4 755 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
1da177e4
LT		 756 }
757
d1646f86
JM		 758 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
759 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
760 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
761 MTHCA_QP_OPTPAR_RRE |
762 MTHCA_QP_OPTPAR_RAE);
763 }
764
1da177e4
LT		 765 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
766
ec34a922
RD		 767 if (ibqp->srq)
768 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
769
1da177e4
LT		 770 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
771 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
772 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
773 }
774 if (attr_mask & IB_QP_RQ_PSN)
775 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
776
777 qp_context->ra_buff_indx =
778 cpu_to_be32(dev->qp_table.rdb_base +
779 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
780 dev->qp_table.rdb_shift));
781
782 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
783
d10ddbf6 784 if (mthca_is_memfree(dev))
1da177e4
LT		 785 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
786
787 if (attr_mask & IB_QP_QKEY) {
788 qp_context->qkey = cpu_to_be32(attr->qkey);
789 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
790 }
791
ec34a922
RD		 792 if (ibqp->srq)
793 qp_context->srqn = cpu_to_be32(1 << 24 |
794 to_msrq(ibqp->srq)->srqn);
795
3fa1fa3e
RD		 796 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
797 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
798 attr->en_sqd_async_notify)
799 sqd_event = 1 << 31;
800
d844183d
RD		 801 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
802 mailbox, sqd_event, &status);
192daa18 803 if (err)
c93b6fba 804 goto out_mailbox;
1da177e4 805 if (status) {
d844183d
RD		 806 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
807 cur_state, new_state, status);
1da177e4 808 err = -EINVAL;
c93b6fba 809 goto out_mailbox;
1da177e4
LT		 810 }
811
192daa18
RD		 812 qp->state = new_state;
813 if (attr_mask & IB_QP_ACCESS_FLAGS)
814 qp->atomic_rd_en = attr->qp_access_flags;
815 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
816 qp->resp_depth = attr->max_dest_rd_atomic;
bf6a9e31
JM		 817 if (attr_mask & IB_QP_PORT)
818 qp->port = attr->port_num;
819 if (attr_mask & IB_QP_ALT_PATH)
820 qp->alt_port = attr->alt_port_num;
1da177e4
LT		 821
822 if (is_sqp(dev, qp))
823 store_attrs(to_msqp(qp), attr, attr_mask);
824
825 /*
c9fe2b32
RD		 826 * If we moved QP0 to RTR, bring the IB link up; if we moved
827 * QP0 to RESET or ERROR, bring the link back down.
1da177e4
LT		 828 */
829 if (is_qp0(dev, qp)) {
830 if (cur_state != IB_QPS_RTR &&
831 new_state == IB_QPS_RTR)
bf6a9e31 832 init_port(dev, qp->port);
1da177e4
LT		 833
834 if (cur_state != IB_QPS_RESET &&
835 cur_state != IB_QPS_ERR &&
836 (new_state == IB_QPS_RESET ||
837 new_state == IB_QPS_ERR))
bf6a9e31 838 mthca_CLOSE_IB(dev, qp->port, &status);
1da177e4
LT		 839 }
840
c9fe2b32
RD		 841 /*
842 * If we moved a kernel QP to RESET, clean up all old CQ
843 * entries and reinitialize the QP.
844 */
192daa18 845 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
a3285aa4 846 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
c9fe2b32
RD		 847 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
848 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
a3285aa4 849 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
c9fe2b32
RD		 850 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
851
0964d916 852 mthca_wq_reset(&qp->sq);
187a2586
MT		 853 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
854
0964d916 855 mthca_wq_reset(&qp->rq);
187a2586 856 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
c9fe2b32
RD		 857
858 if (mthca_is_memfree(dev)) {
859 *qp->sq.db = 0;
860 *qp->rq.db = 0;
861 }
862 }
863
c93b6fba 864out_mailbox:
192daa18 865 mthca_free_mailbox(dev, mailbox);
c93b6fba
RD		 866
867out:
868 mutex_unlock(&qp->mutex);
1da177e4
LT		 869 return err;
870}
871
5b3bc7a6 872static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
77369ed3 873{
77369ed3
JM		 874 /*
875 * Calculate the maximum size of WQE s/g segments, excluding
876 * the next segment and other non-data segments.
877 */
5b3bc7a6 878 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
77369ed3
JM		 879
880 switch (qp->transport) {
881 case MLX:
882 max_data_size -= 2 * sizeof (struct mthca_data_seg);
883 break;
884
885 case UD:
886 if (mthca_is_memfree(dev))
887 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
888 else
889 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
890 break;
891
892 default:
893 max_data_size -= sizeof (struct mthca_raddr_seg);
894 break;
895 }
896
5b3bc7a6
JM		 897 return max_data_size;
898}
899
900static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
901{
77369ed3 902 /* We don't support inline data for kernel QPs (yet). */
5b3bc7a6
JM		 903 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
904}
905
906static void mthca_adjust_qp_caps(struct mthca_dev *dev,
907 struct mthca_pd *pd,
908 struct mthca_qp *qp)
909{
910 int max_data_size = mthca_max_data_size(dev, qp,
911 min(dev->limits.max_desc_sz,
912 1 << qp->sq.wqe_shift));
913
914 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
77369ed3 915
48fd0d1f
MT		 916 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
917 max_data_size / sizeof (struct mthca_data_seg));
918 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
919 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
920 sizeof (struct mthca_next_seg)) /
921 sizeof (struct mthca_data_seg));
77369ed3
JM		 922}
923
1da177e4
LT		 924/*
925 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
926 * rq.max_gs and sq.max_gs must all be assigned.
927 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
928 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
929 * queue)
930 */
931static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
932 struct mthca_pd *pd,
933 struct mthca_qp *qp)
934{
935 int size;
1da177e4
LT		 936 int err = -ENOMEM;
937
938 size = sizeof (struct mthca_next_seg) +
939 qp->rq.max_gs * sizeof (struct mthca_data_seg);
940
77369ed3
JM		 941 if (size > dev->limits.max_desc_sz)
942 return -EINVAL;
943
1da177e4
LT		 944 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
945 qp->rq.wqe_shift++)
946 ; /* nothing */
947
77369ed3 948 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1da177e4
LT		 949 switch (qp->transport) {
950 case MLX:
951 size += 2 * sizeof (struct mthca_data_seg);
952 break;
77369ed3 953
1da177e4 954 case UD:
77369ed3
JM		 955 size += mthca_is_memfree(dev) ?
956 sizeof (struct mthca_arbel_ud_seg) :
957 sizeof (struct mthca_tavor_ud_seg);
1da177e4 958 break;
77369ed3
JM		 959
960 case UC:
961 size += sizeof (struct mthca_raddr_seg);
962 break;
963
964 case RC:
965 size += sizeof (struct mthca_raddr_seg);
966 /*
967 * An atomic op will require an atomic segment, a
968 * remote address segment and one scatter entry.
969 */
970 size = max_t(int, size,
971 sizeof (struct mthca_atomic_seg) +
972 sizeof (struct mthca_raddr_seg) +
973 sizeof (struct mthca_data_seg));
974 break;
975
1da177e4 976 default:
77369ed3 977 break;
1da177e4
LT		 978 }
979
77369ed3
JM		 980 /* Make sure that we have enough space for a bind request */
981 size = max_t(int, size, sizeof (struct mthca_bind_seg));
982
983 size += sizeof (struct mthca_next_seg);
984
985 if (size > dev->limits.max_desc_sz)
986 return -EINVAL;
987
1da177e4
LT		 988 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
989 qp->sq.wqe_shift++)
990 ; /* nothing */
991
992 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
993 1 << qp->sq.wqe_shift);
80c8ec2c
RD		 994
995 /*
996 * If this is a userspace QP, we don't actually have to
997 * allocate anything. All we need is to calculate the WQE
998 * sizes and the send_wqe_offset, so we're done now.
999 */
1000 if (pd->ibpd.uobject)
1001 return 0;
1002
1da177e4
LT		 1003 size = PAGE_ALIGN(qp->send_wqe_offset +
1004 (qp->sq.max << qp->sq.wqe_shift));
1005
1006 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1007 GFP_KERNEL);
1008 if (!qp->wrid)
1009 goto err_out;
1010
87b81670
RD		 1011 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1012 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1da177e4 1013 if (err)
87b81670 1014 goto err_out;
1da177e4 1015
1da177e4
LT		 1016 return 0;
1017
87b81670 1018err_out:
1da177e4 1019 kfree(qp->wrid);
1da177e4
LT		 1020 return err;
1021}
1022
80c8ec2c 1023static void mthca_free_wqe_buf(struct mthca_dev *dev,
1da177e4
LT		 1024 struct mthca_qp *qp)
1025{
87b81670
RD		 1026 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1027 (qp->sq.max << qp->sq.wqe_shift)),
1028 &qp->queue, qp->is_direct, &qp->mr);
80c8ec2c
RD		 1029 kfree(qp->wrid);
1030}
1031
1032static int mthca_map_memfree(struct mthca_dev *dev,
1033 struct mthca_qp *qp)
1034{
1035 int ret;
1da177e4 1036
d10ddbf6 1037 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1038 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1039 if (ret)
1040 return ret;
1041
1042 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1043 if (ret)
1044 goto err_qpc;
1045
2fa5e2eb
RD		 1046 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1047 qp->qpn << dev->qp_table.rdb_shift);
1048 if (ret)
1049 goto err_eqpc;
1da177e4 1050
1da177e4
LT		 1051 }
1052
1053 return 0;
1054
1da177e4
LT		 1055err_eqpc:
1056 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1057
1058err_qpc:
1059 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1060
1061 return ret;
1062}
1063
80c8ec2c
RD		 1064static void mthca_unmap_memfree(struct mthca_dev *dev,
1065 struct mthca_qp *qp)
1066{
1067 mthca_table_put(dev, dev->qp_table.rdb_table,
1068 qp->qpn << dev->qp_table.rdb_shift);
1069 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1070 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1071}
1072
1073static int mthca_alloc_memfree(struct mthca_dev *dev,
1074 struct mthca_qp *qp)
1075{
1076 int ret = 0;
1077
1078 if (mthca_is_memfree(dev)) {
1079 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1080 qp->qpn, &qp->rq.db);
1081 if (qp->rq.db_index < 0)
1082 return ret;
1083
1084 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1085 qp->qpn, &qp->sq.db);
1086 if (qp->sq.db_index < 0)
1087 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1088 }
1089
1090 return ret;
1091}
1092
1da177e4
LT		 1093static void mthca_free_memfree(struct mthca_dev *dev,
1094 struct mthca_qp *qp)
1095{
d10ddbf6 1096 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1097 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1098 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1da177e4
LT		 1099 }
1100}
1101
1da177e4
LT		 1102static int mthca_alloc_qp_common(struct mthca_dev *dev,
1103 struct mthca_pd *pd,
1104 struct mthca_cq *send_cq,
1105 struct mthca_cq *recv_cq,
1106 enum ib_sig_type send_policy,
1107 struct mthca_qp *qp)
1108{
1da177e4
LT		 1109 int ret;
1110 int i;
1111
a3285aa4 1112 qp->refcount = 1;
30a7e8ef 1113 init_waitqueue_head(&qp->wait);
c93b6fba 1114 mutex_init(&qp->mutex);
1da177e4
LT		 1115 qp->state = IB_QPS_RESET;
1116 qp->atomic_rd_en = 0;
1117 qp->resp_depth = 0;
1118 qp->sq_policy = send_policy;
0964d916
MT		 1119 mthca_wq_reset(&qp->sq);
1120 mthca_wq_reset(&qp->rq);
1121
a46f9484
ZB		 1122 spin_lock_init(&qp->sq.lock);
1123 spin_lock_init(&qp->rq.lock);
1da177e4 1124
80c8ec2c 1125 ret = mthca_map_memfree(dev, qp);
1da177e4
LT		 1126 if (ret)
1127 return ret;
1128
1129 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1130 if (ret) {
80c8ec2c
RD		 1131 mthca_unmap_memfree(dev, qp);
1132 return ret;
1133 }
1134
77369ed3
JM		 1135 mthca_adjust_qp_caps(dev, pd, qp);
1136
80c8ec2c
RD		 1137 /*
1138 * If this is a userspace QP, we're done now. The doorbells
1139 * will be allocated and buffers will be initialized in
1140 * userspace.
1141 */
1142 if (pd->ibpd.uobject)
1143 return 0;
1144
1145 ret = mthca_alloc_memfree(dev, qp);
1146 if (ret) {
1147 mthca_free_wqe_buf(dev, qp);
1148 mthca_unmap_memfree(dev, qp);
1da177e4
LT		 1149 return ret;
1150 }
1151
d10ddbf6 1152 if (mthca_is_memfree(dev)) {
ddf841f0
RD		 1153 struct mthca_next_seg *next;
1154 struct mthca_data_seg *scatter;
1155 int size = (sizeof (struct mthca_next_seg) +
1156 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1157
1da177e4 1158 for (i = 0; i < qp->rq.max; ++i) {
ddf841f0
RD		 1159 next = get_recv_wqe(qp, i);
1160 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1161 qp->rq.wqe_shift);
1162 next->ee_nds = cpu_to_be32(size);
1163
1164 for (scatter = (void *) (next + 1);
1165 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1166 ++scatter)
1167 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1da177e4
LT		 1168 }
1169
1170 for (i = 0; i < qp->sq.max; ++i) {
ddf841f0
RD		 1171 next = get_send_wqe(qp, i);
1172 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1173 qp->sq.wqe_shift) +
1174 qp->send_wqe_offset);
1da177e4
LT		 1175 }
1176 }
1177
d6cff021
RD		 1178 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1179 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1180
1da177e4
LT		 1181 return 0;
1182}
1183
80c8ec2c 1184static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
5b3bc7a6 1185 struct mthca_pd *pd, struct mthca_qp *qp)
1da177e4 1186{
5b3bc7a6
JM		 1187 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1188
80c8ec2c 1189 /* Sanity check QP size before proceeding */
5b3bc7a6
JM		 1190 if (cap->max_send_wr > dev->limits.max_wqes ||
1191 cap->max_recv_wr > dev->limits.max_wqes ||
1192 cap->max_send_sge > dev->limits.max_sg ||
1193 cap->max_recv_sge > dev->limits.max_sg ||
1194 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1195 return -EINVAL;
1196
1197 /*
1198 * For MLX transport we need 2 extra S/G entries:
1199 * one for the header and one for the checksum at the end
1200 */
1201 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
80c8ec2c 1202 return -EINVAL;
1da177e4 1203
80c8ec2c
RD		 1204 if (mthca_is_memfree(dev)) {
1205 qp->rq.max = cap->max_recv_wr ?
1206 roundup_pow_of_two(cap->max_recv_wr) : 0;
1207 qp->sq.max = cap->max_send_wr ?
1208 roundup_pow_of_two(cap->max_send_wr) : 0;
1209 } else {
1210 qp->rq.max = cap->max_recv_wr;
1211 qp->sq.max = cap->max_send_wr;
1212 }
1da177e4 1213
80c8ec2c
RD		 1214 qp->rq.max_gs = cap->max_recv_sge;
1215 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1216 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1217 MTHCA_INLINE_CHUNK_SIZE) /
1218 sizeof (struct mthca_data_seg));
1da177e4 1219
80c8ec2c 1220 return 0;
1da177e4
LT		 1221}
1222
1223int mthca_alloc_qp(struct mthca_dev *dev,
1224 struct mthca_pd *pd,
1225 struct mthca_cq *send_cq,
1226 struct mthca_cq *recv_cq,
1227 enum ib_qp_type type,
1228 enum ib_sig_type send_policy,
80c8ec2c 1229 struct ib_qp_cap *cap,
1da177e4
LT		 1230 struct mthca_qp *qp)
1231{
1232 int err;
1233
1da177e4
LT		 1234 switch (type) {
1235 case IB_QPT_RC: qp->transport = RC; break;
1236 case IB_QPT_UC: qp->transport = UC; break;
1237 case IB_QPT_UD: qp->transport = UD; break;
1238 default: return -EINVAL;
1239 }
1240
b3f64967
JM		 1241 err = mthca_set_qp_size(dev, cap, pd, qp);
1242 if (err)
1243 return err;
1244
1da177e4
LT		 1245 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1246 if (qp->qpn == -1)
1247 return -ENOMEM;
1248
bf6a9e31
JM		 1249 /* initialize port to zero for error-catching. */
1250 qp->port = 0;
1251
1da177e4
LT		 1252 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1253 send_policy, qp);
1254 if (err) {
1255 mthca_free(&dev->qp_table.alloc, qp->qpn);
1256 return err;
1257 }
1258
1259 spin_lock_irq(&dev->qp_table.lock);
1260 mthca_array_set(&dev->qp_table.qp,
1261 qp->qpn & (dev->limits.num_qps - 1), qp);
1262 spin_unlock_irq(&dev->qp_table.lock);
1263
1264 return 0;
1265}
1266
a19aa5c5
RD		 1267static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1268{
1269 if (send_cq == recv_cq)
1270 spin_lock_irq(&send_cq->lock);
1271 else if (send_cq->cqn < recv_cq->cqn) {
1272 spin_lock_irq(&send_cq->lock);
1273 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1274 } else {
1275 spin_lock_irq(&recv_cq->lock);
1276 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1277 }
1278}
1279
1280static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1281{
1282 if (send_cq == recv_cq)
1283 spin_unlock_irq(&send_cq->lock);
1284 else if (send_cq->cqn < recv_cq->cqn) {
1285 spin_unlock(&recv_cq->lock);
1286 spin_unlock_irq(&send_cq->lock);
1287 } else {
1288 spin_unlock(&send_cq->lock);
1289 spin_unlock_irq(&recv_cq->lock);
1290 }
1291}
1292
1da177e4
LT		 1293int mthca_alloc_sqp(struct mthca_dev *dev,
1294 struct mthca_pd *pd,
1295 struct mthca_cq *send_cq,
1296 struct mthca_cq *recv_cq,
1297 enum ib_sig_type send_policy,
80c8ec2c 1298 struct ib_qp_cap *cap,
1da177e4
LT		 1299 int qpn,
1300 int port,
1301 struct mthca_sqp *sqp)
1302{
1da177e4 1303 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
80c8ec2c 1304 int err;
1da177e4 1305
b3f64967 1306 sqp->qp.transport = MLX;
5b3bc7a6 1307 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
80c8ec2c
RD		 1308 if (err)
1309 return err;
1da177e4
LT		 1310
1311 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1312 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1313 &sqp->header_dma, GFP_KERNEL);
1314 if (!sqp->header_buf)
1315 return -ENOMEM;
1316
1317 spin_lock_irq(&dev->qp_table.lock);
1318 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1319 err = -EBUSY;
1320 else
1321 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1322 spin_unlock_irq(&dev->qp_table.lock);
1323
1324 if (err)
1325 goto err_out;
1326
bf6a9e31 1327 sqp->qp.port = port;
1da177e4
LT		 1328 sqp->qp.qpn = mqpn;
1329 sqp->qp.transport = MLX;
1330
1331 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1332 send_policy, &sqp->qp);
1333 if (err)
1334 goto err_out_free;
1335
1336 atomic_inc(&pd->sqp_count);
1337
1338 return 0;
1339
1340 err_out_free:
1341 /*
1342 * Lock CQs here, so that CQ polling code can do QP lookup
1343 * without taking a lock.
1344 */
a19aa5c5 1345 mthca_lock_cqs(send_cq, recv_cq);
1da177e4
LT		 1346
1347 spin_lock(&dev->qp_table.lock);
1348 mthca_array_clear(&dev->qp_table.qp, mqpn);
1349 spin_unlock(&dev->qp_table.lock);
1350
a19aa5c5 1351 mthca_unlock_cqs(send_cq, recv_cq);
1da177e4
LT		 1352
1353 err_out:
1354 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1355 sqp->header_buf, sqp->header_dma);
1356
1357 return err;
1358}
1359
a3285aa4
RD		 1360static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1361{
1362 int c;
1363
1364 spin_lock_irq(&dev->qp_table.lock);
1365 c = qp->refcount;
1366 spin_unlock_irq(&dev->qp_table.lock);
1367
1368 return c;
1369}
1370
1da177e4
LT		 1371void mthca_free_qp(struct mthca_dev *dev,
1372 struct mthca_qp *qp)
1373{
1374 u8 status;
1da177e4
LT		 1375 struct mthca_cq *send_cq;
1376 struct mthca_cq *recv_cq;
1377
1378 send_cq = to_mcq(qp->ibqp.send_cq);
1379 recv_cq = to_mcq(qp->ibqp.recv_cq);
1380
1381 /*
1382 * Lock CQs here, so that CQ polling code can do QP lookup
1383 * without taking a lock.
1384 */
a19aa5c5 1385 mthca_lock_cqs(send_cq, recv_cq);
1da177e4
LT		 1386
1387 spin_lock(&dev->qp_table.lock);
1388 mthca_array_clear(&dev->qp_table.qp,
1389 qp->qpn & (dev->limits.num_qps - 1));
a3285aa4 1390 --qp->refcount;
1da177e4
LT		 1391 spin_unlock(&dev->qp_table.lock);
1392
a19aa5c5 1393 mthca_unlock_cqs(send_cq, recv_cq);
1da177e4 1394
a3285aa4 1395 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1da177e4
LT		 1396
1397 if (qp->state != IB_QPS_RESET)
d844183d
RD		 1398 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1399 NULL, 0, &status);
1da177e4 1400
80c8ec2c
RD		 1401 /*
1402 * If this is a userspace QP, the buffers, MR, CQs and so on
1403 * will be cleaned up in userspace, so all we have to do is
1404 * unref the mem-free tables and free the QPN in our table.
1405 */
1406 if (!qp->ibqp.uobject) {
a3285aa4 1407 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
ec34a922 1408 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
80c8ec2c 1409 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
a3285aa4 1410 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
ec34a922 1411 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1da177e4 1412
80c8ec2c
RD		 1413 mthca_free_memfree(dev, qp);
1414 mthca_free_wqe_buf(dev, qp);
1da177e4
LT		 1415 }
1416
80c8ec2c 1417 mthca_unmap_memfree(dev, qp);
1da177e4
LT		 1418
1419 if (is_sqp(dev, qp)) {
1420 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1421 dma_free_coherent(&dev->pdev->dev,
1422 to_msqp(qp)->header_buf_size,
1423 to_msqp(qp)->header_buf,
1424 to_msqp(qp)->header_dma);
1425 } else
1426 mthca_free(&dev->qp_table.alloc, qp->qpn);
1427}
1428
1429/* Create UD header for an MLX send and build a data segment for it */
1430static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1431 int ind, struct ib_send_wr *wr,
1432 struct mthca_mlx_seg *mlx,
1433 struct mthca_data_seg *data)
1434{
1435 int header_size;
1436 int err;
97f52eb4 1437 u16 pkey;
1da177e4
LT		 1438
1439 ib_ud_header_init(256, /* assume a MAD */
9eacee2a 1440 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1da177e4
LT		 1441 &sqp->ud_header);
1442
1443 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1444 if (err)
1445 return err;
1446 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1447 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
97f52eb4
SH		 1448 (sqp->ud_header.lrh.destination_lid ==
1449 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1da177e4
LT		 1450 (sqp->ud_header.lrh.service_level << 8));
1451 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1452 mlx->vcrc = 0;
1453
1454 switch (wr->opcode) {
1455 case IB_WR_SEND:
1456 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1457 sqp->ud_header.immediate_present = 0;
1458 break;
1459 case IB_WR_SEND_WITH_IMM:
1460 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1461 sqp->ud_header.immediate_present = 1;
1462 sqp->ud_header.immediate_data = wr->imm_data;
1463 break;
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
97f52eb4
SH		 1469 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1470 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1da177e4
LT		 1471 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1472 if (!sqp->qp.ibqp.qp_num)
bf6a9e31 1473 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
97f52eb4 1474 sqp->pkey_index, &pkey);
1da177e4 1475 else
bf6a9e31 1476 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
97f52eb4
SH		 1477 wr->wr.ud.pkey_index, &pkey);
1478 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1da177e4
LT		 1479 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1480 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1481 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1482 sqp->qkey : wr->wr.ud.remote_qkey);
1483 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1484
1485 header_size = ib_ud_header_pack(&sqp->ud_header,
1486 sqp->header_buf +
1487 ind * MTHCA_UD_HEADER_SIZE);
1488
1489 data->byte_count = cpu_to_be32(header_size);
1490 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1491 data->addr = cpu_to_be64(sqp->header_dma +
1492 ind * MTHCA_UD_HEADER_SIZE);
1493
1494 return 0;
1495}
1496
1497static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1498 struct ib_cq *ib_cq)
1499{
1500 unsigned cur;
1501 struct mthca_cq *cq;
1502
1503 cur = wq->head - wq->tail;
1504 if (likely(cur + nreq < wq->max))
1505 return 0;
1506
1507 cq = to_mcq(ib_cq);
1508 spin_lock(&cq->lock);
1509 cur = wq->head - wq->tail;
1510 spin_unlock(&cq->lock);
1511
1512 return cur + nreq >= wq->max;
1513}
1514
1515int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1516 struct ib_send_wr **bad_wr)
1517{
1518 struct mthca_dev *dev = to_mdev(ibqp->device);
1519 struct mthca_qp *qp = to_mqp(ibqp);
1520 void *wqe;
1521 void *prev_wqe;
1522 unsigned long flags;
1523 int err = 0;
1524 int nreq;
1525 int i;
1526 int size;
1527 int size0 = 0;
e54b82d7 1528 u32 f0;
1da177e4
LT		 1529 int ind;
1530 u8 op0 = 0;
1531
1532 spin_lock_irqsave(&qp->sq.lock, flags);
1533
1534 /* XXX check that state is OK to post send */
1535
1536 ind = qp->sq.next_ind;
1537
1538 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1539 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1540 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1541 " %d max, %d nreq)\n", qp->qpn,
1542 qp->sq.head, qp->sq.tail,
1543 qp->sq.max, nreq);
1544 err = -ENOMEM;
1545 *bad_wr = wr;
1546 goto out;
1547 }
1548
1549 wqe = get_send_wqe(qp, ind);
1550 prev_wqe = qp->sq.last;
1551 qp->sq.last = wqe;
1552
1553 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1554 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1555 ((struct mthca_next_seg *) wqe)->flags =
1556 ((wr->send_flags & IB_SEND_SIGNALED) ?
1557 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1558 ((wr->send_flags & IB_SEND_SOLICITED) ?
1559 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1560 cpu_to_be32(1);
1561 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1562 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
3fba2317 1563 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1da177e4
LT		 1564
1565 wqe += sizeof (struct mthca_next_seg);
1566 size = sizeof (struct mthca_next_seg) / 16;
1567
1568 switch (qp->transport) {
1569 case RC:
1570 switch (wr->opcode) {
1571 case IB_WR_ATOMIC_CMP_AND_SWP:
1572 case IB_WR_ATOMIC_FETCH_AND_ADD:
1573 ((struct mthca_raddr_seg *) wqe)->raddr =
1574 cpu_to_be64(wr->wr.atomic.remote_addr);
1575 ((struct mthca_raddr_seg *) wqe)->rkey =
1576 cpu_to_be32(wr->wr.atomic.rkey);
1577 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1578
1579 wqe += sizeof (struct mthca_raddr_seg);
1580
1581 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1582 ((struct mthca_atomic_seg *) wqe)->swap_add =
1583 cpu_to_be64(wr->wr.atomic.swap);
1584 ((struct mthca_atomic_seg *) wqe)->compare =
1585 cpu_to_be64(wr->wr.atomic.compare_add);
1586 } else {
1587 ((struct mthca_atomic_seg *) wqe)->swap_add =
1588 cpu_to_be64(wr->wr.atomic.compare_add);
1589 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1590 }
1591
1592 wqe += sizeof (struct mthca_atomic_seg);
62abb841
MT		 1593 size += (sizeof (struct mthca_raddr_seg) +
1594 sizeof (struct mthca_atomic_seg)) / 16;
1da177e4
LT		 1595 break;
1596
1597 case IB_WR_RDMA_WRITE:
1598 case IB_WR_RDMA_WRITE_WITH_IMM:
1599 case IB_WR_RDMA_READ:
1600 ((struct mthca_raddr_seg *) wqe)->raddr =
1601 cpu_to_be64(wr->wr.rdma.remote_addr);
1602 ((struct mthca_raddr_seg *) wqe)->rkey =
1603 cpu_to_be32(wr->wr.rdma.rkey);
1604 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1605 wqe += sizeof (struct mthca_raddr_seg);
1606 size += sizeof (struct mthca_raddr_seg) / 16;
1607 break;
1608
1609 default:
1610 /* No extra segments required for sends */
1611 break;
1612 }
1613
1614 break;
1615
9e6970b5
RD		 1616 case UC:
1617 switch (wr->opcode) {
1618 case IB_WR_RDMA_WRITE:
1619 case IB_WR_RDMA_WRITE_WITH_IMM:
1620 ((struct mthca_raddr_seg *) wqe)->raddr =
1621 cpu_to_be64(wr->wr.rdma.remote_addr);
1622 ((struct mthca_raddr_seg *) wqe)->rkey =
1623 cpu_to_be32(wr->wr.rdma.rkey);
1624 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1625 wqe += sizeof (struct mthca_raddr_seg);
1626 size += sizeof (struct mthca_raddr_seg) / 16;
1627 break;
1628
1629 default:
1630 /* No extra segments required for sends */
1631 break;
1632 }
1633
1634 break;
1635
1da177e4
LT		 1636 case UD:
1637 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1638 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1639 ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1640 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1641 ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1642 cpu_to_be32(wr->wr.ud.remote_qpn);
1643 ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1644 cpu_to_be32(wr->wr.ud.remote_qkey);
1645
1646 wqe += sizeof (struct mthca_tavor_ud_seg);
1647 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1648 break;
1649
1650 case MLX:
1651 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1652 wqe - sizeof (struct mthca_next_seg),
1653 wqe);
1654 if (err) {
1655 *bad_wr = wr;
1656 goto out;
1657 }
1658 wqe += sizeof (struct mthca_data_seg);
1659 size += sizeof (struct mthca_data_seg) / 16;
1660 break;
1661 }
1662
1663 if (wr->num_sge > qp->sq.max_gs) {
1664 mthca_err(dev, "too many gathers\n");
1665 err = -EINVAL;
1666 *bad_wr = wr;
1667 goto out;
1668 }
1669
1670 for (i = 0; i < wr->num_sge; ++i) {
1671 ((struct mthca_data_seg *) wqe)->byte_count =
1672 cpu_to_be32(wr->sg_list[i].length);
1673 ((struct mthca_data_seg *) wqe)->lkey =
1674 cpu_to_be32(wr->sg_list[i].lkey);
1675 ((struct mthca_data_seg *) wqe)->addr =
1676 cpu_to_be64(wr->sg_list[i].addr);
1677 wqe += sizeof (struct mthca_data_seg);
1678 size += sizeof (struct mthca_data_seg) / 16;
1679 }
1680
1681 /* Add one more inline data segment for ICRC */
1682 if (qp->transport == MLX) {
1683 ((struct mthca_data_seg *) wqe)->byte_count =
1684 cpu_to_be32((1 << 31) | 4);
1685 ((u32 *) wqe)[1] = 0;
1686 wqe += sizeof (struct mthca_data_seg);
1687 size += sizeof (struct mthca_data_seg) / 16;
1688 }
1689
1690 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1691
1692 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1693 mthca_err(dev, "opcode invalid\n");
1694 err = -EINVAL;
1695 *bad_wr = wr;
1696 goto out;
1697 }
1698
d6cff021
RD		 1699 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1700 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1701 qp->send_wqe_offset) |
1702 mthca_opcode[wr->opcode]);
1703 wmb();
1704 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
7667abd1
DB		 1705 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1706 ((wr->send_flags & IB_SEND_FENCE) ?
1707 MTHCA_NEXT_FENCE : 0));
1da177e4
LT		 1708
1709 if (!size0) {
1710 size0 = size;
1711 op0 = mthca_opcode[wr->opcode];
e54b82d7
MT		 1712 f0 = wr->send_flags & IB_SEND_FENCE ?
1713 MTHCA_SEND_DOORBELL_FENCE : 0;
1da177e4
LT		 1714 }
1715
1716 ++ind;
1717 if (unlikely(ind >= qp->sq.max))
1718 ind -= qp->sq.max;
1719 }
1720
1721out:
1722 if (likely(nreq)) {
97f52eb4 1723 __be32 doorbell[2];
1da177e4
LT		 1724
1725 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1726 qp->send_wqe_offset) | f0 | op0);
1727 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1728
1729 wmb();
1730
1731 mthca_write64(doorbell,
1732 dev->kar + MTHCA_SEND_DOORBELL,
1733 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1734 }
1735
1736 qp->sq.next_ind = ind;
1737 qp->sq.head += nreq;
1738
1739 spin_unlock_irqrestore(&qp->sq.lock, flags);
1740 return err;
1741}
1742
1743int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1744 struct ib_recv_wr **bad_wr)
1745{
1746 struct mthca_dev *dev = to_mdev(ibqp->device);
1747 struct mthca_qp *qp = to_mqp(ibqp);
ae57e24a 1748 __be32 doorbell[2];
1da177e4
LT		 1749 unsigned long flags;
1750 int err = 0;
1751 int nreq;
1752 int i;
1753 int size;
1754 int size0 = 0;
1755 int ind;
1756 void *wqe;
1757 void *prev_wqe;
1758
1759 spin_lock_irqsave(&qp->rq.lock, flags);
1760
1761 /* XXX check that state is OK to post receive */
1762
1763 ind = qp->rq.next_ind;
1764
23f3bc0f 1765 for (nreq = 0; wr; wr = wr->next) {
1da177e4
LT		 1766 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1767 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1768 " %d max, %d nreq)\n", qp->qpn,
1769 qp->rq.head, qp->rq.tail,
1770 qp->rq.max, nreq);
1771 err = -ENOMEM;
1772 *bad_wr = wr;
1773 goto out;
1774 }
1775
1776 wqe = get_recv_wqe(qp, ind);
1777 prev_wqe = qp->rq.last;
1778 qp->rq.last = wqe;
1779
1780 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1781 ((struct mthca_next_seg *) wqe)->ee_nds =
1782 cpu_to_be32(MTHCA_NEXT_DBD);
1783 ((struct mthca_next_seg *) wqe)->flags = 0;
1784
1785 wqe += sizeof (struct mthca_next_seg);
1786 size = sizeof (struct mthca_next_seg) / 16;
1787
1788 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1789 err = -EINVAL;
1790 *bad_wr = wr;
1791 goto out;
1792 }
1793
1794 for (i = 0; i < wr->num_sge; ++i) {
1795 ((struct mthca_data_seg *) wqe)->byte_count =
1796 cpu_to_be32(wr->sg_list[i].length);
1797 ((struct mthca_data_seg *) wqe)->lkey =
1798 cpu_to_be32(wr->sg_list[i].lkey);
1799 ((struct mthca_data_seg *) wqe)->addr =
1800 cpu_to_be64(wr->sg_list[i].addr);
1801 wqe += sizeof (struct mthca_data_seg);
1802 size += sizeof (struct mthca_data_seg) / 16;
1803 }
1804
1805 qp->wrid[ind] = wr->wr_id;
1806
d6cff021
RD		 1807 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1808 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1809 wmb();
1810 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1811 cpu_to_be32(MTHCA_NEXT_DBD | size);
1da177e4
LT		 1812
1813 if (!size0)
1814 size0 = size;
1815
1816 ++ind;
1817 if (unlikely(ind >= qp->rq.max))
1818 ind -= qp->rq.max;
23f3bc0f
MT		 1819
1820 ++nreq;
1821 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1822 nreq = 0;
1823
1824 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1825 doorbell[1] = cpu_to_be32(qp->qpn << 8);
1826
1827 wmb();
1828
1829 mthca_write64(doorbell,
1830 dev->kar + MTHCA_RECEIVE_DOORBELL,
1831 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1832
1833 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1834 size0 = 0;
1835 }
1da177e4
LT		 1836 }
1837
1838out:
1839 if (likely(nreq)) {
1da177e4
LT		 1840 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1841 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1842
1843 wmb();
1844
1845 mthca_write64(doorbell,
1846 dev->kar + MTHCA_RECEIVE_DOORBELL,
1847 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1848 }
1849
1850 qp->rq.next_ind = ind;
1851 qp->rq.head += nreq;
1852
1853 spin_unlock_irqrestore(&qp->rq.lock, flags);
1854 return err;
1855}
1856
1857int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1858 struct ib_send_wr **bad_wr)
1859{
1860 struct mthca_dev *dev = to_mdev(ibqp->device);
1861 struct mthca_qp *qp = to_mqp(ibqp);
e0ae9ecf 1862 __be32 doorbell[2];
1da177e4
LT		 1863 void *wqe;
1864 void *prev_wqe;
1865 unsigned long flags;
1866 int err = 0;
1867 int nreq;
1868 int i;
1869 int size;
1870 int size0 = 0;
e54b82d7 1871 u32 f0;
1da177e4
LT		 1872 int ind;
1873 u8 op0 = 0;
1874
1875 spin_lock_irqsave(&qp->sq.lock, flags);
1876
1877 /* XXX check that state is OK to post send */
1878
1879 ind = qp->sq.head & (qp->sq.max - 1);
1880
1881 for (nreq = 0; wr; ++nreq, wr = wr->next) {
e0ae9ecf
MT		 1882 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1883 nreq = 0;
1884
1885 doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1886 ((qp->sq.head & 0xffff) << 8) |
1887 f0 | op0);
1888 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1889
1890 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1891 size0 = 0;
1892
1893 /*
1894 * Make sure that descriptors are written before
1895 * doorbell record.
1896 */
1897 wmb();
1898 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1899
1900 /*
1901 * Make sure doorbell record is written before we
1902 * write MMIO send doorbell.
1903 */
1904 wmb();
1905 mthca_write64(doorbell,
1906 dev->kar + MTHCA_SEND_DOORBELL,
1907 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1908 }
1909
1da177e4
LT		 1910 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1911 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1912 " %d max, %d nreq)\n", qp->qpn,
1913 qp->sq.head, qp->sq.tail,
1914 qp->sq.max, nreq);
1915 err = -ENOMEM;
1916 *bad_wr = wr;
1917 goto out;
1918 }
1919
1920 wqe = get_send_wqe(qp, ind);
1921 prev_wqe = qp->sq.last;
1922 qp->sq.last = wqe;
1923
1924 ((struct mthca_next_seg *) wqe)->flags =
1925 ((wr->send_flags & IB_SEND_SIGNALED) ?
1926 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1927 ((wr->send_flags & IB_SEND_SOLICITED) ?
1928 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1929 cpu_to_be32(1);
1930 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1931 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
3fba2317 1932 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1da177e4
LT		 1933
1934 wqe += sizeof (struct mthca_next_seg);
1935 size = sizeof (struct mthca_next_seg) / 16;
1936
1937 switch (qp->transport) {
ddb934e0
RD		 1938 case RC:
1939 switch (wr->opcode) {
1940 case IB_WR_ATOMIC_CMP_AND_SWP:
1941 case IB_WR_ATOMIC_FETCH_AND_ADD:
1942 ((struct mthca_raddr_seg *) wqe)->raddr =
1943 cpu_to_be64(wr->wr.atomic.remote_addr);
1944 ((struct mthca_raddr_seg *) wqe)->rkey =
1945 cpu_to_be32(wr->wr.atomic.rkey);
1946 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1947
1948 wqe += sizeof (struct mthca_raddr_seg);
1949
1950 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1951 ((struct mthca_atomic_seg *) wqe)->swap_add =
1952 cpu_to_be64(wr->wr.atomic.swap);
1953 ((struct mthca_atomic_seg *) wqe)->compare =
1954 cpu_to_be64(wr->wr.atomic.compare_add);
1955 } else {
1956 ((struct mthca_atomic_seg *) wqe)->swap_add =
1957 cpu_to_be64(wr->wr.atomic.compare_add);
1958 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1959 }
1960
1961 wqe += sizeof (struct mthca_atomic_seg);
62abb841
MT		 1962 size += (sizeof (struct mthca_raddr_seg) +
1963 sizeof (struct mthca_atomic_seg)) / 16;
ddb934e0
RD		 1964 break;
1965
9e6970b5
RD		 1966 case IB_WR_RDMA_READ:
1967 case IB_WR_RDMA_WRITE:
1968 case IB_WR_RDMA_WRITE_WITH_IMM:
1969 ((struct mthca_raddr_seg *) wqe)->raddr =
1970 cpu_to_be64(wr->wr.rdma.remote_addr);
1971 ((struct mthca_raddr_seg *) wqe)->rkey =
1972 cpu_to_be32(wr->wr.rdma.rkey);
1973 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1974 wqe += sizeof (struct mthca_raddr_seg);
1975 size += sizeof (struct mthca_raddr_seg) / 16;
1976 break;
1977
1978 default:
1979 /* No extra segments required for sends */
1980 break;
1981 }
1982
1983 break;
1984
1985 case UC:
1986 switch (wr->opcode) {
ddb934e0
RD		 1987 case IB_WR_RDMA_WRITE:
1988 case IB_WR_RDMA_WRITE_WITH_IMM:
ddb934e0
RD		 1989 ((struct mthca_raddr_seg *) wqe)->raddr =
1990 cpu_to_be64(wr->wr.rdma.remote_addr);
1991 ((struct mthca_raddr_seg *) wqe)->rkey =
1992 cpu_to_be32(wr->wr.rdma.rkey);
1993 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1994 wqe += sizeof (struct mthca_raddr_seg);
1995 size += sizeof (struct mthca_raddr_seg) / 16;
1996 break;
1997
1998 default:
1999 /* No extra segments required for sends */
2000 break;
2001 }
2002
2003 break;
2004
1da177e4
LT		 2005 case UD:
2006 memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2007 to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2008 ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2009 cpu_to_be32(wr->wr.ud.remote_qpn);
2010 ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2011 cpu_to_be32(wr->wr.ud.remote_qkey);
2012
2013 wqe += sizeof (struct mthca_arbel_ud_seg);
2014 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2015 break;
2016
2017 case MLX:
2018 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2019 wqe - sizeof (struct mthca_next_seg),
2020 wqe);
2021 if (err) {
2022 *bad_wr = wr;
2023 goto out;
2024 }
2025 wqe += sizeof (struct mthca_data_seg);
2026 size += sizeof (struct mthca_data_seg) / 16;
2027 break;
2028 }
2029
2030 if (wr->num_sge > qp->sq.max_gs) {
2031 mthca_err(dev, "too many gathers\n");
2032 err = -EINVAL;
2033 *bad_wr = wr;
2034 goto out;
2035 }
2036
2037 for (i = 0; i < wr->num_sge; ++i) {
2038 ((struct mthca_data_seg *) wqe)->byte_count =
2039 cpu_to_be32(wr->sg_list[i].length);
2040 ((struct mthca_data_seg *) wqe)->lkey =
2041 cpu_to_be32(wr->sg_list[i].lkey);
2042 ((struct mthca_data_seg *) wqe)->addr =
2043 cpu_to_be64(wr->sg_list[i].addr);
2044 wqe += sizeof (struct mthca_data_seg);
2045 size += sizeof (struct mthca_data_seg) / 16;
2046 }
2047
2048 /* Add one more inline data segment for ICRC */
2049 if (qp->transport == MLX) {
2050 ((struct mthca_data_seg *) wqe)->byte_count =
2051 cpu_to_be32((1 << 31) | 4);
2052 ((u32 *) wqe)[1] = 0;
2053 wqe += sizeof (struct mthca_data_seg);
2054 size += sizeof (struct mthca_data_seg) / 16;
2055 }
2056
2057 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2058
2059 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2060 mthca_err(dev, "opcode invalid\n");
2061 err = -EINVAL;
2062 *bad_wr = wr;
2063 goto out;
2064 }
2065
d6cff021
RD		 2066 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2067 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2068 qp->send_wqe_offset) |
2069 mthca_opcode[wr->opcode]);
2070 wmb();
2071 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
7667abd1 2072 cpu_to_be32(MTHCA_NEXT_DBD | size |
b0b3a8e1
RD		 2073 ((wr->send_flags & IB_SEND_FENCE) ?
2074 MTHCA_NEXT_FENCE : 0));
1da177e4
LT		 2075
2076 if (!size0) {
2077 size0 = size;
2078 op0 = mthca_opcode[wr->opcode];
e54b82d7
MT		 2079 f0 = wr->send_flags & IB_SEND_FENCE ?
2080 MTHCA_SEND_DOORBELL_FENCE : 0;
1da177e4
LT		 2081 }
2082
2083 ++ind;
2084 if (unlikely(ind >= qp->sq.max))
2085 ind -= qp->sq.max;
2086 }
2087
2088out:
2089 if (likely(nreq)) {
1da177e4
LT		 2090 doorbell[0] = cpu_to_be32((nreq << 24) |
2091 ((qp->sq.head & 0xffff) << 8) |
2092 f0 | op0);
2093 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2094
2095 qp->sq.head += nreq;
2096
2097 /*
2098 * Make sure that descriptors are written before
2099 * doorbell record.
2100 */
2101 wmb();
2102 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2103
2104 /*
2105 * Make sure doorbell record is written before we
2106 * write MMIO send doorbell.
2107 */
2108 wmb();
2109 mthca_write64(doorbell,
2110 dev->kar + MTHCA_SEND_DOORBELL,
2111 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2112 }
2113
2114 spin_unlock_irqrestore(&qp->sq.lock, flags);
2115 return err;
2116}
2117
2118int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2119 struct ib_recv_wr **bad_wr)
2120{
2121 struct mthca_dev *dev = to_mdev(ibqp->device);
2122 struct mthca_qp *qp = to_mqp(ibqp);
2123 unsigned long flags;
2124 int err = 0;
2125 int nreq;
2126 int ind;
2127 int i;
2128 void *wqe;
2129
2fa5e2eb 2130 spin_lock_irqsave(&qp->rq.lock, flags);
1da177e4
LT		 2131
2132 /* XXX check that state is OK to post receive */
2133
2134 ind = qp->rq.head & (qp->rq.max - 1);
2135
2136 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2137 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2138 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2139 " %d max, %d nreq)\n", qp->qpn,
2140 qp->rq.head, qp->rq.tail,
2141 qp->rq.max, nreq);
2142 err = -ENOMEM;
2143 *bad_wr = wr;
2144 goto out;
2145 }
2146
2147 wqe = get_recv_wqe(qp, ind);
2148
2149 ((struct mthca_next_seg *) wqe)->flags = 0;
2150
2151 wqe += sizeof (struct mthca_next_seg);
2152
2153 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2154 err = -EINVAL;
2155 *bad_wr = wr;
2156 goto out;
2157 }
2158
2159 for (i = 0; i < wr->num_sge; ++i) {
2160 ((struct mthca_data_seg *) wqe)->byte_count =
2161 cpu_to_be32(wr->sg_list[i].length);
2162 ((struct mthca_data_seg *) wqe)->lkey =
2163 cpu_to_be32(wr->sg_list[i].lkey);
2164 ((struct mthca_data_seg *) wqe)->addr =
2165 cpu_to_be64(wr->sg_list[i].addr);
2166 wqe += sizeof (struct mthca_data_seg);
2167 }
2168
2169 if (i < qp->rq.max_gs) {
2170 ((struct mthca_data_seg *) wqe)->byte_count = 0;
ddf841f0 2171 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1da177e4
LT		 2172 ((struct mthca_data_seg *) wqe)->addr = 0;
2173 }
2174
2175 qp->wrid[ind] = wr->wr_id;
2176
2177 ++ind;
2178 if (unlikely(ind >= qp->rq.max))
2179 ind -= qp->rq.max;
2180 }
2181out:
2182 if (likely(nreq)) {
2183 qp->rq.head += nreq;
2184
2185 /*
2186 * Make sure that descriptors are written before
2187 * doorbell record.
2188 */
2189 wmb();
2190 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2191 }
2192
2193 spin_unlock_irqrestore(&qp->rq.lock, flags);
2194 return err;
2195}
2196
d9b98b0f
RD		 2197void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2198 int index, int *dbd, __be32 *new_wqe)
1da177e4
LT		 2199{
2200 struct mthca_next_seg *next;
2201
ec34a922
RD		 2202 /*
2203 * For SRQs, all WQEs generate a CQE, so we're always at the
2204 * end of the doorbell chain.
2205 */
2206 if (qp->ibqp.srq) {
2207 *new_wqe = 0;
d9b98b0f 2208 return;
ec34a922
RD		 2209 }
2210
1da177e4
LT		 2211 if (is_send)
2212 next = get_send_wqe(qp, index);
2213 else
2214 next = get_recv_wqe(qp, index);
2215
288bdeb4 2216 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
1da177e4
LT		 2217 if (next->ee_nds & cpu_to_be32(0x3f))
2218 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2219 (next->ee_nds & cpu_to_be32(0x3f));
2220 else
2221 *new_wqe = 0;
1da177e4
LT		 2222}
2223
2224int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2225{
2226 int err;
2227 u8 status;
2228 int i;
2229
2230 spin_lock_init(&dev->qp_table.lock);
2231
2232 /*
2233 * We reserve 2 extra QPs per port for the special QPs. The
2234 * special QP for port 1 has to be even, so round up.
2235 */
2236 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2237 err = mthca_alloc_init(&dev->qp_table.alloc,
2238 dev->limits.num_qps,
2239 (1 << 24) - 1,
2240 dev->qp_table.sqp_start +
2241 MTHCA_MAX_PORTS * 2);
2242 if (err)
2243 return err;
2244
2245 err = mthca_array_init(&dev->qp_table.qp,
2246 dev->limits.num_qps);
2247 if (err) {
2248 mthca_alloc_cleanup(&dev->qp_table.alloc);
2249 return err;
2250 }
2251
2252 for (i = 0; i < 2; ++i) {
2253 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2254 dev->qp_table.sqp_start + i * 2,
2255 &status);
2256 if (err)
2257 goto err_out;
2258 if (status) {
2259 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2260 "status %02x, aborting.\n",
2261 status);
2262 err = -EINVAL;
2263 goto err_out;
2264 }
2265 }
2266 return 0;
2267
2268 err_out:
2269 for (i = 0; i < 2; ++i)
2270 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2271
2272 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2273 mthca_alloc_cleanup(&dev->qp_table.alloc);
2274
2275 return err;
2276}
2277
e1f7868c 2278void mthca_cleanup_qp_table(struct mthca_dev *dev)
1da177e4
LT		 2279{
2280 int i;
2281 u8 status;
2282
2283 for (i = 0; i < 2; ++i)
2284 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2285
71eea47d 2286 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
1da177e4
LT		 2287 mthca_alloc_cleanup(&dev->qp_table.alloc);
2288}
Linux kernel - Deliverables
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