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3c2d774c | 1 | /* |
fa6c87d5 | 2 | * Copyright (c) 2006 - 2009 Intel Corporation. All rights reserved. |
3c2d774c GS |
3 | * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #ifndef __NES_H | |
35 | #define __NES_H | |
36 | ||
37 | #include <linux/netdevice.h> | |
38 | #include <linux/inetdevice.h> | |
39 | #include <linux/spinlock.h> | |
40 | #include <linux/kernel.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/pci.h> | |
43 | #include <linux/dma-mapping.h> | |
44 | #include <linux/workqueue.h> | |
45 | #include <linux/slab.h> | |
3c2d774c GS |
46 | #include <asm/io.h> |
47 | #include <linux/crc32c.h> | |
48 | ||
49 | #include <rdma/ib_smi.h> | |
50 | #include <rdma/ib_verbs.h> | |
51 | #include <rdma/ib_pack.h> | |
52 | #include <rdma/rdma_cm.h> | |
53 | #include <rdma/iw_cm.h> | |
54 | ||
55 | #define NES_SEND_FIRST_WRITE | |
56 | ||
57 | #define QUEUE_DISCONNECTS | |
58 | ||
3c2d774c | 59 | #define DRV_NAME "iw_nes" |
26cc5e57 | 60 | #define DRV_VERSION "1.5.0.0" |
3c2d774c GS |
61 | #define PFX DRV_NAME ": " |
62 | ||
63 | /* | |
64 | * NetEffect PCI vendor id and NE010 PCI device id. | |
65 | */ | |
66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ | |
09124e19 CT |
67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 |
68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 | |
69 | #define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110 | |
3c2d774c GS |
70 | #endif |
71 | ||
72 | #define NE020_REV 4 | |
73 | #define NE020_REV1 5 | |
74 | ||
75 | #define BAR_0 0 | |
76 | #define BAR_1 2 | |
77 | ||
78 | #define RX_BUF_SIZE (1536 + 8) | |
79 | #define NES_REG0_SIZE (4 * 1024) | |
80 | #define NES_TX_TIMEOUT (6*HZ) | |
81 | #define NES_FIRST_QPN 64 | |
82 | #define NES_SW_CONTEXT_ALIGN 1024 | |
83 | ||
84 | #define NES_NIC_MAX_NICS 16 | |
85 | #define NES_MAX_ARP_TABLE_SIZE 4096 | |
86 | ||
87 | #define NES_NIC_CEQ_SIZE 8 | |
88 | /* NICs will be on a separate CQ */ | |
89 | #define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32) | |
90 | ||
91 | #define NES_MAX_PORT_COUNT 4 | |
92 | ||
93 | #define MAX_DPC_ITERATIONS 128 | |
94 | ||
3c2d774c GS |
95 | #define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001 |
96 | #define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002 | |
97 | #define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004 | |
98 | #define NES_DRV_OPT_DISABLE_INTF 0x00000008 | |
99 | #define NES_DRV_OPT_ENABLE_MSI 0x00000010 | |
100 | #define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020 | |
101 | #define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040 | |
102 | #define NES_DRV_OPT_NO_INLINE_DATA 0x00000080 | |
103 | #define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100 | |
104 | #define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200 | |
105 | ||
106 | #define NES_AEQ_EVENT_TIMEOUT 2500 | |
107 | #define NES_DISCONNECT_EVENT_TIMEOUT 2000 | |
108 | ||
109 | /* debug levels */ | |
110 | /* must match userspace */ | |
111 | #define NES_DBG_HW 0x00000001 | |
112 | #define NES_DBG_INIT 0x00000002 | |
113 | #define NES_DBG_ISR 0x00000004 | |
114 | #define NES_DBG_PHY 0x00000008 | |
115 | #define NES_DBG_NETDEV 0x00000010 | |
116 | #define NES_DBG_CM 0x00000020 | |
117 | #define NES_DBG_CM1 0x00000040 | |
118 | #define NES_DBG_NIC_RX 0x00000080 | |
119 | #define NES_DBG_NIC_TX 0x00000100 | |
120 | #define NES_DBG_CQP 0x00000200 | |
121 | #define NES_DBG_MMAP 0x00000400 | |
122 | #define NES_DBG_MR 0x00000800 | |
123 | #define NES_DBG_PD 0x00001000 | |
124 | #define NES_DBG_CQ 0x00002000 | |
125 | #define NES_DBG_QP 0x00004000 | |
126 | #define NES_DBG_MOD_QP 0x00008000 | |
127 | #define NES_DBG_AEQ 0x00010000 | |
128 | #define NES_DBG_IW_RX 0x00020000 | |
129 | #define NES_DBG_IW_TX 0x00040000 | |
130 | #define NES_DBG_SHUTDOWN 0x00080000 | |
131 | #define NES_DBG_RSVD1 0x10000000 | |
132 | #define NES_DBG_RSVD2 0x20000000 | |
133 | #define NES_DBG_RSVD3 0x40000000 | |
134 | #define NES_DBG_RSVD4 0x80000000 | |
135 | #define NES_DBG_ALL 0xffffffff | |
136 | ||
137 | #ifdef CONFIG_INFINIBAND_NES_DEBUG | |
138 | #define nes_debug(level, fmt, args...) \ | |
6098d107 | 139 | do { \ |
3c2d774c | 140 | if (level & nes_debug_level) \ |
6098d107 CT |
141 | printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \ |
142 | } while (0) | |
143 | ||
144 | #define assert(expr) \ | |
145 | do { \ | |
146 | if (!(expr)) { \ | |
147 | printk(KERN_ERR PFX "Assertion failed! %s, %s, %s, line %d\n", \ | |
148 | #expr, __FILE__, __func__, __LINE__); \ | |
149 | } \ | |
150 | } while (0) | |
3c2d774c GS |
151 | |
152 | #define NES_EVENT_TIMEOUT 1200000 | |
153 | #else | |
154 | #define nes_debug(level, fmt, args...) | |
155 | #define assert(expr) do {} while (0) | |
156 | ||
157 | #define NES_EVENT_TIMEOUT 100000 | |
158 | #endif | |
159 | ||
160 | #include "nes_hw.h" | |
161 | #include "nes_verbs.h" | |
162 | #include "nes_context.h" | |
163 | #include "nes_user.h" | |
164 | #include "nes_cm.h" | |
165 | ||
166 | extern int max_mtu; | |
3c2d774c GS |
167 | #define max_frame_len (max_mtu+ETH_HLEN) |
168 | extern int interrupt_mod_interval; | |
169 | extern int nes_if_count; | |
170 | extern int mpa_version; | |
171 | extern int disable_mpa_crc; | |
172 | extern unsigned int send_first; | |
173 | extern unsigned int nes_drv_opt; | |
174 | extern unsigned int nes_debug_level; | |
2b537c28 | 175 | extern unsigned int wqm_quanta; |
3c2d774c | 176 | extern struct list_head nes_adapter_list; |
3c2d774c GS |
177 | |
178 | extern atomic_t cm_connects; | |
179 | extern atomic_t cm_accepts; | |
180 | extern atomic_t cm_disconnects; | |
181 | extern atomic_t cm_closes; | |
182 | extern atomic_t cm_connecteds; | |
183 | extern atomic_t cm_connect_reqs; | |
184 | extern atomic_t cm_rejects; | |
185 | extern atomic_t mod_qp_timouts; | |
186 | extern atomic_t qps_created; | |
187 | extern atomic_t qps_destroyed; | |
188 | extern atomic_t sw_qps_destroyed; | |
189 | extern u32 mh_detected; | |
190 | extern u32 mh_pauses_sent; | |
191 | extern u32 cm_packets_sent; | |
192 | extern u32 cm_packets_bounced; | |
193 | extern u32 cm_packets_created; | |
194 | extern u32 cm_packets_received; | |
195 | extern u32 cm_packets_dropped; | |
196 | extern u32 cm_packets_retrans; | |
6e10d2e4 FL |
197 | extern atomic_t cm_listens_created; |
198 | extern atomic_t cm_listens_destroyed; | |
3c2d774c GS |
199 | extern u32 cm_backlog_drops; |
200 | extern atomic_t cm_loopbacks; | |
201 | extern atomic_t cm_nodes_created; | |
202 | extern atomic_t cm_nodes_destroyed; | |
203 | extern atomic_t cm_accel_dropped_pkts; | |
204 | extern atomic_t cm_resets_recvd; | |
205 | ||
3c2d774c GS |
206 | extern u32 int_mod_timer_init; |
207 | extern u32 int_mod_cq_depth_256; | |
208 | extern u32 int_mod_cq_depth_128; | |
209 | extern u32 int_mod_cq_depth_32; | |
210 | extern u32 int_mod_cq_depth_24; | |
211 | extern u32 int_mod_cq_depth_16; | |
212 | extern u32 int_mod_cq_depth_4; | |
213 | extern u32 int_mod_cq_depth_1; | |
214 | ||
3c2d774c GS |
215 | struct nes_device { |
216 | struct nes_adapter *nesadapter; | |
217 | void __iomem *regs; | |
218 | void __iomem *index_reg; | |
219 | struct pci_dev *pcidev; | |
220 | struct net_device *netdev[NES_NIC_MAX_NICS]; | |
221 | u64 link_status_interrupts; | |
222 | struct tasklet_struct dpc_tasklet; | |
223 | spinlock_t indexed_regs_lock; | |
224 | unsigned long csr_start; | |
225 | unsigned long doorbell_region; | |
226 | unsigned long doorbell_start; | |
227 | unsigned long mac_tx_errors; | |
228 | unsigned long mac_pause_frames_sent; | |
229 | unsigned long mac_pause_frames_received; | |
230 | unsigned long mac_rx_errors; | |
231 | unsigned long mac_rx_crc_errors; | |
232 | unsigned long mac_rx_symbol_err_frames; | |
233 | unsigned long mac_rx_jabber_frames; | |
234 | unsigned long mac_rx_oversized_frames; | |
235 | unsigned long mac_rx_short_frames; | |
236 | unsigned long port_rx_discards; | |
237 | unsigned long port_tx_discards; | |
238 | unsigned int mac_index; | |
239 | unsigned int nes_stack_start; | |
240 | ||
241 | /* Control Structures */ | |
242 | void *cqp_vbase; | |
243 | dma_addr_t cqp_pbase; | |
244 | u32 cqp_mem_size; | |
245 | u8 ceq_index; | |
246 | u8 nic_ceq_index; | |
247 | struct nes_hw_cqp cqp; | |
248 | struct nes_hw_cq ccq; | |
249 | struct list_head cqp_avail_reqs; | |
250 | struct list_head cqp_pending_reqs; | |
251 | struct nes_cqp_request *nes_cqp_requests; | |
252 | ||
253 | u32 int_req; | |
254 | u32 int_stat; | |
255 | u32 timer_int_req; | |
256 | u32 timer_only_int_count; | |
257 | u32 intf_int_req; | |
258 | u32 last_mac_tx_pauses; | |
259 | u32 last_used_chunks_tx; | |
260 | struct list_head list; | |
261 | ||
262 | u16 base_doorbell_index; | |
263 | u16 currcq_count; | |
264 | u16 deepcq_count; | |
265 | u8 msi_enabled; | |
266 | u8 netdev_count; | |
267 | u8 napi_isr_ran; | |
268 | u8 disable_rx_flow_control; | |
269 | u8 disable_tx_flow_control; | |
270 | }; | |
271 | ||
272 | ||
30da7cff FL |
273 | static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad) |
274 | { | |
275 | u32 crc_value; | |
276 | crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad)); | |
277 | ||
278 | /* | |
279 | * With commit ef19454b ("[LIB] crc32c: Keep intermediate crc | |
280 | * state in cpu order"), behavior of crc32c changes on | |
281 | * big-endian platforms. Our algorithm expects the previous | |
282 | * behavior; otherwise we have RDMA connection establishment | |
283 | * issue on big-endian. | |
284 | */ | |
285 | return cpu_to_le32(crc_value); | |
286 | } | |
287 | ||
3c2d774c GS |
288 | static inline void |
289 | set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value) | |
290 | { | |
7a5efb62 DW |
291 | wqe_words[index] = cpu_to_le32((u32) value); |
292 | wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value)); | |
3c2d774c GS |
293 | } |
294 | ||
295 | static inline void | |
296 | set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value) | |
297 | { | |
298 | wqe_words[index] = cpu_to_le32(value); | |
299 | } | |
300 | ||
301 | static inline void | |
302 | nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev) | |
303 | { | |
304 | set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_CTX_LOW_IDX, | |
305 | (u64)((unsigned long) &nesdev->cqp)); | |
306 | cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0; | |
307 | cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0; | |
308 | cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0; | |
309 | cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0; | |
310 | cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0; | |
311 | cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0; | |
312 | cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0; | |
313 | } | |
314 | ||
315 | static inline void | |
316 | nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head) | |
317 | { | |
318 | u32 value; | |
319 | value = ((u32)((unsigned long) nesqp)) | head; | |
320 | set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX, | |
321 | (u32)(upper_32_bits((unsigned long)(nesqp)))); | |
322 | set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value); | |
323 | } | |
324 | ||
325 | /* Read from memory-mapped device */ | |
326 | static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index) | |
327 | { | |
328 | unsigned long flags; | |
329 | void __iomem *addr = nesdev->index_reg; | |
330 | u32 value; | |
331 | ||
332 | spin_lock_irqsave(&nesdev->indexed_regs_lock, flags); | |
333 | ||
334 | writel(reg_index, addr); | |
335 | value = readl((void __iomem *)addr + 4); | |
336 | ||
337 | spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags); | |
338 | return value; | |
339 | } | |
340 | ||
341 | static inline u32 nes_read32(const void __iomem *addr) | |
342 | { | |
343 | return readl(addr); | |
344 | } | |
345 | ||
346 | static inline u16 nes_read16(const void __iomem *addr) | |
347 | { | |
348 | return readw(addr); | |
349 | } | |
350 | ||
351 | static inline u8 nes_read8(const void __iomem *addr) | |
352 | { | |
353 | return readb(addr); | |
354 | } | |
355 | ||
356 | /* Write to memory-mapped device */ | |
357 | static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val) | |
358 | { | |
359 | unsigned long flags; | |
360 | void __iomem *addr = nesdev->index_reg; | |
361 | ||
362 | spin_lock_irqsave(&nesdev->indexed_regs_lock, flags); | |
363 | ||
364 | writel(reg_index, addr); | |
365 | writel(val, (void __iomem *)addr + 4); | |
366 | ||
367 | spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags); | |
368 | } | |
369 | ||
370 | static inline void nes_write32(void __iomem *addr, u32 val) | |
371 | { | |
372 | writel(val, addr); | |
373 | } | |
374 | ||
375 | static inline void nes_write16(void __iomem *addr, u16 val) | |
376 | { | |
377 | writew(val, addr); | |
378 | } | |
379 | ||
380 | static inline void nes_write8(void __iomem *addr, u8 val) | |
381 | { | |
382 | writeb(val, addr); | |
383 | } | |
384 | ||
385 | ||
386 | ||
387 | static inline int nes_alloc_resource(struct nes_adapter *nesadapter, | |
388 | unsigned long *resource_array, u32 max_resources, | |
389 | u32 *req_resource_num, u32 *next) | |
390 | { | |
391 | unsigned long flags; | |
392 | u32 resource_num; | |
393 | ||
394 | spin_lock_irqsave(&nesadapter->resource_lock, flags); | |
395 | ||
396 | resource_num = find_next_zero_bit(resource_array, max_resources, *next); | |
397 | if (resource_num >= max_resources) { | |
398 | resource_num = find_first_zero_bit(resource_array, max_resources); | |
399 | if (resource_num >= max_resources) { | |
33718363 | 400 | printk(KERN_ERR PFX "%s: No available resourcess.\n", __func__); |
3c2d774c GS |
401 | spin_unlock_irqrestore(&nesadapter->resource_lock, flags); |
402 | return -EMFILE; | |
403 | } | |
404 | } | |
405 | set_bit(resource_num, resource_array); | |
406 | *next = resource_num+1; | |
407 | if (*next == max_resources) { | |
408 | *next = 0; | |
409 | } | |
410 | spin_unlock_irqrestore(&nesadapter->resource_lock, flags); | |
411 | *req_resource_num = resource_num; | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter, | |
417 | unsigned long *resource_array, u32 resource_num) | |
418 | { | |
419 | unsigned long flags; | |
420 | int bit_is_set; | |
421 | ||
422 | spin_lock_irqsave(&nesadapter->resource_lock, flags); | |
423 | ||
424 | bit_is_set = test_bit(resource_num, resource_array); | |
425 | nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n", | |
426 | resource_num, (bit_is_set ? "": " not")); | |
427 | spin_unlock_irqrestore(&nesadapter->resource_lock, flags); | |
428 | ||
429 | return bit_is_set; | |
430 | } | |
431 | ||
432 | static inline void nes_free_resource(struct nes_adapter *nesadapter, | |
433 | unsigned long *resource_array, u32 resource_num) | |
434 | { | |
435 | unsigned long flags; | |
436 | ||
437 | spin_lock_irqsave(&nesadapter->resource_lock, flags); | |
438 | clear_bit(resource_num, resource_array); | |
439 | spin_unlock_irqrestore(&nesadapter->resource_lock, flags); | |
440 | } | |
441 | ||
442 | static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev) | |
443 | { | |
444 | return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic; | |
445 | } | |
446 | ||
447 | static inline struct nes_pd *to_nespd(struct ib_pd *ibpd) | |
448 | { | |
449 | return container_of(ibpd, struct nes_pd, ibpd); | |
450 | } | |
451 | ||
452 | static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext) | |
453 | { | |
454 | return container_of(ibucontext, struct nes_ucontext, ibucontext); | |
455 | } | |
456 | ||
457 | static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr) | |
458 | { | |
459 | return container_of(ibmr, struct nes_mr, ibmr); | |
460 | } | |
461 | ||
462 | static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr) | |
463 | { | |
464 | return container_of(ibfmr, struct nes_mr, ibfmr); | |
465 | } | |
466 | ||
467 | static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw) | |
468 | { | |
469 | return container_of(ibmw, struct nes_mr, ibmw); | |
470 | } | |
471 | ||
472 | static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr) | |
473 | { | |
474 | return container_of(nesmr, struct nes_fmr, nesmr); | |
475 | } | |
476 | ||
477 | static inline struct nes_cq *to_nescq(struct ib_cq *ibcq) | |
478 | { | |
479 | return container_of(ibcq, struct nes_cq, ibcq); | |
480 | } | |
481 | ||
482 | static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp) | |
483 | { | |
484 | return container_of(ibqp, struct nes_qp, ibqp); | |
485 | } | |
486 | ||
487 | ||
488 | ||
489 | /* nes.c */ | |
490 | void nes_add_ref(struct ib_qp *); | |
491 | void nes_rem_ref(struct ib_qp *); | |
492 | struct ib_qp *nes_get_qp(struct ib_device *, int); | |
493 | ||
494 | ||
495 | /* nes_hw.c */ | |
496 | struct nes_adapter *nes_init_adapter(struct nes_device *, u8); | |
497 | void nes_nic_init_timer_defaults(struct nes_device *, u8); | |
3c2d774c GS |
498 | void nes_destroy_adapter(struct nes_adapter *); |
499 | int nes_init_cqp(struct nes_device *); | |
500 | int nes_init_phy(struct nes_device *); | |
501 | int nes_init_nic_qp(struct nes_device *, struct net_device *); | |
502 | void nes_destroy_nic_qp(struct nes_vnic *); | |
503 | int nes_napi_isr(struct nes_device *); | |
504 | void nes_dpc(unsigned long); | |
3c2d774c | 505 | void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *); |
3c2d774c GS |
506 | void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *); |
507 | int nes_destroy_cqp(struct nes_device *); | |
508 | int nes_nic_cm_xmit(struct sk_buff *, struct net_device *); | |
509 | ||
510 | /* nes_nic.c */ | |
3c2d774c GS |
511 | struct net_device *nes_netdev_init(struct nes_device *, void __iomem *); |
512 | void nes_netdev_destroy(struct net_device *); | |
513 | int nes_nic_cm_xmit(struct sk_buff *, struct net_device *); | |
514 | ||
515 | /* nes_cm.c */ | |
516 | void *nes_cm_create(struct net_device *); | |
517 | int nes_cm_recv(struct sk_buff *, struct net_device *); | |
518 | void nes_update_arp(unsigned char *, u32, u32, u16, u16); | |
519 | void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32); | |
520 | void nes_sock_release(struct nes_qp *, unsigned long *); | |
3c2d774c GS |
521 | void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32); |
522 | int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32); | |
523 | int nes_cm_disconn(struct nes_qp *); | |
524 | void nes_cm_disconn_worker(void *); | |
525 | ||
526 | /* nes_verbs.c */ | |
8b1c9dc4 | 527 | int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32, u32); |
3c2d774c GS |
528 | int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *); |
529 | struct nes_ib_device *nes_init_ofa_device(struct net_device *); | |
530 | void nes_destroy_ofa_device(struct nes_ib_device *); | |
531 | int nes_register_ofa_device(struct nes_ib_device *); | |
3c2d774c GS |
532 | |
533 | /* nes_util.c */ | |
534 | int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *); | |
535 | void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16); | |
536 | void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *); | |
0e1de5d6 ES |
537 | void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16); |
538 | void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16); | |
3c2d774c | 539 | struct nes_cqp_request *nes_get_cqp_request(struct nes_device *); |
1ff66e8c RD |
540 | void nes_free_cqp_request(struct nes_device *nesdev, |
541 | struct nes_cqp_request *cqp_request); | |
542 | void nes_put_cqp_request(struct nes_device *nesdev, | |
543 | struct nes_cqp_request *cqp_request); | |
8294f297 | 544 | void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *); |
3c2d774c GS |
545 | int nes_arp_table(struct nes_device *, u32, u8 *, u32); |
546 | void nes_mh_fix(unsigned long); | |
547 | void nes_clc(unsigned long); | |
548 | void nes_dump_mem(unsigned int, void *, int); | |
549 | u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32); | |
550 | ||
551 | #endif /* __NES_H */ |