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RDMA/ocrdma: Handle CQ overrun error
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
35#include <rdma/ib_addr.h>
36
37#include "ocrdma.h"
38#include "ocrdma_hw.h"
39#include "ocrdma_verbs.h"
40#include "ocrdma_ah.h"
41
42enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81};
82
83enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85};
86
87enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93};
94
95static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96{
f99b1649 97 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 98}
99
100static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101{
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103}
104
105static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106{
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 108 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 109
110 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
111 return NULL;
112 return cqe;
113}
114
115static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
116{
117 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
118}
119
120static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
121{
f99b1649 122 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 123}
124
125static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
126{
127 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 128}
129
130static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
131{
f99b1649 132 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 133}
134
135enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
136{
137 switch (qps) {
138 case OCRDMA_QPS_RST:
139 return IB_QPS_RESET;
140 case OCRDMA_QPS_INIT:
141 return IB_QPS_INIT;
142 case OCRDMA_QPS_RTR:
143 return IB_QPS_RTR;
144 case OCRDMA_QPS_RTS:
145 return IB_QPS_RTS;
146 case OCRDMA_QPS_SQD:
147 case OCRDMA_QPS_SQ_DRAINING:
148 return IB_QPS_SQD;
149 case OCRDMA_QPS_SQE:
150 return IB_QPS_SQE;
151 case OCRDMA_QPS_ERR:
152 return IB_QPS_ERR;
2b50176d 153 }
fe2caefc
PP		 154 return IB_QPS_ERR;
155}
156
abe3afac 157static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 158{
159 switch (qps) {
160 case IB_QPS_RESET:
161 return OCRDMA_QPS_RST;
162 case IB_QPS_INIT:
163 return OCRDMA_QPS_INIT;
164 case IB_QPS_RTR:
165 return OCRDMA_QPS_RTR;
166 case IB_QPS_RTS:
167 return OCRDMA_QPS_RTS;
168 case IB_QPS_SQD:
169 return OCRDMA_QPS_SQD;
170 case IB_QPS_SQE:
171 return OCRDMA_QPS_SQE;
172 case IB_QPS_ERR:
173 return OCRDMA_QPS_ERR;
2b50176d 174 }
fe2caefc
PP		 175 return OCRDMA_QPS_ERR;
176}
177
178static int ocrdma_get_mbx_errno(u32 status)
179{
f99b1649 180 int err_num;
fe2caefc
PP		 181 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
182 OCRDMA_MBX_RSP_STATUS_SHIFT;
183 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
184 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
185
186 switch (mbox_status) {
187 case OCRDMA_MBX_STATUS_OOR:
188 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
189 err_num = -EAGAIN;
190 break;
191
192 case OCRDMA_MBX_STATUS_INVALID_PD:
193 case OCRDMA_MBX_STATUS_INVALID_CQ:
194 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
195 case OCRDMA_MBX_STATUS_INVALID_QP:
196 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
197 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
198 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
200 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
201 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
202 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
203 case OCRDMA_MBX_STATUS_INVALID_LKEY:
204 case OCRDMA_MBX_STATUS_INVALID_VA:
205 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
206 case OCRDMA_MBX_STATUS_INVALID_FBO:
207 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
208 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
209 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
210 case OCRDMA_MBX_STATUS_SRQ_ERROR:
211 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
212 err_num = -EINVAL;
213 break;
214
215 case OCRDMA_MBX_STATUS_PD_INUSE:
216 case OCRDMA_MBX_STATUS_QP_BOUND:
217 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
218 case OCRDMA_MBX_STATUS_MW_BOUND:
219 err_num = -EBUSY;
220 break;
221
222 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
223 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
224 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
225 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
226 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
230 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
231 err_num = -ENOBUFS;
232 break;
233
234 case OCRDMA_MBX_STATUS_FAILED:
235 switch (add_status) {
236 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
237 err_num = -EAGAIN;
238 break;
239 }
240 default:
241 err_num = -EFAULT;
242 }
243 return err_num;
244}
245
246static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
247{
248 int err_num = -EINVAL;
249
250 switch (cqe_status) {
251 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
252 err_num = -EPERM;
253 break;
254 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
255 err_num = -EINVAL;
256 break;
257 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
258 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
f11220ee 259 err_num = -EINVAL;
fe2caefc
PP		 260 break;
261 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
43a6b402 262 default:
f11220ee 263 err_num = -EINVAL;
fe2caefc
PP		 264 break;
265 }
266 return err_num;
267}
268
269void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
270 bool solicited, u16 cqe_popped)
271{
272 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
273
274 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
275 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
276
277 if (armed)
278 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
279 if (solicited)
280 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
281 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
282 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
283}
284
285static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
286{
287 u32 val = 0;
288
289 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
290 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
291 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
292}
293
294static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
295 bool arm, bool clear_int, u16 num_eqe)
296{
297 u32 val = 0;
298
299 val |= eq_id & OCRDMA_EQ_ID_MASK;
300 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
301 if (arm)
302 val |= (1 << OCRDMA_REARM_SHIFT);
303 if (clear_int)
304 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
305 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
306 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
308}
309
310static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
311 u8 opcode, u8 subsys, u32 cmd_len)
312{
313 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
314 cmd_hdr->timeout = 20; /* seconds */
315 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
316}
317
318static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
319{
320 struct ocrdma_mqe *mqe;
321
322 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
323 if (!mqe)
324 return NULL;
325 mqe->hdr.spcl_sge_cnt_emb |=
326 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
327 OCRDMA_MQE_HDR_EMB_MASK;
328 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
329
330 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
331 mqe->hdr.pyld_len);
332 return mqe;
333}
334
335static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
336{
337 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
338}
339
340static int ocrdma_alloc_q(struct ocrdma_dev *dev,
341 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
342{
343 memset(q, 0, sizeof(*q));
344 q->len = len;
345 q->entry_size = entry_size;
346 q->size = len * entry_size;
347 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
348 &q->dma, GFP_KERNEL);
349 if (!q->va)
350 return -ENOMEM;
351 memset(q->va, 0, q->size);
352 return 0;
353}
354
355static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
356 dma_addr_t host_pa, int hw_page_size)
357{
358 int i;
359
360 for (i = 0; i < cnt; i++) {
361 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
362 q_pa[i].hi = (u32) upper_32_bits(host_pa);
363 host_pa += hw_page_size;
364 }
365}
366
abe3afac
RD		 367static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
368 int queue_type)
fe2caefc
PP		 369{
370 u8 opcode = 0;
371 int status;
372 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
373
374 switch (queue_type) {
375 case QTYPE_MCCQ:
376 opcode = OCRDMA_CMD_DELETE_MQ;
377 break;
378 case QTYPE_CQ:
379 opcode = OCRDMA_CMD_DELETE_CQ;
380 break;
381 case QTYPE_EQ:
382 opcode = OCRDMA_CMD_DELETE_EQ;
383 break;
384 default:
385 BUG();
386 }
387 memset(cmd, 0, sizeof(*cmd));
388 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
389 cmd->id = q->id;
390
391 status = be_roce_mcc_cmd(dev->nic_info.netdev,
392 cmd, sizeof(*cmd), NULL, NULL);
393 if (!status)
394 q->created = false;
395 return status;
396}
397
398static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
399{
400 int status;
401 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
402 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
403
404 memset(cmd, 0, sizeof(*cmd));
405 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
406 sizeof(*cmd));
fe2caefc 407
c88bd03f 408 cmd->req.rsvd_version = 2;
fe2caefc
PP		 409 cmd->num_pages = 4;
410 cmd->valid = OCRDMA_CREATE_EQ_VALID;
411 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
412
413 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
414 PAGE_SIZE_4K);
415 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
416 NULL);
417 if (!status) {
418 eq->q.id = rsp->vector_eqid & 0xffff;
c88bd03f 419 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
fe2caefc
PP		 420 eq->q.created = true;
421 }
422 return status;
423}
424
425static int ocrdma_create_eq(struct ocrdma_dev *dev,
426 struct ocrdma_eq *eq, u16 q_len)
427{
428 int status;
429
430 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
431 sizeof(struct ocrdma_eqe));
432 if (status)
433 return status;
434
435 status = ocrdma_mbx_create_eq(dev, eq);
436 if (status)
437 goto mbx_err;
438 eq->dev = dev;
439 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
440
441 return 0;
442mbx_err:
443 ocrdma_free_q(dev, &eq->q);
444 return status;
445}
446
ea617626 447int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
fe2caefc
PP		 448{
449 int irq;
450
451 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
452 irq = dev->nic_info.pdev->irq;
453 else
454 irq = dev->nic_info.msix.vector_list[eq->vector];
455 return irq;
456}
457
458static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
459{
460 if (eq->q.created) {
461 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
fe2caefc
PP		 462 ocrdma_free_q(dev, &eq->q);
463 }
464}
465
466static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
467{
468 int irq;
469
470 /* disarm EQ so that interrupts are not generated
471 * during freeing and EQ delete is in progress.
472 */
473 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
474
475 irq = ocrdma_get_irq(dev, eq);
476 free_irq(irq, eq);
477 _ocrdma_destroy_eq(dev, eq);
478}
479
c88bd03f 480static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
fe2caefc
PP		 481{
482 int i;
483
fe2caefc 484 for (i = 0; i < dev->eq_cnt; i++)
c88bd03f 485 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
fe2caefc
PP		 486}
487
abe3afac
RD		 488static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
489 struct ocrdma_queue_info *cq,
490 struct ocrdma_queue_info *eq)
fe2caefc
PP		 491{
492 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
493 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
494 int status;
495
496 memset(cmd, 0, sizeof(*cmd));
497 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
498 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
499
1afc0454
NG		 500 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
501 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
502 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
503 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
504
fe2caefc 505 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454
NG		 506 cmd->eqn = eq->id;
507 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 508
1afc0454 509 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 510 cq->dma, PAGE_SIZE_4K);
511 status = be_roce_mcc_cmd(dev->nic_info.netdev,
512 cmd, sizeof(*cmd), NULL, NULL);
513 if (!status) {
1afc0454 514 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 515 cq->created = true;
516 }
517 return status;
518}
519
520static u32 ocrdma_encoded_q_len(int q_len)
521{
522 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
523
524 if (len_encoded == 16)
525 len_encoded = 0;
526 return len_encoded;
527}
528
529static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
530 struct ocrdma_queue_info *mq,
531 struct ocrdma_queue_info *cq)
532{
533 int num_pages, status;
534 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
535 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
536 struct ocrdma_pa *pa;
537
538 memset(cmd, 0, sizeof(*cmd));
539 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
540
b1d58b99
NG		 541 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
542 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
543 cmd->req.rsvd_version = 1;
544 cmd->cqid_pages = num_pages;
545 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
546 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
84b105db
NG		 547
548 cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
549 cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
550
b1d58b99
NG		 551 cmd->async_cqid_ringsize = cq->id;
552 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
553 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
554 cmd->valid = OCRDMA_CREATE_MQ_VALID;
555 pa = &cmd->pa[0];
556
fe2caefc
PP		 557 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
558 status = be_roce_mcc_cmd(dev->nic_info.netdev,
559 cmd, sizeof(*cmd), NULL, NULL);
560 if (!status) {
561 mq->id = rsp->id;
562 mq->created = true;
563 }
564 return status;
565}
566
567static int ocrdma_create_mq(struct ocrdma_dev *dev)
568{
569 int status;
570
571 /* Alloc completion queue for Mailbox queue */
572 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
573 sizeof(struct ocrdma_mcqe));
574 if (status)
575 goto alloc_err;
576
ea617626 577 dev->eq_tbl[0].cq_cnt++;
c88bd03f 578 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
fe2caefc
PP		 579 if (status)
580 goto mbx_cq_free;
581
582 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
583 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
584 mutex_init(&dev->mqe_ctx.lock);
585
586 /* Alloc Mailbox queue */
587 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
588 sizeof(struct ocrdma_mqe));
589 if (status)
590 goto mbx_cq_destroy;
591 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
592 if (status)
593 goto mbx_q_free;
594 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
595 return 0;
596
597mbx_q_free:
598 ocrdma_free_q(dev, &dev->mq.sq);
599mbx_cq_destroy:
600 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
601mbx_cq_free:
602 ocrdma_free_q(dev, &dev->mq.cq);
603alloc_err:
604 return status;
605}
606
607static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
608{
609 struct ocrdma_queue_info *mbxq, *cq;
610
611 /* mqe_ctx lock synchronizes with any other pending cmds. */
612 mutex_lock(&dev->mqe_ctx.lock);
613 mbxq = &dev->mq.sq;
614 if (mbxq->created) {
615 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
616 ocrdma_free_q(dev, mbxq);
617 }
618 mutex_unlock(&dev->mqe_ctx.lock);
619
620 cq = &dev->mq.cq;
621 if (cq->created) {
622 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
623 ocrdma_free_q(dev, cq);
624 }
625}
626
627static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
628 struct ocrdma_qp *qp)
629{
630 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
631 enum ib_qp_state old_ib_qps;
632
633 if (qp == NULL)
634 BUG();
057729cb 635 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 636}
637
638static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
639 struct ocrdma_ae_mcqe *cqe)
640{
641 struct ocrdma_qp *qp = NULL;
642 struct ocrdma_cq *cq = NULL;
1228056b 643 struct ib_event ib_evt = { 0 };
fe2caefc
PP		 644 int cq_event = 0;
645 int qp_event = 1;
646 int srq_event = 0;
647 int dev_event = 0;
648 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
649 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
650
651 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
652 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
653 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
654 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
655
e9db2953
RD		 656 ib_evt.device = &dev->ibdev;
657
fe2caefc
PP		 658 switch (type) {
659 case OCRDMA_CQ_ERROR:
660 ib_evt.element.cq = &cq->ibcq;
661 ib_evt.event = IB_EVENT_CQ_ERR;
662 cq_event = 1;
663 qp_event = 0;
664 break;
665 case OCRDMA_CQ_OVERRUN_ERROR:
666 ib_evt.element.cq = &cq->ibcq;
667 ib_evt.event = IB_EVENT_CQ_ERR;
1228056b
SX		 668 cq_event = 1;
669 qp_event = 0;
fe2caefc
PP		 670 break;
671 case OCRDMA_CQ_QPCAT_ERROR:
672 ib_evt.element.qp = &qp->ibqp;
673 ib_evt.event = IB_EVENT_QP_FATAL;
674 ocrdma_process_qpcat_error(dev, qp);
675 break;
676 case OCRDMA_QP_ACCESS_ERROR:
677 ib_evt.element.qp = &qp->ibqp;
678 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
679 break;
680 case OCRDMA_QP_COMM_EST_EVENT:
681 ib_evt.element.qp = &qp->ibqp;
682 ib_evt.event = IB_EVENT_COMM_EST;
683 break;
684 case OCRDMA_SQ_DRAINED_EVENT:
685 ib_evt.element.qp = &qp->ibqp;
686 ib_evt.event = IB_EVENT_SQ_DRAINED;
687 break;
688 case OCRDMA_DEVICE_FATAL_EVENT:
689 ib_evt.element.port_num = 1;
690 ib_evt.event = IB_EVENT_DEVICE_FATAL;
691 qp_event = 0;
692 dev_event = 1;
693 break;
694 case OCRDMA_SRQCAT_ERROR:
695 ib_evt.element.srq = &qp->srq->ibsrq;
696 ib_evt.event = IB_EVENT_SRQ_ERR;
697 srq_event = 1;
698 qp_event = 0;
699 break;
700 case OCRDMA_SRQ_LIMIT_EVENT:
701 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 702 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 703 srq_event = 1;
704 qp_event = 0;
705 break;
706 case OCRDMA_QP_LAST_WQE_EVENT:
707 ib_evt.element.qp = &qp->ibqp;
708 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
709 break;
710 default:
711 cq_event = 0;
712 qp_event = 0;
713 srq_event = 0;
714 dev_event = 0;
ef99c4c2 715 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 716 break;
717 }
718
719 if (qp_event) {
720 if (qp->ibqp.event_handler)
721 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
722 } else if (cq_event) {
723 if (cq->ibcq.event_handler)
724 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
725 } else if (srq_event) {
726 if (qp->srq->ibsrq.event_handler)
727 qp->srq->ibsrq.event_handler(&ib_evt,
728 qp->srq->ibsrq.
729 srq_context);
f99b1649 730 } else if (dev_event) {
1228056b 731 pr_err("%s: Fatal event received\n", dev->ibdev.name);
fe2caefc 732 ib_dispatch_event(&ib_evt);
f99b1649 733 }
fe2caefc
PP		 734
735}
736
84b105db
NG		 737static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
738 struct ocrdma_ae_mcqe *cqe)
739{
740 struct ocrdma_ae_pvid_mcqe *evt;
741 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
742 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
743
744 switch (type) {
745 case OCRDMA_ASYNC_EVENT_PVID_STATE:
746 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
747 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
748 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
749 dev->pvid = ((evt->tag_enabled &
750 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
751 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
752 break;
753 default:
754 /* Not interested evts. */
755 break;
756 }
757}
758
759
fe2caefc
PP		 760static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
761{
762 /* async CQE processing */
763 struct ocrdma_ae_mcqe *cqe = ae_cqe;
764 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
765 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
766
84b105db 767 if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
fe2caefc 768 ocrdma_dispatch_ibevent(dev, cqe);
84b105db
NG		 769 else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
770 ocrdma_process_grp5_aync(dev, cqe);
fe2caefc 771 else
ef99c4c2
NG		 772 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
773 dev->id, evt_code);
fe2caefc
PP		 774}
775
776static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
777{
778 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
779 dev->mqe_ctx.cqe_status = (cqe->status &
780 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
781 dev->mqe_ctx.ext_status =
782 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
783 >> OCRDMA_MCQE_ESTATUS_SHIFT;
784 dev->mqe_ctx.cmd_done = true;
785 wake_up(&dev->mqe_ctx.cmd_wait);
786 } else
ef99c4c2
NG		 787 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
788 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 789}
790
791static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
792{
793 u16 cqe_popped = 0;
794 struct ocrdma_mcqe *cqe;
795
796 while (1) {
797 cqe = ocrdma_get_mcqe(dev);
798 if (cqe == NULL)
799 break;
800 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
801 cqe_popped += 1;
802 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
803 ocrdma_process_acqe(dev, cqe);
804 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
805 ocrdma_process_mcqe(dev, cqe);
806 else
ef99c4c2 807 pr_err("%s() cqe->compl is not set.\n", __func__);
fe2caefc
PP		 808 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
809 ocrdma_mcq_inc_tail(dev);
810 }
811 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
812 return 0;
813}
814
815static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
816 struct ocrdma_cq *cq)
817{
818 unsigned long flags;
819 struct ocrdma_qp *qp;
820 bool buddy_cq_found = false;
821 /* Go through list of QPs in error state which are using this CQ
822 * and invoke its callback handler to trigger CQE processing for
823 * error/flushed CQE. It is rare to find more than few entries in
824 * this list as most consumers stops after getting error CQE.
825 * List is traversed only once when a matching buddy cq found for a QP.
826 */
827 spin_lock_irqsave(&dev->flush_q_lock, flags);
828 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
829 if (qp->srq)
830 continue;
831 /* if wq and rq share the same cq, than comp_handler
832 * is already invoked.
833 */
834 if (qp->sq_cq == qp->rq_cq)
835 continue;
836 /* if completion came on sq, rq's cq is buddy cq.
837 * if completion came on rq, sq's cq is buddy cq.
838 */
839 if (qp->sq_cq == cq)
840 cq = qp->rq_cq;
841 else
842 cq = qp->sq_cq;
843 buddy_cq_found = true;
844 break;
845 }
846 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
847 if (buddy_cq_found == false)
848 return;
849 if (cq->ibcq.comp_handler) {
850 spin_lock_irqsave(&cq->comp_handler_lock, flags);
851 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
852 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
853 }
854}
855
856static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
857{
858 unsigned long flags;
859 struct ocrdma_cq *cq;
860
861 if (cq_idx >= OCRDMA_MAX_CQ)
862 BUG();
863
864 cq = dev->cq_tbl[cq_idx];
ea617626 865 if (cq == NULL)
fe2caefc 866 return;
fe2caefc
PP		 867
868 if (cq->ibcq.comp_handler) {
869 spin_lock_irqsave(&cq->comp_handler_lock, flags);
870 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
871 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
872 }
873 ocrdma_qp_buddy_cq_handler(dev, cq);
874}
875
876static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
877{
878 /* process the MQ-CQE. */
879 if (cq_id == dev->mq.cq.id)
880 ocrdma_mq_cq_handler(dev, cq_id);
881 else
882 ocrdma_qp_cq_handler(dev, cq_id);
883}
884
885static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
886{
887 struct ocrdma_eq *eq = handle;
888 struct ocrdma_dev *dev = eq->dev;
889 struct ocrdma_eqe eqe;
890 struct ocrdma_eqe *ptr;
fe2caefc 891 u16 cq_id;
ea617626
DS		 892 int budget = eq->cq_cnt;
893
894 do {
fe2caefc
PP		 895 ptr = ocrdma_get_eqe(eq);
896 eqe = *ptr;
897 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
898 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
899 break;
ea617626 900
fe2caefc 901 ptr->id_valid = 0;
ea617626
DS		 902 /* ring eq doorbell as soon as its consumed. */
903 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
fe2caefc
PP		 904 /* check whether its CQE or not. */
905 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
906 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
907 ocrdma_cq_handler(dev, cq_id);
908 }
909 ocrdma_eq_inc_tail(eq);
ea617626
DS		 910
911 /* There can be a stale EQE after the last bound CQ is
912 * destroyed. EQE valid and budget == 0 implies this.
913 */
914 if (budget)
915 budget--;
916
917 } while (budget);
918
919 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
fe2caefc
PP		 920 return IRQ_HANDLED;
921}
922
923static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
924{
925 struct ocrdma_mqe *mqe;
926
927 dev->mqe_ctx.tag = dev->mq.sq.head;
928 dev->mqe_ctx.cmd_done = false;
929 mqe = ocrdma_get_mqe(dev);
930 cmd->hdr.tag_lo = dev->mq.sq.head;
931 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
932 /* make sure descriptor is written before ringing doorbell */
933 wmb();
934 ocrdma_mq_inc_head(dev);
935 ocrdma_ring_mq_db(dev);
936}
937
938static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
939{
940 long status;
941 /* 30 sec timeout */
942 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
943 (dev->mqe_ctx.cmd_done != false),
944 msecs_to_jiffies(30000));
945 if (status)
946 return 0;
947 else
948 return -1;
949}
950
951/* issue a mailbox command on the MQ */
952static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
953{
954 int status = 0;
955 u16 cqe_status, ext_status;
956 struct ocrdma_mqe *rsp;
957
958 mutex_lock(&dev->mqe_ctx.lock);
959 ocrdma_post_mqe(dev, mqe);
960 status = ocrdma_wait_mqe_cmpl(dev);
961 if (status)
962 goto mbx_err;
963 cqe_status = dev->mqe_ctx.cqe_status;
964 ext_status = dev->mqe_ctx.ext_status;
965 rsp = ocrdma_get_mqe_rsp(dev);
966 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
967 if (cqe_status || ext_status) {
f99b1649
NG		 968 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
969 __func__,
fe2caefc
PP		 970 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
971 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
972 status = ocrdma_get_mbx_cqe_errno(cqe_status);
973 goto mbx_err;
974 }
975 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
976 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
977mbx_err:
978 mutex_unlock(&dev->mqe_ctx.lock);
979 return status;
980}
981
982static void ocrdma_get_attr(struct ocrdma_dev *dev,
983 struct ocrdma_dev_attr *attr,
984 struct ocrdma_mbx_query_config *rsp)
985{
fe2caefc
PP		 986 attr->max_pd =
987 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
988 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
989 attr->max_qp =
990 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
991 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
992 attr->max_send_sge = ((rsp->max_write_send_sge &
993 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
994 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
995 attr->max_recv_sge = (rsp->max_write_send_sge &
996 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
997 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 998 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
999 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1000 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
45e86b33
NG		 1001 attr->max_rdma_sge = (rsp->max_write_send_sge &
1002 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1003 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
fe2caefc
PP		 1004 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1005 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1006 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
7c33880c
NG		 1007 attr->max_srq =
1008 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1009 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
fe2caefc
PP		 1010 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1011 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1012 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1013 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1014 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1015 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1016 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1017 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1018 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1019 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1020 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1021 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
ac578aef 1022 attr->max_mw = rsp->max_mw;
fe2caefc
PP		 1023 attr->max_mr = rsp->max_mr;
1024 attr->max_mr_size = ~0ull;
1025 attr->max_fmr = 0;
1026 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1027 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1028 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1029 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
c43e9ab8
NG		 1030 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1031 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1032 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
fe2caefc
PP		 1033 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1034 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1035 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1036 OCRDMA_WQE_STRIDE;
1037 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1038 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1039 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1040 OCRDMA_WQE_STRIDE;
1041 attr->max_inline_data =
1042 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1043 sizeof(struct ocrdma_sge));
21c3391a 1044 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1045 attr->ird = 1;
1046 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1047 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1048 }
1049 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1050 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1051 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1052 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1053}
1054
1055static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1056 struct ocrdma_fw_conf_rsp *conf)
1057{
1058 u32 fn_mode;
1059
1060 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1061 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1062 return -EINVAL;
1063 dev->base_eqid = conf->base_eqid;
1064 dev->max_eq = conf->max_eq;
fe2caefc
PP		 1065 return 0;
1066}
1067
1068/* can be issued only during init time. */
1069static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1070{
1071 int status = -ENOMEM;
1072 struct ocrdma_mqe *cmd;
1073 struct ocrdma_fw_ver_rsp *rsp;
1074
1075 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1076 if (!cmd)
1077 return -ENOMEM;
1078 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1079 OCRDMA_CMD_GET_FW_VER,
1080 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1081
1082 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1083 if (status)
1084 goto mbx_err;
1085 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1086 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1087 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1088 sizeof(rsp->running_ver));
1089 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1090mbx_err:
1091 kfree(cmd);
1092 return status;
1093}
1094
1095/* can be issued only during init time. */
1096static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1097{
1098 int status = -ENOMEM;
1099 struct ocrdma_mqe *cmd;
1100 struct ocrdma_fw_conf_rsp *rsp;
1101
1102 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1103 if (!cmd)
1104 return -ENOMEM;
1105 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1106 OCRDMA_CMD_GET_FW_CONFIG,
1107 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1108 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1109 if (status)
1110 goto mbx_err;
1111 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1112 status = ocrdma_check_fw_config(dev, rsp);
1113mbx_err:
1114 kfree(cmd);
1115 return status;
1116}
1117
1118static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1119{
1120 int status = -ENOMEM;
1121 struct ocrdma_mbx_query_config *rsp;
1122 struct ocrdma_mqe *cmd;
1123
1124 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1125 if (!cmd)
1126 return status;
1127 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1128 if (status)
1129 goto mbx_err;
1130 rsp = (struct ocrdma_mbx_query_config *)cmd;
1131 ocrdma_get_attr(dev, &dev->attr, rsp);
1132mbx_err:
1133 kfree(cmd);
1134 return status;
1135}
1136
f24ceba6
NG		 1137int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1138{
1139 int status = -ENOMEM;
1140 struct ocrdma_get_link_speed_rsp *rsp;
1141 struct ocrdma_mqe *cmd;
1142
1143 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1144 sizeof(*cmd));
1145 if (!cmd)
1146 return status;
1147 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1148 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1149 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1150
1151 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1152
1153 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1154 if (status)
1155 goto mbx_err;
1156
1157 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1158 *lnk_speed = rsp->phys_port_speed;
1159
1160mbx_err:
1161 kfree(cmd);
1162 return status;
1163}
1164
fe2caefc
PP		 1165int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1166{
1167 int status = -ENOMEM;
1168 struct ocrdma_alloc_pd *cmd;
1169 struct ocrdma_alloc_pd_rsp *rsp;
1170
1171 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1172 if (!cmd)
1173 return status;
1174 if (pd->dpp_enabled)
1175 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1176 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1177 if (status)
1178 goto mbx_err;
1179 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1180 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1181 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1182 pd->dpp_enabled = true;
1183 pd->dpp_page = rsp->dpp_page_pdid >>
1184 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1185 } else {
1186 pd->dpp_enabled = false;
1187 pd->num_dpp_qp = 0;
1188 }
1189mbx_err:
1190 kfree(cmd);
1191 return status;
1192}
1193
1194int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1195{
1196 int status = -ENOMEM;
1197 struct ocrdma_dealloc_pd *cmd;
1198
1199 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1200 if (!cmd)
1201 return status;
1202 cmd->id = pd->id;
1203 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1204 kfree(cmd);
1205 return status;
1206}
1207
1208static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1209 int *num_pages, int *page_size)
1210{
1211 int i;
1212 int mem_size;
1213
1214 *num_entries = roundup_pow_of_two(*num_entries);
1215 mem_size = *num_entries * entry_size;
1216 /* find the possible lowest possible multiplier */
1217 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1218 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1219 break;
1220 }
1221 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1222 return -EINVAL;
1223 mem_size = roundup(mem_size,
1224 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1225 *num_pages =
1226 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1227 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1228 *num_entries = mem_size / entry_size;
1229 return 0;
1230}
1231
1232static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1233{
1234 int i ;
1235 int status = 0;
1236 int max_ah;
1237 struct ocrdma_create_ah_tbl *cmd;
1238 struct ocrdma_create_ah_tbl_rsp *rsp;
1239 struct pci_dev *pdev = dev->nic_info.pdev;
1240 dma_addr_t pa;
1241 struct ocrdma_pbe *pbes;
1242
1243 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1244 if (!cmd)
1245 return status;
1246
1247 max_ah = OCRDMA_MAX_AH;
1248 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1249
1250 /* number of PBEs in PBL */
1251 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1252 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1253 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1254
1255 /* page size */
1256 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1257 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1258 break;
1259 }
1260 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1261 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1262
1263 /* ah_entry size */
1264 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1265 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1266 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1267
1268 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1269 &dev->av_tbl.pbl.pa,
1270 GFP_KERNEL);
1271 if (dev->av_tbl.pbl.va == NULL)
1272 goto mem_err;
1273
1274 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1275 &pa, GFP_KERNEL);
1276 if (dev->av_tbl.va == NULL)
1277 goto mem_err_ah;
1278 dev->av_tbl.pa = pa;
1279 dev->av_tbl.num_ah = max_ah;
1280 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1281
1282 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1283 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1284 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1285 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1286 pa += PAGE_SIZE;
1287 }
1288 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1289 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1290 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1291 if (status)
1292 goto mbx_err;
1293 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1294 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1295 kfree(cmd);
1296 return 0;
1297
1298mbx_err:
1299 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1300 dev->av_tbl.pa);
1301 dev->av_tbl.va = NULL;
1302mem_err_ah:
1303 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1304 dev->av_tbl.pbl.pa);
1305 dev->av_tbl.pbl.va = NULL;
1306 dev->av_tbl.size = 0;
1307mem_err:
1308 kfree(cmd);
1309 return status;
1310}
1311
1312static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1313{
1314 struct ocrdma_delete_ah_tbl *cmd;
1315 struct pci_dev *pdev = dev->nic_info.pdev;
1316
1317 if (dev->av_tbl.va == NULL)
1318 return;
1319
1320 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1321 if (!cmd)
1322 return;
1323 cmd->ahid = dev->av_tbl.ahid;
1324
1325 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1326 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1327 dev->av_tbl.pa);
1328 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1329 dev->av_tbl.pbl.pa);
1330 kfree(cmd);
1331}
1332
1333/* Multiple CQs uses the EQ. This routine returns least used
1334 * EQ to associate with CQ. This will distributes the interrupt
1335 * processing and CPU load to associated EQ, vector and so to that CPU.
1336 */
1337static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1338{
1339 int i, selected_eq = 0, cq_cnt = 0;
1340 u16 eq_id;
1341
1342 mutex_lock(&dev->dev_lock);
c88bd03f
NG		 1343 cq_cnt = dev->eq_tbl[0].cq_cnt;
1344 eq_id = dev->eq_tbl[0].q.id;
fe2caefc
PP		 1345 /* find the EQ which is has the least number of
1346 * CQs associated with it.
1347 */
1348 for (i = 0; i < dev->eq_cnt; i++) {
c88bd03f
NG		 1349 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1350 cq_cnt = dev->eq_tbl[i].cq_cnt;
1351 eq_id = dev->eq_tbl[i].q.id;
fe2caefc
PP		 1352 selected_eq = i;
1353 }
1354 }
c88bd03f 1355 dev->eq_tbl[selected_eq].cq_cnt += 1;
fe2caefc
PP		 1356 mutex_unlock(&dev->dev_lock);
1357 return eq_id;
1358}
1359
1360static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1361{
1362 int i;
1363
1364 mutex_lock(&dev->dev_lock);
ea617626
DS		 1365 i = ocrdma_get_eq_table_index(dev, eq_id);
1366 if (i == -EINVAL)
1367 BUG();
1368 dev->eq_tbl[i].cq_cnt -= 1;
fe2caefc
PP		 1369 mutex_unlock(&dev->dev_lock);
1370}
1371
1372int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
cffce990 1373 int entries, int dpp_cq, u16 pd_id)
fe2caefc
PP		 1374{
1375 int status = -ENOMEM; int max_hw_cqe;
1376 struct pci_dev *pdev = dev->nic_info.pdev;
1377 struct ocrdma_create_cq *cmd;
1378 struct ocrdma_create_cq_rsp *rsp;
1379 u32 hw_pages, cqe_size, page_size, cqe_count;
1380
fe2caefc 1381 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1382 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1383 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1384 return -EINVAL;
1385 }
21c3391a 1386 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
fe2caefc
PP		 1387 return -EINVAL;
1388
1389 if (dpp_cq) {
1390 cq->max_hw_cqe = 1;
1391 max_hw_cqe = 1;
1392 cqe_size = OCRDMA_DPP_CQE_SIZE;
1393 hw_pages = 1;
1394 } else {
1395 cq->max_hw_cqe = dev->attr.max_cqe;
1396 max_hw_cqe = dev->attr.max_cqe;
1397 cqe_size = sizeof(struct ocrdma_cqe);
1398 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1399 }
1400
1401 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1402
1403 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1404 if (!cmd)
1405 return -ENOMEM;
1406 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1407 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1408 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1409 if (!cq->va) {
1410 status = -ENOMEM;
1411 goto mem_err;
1412 }
1413 memset(cq->va, 0, cq->len);
1414 page_size = cq->len / hw_pages;
1415 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1416 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1417 cmd->cmd.pgsz_pgcnt |= hw_pages;
1418 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1419
fe2caefc 1420 cq->eqn = ocrdma_bind_eq(dev);
cffce990 1421 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
fe2caefc 1422 cqe_count = cq->len / cqe_size;
ea617626 1423 cq->cqe_cnt = cqe_count;
f99b1649 1424 if (cqe_count > 1024) {
fe2caefc
PP		 1425 /* Set cnt to 3 to indicate more than 1024 cq entries */
1426 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1427 } else {
fe2caefc
PP		 1428 u8 count = 0;
1429 switch (cqe_count) {
1430 case 256:
1431 count = 0;
1432 break;
1433 case 512:
1434 count = 1;
1435 break;
1436 case 1024:
1437 count = 2;
1438 break;
1439 default:
1440 goto mbx_err;
1441 }
1442 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1443 }
1444 /* shared eq between all the consumer cqs. */
1445 cmd->cmd.eqn = cq->eqn;
21c3391a 1446 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1447 if (dpp_cq)
1448 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1449 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1450 cq->phase_change = false;
1451 cmd->cmd.cqe_count = (cq->len / cqe_size);
1452 } else {
1453 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1454 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1455 cq->phase_change = true;
1456 }
1457
cffce990 1458 cmd->cmd.pd_id = pd_id; /* valid only for v3 */
fe2caefc
PP		 1459 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1460 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1461 if (status)
1462 goto mbx_err;
1463
1464 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1465 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1466 kfree(cmd);
1467 return 0;
1468mbx_err:
1469 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1470 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1471mem_err:
1472 kfree(cmd);
1473 return status;
1474}
1475
1476int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1477{
1478 int status = -ENOMEM;
1479 struct ocrdma_destroy_cq *cmd;
1480
1481 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1482 if (!cmd)
1483 return status;
1484 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1485 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1486
1487 cmd->bypass_flush_qid |=
1488 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1489 OCRDMA_DESTROY_CQ_QID_MASK;
1490
fe2caefc 1491 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
ea617626 1492 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc 1493 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
fe2caefc
PP		 1494 kfree(cmd);
1495 return status;
1496}
1497
1498int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1499 u32 pdid, int addr_check)
1500{
1501 int status = -ENOMEM;
1502 struct ocrdma_alloc_lkey *cmd;
1503 struct ocrdma_alloc_lkey_rsp *rsp;
1504
1505 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1506 if (!cmd)
1507 return status;
1508 cmd->pdid = pdid;
1509 cmd->pbl_sz_flags |= addr_check;
1510 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1511 cmd->pbl_sz_flags |=
1512 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1513 cmd->pbl_sz_flags |=
1514 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1515 cmd->pbl_sz_flags |=
1516 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1517 cmd->pbl_sz_flags |=
1518 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1519 cmd->pbl_sz_flags |=
1520 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1521
1522 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1523 if (status)
1524 goto mbx_err;
1525 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1526 hwmr->lkey = rsp->lrkey;
1527mbx_err:
1528 kfree(cmd);
1529 return status;
1530}
1531
1532int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1533{
1534 int status = -ENOMEM;
1535 struct ocrdma_dealloc_lkey *cmd;
1536
1537 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1538 if (!cmd)
1539 return -ENOMEM;
1540 cmd->lkey = lkey;
1541 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1542 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1543 if (status)
1544 goto mbx_err;
1545mbx_err:
1546 kfree(cmd);
1547 return status;
1548}
1549
1550static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1551 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1552{
1553 int status = -ENOMEM;
1554 int i;
1555 struct ocrdma_reg_nsmr *cmd;
1556 struct ocrdma_reg_nsmr_rsp *rsp;
1557
1558 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1559 if (!cmd)
1560 return -ENOMEM;
1561 cmd->num_pbl_pdid =
1562 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
2b51a9b9 1563 cmd->fr_mr = hwmr->fr_mr;
fe2caefc
PP		 1564
1565 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1566 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1567 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1568 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1569 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1570 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1571 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1572 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1573 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1574 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1575 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1576
1577 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1578 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1579 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1580 cmd->totlen_low = hwmr->len;
1581 cmd->totlen_high = upper_32_bits(hwmr->len);
1582 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1583 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1584 cmd->va_loaddr = (u32) hwmr->va;
1585 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1586
1587 for (i = 0; i < pbl_cnt; i++) {
1588 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1589 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1590 }
1591 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1592 if (status)
1593 goto mbx_err;
1594 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1595 hwmr->lkey = rsp->lrkey;
1596mbx_err:
1597 kfree(cmd);
1598 return status;
1599}
1600
1601static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1602 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1603 u32 pbl_offset, u32 last)
1604{
1605 int status = -ENOMEM;
1606 int i;
1607 struct ocrdma_reg_nsmr_cont *cmd;
1608
1609 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1610 if (!cmd)
1611 return -ENOMEM;
1612 cmd->lrkey = hwmr->lkey;
1613 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1614 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1615 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1616
1617 for (i = 0; i < pbl_cnt; i++) {
1618 cmd->pbl[i].lo =
1619 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1620 cmd->pbl[i].hi =
1621 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1622 }
1623 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1624 if (status)
1625 goto mbx_err;
1626mbx_err:
1627 kfree(cmd);
1628 return status;
1629}
1630
1631int ocrdma_reg_mr(struct ocrdma_dev *dev,
1632 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1633{
1634 int status;
1635 u32 last = 0;
1636 u32 cur_pbl_cnt, pbl_offset;
1637 u32 pending_pbl_cnt = hwmr->num_pbls;
1638
1639 pbl_offset = 0;
1640 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1641 if (cur_pbl_cnt == pending_pbl_cnt)
1642 last = 1;
1643
1644 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1645 cur_pbl_cnt, hwmr->pbe_size, last);
1646 if (status) {
ef99c4c2 1647 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 1648 return status;
1649 }
1650 /* if there is no more pbls to register then exit. */
1651 if (last)
1652 return 0;
1653
1654 while (!last) {
1655 pbl_offset += cur_pbl_cnt;
1656 pending_pbl_cnt -= cur_pbl_cnt;
1657 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1658 /* if we reach the end of the pbls, then need to set the last
1659 * bit, indicating no more pbls to register for this memory key.
1660 */
1661 if (cur_pbl_cnt == pending_pbl_cnt)
1662 last = 1;
1663
1664 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1665 pbl_offset, last);
1666 if (status)
1667 break;
1668 }
1669 if (status)
ef99c4c2 1670 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 1671
1672 return status;
1673}
1674
1675bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1676{
1677 struct ocrdma_qp *tmp;
1678 bool found = false;
1679 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1680 if (qp == tmp) {
1681 found = true;
1682 break;
1683 }
1684 }
1685 return found;
1686}
1687
1688bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1689{
1690 struct ocrdma_qp *tmp;
1691 bool found = false;
1692 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1693 if (qp == tmp) {
1694 found = true;
1695 break;
1696 }
1697 }
1698 return found;
1699}
1700
1701void ocrdma_flush_qp(struct ocrdma_qp *qp)
1702{
1703 bool found;
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1707 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1708 if (!found)
1709 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1710 if (!qp->srq) {
1711 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1712 if (!found)
1713 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1714 }
1715 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1716}
1717
f11220ee
NG		 1718static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1719{
1720 qp->sq.head = 0;
1721 qp->sq.tail = 0;
1722 qp->rq.head = 0;
1723 qp->rq.tail = 0;
1724}
1725
057729cb
NG		 1726int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1727 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 1728{
1729 unsigned long flags;
1730 int status = 0;
1731 enum ocrdma_qp_state new_state;
1732 new_state = get_ocrdma_qp_state(new_ib_state);
1733
1734 /* sync with wqe and rqe posting */
1735 spin_lock_irqsave(&qp->q_lock, flags);
1736
1737 if (old_ib_state)
1738 *old_ib_state = get_ibqp_state(qp->state);
1739 if (new_state == qp->state) {
1740 spin_unlock_irqrestore(&qp->q_lock, flags);
1741 return 1;
1742 }
1743
057729cb 1744
f11220ee
NG		 1745 if (new_state == OCRDMA_QPS_INIT) {
1746 ocrdma_init_hwq_ptr(qp);
1747 ocrdma_del_flush_qp(qp);
1748 } else if (new_state == OCRDMA_QPS_ERR) {
057729cb 1749 ocrdma_flush_qp(qp);
f11220ee 1750 }
057729cb
NG		 1751
1752 qp->state = new_state;
fe2caefc
PP		 1753
1754 spin_unlock_irqrestore(&qp->q_lock, flags);
1755 return status;
1756}
1757
1758static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1759{
1760 u32 flags = 0;
1761 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1762 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1763 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1764 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1765 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1766 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1767 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1768 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1769 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1770 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1771 return flags;
1772}
1773
1774static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1775 struct ib_qp_init_attr *attrs,
1776 struct ocrdma_qp *qp)
1777{
1778 int status;
1779 u32 len, hw_pages, hw_page_size;
1780 dma_addr_t pa;
1781 struct ocrdma_dev *dev = qp->dev;
1782 struct pci_dev *pdev = dev->nic_info.pdev;
1783 u32 max_wqe_allocated;
1784 u32 max_sges = attrs->cap.max_send_sge;
1785
43a6b402 1786 /* QP1 may exceed 127 */
6ebacdfc 1787 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
43a6b402 1788 dev->attr.max_wqe);
fe2caefc
PP		 1789
1790 status = ocrdma_build_q_conf(&max_wqe_allocated,
1791 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1792 if (status) {
ef99c4c2
NG		 1793 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1794 max_wqe_allocated);
fe2caefc
PP		 1795 return -EINVAL;
1796 }
1797 qp->sq.max_cnt = max_wqe_allocated;
1798 len = (hw_pages * hw_page_size);
1799
1800 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1801 if (!qp->sq.va)
1802 return -EINVAL;
1803 memset(qp->sq.va, 0, len);
1804 qp->sq.len = len;
1805 qp->sq.pa = pa;
1806 qp->sq.entry_size = dev->attr.wqe_size;
1807 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1808
1809 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1810 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1811 cmd->num_wq_rq_pages |= (hw_pages <<
1812 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1813 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1814 cmd->max_sge_send_write |= (max_sges <<
1815 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1816 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1817 cmd->max_sge_send_write |= (max_sges <<
1818 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1819 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1820 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1821 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1822 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1823 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1824 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1825 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1826 return 0;
1827}
1828
1829static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1830 struct ib_qp_init_attr *attrs,
1831 struct ocrdma_qp *qp)
1832{
1833 int status;
1834 u32 len, hw_pages, hw_page_size;
1835 dma_addr_t pa = 0;
1836 struct ocrdma_dev *dev = qp->dev;
1837 struct pci_dev *pdev = dev->nic_info.pdev;
1838 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1839
1840 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1841 &hw_pages, &hw_page_size);
1842 if (status) {
ef99c4c2
NG		 1843 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1844 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 1845 return status;
1846 }
1847 qp->rq.max_cnt = max_rqe_allocated;
1848 len = (hw_pages * hw_page_size);
1849
1850 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1851 if (!qp->rq.va)
c94e15c5 1852 return -ENOMEM;
fe2caefc
PP		 1853 memset(qp->rq.va, 0, len);
1854 qp->rq.pa = pa;
1855 qp->rq.len = len;
1856 qp->rq.entry_size = dev->attr.rqe_size;
1857
1858 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1859 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1860 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1861 cmd->num_wq_rq_pages |=
1862 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1863 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1864 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1865 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1866 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1867 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1868 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1869 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1870 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1871 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1872 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1873 return 0;
1874}
1875
1876static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1877 struct ocrdma_pd *pd,
1878 struct ocrdma_qp *qp,
1879 u8 enable_dpp_cq, u16 dpp_cq_id)
1880{
1881 pd->num_dpp_qp--;
1882 qp->dpp_enabled = true;
1883 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1884 if (!enable_dpp_cq)
1885 return;
1886 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1887 cmd->dpp_credits_cqid = dpp_cq_id;
1888 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1889 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1890}
1891
1892static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1893 struct ocrdma_qp *qp)
1894{
1895 struct ocrdma_dev *dev = qp->dev;
1896 struct pci_dev *pdev = dev->nic_info.pdev;
1897 dma_addr_t pa = 0;
1898 int ird_page_size = dev->attr.ird_page_size;
1899 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
43a6b402
NG		 1900 struct ocrdma_hdr_wqe *rqe;
1901 int i = 0;
fe2caefc
PP		 1902
1903 if (dev->attr.ird == 0)
1904 return 0;
1905
1906 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1907 &pa, GFP_KERNEL);
1908 if (!qp->ird_q_va)
1909 return -ENOMEM;
1910 memset(qp->ird_q_va, 0, ird_q_len);
1911 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1912 pa, ird_page_size);
43a6b402
NG		 1913 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
1914 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
1915 (i * dev->attr.rqe_size));
1916 rqe->cw = 0;
1917 rqe->cw |= 2;
1918 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
1919 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
1920 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
1921 }
fe2caefc
PP		 1922 return 0;
1923}
1924
1925static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1926 struct ocrdma_qp *qp,
1927 struct ib_qp_init_attr *attrs,
1928 u16 *dpp_offset, u16 *dpp_credit_lmt)
1929{
1930 u32 max_wqe_allocated, max_rqe_allocated;
1931 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1932 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1933 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1934 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1935 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1936 qp->dpp_enabled = false;
1937 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1938 qp->dpp_enabled = true;
1939 *dpp_credit_lmt = (rsp->dpp_response &
1940 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1941 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1942 *dpp_offset = (rsp->dpp_response &
1943 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1944 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1945 }
1946 max_wqe_allocated =
1947 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1948 max_wqe_allocated = 1 << max_wqe_allocated;
1949 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1950
fe2caefc
PP		 1951 qp->sq.max_cnt = max_wqe_allocated;
1952 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1953
1954 if (!attrs->srq) {
1955 qp->rq.max_cnt = max_rqe_allocated;
1956 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 1957 }
1958}
1959
1960int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1961 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1962 u16 *dpp_credit_lmt)
1963{
1964 int status = -ENOMEM;
1965 u32 flags = 0;
1966 struct ocrdma_dev *dev = qp->dev;
1967 struct ocrdma_pd *pd = qp->pd;
1968 struct pci_dev *pdev = dev->nic_info.pdev;
1969 struct ocrdma_cq *cq;
1970 struct ocrdma_create_qp_req *cmd;
1971 struct ocrdma_create_qp_rsp *rsp;
1972 int qptype;
1973
1974 switch (attrs->qp_type) {
1975 case IB_QPT_GSI:
1976 qptype = OCRDMA_QPT_GSI;
1977 break;
1978 case IB_QPT_RC:
1979 qptype = OCRDMA_QPT_RC;
1980 break;
1981 case IB_QPT_UD:
1982 qptype = OCRDMA_QPT_UD;
1983 break;
1984 default:
1985 return -EINVAL;
2b50176d 1986 }
fe2caefc
PP		 1987
1988 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
1989 if (!cmd)
1990 return status;
1991 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
1992 OCRDMA_CREATE_QP_REQ_QPT_MASK;
1993 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
1994 if (status)
1995 goto sq_err;
1996
1997 if (attrs->srq) {
1998 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
1999 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2000 cmd->rq_addr[0].lo = srq->id;
2001 qp->srq = srq;
2002 } else {
2003 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2004 if (status)
2005 goto rq_err;
2006 }
2007
2008 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2009 if (status)
2010 goto mbx_err;
2011
2012 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2013 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2014
2015 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2016
2017 cmd->max_sge_recv_flags |= flags;
2018 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2019 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2020 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2021 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2022 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2023 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2024 cq = get_ocrdma_cq(attrs->send_cq);
2025 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2026 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2027 qp->sq_cq = cq;
2028 cq = get_ocrdma_cq(attrs->recv_cq);
2029 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2030 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2031 qp->rq_cq = cq;
2032
1eebbb6e 2033 if (pd->dpp_enabled && pd->num_dpp_qp) {
fe2caefc
PP		 2034 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2035 dpp_cq_id);
f99b1649 2036 }
fe2caefc
PP		 2037
2038 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2039 if (status)
2040 goto mbx_err;
2041 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2042 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2043 qp->state = OCRDMA_QPS_RST;
2044 kfree(cmd);
2045 return 0;
2046mbx_err:
2047 if (qp->rq.va)
2048 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2049rq_err:
ef99c4c2 2050 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 2051 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2052sq_err:
ef99c4c2 2053 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 2054 kfree(cmd);
2055 return status;
2056}
2057
2058int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2059 struct ocrdma_qp_params *param)
2060{
2061 int status = -ENOMEM;
2062 struct ocrdma_query_qp *cmd;
2063 struct ocrdma_query_qp_rsp *rsp;
2064
2065 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2066 if (!cmd)
2067 return status;
2068 cmd->qp_id = qp->id;
2069 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2070 if (status)
2071 goto mbx_err;
2072 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2073 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2074mbx_err:
2075 kfree(cmd);
2076 return status;
2077}
2078
f99b1649 2079static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc
PP		 2080 struct ocrdma_modify_qp *cmd,
2081 struct ib_qp_attr *attrs)
2082{
f99b1649 2083 int status;
fe2caefc 2084 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2085 union ib_gid sgid, zgid;
fe2caefc
PP		 2086 u32 vlan_id;
2087 u8 mac_addr[6];
9c58726b 2088
fe2caefc 2089 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
f99b1649 2090 return -EINVAL;
fe2caefc
PP		 2091 cmd->params.tclass_sq_psn |=
2092 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2093 cmd->params.rnt_rc_sl_fl |=
2094 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2b51a9b9 2095 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
fe2caefc
PP		 2096 cmd->params.hop_lmt_rq_psn |=
2097 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2098 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2099 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2100 sizeof(cmd->params.dgid));
f99b1649 2101 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
fe2caefc 2102 ah_attr->grh.sgid_index, &sgid);
f99b1649
NG		 2103 if (status)
2104 return status;
9c58726b
NG		 2105
2106 memset(&zgid, 0, sizeof(zgid));
2107 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2108 return -EINVAL;
2109
fe2caefc
PP		 2110 qp->sgid_idx = ah_attr->grh.sgid_index;
2111 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
40aca6ff 2112 ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
fe2caefc
PP		 2113 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2114 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2115 /* convert them to LE format. */
2116 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2117 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2118 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
40aca6ff 2119 vlan_id = ah_attr->vlan_id;
fe2caefc
PP		 2120 if (vlan_id && (vlan_id < 0x1000)) {
2121 cmd->params.vlan_dmac_b4_to_b5 |=
2122 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2123 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2124 }
f99b1649 2125 return 0;
fe2caefc
PP		 2126}
2127
2128static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2129 struct ocrdma_modify_qp *cmd,
bc1b04ab 2130 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2131{
2132 int status = 0;
fe2caefc
PP		 2133
2134 if (attr_mask & IB_QP_PKEY_INDEX) {
2135 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2136 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2137 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2138 }
2139 if (attr_mask & IB_QP_QKEY) {
2140 qp->qkey = attrs->qkey;
2141 cmd->params.qkey = attrs->qkey;
2142 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2143 }
f99b1649
NG		 2144 if (attr_mask & IB_QP_AV) {
2145 status = ocrdma_set_av_params(qp, cmd, attrs);
2146 if (status)
2147 return status;
2148 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc
PP		 2149 /* set the default mac address for UD, GSI QPs */
2150 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2151 (qp->dev->nic_info.mac_addr[1] << 8) |
2152 (qp->dev->nic_info.mac_addr[2] << 16) |
2153 (qp->dev->nic_info.mac_addr[3] << 24);
2154 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2155 (qp->dev->nic_info.mac_addr[5] << 8);
2156 }
2157 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2158 attrs->en_sqd_async_notify) {
2159 cmd->params.max_sge_recv_flags |=
2160 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2161 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2162 }
2163 if (attr_mask & IB_QP_DEST_QPN) {
2164 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2165 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2166 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2167 }
2168 if (attr_mask & IB_QP_PATH_MTU) {
d3cb6c0b
NG		 2169 if (attrs->path_mtu < IB_MTU_256 ||
2170 attrs->path_mtu > IB_MTU_4096) {
fe2caefc
PP		 2171 status = -EINVAL;
2172 goto pmtu_err;
2173 }
2174 cmd->params.path_mtu_pkey_indx |=
2175 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2176 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2177 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2178 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2179 }
2180 if (attr_mask & IB_QP_TIMEOUT) {
2181 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2182 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2183 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2184 }
2185 if (attr_mask & IB_QP_RETRY_CNT) {
2186 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2187 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2188 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2189 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2190 }
2191 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2192 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2193 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2194 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2195 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2196 }
2197 if (attr_mask & IB_QP_RNR_RETRY) {
2198 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2199 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2200 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2201 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2202 }
2203 if (attr_mask & IB_QP_SQ_PSN) {
2204 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2205 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2206 }
2207 if (attr_mask & IB_QP_RQ_PSN) {
2208 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2209 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2210 }
2211 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2212 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2213 status = -EINVAL;
2214 goto pmtu_err;
2215 }
2216 qp->max_ord = attrs->max_rd_atomic;
2217 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2218 }
2219 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2220 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2221 status = -EINVAL;
2222 goto pmtu_err;
2223 }
2224 qp->max_ird = attrs->max_dest_rd_atomic;
2225 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2226 }
2227 cmd->params.max_ord_ird = (qp->max_ord <<
2228 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2229 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2230pmtu_err:
2231 return status;
2232}
2233
2234int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
bc1b04ab 2235 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2236{
2237 int status = -ENOMEM;
2238 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2239
2240 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2241 if (!cmd)
2242 return status;
2243
2244 cmd->params.id = qp->id;
2245 cmd->flags = 0;
2246 if (attr_mask & IB_QP_STATE) {
2247 cmd->params.max_sge_recv_flags |=
2248 (get_ocrdma_qp_state(attrs->qp_state) <<
2249 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2250 OCRDMA_QP_PARAMS_STATE_MASK;
2251 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2252 } else {
fe2caefc
PP		 2253 cmd->params.max_sge_recv_flags |=
2254 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2255 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2256 }
2257
bc1b04ab 2258 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
fe2caefc
PP		 2259 if (status)
2260 goto mbx_err;
2261 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2262 if (status)
2263 goto mbx_err;
c592c423 2264
fe2caefc
PP		 2265mbx_err:
2266 kfree(cmd);
2267 return status;
2268}
2269
2270int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2271{
2272 int status = -ENOMEM;
2273 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2274 struct pci_dev *pdev = dev->nic_info.pdev;
2275
2276 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2277 if (!cmd)
2278 return status;
2279 cmd->qp_id = qp->id;
2280 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2281 if (status)
2282 goto mbx_err;
c592c423 2283
fe2caefc
PP		 2284mbx_err:
2285 kfree(cmd);
2286 if (qp->sq.va)
2287 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2288 if (!qp->srq && qp->rq.va)
2289 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2290 if (qp->dpp_enabled)
2291 qp->pd->num_dpp_qp++;
2292 return status;
2293}
2294
1afc0454 2295int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2296 struct ib_srq_init_attr *srq_attr,
2297 struct ocrdma_pd *pd)
2298{
2299 int status = -ENOMEM;
2300 int hw_pages, hw_page_size;
2301 int len;
2302 struct ocrdma_create_srq_rsp *rsp;
2303 struct ocrdma_create_srq *cmd;
2304 dma_addr_t pa;
fe2caefc
PP		 2305 struct pci_dev *pdev = dev->nic_info.pdev;
2306 u32 max_rqe_allocated;
2307
2308 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2309 if (!cmd)
2310 return status;
2311
2312 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2313 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2314 status = ocrdma_build_q_conf(&max_rqe_allocated,
2315 dev->attr.rqe_size,
2316 &hw_pages, &hw_page_size);
2317 if (status) {
ef99c4c2
NG		 2318 pr_err("%s() req. max_wr=0x%x\n", __func__,
2319 srq_attr->attr.max_wr);
fe2caefc
PP		 2320 status = -EINVAL;
2321 goto ret;
2322 }
2323 len = hw_pages * hw_page_size;
2324 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2325 if (!srq->rq.va) {
2326 status = -ENOMEM;
2327 goto ret;
2328 }
2329 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2330
2331 srq->rq.entry_size = dev->attr.rqe_size;
2332 srq->rq.pa = pa;
2333 srq->rq.len = len;
2334 srq->rq.max_cnt = max_rqe_allocated;
2335
2336 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2337 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2338 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2339
2340 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2341 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2342 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2343 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2344 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2345 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2346
2347 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2348 if (status)
2349 goto mbx_err;
2350 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2351 srq->id = rsp->id;
2352 srq->rq.dbid = rsp->id;
2353 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2354 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2355 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2356 max_rqe_allocated = (1 << max_rqe_allocated);
2357 srq->rq.max_cnt = max_rqe_allocated;
2358 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2359 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2360 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2361 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2362 goto ret;
2363mbx_err:
2364 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2365ret:
2366 kfree(cmd);
2367 return status;
2368}
2369
2370int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2371{
2372 int status = -ENOMEM;
2373 struct ocrdma_modify_srq *cmd;
f11220ee
NG		 2374 struct ocrdma_pd *pd = srq->pd;
2375 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
1afc0454 2376
d7e19c0a 2377 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2378 if (!cmd)
2379 return status;
2380 cmd->id = srq->id;
2381 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2382 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2383 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2384 kfree(cmd);
2385 return status;
2386}
2387
2388int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2389{
2390 int status = -ENOMEM;
2391 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2392 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2393
d7e19c0a 2394 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2395 if (!cmd)
2396 return status;
2397 cmd->id = srq->rq.dbid;
1afc0454 2398 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2399 if (status == 0) {
2400 struct ocrdma_query_srq_rsp *rsp =
2401 (struct ocrdma_query_srq_rsp *)cmd;
2402 srq_attr->max_sge =
2403 rsp->srq_lmt_max_sge &
2404 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2405 srq_attr->max_wr =
2406 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2407 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2408 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2409 }
2410 kfree(cmd);
2411 return status;
2412}
2413
2414int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2415{
2416 int status = -ENOMEM;
2417 struct ocrdma_destroy_srq *cmd;
2418 struct pci_dev *pdev = dev->nic_info.pdev;
2419 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2420 if (!cmd)
2421 return status;
2422 cmd->id = srq->id;
1afc0454 2423 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2424 if (srq->rq.va)
2425 dma_free_coherent(&pdev->dev, srq->rq.len,
2426 srq->rq.va, srq->rq.pa);
2427 kfree(cmd);
2428 return status;
2429}
2430
2431int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2432{
2433 int i;
2434 int status = -EINVAL;
2435 struct ocrdma_av *av;
2436 unsigned long flags;
2437
2438 av = dev->av_tbl.va;
2439 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2440 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2441 if (av->valid == 0) {
2442 av->valid = OCRDMA_AV_VALID;
2443 ah->av = av;
2444 ah->id = i;
2445 status = 0;
2446 break;
2447 }
2448 av++;
2449 }
2450 if (i == dev->av_tbl.num_ah)
2451 status = -EAGAIN;
2452 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2453 return status;
2454}
2455
2456int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2457{
2458 unsigned long flags;
2459 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2460 ah->av->valid = 0;
2461 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2462 return 0;
2463}
2464
c88bd03f 2465static int ocrdma_create_eqs(struct ocrdma_dev *dev)
fe2caefc 2466{
da496438 2467 int num_eq, i, status = 0;
fe2caefc
PP		 2468 int irq;
2469 unsigned long flags = 0;
2470
2471 num_eq = dev->nic_info.msix.num_vectors -
2472 dev->nic_info.msix.start_vector;
2473 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2474 num_eq = 1;
2475 flags = IRQF_SHARED;
f99b1649 2476 } else {
fe2caefc 2477 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 2478 }
2479
c88bd03f
NG		 2480 if (!num_eq)
2481 return -EINVAL;
2482
2483 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2484 if (!dev->eq_tbl)
fe2caefc
PP		 2485 return -ENOMEM;
2486
2487 for (i = 0; i < num_eq; i++) {
c88bd03f 2488 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
fe2caefc
PP		 2489 OCRDMA_EQ_LEN);
2490 if (status) {
2491 status = -EINVAL;
2492 break;
2493 }
c88bd03f 2494 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
fe2caefc 2495 dev->id, i);
c88bd03f 2496 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
fe2caefc 2497 status = request_irq(irq, ocrdma_irq_handler, flags,
c88bd03f
NG		 2498 dev->eq_tbl[i].irq_name,
2499 &dev->eq_tbl[i]);
2500 if (status)
2501 goto done;
fe2caefc
PP		 2502 dev->eq_cnt += 1;
2503 }
2504 /* one eq is sufficient for data path to work */
c88bd03f
NG		 2505 return 0;
2506done:
2507 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2508 return status;
2509}
2510
2511int ocrdma_init_hw(struct ocrdma_dev *dev)
2512{
2513 int status;
c88bd03f
NG		 2514
2515 /* create the eqs */
2516 status = ocrdma_create_eqs(dev);
fe2caefc
PP		 2517 if (status)
2518 goto qpeq_err;
2519 status = ocrdma_create_mq(dev);
2520 if (status)
2521 goto mq_err;
2522 status = ocrdma_mbx_query_fw_config(dev);
2523 if (status)
2524 goto conf_err;
2525 status = ocrdma_mbx_query_dev(dev);
2526 if (status)
2527 goto conf_err;
2528 status = ocrdma_mbx_query_fw_ver(dev);
2529 if (status)
2530 goto conf_err;
2531 status = ocrdma_mbx_create_ah_tbl(dev);
2532 if (status)
2533 goto conf_err;
2534 return 0;
2535
2536conf_err:
2537 ocrdma_destroy_mq(dev);
2538mq_err:
c88bd03f 2539 ocrdma_destroy_eqs(dev);
fe2caefc 2540qpeq_err:
ef99c4c2 2541 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2542 return status;
2543}
2544
2545void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2546{
2547 ocrdma_mbx_delete_ah_tbl(dev);
2548
c88bd03f
NG		 2549 /* cleanup the eqs */
2550 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2551
2552 /* cleanup the control path */
2553 ocrdma_destroy_mq(dev);
fe2caefc 2554}
Linux kernel - Deliverables
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