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RDMA/ocrdma: Remove use_cnt for queues
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
35#include <rdma/ib_addr.h>
36
37#include "ocrdma.h"
38#include "ocrdma_hw.h"
39#include "ocrdma_verbs.h"
40#include "ocrdma_ah.h"
41
42enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81};
82
83enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85};
86
87enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93};
94
95static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96{
97 return (u8 *)eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
98}
99
100static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101{
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103}
104
105static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106{
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
108 ((u8 *) dev->mq.cq.va +
109 (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
110
111 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
112 return NULL;
113 return cqe;
114}
115
116static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
117{
118 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
119}
120
121static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
122{
123 return (struct ocrdma_mqe *)((u8 *) dev->mq.sq.va +
124 (dev->mq.sq.head *
125 sizeof(struct ocrdma_mqe)));
126}
127
128static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
129{
130 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 131}
132
133static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
134{
135 return (void *)((u8 *) dev->mq.sq.va +
136 (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe)));
137}
138
139enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
140{
141 switch (qps) {
142 case OCRDMA_QPS_RST:
143 return IB_QPS_RESET;
144 case OCRDMA_QPS_INIT:
145 return IB_QPS_INIT;
146 case OCRDMA_QPS_RTR:
147 return IB_QPS_RTR;
148 case OCRDMA_QPS_RTS:
149 return IB_QPS_RTS;
150 case OCRDMA_QPS_SQD:
151 case OCRDMA_QPS_SQ_DRAINING:
152 return IB_QPS_SQD;
153 case OCRDMA_QPS_SQE:
154 return IB_QPS_SQE;
155 case OCRDMA_QPS_ERR:
156 return IB_QPS_ERR;
157 };
158 return IB_QPS_ERR;
159}
160
abe3afac 161static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 162{
163 switch (qps) {
164 case IB_QPS_RESET:
165 return OCRDMA_QPS_RST;
166 case IB_QPS_INIT:
167 return OCRDMA_QPS_INIT;
168 case IB_QPS_RTR:
169 return OCRDMA_QPS_RTR;
170 case IB_QPS_RTS:
171 return OCRDMA_QPS_RTS;
172 case IB_QPS_SQD:
173 return OCRDMA_QPS_SQD;
174 case IB_QPS_SQE:
175 return OCRDMA_QPS_SQE;
176 case IB_QPS_ERR:
177 return OCRDMA_QPS_ERR;
178 };
179 return OCRDMA_QPS_ERR;
180}
181
182static int ocrdma_get_mbx_errno(u32 status)
183{
184 int err_num = -EFAULT;
185 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
186 OCRDMA_MBX_RSP_STATUS_SHIFT;
187 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
188 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
189
190 switch (mbox_status) {
191 case OCRDMA_MBX_STATUS_OOR:
192 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
193 err_num = -EAGAIN;
194 break;
195
196 case OCRDMA_MBX_STATUS_INVALID_PD:
197 case OCRDMA_MBX_STATUS_INVALID_CQ:
198 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
199 case OCRDMA_MBX_STATUS_INVALID_QP:
200 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
201 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
202 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
203 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
204 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
205 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
206 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
207 case OCRDMA_MBX_STATUS_INVALID_LKEY:
208 case OCRDMA_MBX_STATUS_INVALID_VA:
209 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
210 case OCRDMA_MBX_STATUS_INVALID_FBO:
211 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
212 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
213 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
214 case OCRDMA_MBX_STATUS_SRQ_ERROR:
215 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
216 err_num = -EINVAL;
217 break;
218
219 case OCRDMA_MBX_STATUS_PD_INUSE:
220 case OCRDMA_MBX_STATUS_QP_BOUND:
221 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
222 case OCRDMA_MBX_STATUS_MW_BOUND:
223 err_num = -EBUSY;
224 break;
225
226 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
227 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
228 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
230 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
231 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
232 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
233 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
234 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
235 err_num = -ENOBUFS;
236 break;
237
238 case OCRDMA_MBX_STATUS_FAILED:
239 switch (add_status) {
240 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
241 err_num = -EAGAIN;
242 break;
243 }
244 default:
245 err_num = -EFAULT;
246 }
247 return err_num;
248}
249
250static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
251{
252 int err_num = -EINVAL;
253
254 switch (cqe_status) {
255 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
256 err_num = -EPERM;
257 break;
258 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
259 err_num = -EINVAL;
260 break;
261 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
262 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
263 err_num = -EAGAIN;
264 break;
265 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
266 err_num = -EIO;
267 break;
268 }
269 return err_num;
270}
271
272void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
273 bool solicited, u16 cqe_popped)
274{
275 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
276
277 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
278 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
279
280 if (armed)
281 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
282 if (solicited)
283 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
284 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
285 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
286}
287
288static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
289{
290 u32 val = 0;
291
292 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
293 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
294 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
295}
296
297static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
298 bool arm, bool clear_int, u16 num_eqe)
299{
300 u32 val = 0;
301
302 val |= eq_id & OCRDMA_EQ_ID_MASK;
303 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
304 if (arm)
305 val |= (1 << OCRDMA_REARM_SHIFT);
306 if (clear_int)
307 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
308 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
309 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
310 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
311}
312
313static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
314 u8 opcode, u8 subsys, u32 cmd_len)
315{
316 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
317 cmd_hdr->timeout = 20; /* seconds */
318 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
319}
320
321static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
322{
323 struct ocrdma_mqe *mqe;
324
325 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
326 if (!mqe)
327 return NULL;
328 mqe->hdr.spcl_sge_cnt_emb |=
329 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
330 OCRDMA_MQE_HDR_EMB_MASK;
331 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
332
333 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
334 mqe->hdr.pyld_len);
335 return mqe;
336}
337
338static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
339{
340 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
341}
342
343static int ocrdma_alloc_q(struct ocrdma_dev *dev,
344 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
345{
346 memset(q, 0, sizeof(*q));
347 q->len = len;
348 q->entry_size = entry_size;
349 q->size = len * entry_size;
350 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
351 &q->dma, GFP_KERNEL);
352 if (!q->va)
353 return -ENOMEM;
354 memset(q->va, 0, q->size);
355 return 0;
356}
357
358static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
359 dma_addr_t host_pa, int hw_page_size)
360{
361 int i;
362
363 for (i = 0; i < cnt; i++) {
364 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
365 q_pa[i].hi = (u32) upper_32_bits(host_pa);
366 host_pa += hw_page_size;
367 }
368}
369
370static void ocrdma_assign_eq_vect_gen2(struct ocrdma_dev *dev,
371 struct ocrdma_eq *eq)
372{
373 /* assign vector and update vector id for next EQ */
374 eq->vector = dev->nic_info.msix.start_vector;
375 dev->nic_info.msix.start_vector += 1;
376}
377
378static void ocrdma_free_eq_vect_gen2(struct ocrdma_dev *dev)
379{
380 /* this assumes that EQs are freed in exactly reverse order
381 * as its allocation.
382 */
383 dev->nic_info.msix.start_vector -= 1;
384}
385
abe3afac
RD		 386static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
387 int queue_type)
fe2caefc
PP		 388{
389 u8 opcode = 0;
390 int status;
391 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
392
393 switch (queue_type) {
394 case QTYPE_MCCQ:
395 opcode = OCRDMA_CMD_DELETE_MQ;
396 break;
397 case QTYPE_CQ:
398 opcode = OCRDMA_CMD_DELETE_CQ;
399 break;
400 case QTYPE_EQ:
401 opcode = OCRDMA_CMD_DELETE_EQ;
402 break;
403 default:
404 BUG();
405 }
406 memset(cmd, 0, sizeof(*cmd));
407 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
408 cmd->id = q->id;
409
410 status = be_roce_mcc_cmd(dev->nic_info.netdev,
411 cmd, sizeof(*cmd), NULL, NULL);
412 if (!status)
413 q->created = false;
414 return status;
415}
416
417static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
418{
419 int status;
420 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
421 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
422
423 memset(cmd, 0, sizeof(*cmd));
424 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
425 sizeof(*cmd));
426 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
427 cmd->req.rsvd_version = 0;
428 else
429 cmd->req.rsvd_version = 2;
430
431 cmd->num_pages = 4;
432 cmd->valid = OCRDMA_CREATE_EQ_VALID;
433 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
434
435 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
436 PAGE_SIZE_4K);
437 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
438 NULL);
439 if (!status) {
440 eq->q.id = rsp->vector_eqid & 0xffff;
441 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
442 ocrdma_assign_eq_vect_gen2(dev, eq);
443 else {
444 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
445 dev->nic_info.msix.start_vector += 1;
446 }
447 eq->q.created = true;
448 }
449 return status;
450}
451
452static int ocrdma_create_eq(struct ocrdma_dev *dev,
453 struct ocrdma_eq *eq, u16 q_len)
454{
455 int status;
456
457 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
458 sizeof(struct ocrdma_eqe));
459 if (status)
460 return status;
461
462 status = ocrdma_mbx_create_eq(dev, eq);
463 if (status)
464 goto mbx_err;
465 eq->dev = dev;
466 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
467
468 return 0;
469mbx_err:
470 ocrdma_free_q(dev, &eq->q);
471 return status;
472}
473
474static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
475{
476 int irq;
477
478 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
479 irq = dev->nic_info.pdev->irq;
480 else
481 irq = dev->nic_info.msix.vector_list[eq->vector];
482 return irq;
483}
484
485static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
486{
487 if (eq->q.created) {
488 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
489 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
490 ocrdma_free_eq_vect_gen2(dev);
491 ocrdma_free_q(dev, &eq->q);
492 }
493}
494
495static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
496{
497 int irq;
498
499 /* disarm EQ so that interrupts are not generated
500 * during freeing and EQ delete is in progress.
501 */
502 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
503
504 irq = ocrdma_get_irq(dev, eq);
505 free_irq(irq, eq);
506 _ocrdma_destroy_eq(dev, eq);
507}
508
509static void ocrdma_destroy_qp_eqs(struct ocrdma_dev *dev)
510{
511 int i;
512
513 /* deallocate the data path eqs */
514 for (i = 0; i < dev->eq_cnt; i++)
515 ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
516}
517
abe3afac
RD		 518static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
519 struct ocrdma_queue_info *cq,
520 struct ocrdma_queue_info *eq)
fe2caefc
PP		 521{
522 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
523 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
524 int status;
525
526 memset(cmd, 0, sizeof(*cmd));
527 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
528 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
529
530 cmd->pgsz_pgcnt = PAGES_4K_SPANNED(cq->va, cq->size);
531 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
532 cmd->eqn = (eq->id << OCRDMA_CREATE_CQ_EQID_SHIFT);
533
534 ocrdma_build_q_pages(&cmd->pa[0], cmd->pgsz_pgcnt,
535 cq->dma, PAGE_SIZE_4K);
536 status = be_roce_mcc_cmd(dev->nic_info.netdev,
537 cmd, sizeof(*cmd), NULL, NULL);
538 if (!status) {
539 cq->id = (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
540 cq->created = true;
541 }
542 return status;
543}
544
545static u32 ocrdma_encoded_q_len(int q_len)
546{
547 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
548
549 if (len_encoded == 16)
550 len_encoded = 0;
551 return len_encoded;
552}
553
554static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
555 struct ocrdma_queue_info *mq,
556 struct ocrdma_queue_info *cq)
557{
558 int num_pages, status;
559 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
560 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
561 struct ocrdma_pa *pa;
562
563 memset(cmd, 0, sizeof(*cmd));
564 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
565
566 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
567 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ,
568 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
569 cmd->v0.pages = num_pages;
570 cmd->v0.async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
571 cmd->v0.async_cqid_valid = (cq->id << 1);
572 cmd->v0.cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
573 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
574 cmd->v0.cqid_ringsize |=
575 (cq->id << OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT);
576 cmd->v0.valid = OCRDMA_CREATE_MQ_VALID;
577 pa = &cmd->v0.pa[0];
578 } else {
579 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
580 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
581 cmd->req.rsvd_version = 1;
582 cmd->v1.cqid_pages = num_pages;
583 cmd->v1.cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
584 cmd->v1.async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
585 cmd->v1.async_event_bitmap = Bit(20);
586 cmd->v1.async_cqid_ringsize = cq->id;
587 cmd->v1.async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
588 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
589 cmd->v1.valid = OCRDMA_CREATE_MQ_VALID;
590 pa = &cmd->v1.pa[0];
591 }
592 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
593 status = be_roce_mcc_cmd(dev->nic_info.netdev,
594 cmd, sizeof(*cmd), NULL, NULL);
595 if (!status) {
596 mq->id = rsp->id;
597 mq->created = true;
598 }
599 return status;
600}
601
602static int ocrdma_create_mq(struct ocrdma_dev *dev)
603{
604 int status;
605
606 /* Alloc completion queue for Mailbox queue */
607 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
608 sizeof(struct ocrdma_mcqe));
609 if (status)
610 goto alloc_err;
611
612 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->meq.q);
613 if (status)
614 goto mbx_cq_free;
615
616 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
617 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
618 mutex_init(&dev->mqe_ctx.lock);
619
620 /* Alloc Mailbox queue */
621 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
622 sizeof(struct ocrdma_mqe));
623 if (status)
624 goto mbx_cq_destroy;
625 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
626 if (status)
627 goto mbx_q_free;
628 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
629 return 0;
630
631mbx_q_free:
632 ocrdma_free_q(dev, &dev->mq.sq);
633mbx_cq_destroy:
634 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
635mbx_cq_free:
636 ocrdma_free_q(dev, &dev->mq.cq);
637alloc_err:
638 return status;
639}
640
641static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
642{
643 struct ocrdma_queue_info *mbxq, *cq;
644
645 /* mqe_ctx lock synchronizes with any other pending cmds. */
646 mutex_lock(&dev->mqe_ctx.lock);
647 mbxq = &dev->mq.sq;
648 if (mbxq->created) {
649 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
650 ocrdma_free_q(dev, mbxq);
651 }
652 mutex_unlock(&dev->mqe_ctx.lock);
653
654 cq = &dev->mq.cq;
655 if (cq->created) {
656 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
657 ocrdma_free_q(dev, cq);
658 }
659}
660
661static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
662 struct ocrdma_qp *qp)
663{
664 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
665 enum ib_qp_state old_ib_qps;
666
667 if (qp == NULL)
668 BUG();
669 ocrdma_qp_state_machine(qp, new_ib_qps, &old_ib_qps);
670}
671
672static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
673 struct ocrdma_ae_mcqe *cqe)
674{
675 struct ocrdma_qp *qp = NULL;
676 struct ocrdma_cq *cq = NULL;
e9db2953 677 struct ib_event ib_evt;
fe2caefc
PP		 678 int cq_event = 0;
679 int qp_event = 1;
680 int srq_event = 0;
681 int dev_event = 0;
682 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
683 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
684
685 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
686 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
687 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
688 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
689
e9db2953
RD		 690 ib_evt.device = &dev->ibdev;
691
fe2caefc
PP		 692 switch (type) {
693 case OCRDMA_CQ_ERROR:
694 ib_evt.element.cq = &cq->ibcq;
695 ib_evt.event = IB_EVENT_CQ_ERR;
696 cq_event = 1;
697 qp_event = 0;
698 break;
699 case OCRDMA_CQ_OVERRUN_ERROR:
700 ib_evt.element.cq = &cq->ibcq;
701 ib_evt.event = IB_EVENT_CQ_ERR;
702 break;
703 case OCRDMA_CQ_QPCAT_ERROR:
704 ib_evt.element.qp = &qp->ibqp;
705 ib_evt.event = IB_EVENT_QP_FATAL;
706 ocrdma_process_qpcat_error(dev, qp);
707 break;
708 case OCRDMA_QP_ACCESS_ERROR:
709 ib_evt.element.qp = &qp->ibqp;
710 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
711 break;
712 case OCRDMA_QP_COMM_EST_EVENT:
713 ib_evt.element.qp = &qp->ibqp;
714 ib_evt.event = IB_EVENT_COMM_EST;
715 break;
716 case OCRDMA_SQ_DRAINED_EVENT:
717 ib_evt.element.qp = &qp->ibqp;
718 ib_evt.event = IB_EVENT_SQ_DRAINED;
719 break;
720 case OCRDMA_DEVICE_FATAL_EVENT:
721 ib_evt.element.port_num = 1;
722 ib_evt.event = IB_EVENT_DEVICE_FATAL;
723 qp_event = 0;
724 dev_event = 1;
725 break;
726 case OCRDMA_SRQCAT_ERROR:
727 ib_evt.element.srq = &qp->srq->ibsrq;
728 ib_evt.event = IB_EVENT_SRQ_ERR;
729 srq_event = 1;
730 qp_event = 0;
731 break;
732 case OCRDMA_SRQ_LIMIT_EVENT:
733 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 734 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 735 srq_event = 1;
736 qp_event = 0;
737 break;
738 case OCRDMA_QP_LAST_WQE_EVENT:
739 ib_evt.element.qp = &qp->ibqp;
740 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
741 break;
742 default:
743 cq_event = 0;
744 qp_event = 0;
745 srq_event = 0;
746 dev_event = 0;
747 ocrdma_err("%s() unknown type=0x%x\n", __func__, type);
748 break;
749 }
750
751 if (qp_event) {
752 if (qp->ibqp.event_handler)
753 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
754 } else if (cq_event) {
755 if (cq->ibcq.event_handler)
756 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
757 } else if (srq_event) {
758 if (qp->srq->ibsrq.event_handler)
759 qp->srq->ibsrq.event_handler(&ib_evt,
760 qp->srq->ibsrq.
761 srq_context);
762 } else if (dev_event)
763 ib_dispatch_event(&ib_evt);
764
765}
766
767static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
768{
769 /* async CQE processing */
770 struct ocrdma_ae_mcqe *cqe = ae_cqe;
771 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
772 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
773
774 if (evt_code == OCRDMA_ASYNC_EVE_CODE)
775 ocrdma_dispatch_ibevent(dev, cqe);
776 else
777 ocrdma_err("%s(%d) invalid evt code=0x%x\n",
778 __func__, dev->id, evt_code);
779}
780
781static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
782{
783 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
784 dev->mqe_ctx.cqe_status = (cqe->status &
785 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
786 dev->mqe_ctx.ext_status =
787 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
788 >> OCRDMA_MCQE_ESTATUS_SHIFT;
789 dev->mqe_ctx.cmd_done = true;
790 wake_up(&dev->mqe_ctx.cmd_wait);
791 } else
792 ocrdma_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
793 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
794}
795
796static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
797{
798 u16 cqe_popped = 0;
799 struct ocrdma_mcqe *cqe;
800
801 while (1) {
802 cqe = ocrdma_get_mcqe(dev);
803 if (cqe == NULL)
804 break;
805 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
806 cqe_popped += 1;
807 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
808 ocrdma_process_acqe(dev, cqe);
809 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
810 ocrdma_process_mcqe(dev, cqe);
811 else
812 ocrdma_err("%s() cqe->compl is not set.\n", __func__);
813 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
814 ocrdma_mcq_inc_tail(dev);
815 }
816 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
817 return 0;
818}
819
820static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
821 struct ocrdma_cq *cq)
822{
823 unsigned long flags;
824 struct ocrdma_qp *qp;
825 bool buddy_cq_found = false;
826 /* Go through list of QPs in error state which are using this CQ
827 * and invoke its callback handler to trigger CQE processing for
828 * error/flushed CQE. It is rare to find more than few entries in
829 * this list as most consumers stops after getting error CQE.
830 * List is traversed only once when a matching buddy cq found for a QP.
831 */
832 spin_lock_irqsave(&dev->flush_q_lock, flags);
833 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
834 if (qp->srq)
835 continue;
836 /* if wq and rq share the same cq, than comp_handler
837 * is already invoked.
838 */
839 if (qp->sq_cq == qp->rq_cq)
840 continue;
841 /* if completion came on sq, rq's cq is buddy cq.
842 * if completion came on rq, sq's cq is buddy cq.
843 */
844 if (qp->sq_cq == cq)
845 cq = qp->rq_cq;
846 else
847 cq = qp->sq_cq;
848 buddy_cq_found = true;
849 break;
850 }
851 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
852 if (buddy_cq_found == false)
853 return;
854 if (cq->ibcq.comp_handler) {
855 spin_lock_irqsave(&cq->comp_handler_lock, flags);
856 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
857 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
858 }
859}
860
861static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
862{
863 unsigned long flags;
864 struct ocrdma_cq *cq;
865
866 if (cq_idx >= OCRDMA_MAX_CQ)
867 BUG();
868
869 cq = dev->cq_tbl[cq_idx];
870 if (cq == NULL) {
871 ocrdma_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
872 return;
873 }
874 spin_lock_irqsave(&cq->cq_lock, flags);
875 cq->armed = false;
876 cq->solicited = false;
877 spin_unlock_irqrestore(&cq->cq_lock, flags);
878
879 ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
880
881 if (cq->ibcq.comp_handler) {
882 spin_lock_irqsave(&cq->comp_handler_lock, flags);
883 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
884 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
885 }
886 ocrdma_qp_buddy_cq_handler(dev, cq);
887}
888
889static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
890{
891 /* process the MQ-CQE. */
892 if (cq_id == dev->mq.cq.id)
893 ocrdma_mq_cq_handler(dev, cq_id);
894 else
895 ocrdma_qp_cq_handler(dev, cq_id);
896}
897
898static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
899{
900 struct ocrdma_eq *eq = handle;
901 struct ocrdma_dev *dev = eq->dev;
902 struct ocrdma_eqe eqe;
903 struct ocrdma_eqe *ptr;
904 u16 eqe_popped = 0;
905 u16 cq_id;
906 while (1) {
907 ptr = ocrdma_get_eqe(eq);
908 eqe = *ptr;
909 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
910 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
911 break;
912 eqe_popped += 1;
913 ptr->id_valid = 0;
914 /* check whether its CQE or not. */
915 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
916 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
917 ocrdma_cq_handler(dev, cq_id);
918 }
919 ocrdma_eq_inc_tail(eq);
920 }
921 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
922 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
923 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
924 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
925 return IRQ_HANDLED;
926}
927
928static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
929{
930 struct ocrdma_mqe *mqe;
931
932 dev->mqe_ctx.tag = dev->mq.sq.head;
933 dev->mqe_ctx.cmd_done = false;
934 mqe = ocrdma_get_mqe(dev);
935 cmd->hdr.tag_lo = dev->mq.sq.head;
936 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
937 /* make sure descriptor is written before ringing doorbell */
938 wmb();
939 ocrdma_mq_inc_head(dev);
940 ocrdma_ring_mq_db(dev);
941}
942
943static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
944{
945 long status;
946 /* 30 sec timeout */
947 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
948 (dev->mqe_ctx.cmd_done != false),
949 msecs_to_jiffies(30000));
950 if (status)
951 return 0;
952 else
953 return -1;
954}
955
956/* issue a mailbox command on the MQ */
957static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
958{
959 int status = 0;
960 u16 cqe_status, ext_status;
961 struct ocrdma_mqe *rsp;
962
963 mutex_lock(&dev->mqe_ctx.lock);
964 ocrdma_post_mqe(dev, mqe);
965 status = ocrdma_wait_mqe_cmpl(dev);
966 if (status)
967 goto mbx_err;
968 cqe_status = dev->mqe_ctx.cqe_status;
969 ext_status = dev->mqe_ctx.ext_status;
970 rsp = ocrdma_get_mqe_rsp(dev);
971 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
972 if (cqe_status || ext_status) {
973 ocrdma_err
974 ("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
975 __func__,
976 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
977 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
978 status = ocrdma_get_mbx_cqe_errno(cqe_status);
979 goto mbx_err;
980 }
981 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
982 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
983mbx_err:
984 mutex_unlock(&dev->mqe_ctx.lock);
985 return status;
986}
987
988static void ocrdma_get_attr(struct ocrdma_dev *dev,
989 struct ocrdma_dev_attr *attr,
990 struct ocrdma_mbx_query_config *rsp)
991{
fe2caefc
PP		 992 attr->max_pd =
993 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
994 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
995 attr->max_qp =
996 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
997 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
998 attr->max_send_sge = ((rsp->max_write_send_sge &
999 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1000 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1001 attr->max_recv_sge = (rsp->max_write_send_sge &
1002 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1003 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 1004 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1005 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1006 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
fe2caefc
PP		 1007 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1008 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1009 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1010 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1011 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1012 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1013 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1014 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1015 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1016 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1017 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1018 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1019 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1020 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1021 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1022 attr->max_mr = rsp->max_mr;
1023 attr->max_mr_size = ~0ull;
1024 attr->max_fmr = 0;
1025 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1026 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1027 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1028 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1029 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1030 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1031 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1032 OCRDMA_WQE_STRIDE;
1033 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1034 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1035 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1036 OCRDMA_WQE_STRIDE;
1037 attr->max_inline_data =
1038 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1039 sizeof(struct ocrdma_sge));
fe2caefc 1040 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
fe2caefc
PP		 1041 attr->ird = 1;
1042 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1043 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1044 }
1045 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1046 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1047 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1048 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1049}
1050
1051static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1052 struct ocrdma_fw_conf_rsp *conf)
1053{
1054 u32 fn_mode;
1055
1056 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1057 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1058 return -EINVAL;
1059 dev->base_eqid = conf->base_eqid;
1060 dev->max_eq = conf->max_eq;
1061 dev->attr.max_cq = OCRDMA_MAX_CQ - 1;
1062 return 0;
1063}
1064
1065/* can be issued only during init time. */
1066static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1067{
1068 int status = -ENOMEM;
1069 struct ocrdma_mqe *cmd;
1070 struct ocrdma_fw_ver_rsp *rsp;
1071
1072 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1073 if (!cmd)
1074 return -ENOMEM;
1075 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1076 OCRDMA_CMD_GET_FW_VER,
1077 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1078
1079 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1080 if (status)
1081 goto mbx_err;
1082 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1083 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1084 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1085 sizeof(rsp->running_ver));
1086 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1087mbx_err:
1088 kfree(cmd);
1089 return status;
1090}
1091
1092/* can be issued only during init time. */
1093static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1094{
1095 int status = -ENOMEM;
1096 struct ocrdma_mqe *cmd;
1097 struct ocrdma_fw_conf_rsp *rsp;
1098
1099 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1100 if (!cmd)
1101 return -ENOMEM;
1102 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1103 OCRDMA_CMD_GET_FW_CONFIG,
1104 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1105 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1106 if (status)
1107 goto mbx_err;
1108 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1109 status = ocrdma_check_fw_config(dev, rsp);
1110mbx_err:
1111 kfree(cmd);
1112 return status;
1113}
1114
1115static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1116{
1117 int status = -ENOMEM;
1118 struct ocrdma_mbx_query_config *rsp;
1119 struct ocrdma_mqe *cmd;
1120
1121 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1122 if (!cmd)
1123 return status;
1124 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1125 if (status)
1126 goto mbx_err;
1127 rsp = (struct ocrdma_mbx_query_config *)cmd;
1128 ocrdma_get_attr(dev, &dev->attr, rsp);
1129mbx_err:
1130 kfree(cmd);
1131 return status;
1132}
1133
1134int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1135{
1136 int status = -ENOMEM;
1137 struct ocrdma_alloc_pd *cmd;
1138 struct ocrdma_alloc_pd_rsp *rsp;
1139
1140 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1141 if (!cmd)
1142 return status;
1143 if (pd->dpp_enabled)
1144 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1145 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1146 if (status)
1147 goto mbx_err;
1148 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1149 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1150 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1151 pd->dpp_enabled = true;
1152 pd->dpp_page = rsp->dpp_page_pdid >>
1153 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1154 } else {
1155 pd->dpp_enabled = false;
1156 pd->num_dpp_qp = 0;
1157 }
1158mbx_err:
1159 kfree(cmd);
1160 return status;
1161}
1162
1163int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1164{
1165 int status = -ENOMEM;
1166 struct ocrdma_dealloc_pd *cmd;
1167
1168 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1169 if (!cmd)
1170 return status;
1171 cmd->id = pd->id;
1172 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1173 kfree(cmd);
1174 return status;
1175}
1176
1177static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1178 int *num_pages, int *page_size)
1179{
1180 int i;
1181 int mem_size;
1182
1183 *num_entries = roundup_pow_of_two(*num_entries);
1184 mem_size = *num_entries * entry_size;
1185 /* find the possible lowest possible multiplier */
1186 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1187 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1188 break;
1189 }
1190 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1191 return -EINVAL;
1192 mem_size = roundup(mem_size,
1193 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1194 *num_pages =
1195 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1196 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1197 *num_entries = mem_size / entry_size;
1198 return 0;
1199}
1200
1201static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1202{
1203 int i ;
1204 int status = 0;
1205 int max_ah;
1206 struct ocrdma_create_ah_tbl *cmd;
1207 struct ocrdma_create_ah_tbl_rsp *rsp;
1208 struct pci_dev *pdev = dev->nic_info.pdev;
1209 dma_addr_t pa;
1210 struct ocrdma_pbe *pbes;
1211
1212 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1213 if (!cmd)
1214 return status;
1215
1216 max_ah = OCRDMA_MAX_AH;
1217 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1218
1219 /* number of PBEs in PBL */
1220 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1221 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1222 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1223
1224 /* page size */
1225 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1226 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1227 break;
1228 }
1229 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1230 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1231
1232 /* ah_entry size */
1233 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1234 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1235 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1236
1237 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1238 &dev->av_tbl.pbl.pa,
1239 GFP_KERNEL);
1240 if (dev->av_tbl.pbl.va == NULL)
1241 goto mem_err;
1242
1243 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1244 &pa, GFP_KERNEL);
1245 if (dev->av_tbl.va == NULL)
1246 goto mem_err_ah;
1247 dev->av_tbl.pa = pa;
1248 dev->av_tbl.num_ah = max_ah;
1249 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1250
1251 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1252 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1253 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1254 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1255 pa += PAGE_SIZE;
1256 }
1257 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1258 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1259 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1260 if (status)
1261 goto mbx_err;
1262 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1263 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1264 kfree(cmd);
1265 return 0;
1266
1267mbx_err:
1268 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1269 dev->av_tbl.pa);
1270 dev->av_tbl.va = NULL;
1271mem_err_ah:
1272 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1273 dev->av_tbl.pbl.pa);
1274 dev->av_tbl.pbl.va = NULL;
1275 dev->av_tbl.size = 0;
1276mem_err:
1277 kfree(cmd);
1278 return status;
1279}
1280
1281static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1282{
1283 struct ocrdma_delete_ah_tbl *cmd;
1284 struct pci_dev *pdev = dev->nic_info.pdev;
1285
1286 if (dev->av_tbl.va == NULL)
1287 return;
1288
1289 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1290 if (!cmd)
1291 return;
1292 cmd->ahid = dev->av_tbl.ahid;
1293
1294 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1295 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1296 dev->av_tbl.pa);
1297 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1298 dev->av_tbl.pbl.pa);
1299 kfree(cmd);
1300}
1301
1302/* Multiple CQs uses the EQ. This routine returns least used
1303 * EQ to associate with CQ. This will distributes the interrupt
1304 * processing and CPU load to associated EQ, vector and so to that CPU.
1305 */
1306static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1307{
1308 int i, selected_eq = 0, cq_cnt = 0;
1309 u16 eq_id;
1310
1311 mutex_lock(&dev->dev_lock);
1312 cq_cnt = dev->qp_eq_tbl[0].cq_cnt;
1313 eq_id = dev->qp_eq_tbl[0].q.id;
1314 /* find the EQ which is has the least number of
1315 * CQs associated with it.
1316 */
1317 for (i = 0; i < dev->eq_cnt; i++) {
1318 if (dev->qp_eq_tbl[i].cq_cnt < cq_cnt) {
1319 cq_cnt = dev->qp_eq_tbl[i].cq_cnt;
1320 eq_id = dev->qp_eq_tbl[i].q.id;
1321 selected_eq = i;
1322 }
1323 }
1324 dev->qp_eq_tbl[selected_eq].cq_cnt += 1;
1325 mutex_unlock(&dev->dev_lock);
1326 return eq_id;
1327}
1328
1329static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1330{
1331 int i;
1332
1333 mutex_lock(&dev->dev_lock);
1334 for (i = 0; i < dev->eq_cnt; i++) {
1335 if (dev->qp_eq_tbl[i].q.id != eq_id)
1336 continue;
1337 dev->qp_eq_tbl[i].cq_cnt -= 1;
1338 break;
1339 }
1340 mutex_unlock(&dev->dev_lock);
1341}
1342
1343int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1344 int entries, int dpp_cq)
1345{
1346 int status = -ENOMEM; int max_hw_cqe;
1347 struct pci_dev *pdev = dev->nic_info.pdev;
1348 struct ocrdma_create_cq *cmd;
1349 struct ocrdma_create_cq_rsp *rsp;
1350 u32 hw_pages, cqe_size, page_size, cqe_count;
1351
1352 if (dpp_cq)
1353 return -EINVAL;
1354 if (entries > dev->attr.max_cqe) {
1355 ocrdma_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1356 __func__, dev->id, dev->attr.max_cqe, entries);
1357 return -EINVAL;
1358 }
1359 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1360 return -EINVAL;
1361
1362 if (dpp_cq) {
1363 cq->max_hw_cqe = 1;
1364 max_hw_cqe = 1;
1365 cqe_size = OCRDMA_DPP_CQE_SIZE;
1366 hw_pages = 1;
1367 } else {
1368 cq->max_hw_cqe = dev->attr.max_cqe;
1369 max_hw_cqe = dev->attr.max_cqe;
1370 cqe_size = sizeof(struct ocrdma_cqe);
1371 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1372 }
1373
1374 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1375
1376 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1377 if (!cmd)
1378 return -ENOMEM;
1379 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1380 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1381 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1382 if (!cq->va) {
1383 status = -ENOMEM;
1384 goto mem_err;
1385 }
1386 memset(cq->va, 0, cq->len);
1387 page_size = cq->len / hw_pages;
1388 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1389 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1390 cmd->cmd.pgsz_pgcnt |= hw_pages;
1391 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1392
1393 if (dev->eq_cnt < 0)
1394 goto eq_err;
1395 cq->eqn = ocrdma_bind_eq(dev);
1396 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
1397 cqe_count = cq->len / cqe_size;
1398 if (cqe_count > 1024)
1399 /* Set cnt to 3 to indicate more than 1024 cq entries */
1400 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1401 else {
1402 u8 count = 0;
1403 switch (cqe_count) {
1404 case 256:
1405 count = 0;
1406 break;
1407 case 512:
1408 count = 1;
1409 break;
1410 case 1024:
1411 count = 2;
1412 break;
1413 default:
1414 goto mbx_err;
1415 }
1416 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1417 }
1418 /* shared eq between all the consumer cqs. */
1419 cmd->cmd.eqn = cq->eqn;
1420 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1421 if (dpp_cq)
1422 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1423 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1424 cq->phase_change = false;
1425 cmd->cmd.cqe_count = (cq->len / cqe_size);
1426 } else {
1427 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1428 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1429 cq->phase_change = true;
1430 }
1431
1432 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1433 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1434 if (status)
1435 goto mbx_err;
1436
1437 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1438 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1439 kfree(cmd);
1440 return 0;
1441mbx_err:
1442 ocrdma_unbind_eq(dev, cq->eqn);
1443eq_err:
1444 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1445mem_err:
1446 kfree(cmd);
1447 return status;
1448}
1449
1450int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1451{
1452 int status = -ENOMEM;
1453 struct ocrdma_destroy_cq *cmd;
1454
1455 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1456 if (!cmd)
1457 return status;
1458 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1459 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1460
1461 cmd->bypass_flush_qid |=
1462 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1463 OCRDMA_DESTROY_CQ_QID_MASK;
1464
1465 ocrdma_unbind_eq(dev, cq->eqn);
1466 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1467 if (status)
1468 goto mbx_err;
1469 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1470mbx_err:
1471 kfree(cmd);
1472 return status;
1473}
1474
1475int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1476 u32 pdid, int addr_check)
1477{
1478 int status = -ENOMEM;
1479 struct ocrdma_alloc_lkey *cmd;
1480 struct ocrdma_alloc_lkey_rsp *rsp;
1481
1482 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1483 if (!cmd)
1484 return status;
1485 cmd->pdid = pdid;
1486 cmd->pbl_sz_flags |= addr_check;
1487 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1488 cmd->pbl_sz_flags |=
1489 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1490 cmd->pbl_sz_flags |=
1491 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1492 cmd->pbl_sz_flags |=
1493 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1494 cmd->pbl_sz_flags |=
1495 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1496 cmd->pbl_sz_flags |=
1497 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1498
1499 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1500 if (status)
1501 goto mbx_err;
1502 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1503 hwmr->lkey = rsp->lrkey;
1504mbx_err:
1505 kfree(cmd);
1506 return status;
1507}
1508
1509int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1510{
1511 int status = -ENOMEM;
1512 struct ocrdma_dealloc_lkey *cmd;
1513
1514 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1515 if (!cmd)
1516 return -ENOMEM;
1517 cmd->lkey = lkey;
1518 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1519 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1520 if (status)
1521 goto mbx_err;
1522mbx_err:
1523 kfree(cmd);
1524 return status;
1525}
1526
1527static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1528 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1529{
1530 int status = -ENOMEM;
1531 int i;
1532 struct ocrdma_reg_nsmr *cmd;
1533 struct ocrdma_reg_nsmr_rsp *rsp;
1534
1535 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1536 if (!cmd)
1537 return -ENOMEM;
1538 cmd->num_pbl_pdid =
1539 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1540
1541 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1542 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1543 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1544 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1545 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1546 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1547 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1548 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1549 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1550 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1551 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1552
1553 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1554 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1555 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1556 cmd->totlen_low = hwmr->len;
1557 cmd->totlen_high = upper_32_bits(hwmr->len);
1558 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1559 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1560 cmd->va_loaddr = (u32) hwmr->va;
1561 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1562
1563 for (i = 0; i < pbl_cnt; i++) {
1564 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1565 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1566 }
1567 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1568 if (status)
1569 goto mbx_err;
1570 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1571 hwmr->lkey = rsp->lrkey;
1572mbx_err:
1573 kfree(cmd);
1574 return status;
1575}
1576
1577static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1578 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1579 u32 pbl_offset, u32 last)
1580{
1581 int status = -ENOMEM;
1582 int i;
1583 struct ocrdma_reg_nsmr_cont *cmd;
1584
1585 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1586 if (!cmd)
1587 return -ENOMEM;
1588 cmd->lrkey = hwmr->lkey;
1589 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1590 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1591 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1592
1593 for (i = 0; i < pbl_cnt; i++) {
1594 cmd->pbl[i].lo =
1595 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1596 cmd->pbl[i].hi =
1597 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1598 }
1599 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1600 if (status)
1601 goto mbx_err;
1602mbx_err:
1603 kfree(cmd);
1604 return status;
1605}
1606
1607int ocrdma_reg_mr(struct ocrdma_dev *dev,
1608 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1609{
1610 int status;
1611 u32 last = 0;
1612 u32 cur_pbl_cnt, pbl_offset;
1613 u32 pending_pbl_cnt = hwmr->num_pbls;
1614
1615 pbl_offset = 0;
1616 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1617 if (cur_pbl_cnt == pending_pbl_cnt)
1618 last = 1;
1619
1620 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1621 cur_pbl_cnt, hwmr->pbe_size, last);
1622 if (status) {
1623 ocrdma_err("%s() status=%d\n", __func__, status);
1624 return status;
1625 }
1626 /* if there is no more pbls to register then exit. */
1627 if (last)
1628 return 0;
1629
1630 while (!last) {
1631 pbl_offset += cur_pbl_cnt;
1632 pending_pbl_cnt -= cur_pbl_cnt;
1633 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1634 /* if we reach the end of the pbls, then need to set the last
1635 * bit, indicating no more pbls to register for this memory key.
1636 */
1637 if (cur_pbl_cnt == pending_pbl_cnt)
1638 last = 1;
1639
1640 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1641 pbl_offset, last);
1642 if (status)
1643 break;
1644 }
1645 if (status)
1646 ocrdma_err("%s() err. status=%d\n", __func__, status);
1647
1648 return status;
1649}
1650
1651bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1652{
1653 struct ocrdma_qp *tmp;
1654 bool found = false;
1655 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1656 if (qp == tmp) {
1657 found = true;
1658 break;
1659 }
1660 }
1661 return found;
1662}
1663
1664bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1665{
1666 struct ocrdma_qp *tmp;
1667 bool found = false;
1668 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1669 if (qp == tmp) {
1670 found = true;
1671 break;
1672 }
1673 }
1674 return found;
1675}
1676
1677void ocrdma_flush_qp(struct ocrdma_qp *qp)
1678{
1679 bool found;
1680 unsigned long flags;
1681
1682 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1683 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1684 if (!found)
1685 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1686 if (!qp->srq) {
1687 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1688 if (!found)
1689 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1690 }
1691 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1692}
1693
1694int ocrdma_qp_state_machine(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1695 enum ib_qp_state *old_ib_state)
1696{
1697 unsigned long flags;
1698 int status = 0;
1699 enum ocrdma_qp_state new_state;
1700 new_state = get_ocrdma_qp_state(new_ib_state);
1701
1702 /* sync with wqe and rqe posting */
1703 spin_lock_irqsave(&qp->q_lock, flags);
1704
1705 if (old_ib_state)
1706 *old_ib_state = get_ibqp_state(qp->state);
1707 if (new_state == qp->state) {
1708 spin_unlock_irqrestore(&qp->q_lock, flags);
1709 return 1;
1710 }
1711
1712 switch (qp->state) {
1713 case OCRDMA_QPS_RST:
1714 switch (new_state) {
1715 case OCRDMA_QPS_RST:
1716 case OCRDMA_QPS_INIT:
1717 break;
1718 default:
1719 status = -EINVAL;
1720 break;
1721 };
1722 break;
1723 case OCRDMA_QPS_INIT:
1724 /* qps: INIT->XXX */
1725 switch (new_state) {
1726 case OCRDMA_QPS_INIT:
1727 case OCRDMA_QPS_RTR:
1728 break;
1729 case OCRDMA_QPS_ERR:
1730 ocrdma_flush_qp(qp);
1731 break;
1732 default:
1733 status = -EINVAL;
1734 break;
1735 };
1736 break;
1737 case OCRDMA_QPS_RTR:
1738 /* qps: RTS->XXX */
1739 switch (new_state) {
1740 case OCRDMA_QPS_RTS:
1741 break;
1742 case OCRDMA_QPS_ERR:
1743 ocrdma_flush_qp(qp);
1744 break;
1745 default:
1746 status = -EINVAL;
1747 break;
1748 };
1749 break;
1750 case OCRDMA_QPS_RTS:
1751 /* qps: RTS->XXX */
1752 switch (new_state) {
1753 case OCRDMA_QPS_SQD:
1754 case OCRDMA_QPS_SQE:
1755 break;
1756 case OCRDMA_QPS_ERR:
1757 ocrdma_flush_qp(qp);
1758 break;
1759 default:
1760 status = -EINVAL;
1761 break;
1762 };
1763 break;
1764 case OCRDMA_QPS_SQD:
1765 /* qps: SQD->XXX */
1766 switch (new_state) {
1767 case OCRDMA_QPS_RTS:
1768 case OCRDMA_QPS_SQE:
1769 case OCRDMA_QPS_ERR:
1770 break;
1771 default:
1772 status = -EINVAL;
1773 break;
1774 };
1775 break;
1776 case OCRDMA_QPS_SQE:
1777 switch (new_state) {
1778 case OCRDMA_QPS_RTS:
1779 case OCRDMA_QPS_ERR:
1780 break;
1781 default:
1782 status = -EINVAL;
1783 break;
1784 };
1785 break;
1786 case OCRDMA_QPS_ERR:
1787 /* qps: ERR->XXX */
1788 switch (new_state) {
1789 case OCRDMA_QPS_RST:
1790 break;
1791 default:
1792 status = -EINVAL;
1793 break;
1794 };
1795 break;
1796 default:
1797 status = -EINVAL;
1798 break;
1799 };
1800 if (!status)
1801 qp->state = new_state;
1802
1803 spin_unlock_irqrestore(&qp->q_lock, flags);
1804 return status;
1805}
1806
1807static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1808{
1809 u32 flags = 0;
1810 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1811 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1812 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1813 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1814 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1815 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1816 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1817 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1818 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1819 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1820 return flags;
1821}
1822
1823static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1824 struct ib_qp_init_attr *attrs,
1825 struct ocrdma_qp *qp)
1826{
1827 int status;
1828 u32 len, hw_pages, hw_page_size;
1829 dma_addr_t pa;
1830 struct ocrdma_dev *dev = qp->dev;
1831 struct pci_dev *pdev = dev->nic_info.pdev;
1832 u32 max_wqe_allocated;
1833 u32 max_sges = attrs->cap.max_send_sge;
1834
1835 max_wqe_allocated = attrs->cap.max_send_wr;
1836 /* need to allocate one extra to for GEN1 family */
1837 if (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY)
1838 max_wqe_allocated += 1;
1839
1840 status = ocrdma_build_q_conf(&max_wqe_allocated,
1841 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1842 if (status) {
1843 ocrdma_err("%s() req. max_send_wr=0x%x\n", __func__,
1844 max_wqe_allocated);
1845 return -EINVAL;
1846 }
1847 qp->sq.max_cnt = max_wqe_allocated;
1848 len = (hw_pages * hw_page_size);
1849
1850 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1851 if (!qp->sq.va)
1852 return -EINVAL;
1853 memset(qp->sq.va, 0, len);
1854 qp->sq.len = len;
1855 qp->sq.pa = pa;
1856 qp->sq.entry_size = dev->attr.wqe_size;
1857 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1858
1859 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1860 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1861 cmd->num_wq_rq_pages |= (hw_pages <<
1862 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1863 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1864 cmd->max_sge_send_write |= (max_sges <<
1865 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1866 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1867 cmd->max_sge_send_write |= (max_sges <<
1868 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1869 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1870 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1871 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1872 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1873 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1874 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1875 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1876 return 0;
1877}
1878
1879static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1880 struct ib_qp_init_attr *attrs,
1881 struct ocrdma_qp *qp)
1882{
1883 int status;
1884 u32 len, hw_pages, hw_page_size;
1885 dma_addr_t pa = 0;
1886 struct ocrdma_dev *dev = qp->dev;
1887 struct pci_dev *pdev = dev->nic_info.pdev;
1888 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1889
1890 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1891 &hw_pages, &hw_page_size);
1892 if (status) {
1893 ocrdma_err("%s() req. max_recv_wr=0x%x\n", __func__,
1894 attrs->cap.max_recv_wr + 1);
1895 return status;
1896 }
1897 qp->rq.max_cnt = max_rqe_allocated;
1898 len = (hw_pages * hw_page_size);
1899
1900 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1901 if (!qp->rq.va)
1902 return status;
1903 memset(qp->rq.va, 0, len);
1904 qp->rq.pa = pa;
1905 qp->rq.len = len;
1906 qp->rq.entry_size = dev->attr.rqe_size;
1907
1908 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1909 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1910 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1911 cmd->num_wq_rq_pages |=
1912 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1913 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1914 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1915 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1916 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1917 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1918 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1919 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1920 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1921 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1922 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1923 return 0;
1924}
1925
1926static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1927 struct ocrdma_pd *pd,
1928 struct ocrdma_qp *qp,
1929 u8 enable_dpp_cq, u16 dpp_cq_id)
1930{
1931 pd->num_dpp_qp--;
1932 qp->dpp_enabled = true;
1933 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1934 if (!enable_dpp_cq)
1935 return;
1936 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1937 cmd->dpp_credits_cqid = dpp_cq_id;
1938 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1939 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1940}
1941
1942static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1943 struct ocrdma_qp *qp)
1944{
1945 struct ocrdma_dev *dev = qp->dev;
1946 struct pci_dev *pdev = dev->nic_info.pdev;
1947 dma_addr_t pa = 0;
1948 int ird_page_size = dev->attr.ird_page_size;
1949 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
1950
1951 if (dev->attr.ird == 0)
1952 return 0;
1953
1954 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1955 &pa, GFP_KERNEL);
1956 if (!qp->ird_q_va)
1957 return -ENOMEM;
1958 memset(qp->ird_q_va, 0, ird_q_len);
1959 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1960 pa, ird_page_size);
1961 return 0;
1962}
1963
1964static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1965 struct ocrdma_qp *qp,
1966 struct ib_qp_init_attr *attrs,
1967 u16 *dpp_offset, u16 *dpp_credit_lmt)
1968{
1969 u32 max_wqe_allocated, max_rqe_allocated;
1970 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1971 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1972 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1973 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1974 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1975 qp->dpp_enabled = false;
1976 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1977 qp->dpp_enabled = true;
1978 *dpp_credit_lmt = (rsp->dpp_response &
1979 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1980 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1981 *dpp_offset = (rsp->dpp_response &
1982 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1983 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1984 }
1985 max_wqe_allocated =
1986 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1987 max_wqe_allocated = 1 << max_wqe_allocated;
1988 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1989
fe2caefc
PP		 1990 qp->sq.max_cnt = max_wqe_allocated;
1991 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1992
1993 if (!attrs->srq) {
1994 qp->rq.max_cnt = max_rqe_allocated;
1995 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 1996 }
1997}
1998
1999int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2000 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2001 u16 *dpp_credit_lmt)
2002{
2003 int status = -ENOMEM;
2004 u32 flags = 0;
2005 struct ocrdma_dev *dev = qp->dev;
2006 struct ocrdma_pd *pd = qp->pd;
2007 struct pci_dev *pdev = dev->nic_info.pdev;
2008 struct ocrdma_cq *cq;
2009 struct ocrdma_create_qp_req *cmd;
2010 struct ocrdma_create_qp_rsp *rsp;
2011 int qptype;
2012
2013 switch (attrs->qp_type) {
2014 case IB_QPT_GSI:
2015 qptype = OCRDMA_QPT_GSI;
2016 break;
2017 case IB_QPT_RC:
2018 qptype = OCRDMA_QPT_RC;
2019 break;
2020 case IB_QPT_UD:
2021 qptype = OCRDMA_QPT_UD;
2022 break;
2023 default:
2024 return -EINVAL;
2025 };
2026
2027 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2028 if (!cmd)
2029 return status;
2030 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2031 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2032 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2033 if (status)
2034 goto sq_err;
2035
2036 if (attrs->srq) {
2037 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2038 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2039 cmd->rq_addr[0].lo = srq->id;
2040 qp->srq = srq;
2041 } else {
2042 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2043 if (status)
2044 goto rq_err;
2045 }
2046
2047 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2048 if (status)
2049 goto mbx_err;
2050
2051 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2052 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2053
2054 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2055
2056 cmd->max_sge_recv_flags |= flags;
2057 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2058 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2059 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2060 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2061 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2062 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2063 cq = get_ocrdma_cq(attrs->send_cq);
2064 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2065 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2066 qp->sq_cq = cq;
2067 cq = get_ocrdma_cq(attrs->recv_cq);
2068 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2069 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2070 qp->rq_cq = cq;
2071
2072 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2073 (attrs->cap.max_inline_data <= dev->attr.max_inline_data))
2074 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2075 dpp_cq_id);
2076
2077 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2078 if (status)
2079 goto mbx_err;
2080 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2081 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2082 qp->state = OCRDMA_QPS_RST;
2083 kfree(cmd);
2084 return 0;
2085mbx_err:
2086 if (qp->rq.va)
2087 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2088rq_err:
2089 ocrdma_err("%s(%d) rq_err\n", __func__, dev->id);
2090 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2091sq_err:
2092 ocrdma_err("%s(%d) sq_err\n", __func__, dev->id);
2093 kfree(cmd);
2094 return status;
2095}
2096
2097int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2098 struct ocrdma_qp_params *param)
2099{
2100 int status = -ENOMEM;
2101 struct ocrdma_query_qp *cmd;
2102 struct ocrdma_query_qp_rsp *rsp;
2103
2104 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2105 if (!cmd)
2106 return status;
2107 cmd->qp_id = qp->id;
2108 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2109 if (status)
2110 goto mbx_err;
2111 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2112 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2113mbx_err:
2114 kfree(cmd);
2115 return status;
2116}
2117
2118int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid,
2119 u8 *mac_addr)
2120{
2121 struct in6_addr in6;
2122
2123 memcpy(&in6, dgid, sizeof in6);
2124 if (rdma_is_multicast_addr(&in6))
2125 rdma_get_mcast_mac(&in6, mac_addr);
2126 else if (rdma_link_local_addr(&in6))
2127 rdma_get_ll_mac(&in6, mac_addr);
2128 else {
2129 ocrdma_err("%s() fail to resolve mac_addr.\n", __func__);
2130 return -EINVAL;
2131 }
2132 return 0;
2133}
2134
2135static void ocrdma_set_av_params(struct ocrdma_qp *qp,
2136 struct ocrdma_modify_qp *cmd,
2137 struct ib_qp_attr *attrs)
2138{
2139 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2140 union ib_gid sgid;
2141 u32 vlan_id;
2142 u8 mac_addr[6];
2143 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2144 return;
2145 cmd->params.tclass_sq_psn |=
2146 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2147 cmd->params.rnt_rc_sl_fl |=
2148 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2149 cmd->params.hop_lmt_rq_psn |=
2150 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2151 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2152 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2153 sizeof(cmd->params.dgid));
2154 ocrdma_query_gid(&qp->dev->ibdev, 1,
2155 ah_attr->grh.sgid_index, &sgid);
2156 qp->sgid_idx = ah_attr->grh.sgid_index;
2157 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2158 ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]);
2159 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2160 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2161 /* convert them to LE format. */
2162 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2163 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2164 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2165 vlan_id = rdma_get_vlan_id(&sgid);
2166 if (vlan_id && (vlan_id < 0x1000)) {
2167 cmd->params.vlan_dmac_b4_to_b5 |=
2168 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2169 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2170 }
2171}
2172
2173static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2174 struct ocrdma_modify_qp *cmd,
2175 struct ib_qp_attr *attrs, int attr_mask,
2176 enum ib_qp_state old_qps)
2177{
2178 int status = 0;
2179 struct net_device *netdev = qp->dev->nic_info.netdev;
2180 int eth_mtu = iboe_get_mtu(netdev->mtu);
2181
2182 if (attr_mask & IB_QP_PKEY_INDEX) {
2183 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2184 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2185 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2186 }
2187 if (attr_mask & IB_QP_QKEY) {
2188 qp->qkey = attrs->qkey;
2189 cmd->params.qkey = attrs->qkey;
2190 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2191 }
2192 if (attr_mask & IB_QP_AV)
2193 ocrdma_set_av_params(qp, cmd, attrs);
2194 else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2195 /* set the default mac address for UD, GSI QPs */
2196 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2197 (qp->dev->nic_info.mac_addr[1] << 8) |
2198 (qp->dev->nic_info.mac_addr[2] << 16) |
2199 (qp->dev->nic_info.mac_addr[3] << 24);
2200 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2201 (qp->dev->nic_info.mac_addr[5] << 8);
2202 }
2203 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2204 attrs->en_sqd_async_notify) {
2205 cmd->params.max_sge_recv_flags |=
2206 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2207 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2208 }
2209 if (attr_mask & IB_QP_DEST_QPN) {
2210 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2211 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2212 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2213 }
2214 if (attr_mask & IB_QP_PATH_MTU) {
2215 if (ib_mtu_enum_to_int(eth_mtu) <
2216 ib_mtu_enum_to_int(attrs->path_mtu)) {
2217 status = -EINVAL;
2218 goto pmtu_err;
2219 }
2220 cmd->params.path_mtu_pkey_indx |=
2221 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2222 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2223 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2224 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2225 }
2226 if (attr_mask & IB_QP_TIMEOUT) {
2227 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2228 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2229 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2230 }
2231 if (attr_mask & IB_QP_RETRY_CNT) {
2232 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2233 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2234 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2235 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2236 }
2237 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2238 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2239 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2240 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2241 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2242 }
2243 if (attr_mask & IB_QP_RNR_RETRY) {
2244 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2245 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2246 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2247 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2248 }
2249 if (attr_mask & IB_QP_SQ_PSN) {
2250 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2251 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2252 }
2253 if (attr_mask & IB_QP_RQ_PSN) {
2254 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2255 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2256 }
2257 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2258 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2259 status = -EINVAL;
2260 goto pmtu_err;
2261 }
2262 qp->max_ord = attrs->max_rd_atomic;
2263 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2264 }
2265 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2266 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2267 status = -EINVAL;
2268 goto pmtu_err;
2269 }
2270 qp->max_ird = attrs->max_dest_rd_atomic;
2271 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2272 }
2273 cmd->params.max_ord_ird = (qp->max_ord <<
2274 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2275 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2276pmtu_err:
2277 return status;
2278}
2279
2280int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2281 struct ib_qp_attr *attrs, int attr_mask,
2282 enum ib_qp_state old_qps)
2283{
2284 int status = -ENOMEM;
2285 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2286
2287 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2288 if (!cmd)
2289 return status;
2290
2291 cmd->params.id = qp->id;
2292 cmd->flags = 0;
2293 if (attr_mask & IB_QP_STATE) {
2294 cmd->params.max_sge_recv_flags |=
2295 (get_ocrdma_qp_state(attrs->qp_state) <<
2296 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2297 OCRDMA_QP_PARAMS_STATE_MASK;
2298 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2299 } else
2300 cmd->params.max_sge_recv_flags |=
2301 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2302 OCRDMA_QP_PARAMS_STATE_MASK;
2303 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps);
2304 if (status)
2305 goto mbx_err;
2306 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2307 if (status)
2308 goto mbx_err;
c592c423 2309
fe2caefc
PP		 2310mbx_err:
2311 kfree(cmd);
2312 return status;
2313}
2314
2315int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2316{
2317 int status = -ENOMEM;
2318 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2319 struct pci_dev *pdev = dev->nic_info.pdev;
2320
2321 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2322 if (!cmd)
2323 return status;
2324 cmd->qp_id = qp->id;
2325 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2326 if (status)
2327 goto mbx_err;
c592c423 2328
fe2caefc
PP		 2329mbx_err:
2330 kfree(cmd);
2331 if (qp->sq.va)
2332 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2333 if (!qp->srq && qp->rq.va)
2334 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2335 if (qp->dpp_enabled)
2336 qp->pd->num_dpp_qp++;
2337 return status;
2338}
2339
2340int ocrdma_mbx_create_srq(struct ocrdma_srq *srq,
2341 struct ib_srq_init_attr *srq_attr,
2342 struct ocrdma_pd *pd)
2343{
2344 int status = -ENOMEM;
2345 int hw_pages, hw_page_size;
2346 int len;
2347 struct ocrdma_create_srq_rsp *rsp;
2348 struct ocrdma_create_srq *cmd;
2349 dma_addr_t pa;
2350 struct ocrdma_dev *dev = srq->dev;
2351 struct pci_dev *pdev = dev->nic_info.pdev;
2352 u32 max_rqe_allocated;
2353
2354 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2355 if (!cmd)
2356 return status;
2357
2358 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2359 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2360 status = ocrdma_build_q_conf(&max_rqe_allocated,
2361 dev->attr.rqe_size,
2362 &hw_pages, &hw_page_size);
2363 if (status) {
2364 ocrdma_err("%s() req. max_wr=0x%x\n", __func__,
2365 srq_attr->attr.max_wr);
2366 status = -EINVAL;
2367 goto ret;
2368 }
2369 len = hw_pages * hw_page_size;
2370 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2371 if (!srq->rq.va) {
2372 status = -ENOMEM;
2373 goto ret;
2374 }
2375 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2376
2377 srq->rq.entry_size = dev->attr.rqe_size;
2378 srq->rq.pa = pa;
2379 srq->rq.len = len;
2380 srq->rq.max_cnt = max_rqe_allocated;
2381
2382 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2383 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2384 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2385
2386 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2387 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2388 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2389 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2390 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2391 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2392
2393 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2394 if (status)
2395 goto mbx_err;
2396 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2397 srq->id = rsp->id;
2398 srq->rq.dbid = rsp->id;
2399 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2400 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2401 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2402 max_rqe_allocated = (1 << max_rqe_allocated);
2403 srq->rq.max_cnt = max_rqe_allocated;
2404 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2405 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2406 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2407 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2408 goto ret;
2409mbx_err:
2410 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2411ret:
2412 kfree(cmd);
2413 return status;
2414}
2415
2416int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2417{
2418 int status = -ENOMEM;
2419 struct ocrdma_modify_srq *cmd;
2420 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2421 if (!cmd)
2422 return status;
2423 cmd->id = srq->id;
2424 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2425 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2426 status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2427 kfree(cmd);
2428 return status;
2429}
2430
2431int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2432{
2433 int status = -ENOMEM;
2434 struct ocrdma_query_srq *cmd;
2435 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2436 if (!cmd)
2437 return status;
2438 cmd->id = srq->rq.dbid;
2439 status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2440 if (status == 0) {
2441 struct ocrdma_query_srq_rsp *rsp =
2442 (struct ocrdma_query_srq_rsp *)cmd;
2443 srq_attr->max_sge =
2444 rsp->srq_lmt_max_sge &
2445 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2446 srq_attr->max_wr =
2447 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2448 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2449 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2450 }
2451 kfree(cmd);
2452 return status;
2453}
2454
2455int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2456{
2457 int status = -ENOMEM;
2458 struct ocrdma_destroy_srq *cmd;
2459 struct pci_dev *pdev = dev->nic_info.pdev;
2460 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2461 if (!cmd)
2462 return status;
2463 cmd->id = srq->id;
2464 status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2465 if (srq->rq.va)
2466 dma_free_coherent(&pdev->dev, srq->rq.len,
2467 srq->rq.va, srq->rq.pa);
2468 kfree(cmd);
2469 return status;
2470}
2471
2472int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2473{
2474 int i;
2475 int status = -EINVAL;
2476 struct ocrdma_av *av;
2477 unsigned long flags;
2478
2479 av = dev->av_tbl.va;
2480 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2481 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2482 if (av->valid == 0) {
2483 av->valid = OCRDMA_AV_VALID;
2484 ah->av = av;
2485 ah->id = i;
2486 status = 0;
2487 break;
2488 }
2489 av++;
2490 }
2491 if (i == dev->av_tbl.num_ah)
2492 status = -EAGAIN;
2493 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2494 return status;
2495}
2496
2497int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2498{
2499 unsigned long flags;
2500 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2501 ah->av->valid = 0;
2502 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2503 return 0;
2504}
2505
2506static int ocrdma_create_mq_eq(struct ocrdma_dev *dev)
2507{
2508 int status;
2509 int irq;
2510 unsigned long flags = 0;
2511 int num_eq = 0;
2512
2513 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
2514 flags = IRQF_SHARED;
2515 else {
2516 num_eq = dev->nic_info.msix.num_vectors -
2517 dev->nic_info.msix.start_vector;
2518 /* minimum two vectors/eq are required for rdma to work.
2519 * one for control path and one for data path.
2520 */
2521 if (num_eq < 2)
2522 return -EBUSY;
2523 }
2524
2525 status = ocrdma_create_eq(dev, &dev->meq, OCRDMA_EQ_LEN);
2526 if (status)
2527 return status;
2528 sprintf(dev->meq.irq_name, "ocrdma_mq%d", dev->id);
2529 irq = ocrdma_get_irq(dev, &dev->meq);
2530 status = request_irq(irq, ocrdma_irq_handler, flags, dev->meq.irq_name,
2531 &dev->meq);
2532 if (status)
2533 _ocrdma_destroy_eq(dev, &dev->meq);
2534 return status;
2535}
2536
2537static int ocrdma_create_qp_eqs(struct ocrdma_dev *dev)
2538{
da496438 2539 int num_eq, i, status = 0;
fe2caefc
PP		 2540 int irq;
2541 unsigned long flags = 0;
2542
2543 num_eq = dev->nic_info.msix.num_vectors -
2544 dev->nic_info.msix.start_vector;
2545 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2546 num_eq = 1;
2547 flags = IRQF_SHARED;
2548 } else
2549 num_eq = min_t(u32, num_eq, num_online_cpus());
2550 dev->qp_eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2551 if (!dev->qp_eq_tbl)
2552 return -ENOMEM;
2553
2554 for (i = 0; i < num_eq; i++) {
2555 status = ocrdma_create_eq(dev, &dev->qp_eq_tbl[i],
2556 OCRDMA_EQ_LEN);
2557 if (status) {
2558 status = -EINVAL;
2559 break;
2560 }
2561 sprintf(dev->qp_eq_tbl[i].irq_name, "ocrdma_qp%d-%d",
2562 dev->id, i);
2563 irq = ocrdma_get_irq(dev, &dev->qp_eq_tbl[i]);
2564 status = request_irq(irq, ocrdma_irq_handler, flags,
2565 dev->qp_eq_tbl[i].irq_name,
2566 &dev->qp_eq_tbl[i]);
2567 if (status) {
2568 _ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
2569 status = -EINVAL;
2570 break;
2571 }
2572 dev->eq_cnt += 1;
2573 }
2574 /* one eq is sufficient for data path to work */
2575 if (dev->eq_cnt >= 1)
2576 return 0;
2577 if (status)
2578 ocrdma_destroy_qp_eqs(dev);
2579 return status;
2580}
2581
2582int ocrdma_init_hw(struct ocrdma_dev *dev)
2583{
2584 int status;
2585 /* set up control path eq */
2586 status = ocrdma_create_mq_eq(dev);
2587 if (status)
2588 return status;
2589 /* set up data path eq */
2590 status = ocrdma_create_qp_eqs(dev);
2591 if (status)
2592 goto qpeq_err;
2593 status = ocrdma_create_mq(dev);
2594 if (status)
2595 goto mq_err;
2596 status = ocrdma_mbx_query_fw_config(dev);
2597 if (status)
2598 goto conf_err;
2599 status = ocrdma_mbx_query_dev(dev);
2600 if (status)
2601 goto conf_err;
2602 status = ocrdma_mbx_query_fw_ver(dev);
2603 if (status)
2604 goto conf_err;
2605 status = ocrdma_mbx_create_ah_tbl(dev);
2606 if (status)
2607 goto conf_err;
2608 return 0;
2609
2610conf_err:
2611 ocrdma_destroy_mq(dev);
2612mq_err:
2613 ocrdma_destroy_qp_eqs(dev);
2614qpeq_err:
2615 ocrdma_destroy_eq(dev, &dev->meq);
2616 ocrdma_err("%s() status=%d\n", __func__, status);
2617 return status;
2618}
2619
2620void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2621{
2622 ocrdma_mbx_delete_ah_tbl(dev);
2623
2624 /* cleanup the data path eqs */
2625 ocrdma_destroy_qp_eqs(dev);
2626
2627 /* cleanup the control path */
2628 ocrdma_destroy_mq(dev);
2629 ocrdma_destroy_eq(dev, &dev->meq);
2630}
Linux kernel - Deliverables
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