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RDMA/ocrdma: FRMA code cleanup
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
35#include <rdma/ib_addr.h>
36
37#include "ocrdma.h"
38#include "ocrdma_hw.h"
39#include "ocrdma_verbs.h"
40#include "ocrdma_ah.h"
41
42enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81};
82
83enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85};
86
87enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93};
94
95static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96{
f99b1649 97 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 98}
99
100static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101{
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103}
104
105static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106{
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 108 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 109
110 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
111 return NULL;
112 return cqe;
113}
114
115static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
116{
117 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
118}
119
120static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
121{
f99b1649 122 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 123}
124
125static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
126{
127 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 128}
129
130static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
131{
f99b1649 132 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 133}
134
135enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
136{
137 switch (qps) {
138 case OCRDMA_QPS_RST:
139 return IB_QPS_RESET;
140 case OCRDMA_QPS_INIT:
141 return IB_QPS_INIT;
142 case OCRDMA_QPS_RTR:
143 return IB_QPS_RTR;
144 case OCRDMA_QPS_RTS:
145 return IB_QPS_RTS;
146 case OCRDMA_QPS_SQD:
147 case OCRDMA_QPS_SQ_DRAINING:
148 return IB_QPS_SQD;
149 case OCRDMA_QPS_SQE:
150 return IB_QPS_SQE;
151 case OCRDMA_QPS_ERR:
152 return IB_QPS_ERR;
153 };
154 return IB_QPS_ERR;
155}
156
abe3afac 157static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 158{
159 switch (qps) {
160 case IB_QPS_RESET:
161 return OCRDMA_QPS_RST;
162 case IB_QPS_INIT:
163 return OCRDMA_QPS_INIT;
164 case IB_QPS_RTR:
165 return OCRDMA_QPS_RTR;
166 case IB_QPS_RTS:
167 return OCRDMA_QPS_RTS;
168 case IB_QPS_SQD:
169 return OCRDMA_QPS_SQD;
170 case IB_QPS_SQE:
171 return OCRDMA_QPS_SQE;
172 case IB_QPS_ERR:
173 return OCRDMA_QPS_ERR;
174 };
175 return OCRDMA_QPS_ERR;
176}
177
178static int ocrdma_get_mbx_errno(u32 status)
179{
f99b1649 180 int err_num;
fe2caefc
PP		 181 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
182 OCRDMA_MBX_RSP_STATUS_SHIFT;
183 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
184 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
185
186 switch (mbox_status) {
187 case OCRDMA_MBX_STATUS_OOR:
188 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
189 err_num = -EAGAIN;
190 break;
191
192 case OCRDMA_MBX_STATUS_INVALID_PD:
193 case OCRDMA_MBX_STATUS_INVALID_CQ:
194 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
195 case OCRDMA_MBX_STATUS_INVALID_QP:
196 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
197 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
198 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
200 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
201 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
202 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
203 case OCRDMA_MBX_STATUS_INVALID_LKEY:
204 case OCRDMA_MBX_STATUS_INVALID_VA:
205 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
206 case OCRDMA_MBX_STATUS_INVALID_FBO:
207 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
208 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
209 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
210 case OCRDMA_MBX_STATUS_SRQ_ERROR:
211 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
212 err_num = -EINVAL;
213 break;
214
215 case OCRDMA_MBX_STATUS_PD_INUSE:
216 case OCRDMA_MBX_STATUS_QP_BOUND:
217 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
218 case OCRDMA_MBX_STATUS_MW_BOUND:
219 err_num = -EBUSY;
220 break;
221
222 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
223 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
224 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
225 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
226 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
230 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
231 err_num = -ENOBUFS;
232 break;
233
234 case OCRDMA_MBX_STATUS_FAILED:
235 switch (add_status) {
236 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
237 err_num = -EAGAIN;
238 break;
239 }
240 default:
241 err_num = -EFAULT;
242 }
243 return err_num;
244}
245
246static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
247{
248 int err_num = -EINVAL;
249
250 switch (cqe_status) {
251 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
252 err_num = -EPERM;
253 break;
254 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
255 err_num = -EINVAL;
256 break;
257 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
258 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
f11220ee 259 err_num = -EINVAL;
fe2caefc
PP		 260 break;
261 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
43a6b402 262 default:
f11220ee 263 err_num = -EINVAL;
fe2caefc
PP		 264 break;
265 }
266 return err_num;
267}
268
269void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
270 bool solicited, u16 cqe_popped)
271{
272 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
273
274 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
275 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
276
277 if (armed)
278 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
279 if (solicited)
280 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
281 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
282 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
283}
284
285static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
286{
287 u32 val = 0;
288
289 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
290 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
291 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
292}
293
294static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
295 bool arm, bool clear_int, u16 num_eqe)
296{
297 u32 val = 0;
298
299 val |= eq_id & OCRDMA_EQ_ID_MASK;
300 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
301 if (arm)
302 val |= (1 << OCRDMA_REARM_SHIFT);
303 if (clear_int)
304 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
305 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
306 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
308}
309
310static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
311 u8 opcode, u8 subsys, u32 cmd_len)
312{
313 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
314 cmd_hdr->timeout = 20; /* seconds */
315 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
316}
317
318static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
319{
320 struct ocrdma_mqe *mqe;
321
322 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
323 if (!mqe)
324 return NULL;
325 mqe->hdr.spcl_sge_cnt_emb |=
326 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
327 OCRDMA_MQE_HDR_EMB_MASK;
328 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
329
330 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
331 mqe->hdr.pyld_len);
332 return mqe;
333}
334
335static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
336{
337 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
338}
339
340static int ocrdma_alloc_q(struct ocrdma_dev *dev,
341 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
342{
343 memset(q, 0, sizeof(*q));
344 q->len = len;
345 q->entry_size = entry_size;
346 q->size = len * entry_size;
347 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
348 &q->dma, GFP_KERNEL);
349 if (!q->va)
350 return -ENOMEM;
351 memset(q->va, 0, q->size);
352 return 0;
353}
354
355static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
356 dma_addr_t host_pa, int hw_page_size)
357{
358 int i;
359
360 for (i = 0; i < cnt; i++) {
361 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
362 q_pa[i].hi = (u32) upper_32_bits(host_pa);
363 host_pa += hw_page_size;
364 }
365}
366
abe3afac
RD		 367static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
368 int queue_type)
fe2caefc
PP		 369{
370 u8 opcode = 0;
371 int status;
372 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
373
374 switch (queue_type) {
375 case QTYPE_MCCQ:
376 opcode = OCRDMA_CMD_DELETE_MQ;
377 break;
378 case QTYPE_CQ:
379 opcode = OCRDMA_CMD_DELETE_CQ;
380 break;
381 case QTYPE_EQ:
382 opcode = OCRDMA_CMD_DELETE_EQ;
383 break;
384 default:
385 BUG();
386 }
387 memset(cmd, 0, sizeof(*cmd));
388 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
389 cmd->id = q->id;
390
391 status = be_roce_mcc_cmd(dev->nic_info.netdev,
392 cmd, sizeof(*cmd), NULL, NULL);
393 if (!status)
394 q->created = false;
395 return status;
396}
397
398static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
399{
400 int status;
401 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
402 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
403
404 memset(cmd, 0, sizeof(*cmd));
405 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
406 sizeof(*cmd));
fe2caefc 407
c88bd03f 408 cmd->req.rsvd_version = 2;
fe2caefc
PP		 409 cmd->num_pages = 4;
410 cmd->valid = OCRDMA_CREATE_EQ_VALID;
411 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
412
413 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
414 PAGE_SIZE_4K);
415 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
416 NULL);
417 if (!status) {
418 eq->q.id = rsp->vector_eqid & 0xffff;
c88bd03f 419 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
fe2caefc
PP		 420 eq->q.created = true;
421 }
422 return status;
423}
424
425static int ocrdma_create_eq(struct ocrdma_dev *dev,
426 struct ocrdma_eq *eq, u16 q_len)
427{
428 int status;
429
430 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
431 sizeof(struct ocrdma_eqe));
432 if (status)
433 return status;
434
435 status = ocrdma_mbx_create_eq(dev, eq);
436 if (status)
437 goto mbx_err;
438 eq->dev = dev;
439 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
440
441 return 0;
442mbx_err:
443 ocrdma_free_q(dev, &eq->q);
444 return status;
445}
446
447static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
448{
449 int irq;
450
451 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
452 irq = dev->nic_info.pdev->irq;
453 else
454 irq = dev->nic_info.msix.vector_list[eq->vector];
455 return irq;
456}
457
458static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
459{
460 if (eq->q.created) {
461 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
fe2caefc
PP		 462 ocrdma_free_q(dev, &eq->q);
463 }
464}
465
466static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
467{
468 int irq;
469
470 /* disarm EQ so that interrupts are not generated
471 * during freeing and EQ delete is in progress.
472 */
473 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
474
475 irq = ocrdma_get_irq(dev, eq);
476 free_irq(irq, eq);
477 _ocrdma_destroy_eq(dev, eq);
478}
479
c88bd03f 480static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
fe2caefc
PP		 481{
482 int i;
483
fe2caefc 484 for (i = 0; i < dev->eq_cnt; i++)
c88bd03f 485 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
fe2caefc
PP		 486}
487
abe3afac
RD		 488static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
489 struct ocrdma_queue_info *cq,
490 struct ocrdma_queue_info *eq)
fe2caefc
PP		 491{
492 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
493 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
494 int status;
495
496 memset(cmd, 0, sizeof(*cmd));
497 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
498 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
499
1afc0454
NG		 500 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
501 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
502 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
503 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
504
fe2caefc 505 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454
NG		 506 cmd->eqn = eq->id;
507 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 508
1afc0454 509 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 510 cq->dma, PAGE_SIZE_4K);
511 status = be_roce_mcc_cmd(dev->nic_info.netdev,
512 cmd, sizeof(*cmd), NULL, NULL);
513 if (!status) {
1afc0454 514 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 515 cq->created = true;
516 }
517 return status;
518}
519
520static u32 ocrdma_encoded_q_len(int q_len)
521{
522 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
523
524 if (len_encoded == 16)
525 len_encoded = 0;
526 return len_encoded;
527}
528
529static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
530 struct ocrdma_queue_info *mq,
531 struct ocrdma_queue_info *cq)
532{
533 int num_pages, status;
534 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
535 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
536 struct ocrdma_pa *pa;
537
538 memset(cmd, 0, sizeof(*cmd));
539 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
540
b1d58b99
NG		 541 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
542 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
543 cmd->req.rsvd_version = 1;
544 cmd->cqid_pages = num_pages;
545 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
546 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
547 cmd->async_event_bitmap = Bit(20);
548 cmd->async_cqid_ringsize = cq->id;
549 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
550 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
551 cmd->valid = OCRDMA_CREATE_MQ_VALID;
552 pa = &cmd->pa[0];
553
fe2caefc
PP		 554 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
555 status = be_roce_mcc_cmd(dev->nic_info.netdev,
556 cmd, sizeof(*cmd), NULL, NULL);
557 if (!status) {
558 mq->id = rsp->id;
559 mq->created = true;
560 }
561 return status;
562}
563
564static int ocrdma_create_mq(struct ocrdma_dev *dev)
565{
566 int status;
567
568 /* Alloc completion queue for Mailbox queue */
569 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
570 sizeof(struct ocrdma_mcqe));
571 if (status)
572 goto alloc_err;
573
c88bd03f 574 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
fe2caefc
PP		 575 if (status)
576 goto mbx_cq_free;
577
578 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
579 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
580 mutex_init(&dev->mqe_ctx.lock);
581
582 /* Alloc Mailbox queue */
583 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
584 sizeof(struct ocrdma_mqe));
585 if (status)
586 goto mbx_cq_destroy;
587 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
588 if (status)
589 goto mbx_q_free;
590 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
591 return 0;
592
593mbx_q_free:
594 ocrdma_free_q(dev, &dev->mq.sq);
595mbx_cq_destroy:
596 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
597mbx_cq_free:
598 ocrdma_free_q(dev, &dev->mq.cq);
599alloc_err:
600 return status;
601}
602
603static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
604{
605 struct ocrdma_queue_info *mbxq, *cq;
606
607 /* mqe_ctx lock synchronizes with any other pending cmds. */
608 mutex_lock(&dev->mqe_ctx.lock);
609 mbxq = &dev->mq.sq;
610 if (mbxq->created) {
611 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
612 ocrdma_free_q(dev, mbxq);
613 }
614 mutex_unlock(&dev->mqe_ctx.lock);
615
616 cq = &dev->mq.cq;
617 if (cq->created) {
618 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
619 ocrdma_free_q(dev, cq);
620 }
621}
622
623static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
624 struct ocrdma_qp *qp)
625{
626 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
627 enum ib_qp_state old_ib_qps;
628
629 if (qp == NULL)
630 BUG();
057729cb 631 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 632}
633
634static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
635 struct ocrdma_ae_mcqe *cqe)
636{
637 struct ocrdma_qp *qp = NULL;
638 struct ocrdma_cq *cq = NULL;
e9db2953 639 struct ib_event ib_evt;
fe2caefc
PP		 640 int cq_event = 0;
641 int qp_event = 1;
642 int srq_event = 0;
643 int dev_event = 0;
644 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
645 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
646
647 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
648 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
649 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
650 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
651
e9db2953
RD		 652 ib_evt.device = &dev->ibdev;
653
fe2caefc
PP		 654 switch (type) {
655 case OCRDMA_CQ_ERROR:
656 ib_evt.element.cq = &cq->ibcq;
657 ib_evt.event = IB_EVENT_CQ_ERR;
658 cq_event = 1;
659 qp_event = 0;
660 break;
661 case OCRDMA_CQ_OVERRUN_ERROR:
662 ib_evt.element.cq = &cq->ibcq;
663 ib_evt.event = IB_EVENT_CQ_ERR;
664 break;
665 case OCRDMA_CQ_QPCAT_ERROR:
666 ib_evt.element.qp = &qp->ibqp;
667 ib_evt.event = IB_EVENT_QP_FATAL;
668 ocrdma_process_qpcat_error(dev, qp);
669 break;
670 case OCRDMA_QP_ACCESS_ERROR:
671 ib_evt.element.qp = &qp->ibqp;
672 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
673 break;
674 case OCRDMA_QP_COMM_EST_EVENT:
675 ib_evt.element.qp = &qp->ibqp;
676 ib_evt.event = IB_EVENT_COMM_EST;
677 break;
678 case OCRDMA_SQ_DRAINED_EVENT:
679 ib_evt.element.qp = &qp->ibqp;
680 ib_evt.event = IB_EVENT_SQ_DRAINED;
681 break;
682 case OCRDMA_DEVICE_FATAL_EVENT:
683 ib_evt.element.port_num = 1;
684 ib_evt.event = IB_EVENT_DEVICE_FATAL;
685 qp_event = 0;
686 dev_event = 1;
687 break;
688 case OCRDMA_SRQCAT_ERROR:
689 ib_evt.element.srq = &qp->srq->ibsrq;
690 ib_evt.event = IB_EVENT_SRQ_ERR;
691 srq_event = 1;
692 qp_event = 0;
693 break;
694 case OCRDMA_SRQ_LIMIT_EVENT:
695 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 696 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 697 srq_event = 1;
698 qp_event = 0;
699 break;
700 case OCRDMA_QP_LAST_WQE_EVENT:
701 ib_evt.element.qp = &qp->ibqp;
702 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
703 break;
704 default:
705 cq_event = 0;
706 qp_event = 0;
707 srq_event = 0;
708 dev_event = 0;
ef99c4c2 709 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 710 break;
711 }
712
713 if (qp_event) {
714 if (qp->ibqp.event_handler)
715 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
716 } else if (cq_event) {
717 if (cq->ibcq.event_handler)
718 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
719 } else if (srq_event) {
720 if (qp->srq->ibsrq.event_handler)
721 qp->srq->ibsrq.event_handler(&ib_evt,
722 qp->srq->ibsrq.
723 srq_context);
f99b1649 724 } else if (dev_event) {
fe2caefc 725 ib_dispatch_event(&ib_evt);
f99b1649 726 }
fe2caefc
PP		 727
728}
729
730static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
731{
732 /* async CQE processing */
733 struct ocrdma_ae_mcqe *cqe = ae_cqe;
734 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
735 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
736
737 if (evt_code == OCRDMA_ASYNC_EVE_CODE)
738 ocrdma_dispatch_ibevent(dev, cqe);
739 else
ef99c4c2
NG		 740 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
741 dev->id, evt_code);
fe2caefc
PP		 742}
743
744static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
745{
746 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
747 dev->mqe_ctx.cqe_status = (cqe->status &
748 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
749 dev->mqe_ctx.ext_status =
750 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
751 >> OCRDMA_MCQE_ESTATUS_SHIFT;
752 dev->mqe_ctx.cmd_done = true;
753 wake_up(&dev->mqe_ctx.cmd_wait);
754 } else
ef99c4c2
NG		 755 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
756 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 757}
758
759static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
760{
761 u16 cqe_popped = 0;
762 struct ocrdma_mcqe *cqe;
763
764 while (1) {
765 cqe = ocrdma_get_mcqe(dev);
766 if (cqe == NULL)
767 break;
768 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
769 cqe_popped += 1;
770 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
771 ocrdma_process_acqe(dev, cqe);
772 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
773 ocrdma_process_mcqe(dev, cqe);
774 else
ef99c4c2 775 pr_err("%s() cqe->compl is not set.\n", __func__);
fe2caefc
PP		 776 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
777 ocrdma_mcq_inc_tail(dev);
778 }
779 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
780 return 0;
781}
782
783static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
784 struct ocrdma_cq *cq)
785{
786 unsigned long flags;
787 struct ocrdma_qp *qp;
788 bool buddy_cq_found = false;
789 /* Go through list of QPs in error state which are using this CQ
790 * and invoke its callback handler to trigger CQE processing for
791 * error/flushed CQE. It is rare to find more than few entries in
792 * this list as most consumers stops after getting error CQE.
793 * List is traversed only once when a matching buddy cq found for a QP.
794 */
795 spin_lock_irqsave(&dev->flush_q_lock, flags);
796 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
797 if (qp->srq)
798 continue;
799 /* if wq and rq share the same cq, than comp_handler
800 * is already invoked.
801 */
802 if (qp->sq_cq == qp->rq_cq)
803 continue;
804 /* if completion came on sq, rq's cq is buddy cq.
805 * if completion came on rq, sq's cq is buddy cq.
806 */
807 if (qp->sq_cq == cq)
808 cq = qp->rq_cq;
809 else
810 cq = qp->sq_cq;
811 buddy_cq_found = true;
812 break;
813 }
814 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
815 if (buddy_cq_found == false)
816 return;
817 if (cq->ibcq.comp_handler) {
818 spin_lock_irqsave(&cq->comp_handler_lock, flags);
819 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
820 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
821 }
822}
823
824static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
825{
826 unsigned long flags;
827 struct ocrdma_cq *cq;
828
829 if (cq_idx >= OCRDMA_MAX_CQ)
830 BUG();
831
832 cq = dev->cq_tbl[cq_idx];
833 if (cq == NULL) {
ef99c4c2 834 pr_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
fe2caefc
PP		 835 return;
836 }
837 spin_lock_irqsave(&cq->cq_lock, flags);
838 cq->armed = false;
839 cq->solicited = false;
840 spin_unlock_irqrestore(&cq->cq_lock, flags);
841
842 ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
843
844 if (cq->ibcq.comp_handler) {
845 spin_lock_irqsave(&cq->comp_handler_lock, flags);
846 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
847 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
848 }
849 ocrdma_qp_buddy_cq_handler(dev, cq);
850}
851
852static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
853{
854 /* process the MQ-CQE. */
855 if (cq_id == dev->mq.cq.id)
856 ocrdma_mq_cq_handler(dev, cq_id);
857 else
858 ocrdma_qp_cq_handler(dev, cq_id);
859}
860
861static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
862{
863 struct ocrdma_eq *eq = handle;
864 struct ocrdma_dev *dev = eq->dev;
865 struct ocrdma_eqe eqe;
866 struct ocrdma_eqe *ptr;
867 u16 eqe_popped = 0;
868 u16 cq_id;
869 while (1) {
870 ptr = ocrdma_get_eqe(eq);
871 eqe = *ptr;
872 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
873 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
874 break;
875 eqe_popped += 1;
876 ptr->id_valid = 0;
877 /* check whether its CQE or not. */
878 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
879 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
880 ocrdma_cq_handler(dev, cq_id);
881 }
882 ocrdma_eq_inc_tail(eq);
883 }
884 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
885 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
886 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
887 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
888 return IRQ_HANDLED;
889}
890
891static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
892{
893 struct ocrdma_mqe *mqe;
894
895 dev->mqe_ctx.tag = dev->mq.sq.head;
896 dev->mqe_ctx.cmd_done = false;
897 mqe = ocrdma_get_mqe(dev);
898 cmd->hdr.tag_lo = dev->mq.sq.head;
899 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
900 /* make sure descriptor is written before ringing doorbell */
901 wmb();
902 ocrdma_mq_inc_head(dev);
903 ocrdma_ring_mq_db(dev);
904}
905
906static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
907{
908 long status;
909 /* 30 sec timeout */
910 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
911 (dev->mqe_ctx.cmd_done != false),
912 msecs_to_jiffies(30000));
913 if (status)
914 return 0;
915 else
916 return -1;
917}
918
919/* issue a mailbox command on the MQ */
920static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
921{
922 int status = 0;
923 u16 cqe_status, ext_status;
924 struct ocrdma_mqe *rsp;
925
926 mutex_lock(&dev->mqe_ctx.lock);
927 ocrdma_post_mqe(dev, mqe);
928 status = ocrdma_wait_mqe_cmpl(dev);
929 if (status)
930 goto mbx_err;
931 cqe_status = dev->mqe_ctx.cqe_status;
932 ext_status = dev->mqe_ctx.ext_status;
933 rsp = ocrdma_get_mqe_rsp(dev);
934 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
935 if (cqe_status || ext_status) {
f99b1649
NG		 936 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
937 __func__,
fe2caefc
PP		 938 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
939 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
940 status = ocrdma_get_mbx_cqe_errno(cqe_status);
941 goto mbx_err;
942 }
943 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
944 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
945mbx_err:
946 mutex_unlock(&dev->mqe_ctx.lock);
947 return status;
948}
949
950static void ocrdma_get_attr(struct ocrdma_dev *dev,
951 struct ocrdma_dev_attr *attr,
952 struct ocrdma_mbx_query_config *rsp)
953{
fe2caefc
PP		 954 attr->max_pd =
955 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
956 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
957 attr->max_qp =
958 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
959 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
960 attr->max_send_sge = ((rsp->max_write_send_sge &
961 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
962 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
963 attr->max_recv_sge = (rsp->max_write_send_sge &
964 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
965 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 966 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
967 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
968 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
45e86b33
NG		 969 attr->max_rdma_sge = (rsp->max_write_send_sge &
970 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
971 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
fe2caefc
PP		 972 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
973 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
974 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
7c33880c
NG		 975 attr->max_srq =
976 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
977 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
fe2caefc
PP		 978 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
979 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
980 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
981 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
982 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
983 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
984 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
985 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
986 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
987 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
988 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
989 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
990 attr->max_mr = rsp->max_mr;
991 attr->max_mr_size = ~0ull;
992 attr->max_fmr = 0;
993 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
994 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
995 attr->max_cqe = rsp->max_cq_cqes_per_cq &
996 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
997 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
998 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
999 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1000 OCRDMA_WQE_STRIDE;
1001 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1002 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1003 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1004 OCRDMA_WQE_STRIDE;
1005 attr->max_inline_data =
1006 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1007 sizeof(struct ocrdma_sge));
fe2caefc 1008 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
fe2caefc
PP		 1009 attr->ird = 1;
1010 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1011 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1012 }
1013 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1014 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1015 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1016 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1017}
1018
1019static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1020 struct ocrdma_fw_conf_rsp *conf)
1021{
1022 u32 fn_mode;
1023
1024 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1025 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1026 return -EINVAL;
1027 dev->base_eqid = conf->base_eqid;
1028 dev->max_eq = conf->max_eq;
1029 dev->attr.max_cq = OCRDMA_MAX_CQ - 1;
1030 return 0;
1031}
1032
1033/* can be issued only during init time. */
1034static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1035{
1036 int status = -ENOMEM;
1037 struct ocrdma_mqe *cmd;
1038 struct ocrdma_fw_ver_rsp *rsp;
1039
1040 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1041 if (!cmd)
1042 return -ENOMEM;
1043 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1044 OCRDMA_CMD_GET_FW_VER,
1045 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1046
1047 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1048 if (status)
1049 goto mbx_err;
1050 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1051 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1052 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1053 sizeof(rsp->running_ver));
1054 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1055mbx_err:
1056 kfree(cmd);
1057 return status;
1058}
1059
1060/* can be issued only during init time. */
1061static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1062{
1063 int status = -ENOMEM;
1064 struct ocrdma_mqe *cmd;
1065 struct ocrdma_fw_conf_rsp *rsp;
1066
1067 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1068 if (!cmd)
1069 return -ENOMEM;
1070 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1071 OCRDMA_CMD_GET_FW_CONFIG,
1072 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1073 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1074 if (status)
1075 goto mbx_err;
1076 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1077 status = ocrdma_check_fw_config(dev, rsp);
1078mbx_err:
1079 kfree(cmd);
1080 return status;
1081}
1082
1083static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1084{
1085 int status = -ENOMEM;
1086 struct ocrdma_mbx_query_config *rsp;
1087 struct ocrdma_mqe *cmd;
1088
1089 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1090 if (!cmd)
1091 return status;
1092 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1093 if (status)
1094 goto mbx_err;
1095 rsp = (struct ocrdma_mbx_query_config *)cmd;
1096 ocrdma_get_attr(dev, &dev->attr, rsp);
1097mbx_err:
1098 kfree(cmd);
1099 return status;
1100}
1101
1102int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1103{
1104 int status = -ENOMEM;
1105 struct ocrdma_alloc_pd *cmd;
1106 struct ocrdma_alloc_pd_rsp *rsp;
1107
1108 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1109 if (!cmd)
1110 return status;
1111 if (pd->dpp_enabled)
1112 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1113 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1114 if (status)
1115 goto mbx_err;
1116 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1117 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1118 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1119 pd->dpp_enabled = true;
1120 pd->dpp_page = rsp->dpp_page_pdid >>
1121 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1122 } else {
1123 pd->dpp_enabled = false;
1124 pd->num_dpp_qp = 0;
1125 }
1126mbx_err:
1127 kfree(cmd);
1128 return status;
1129}
1130
1131int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1132{
1133 int status = -ENOMEM;
1134 struct ocrdma_dealloc_pd *cmd;
1135
1136 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1137 if (!cmd)
1138 return status;
1139 cmd->id = pd->id;
1140 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1141 kfree(cmd);
1142 return status;
1143}
1144
1145static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1146 int *num_pages, int *page_size)
1147{
1148 int i;
1149 int mem_size;
1150
1151 *num_entries = roundup_pow_of_two(*num_entries);
1152 mem_size = *num_entries * entry_size;
1153 /* find the possible lowest possible multiplier */
1154 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1155 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1156 break;
1157 }
1158 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1159 return -EINVAL;
1160 mem_size = roundup(mem_size,
1161 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1162 *num_pages =
1163 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1164 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1165 *num_entries = mem_size / entry_size;
1166 return 0;
1167}
1168
1169static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1170{
1171 int i ;
1172 int status = 0;
1173 int max_ah;
1174 struct ocrdma_create_ah_tbl *cmd;
1175 struct ocrdma_create_ah_tbl_rsp *rsp;
1176 struct pci_dev *pdev = dev->nic_info.pdev;
1177 dma_addr_t pa;
1178 struct ocrdma_pbe *pbes;
1179
1180 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1181 if (!cmd)
1182 return status;
1183
1184 max_ah = OCRDMA_MAX_AH;
1185 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1186
1187 /* number of PBEs in PBL */
1188 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1189 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1190 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1191
1192 /* page size */
1193 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1194 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1195 break;
1196 }
1197 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1198 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1199
1200 /* ah_entry size */
1201 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1202 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1203 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1204
1205 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1206 &dev->av_tbl.pbl.pa,
1207 GFP_KERNEL);
1208 if (dev->av_tbl.pbl.va == NULL)
1209 goto mem_err;
1210
1211 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1212 &pa, GFP_KERNEL);
1213 if (dev->av_tbl.va == NULL)
1214 goto mem_err_ah;
1215 dev->av_tbl.pa = pa;
1216 dev->av_tbl.num_ah = max_ah;
1217 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1218
1219 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1220 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1221 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1222 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1223 pa += PAGE_SIZE;
1224 }
1225 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1226 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1227 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1228 if (status)
1229 goto mbx_err;
1230 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1231 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1232 kfree(cmd);
1233 return 0;
1234
1235mbx_err:
1236 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1237 dev->av_tbl.pa);
1238 dev->av_tbl.va = NULL;
1239mem_err_ah:
1240 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1241 dev->av_tbl.pbl.pa);
1242 dev->av_tbl.pbl.va = NULL;
1243 dev->av_tbl.size = 0;
1244mem_err:
1245 kfree(cmd);
1246 return status;
1247}
1248
1249static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1250{
1251 struct ocrdma_delete_ah_tbl *cmd;
1252 struct pci_dev *pdev = dev->nic_info.pdev;
1253
1254 if (dev->av_tbl.va == NULL)
1255 return;
1256
1257 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1258 if (!cmd)
1259 return;
1260 cmd->ahid = dev->av_tbl.ahid;
1261
1262 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1263 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1264 dev->av_tbl.pa);
1265 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1266 dev->av_tbl.pbl.pa);
1267 kfree(cmd);
1268}
1269
1270/* Multiple CQs uses the EQ. This routine returns least used
1271 * EQ to associate with CQ. This will distributes the interrupt
1272 * processing and CPU load to associated EQ, vector and so to that CPU.
1273 */
1274static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1275{
1276 int i, selected_eq = 0, cq_cnt = 0;
1277 u16 eq_id;
1278
1279 mutex_lock(&dev->dev_lock);
c88bd03f
NG		 1280 cq_cnt = dev->eq_tbl[0].cq_cnt;
1281 eq_id = dev->eq_tbl[0].q.id;
fe2caefc
PP		 1282 /* find the EQ which is has the least number of
1283 * CQs associated with it.
1284 */
1285 for (i = 0; i < dev->eq_cnt; i++) {
c88bd03f
NG		 1286 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1287 cq_cnt = dev->eq_tbl[i].cq_cnt;
1288 eq_id = dev->eq_tbl[i].q.id;
fe2caefc
PP		 1289 selected_eq = i;
1290 }
1291 }
c88bd03f 1292 dev->eq_tbl[selected_eq].cq_cnt += 1;
fe2caefc
PP		 1293 mutex_unlock(&dev->dev_lock);
1294 return eq_id;
1295}
1296
1297static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1298{
1299 int i;
1300
1301 mutex_lock(&dev->dev_lock);
1302 for (i = 0; i < dev->eq_cnt; i++) {
c88bd03f 1303 if (dev->eq_tbl[i].q.id != eq_id)
fe2caefc 1304 continue;
c88bd03f 1305 dev->eq_tbl[i].cq_cnt -= 1;
fe2caefc
PP		 1306 break;
1307 }
1308 mutex_unlock(&dev->dev_lock);
1309}
1310
1311int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1312 int entries, int dpp_cq)
1313{
1314 int status = -ENOMEM; int max_hw_cqe;
1315 struct pci_dev *pdev = dev->nic_info.pdev;
1316 struct ocrdma_create_cq *cmd;
1317 struct ocrdma_create_cq_rsp *rsp;
1318 u32 hw_pages, cqe_size, page_size, cqe_count;
1319
fe2caefc 1320 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1321 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1322 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1323 return -EINVAL;
1324 }
1325 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1326 return -EINVAL;
1327
1328 if (dpp_cq) {
1329 cq->max_hw_cqe = 1;
1330 max_hw_cqe = 1;
1331 cqe_size = OCRDMA_DPP_CQE_SIZE;
1332 hw_pages = 1;
1333 } else {
1334 cq->max_hw_cqe = dev->attr.max_cqe;
1335 max_hw_cqe = dev->attr.max_cqe;
1336 cqe_size = sizeof(struct ocrdma_cqe);
1337 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1338 }
1339
1340 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1341
1342 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1343 if (!cmd)
1344 return -ENOMEM;
1345 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1346 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1347 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1348 if (!cq->va) {
1349 status = -ENOMEM;
1350 goto mem_err;
1351 }
1352 memset(cq->va, 0, cq->len);
1353 page_size = cq->len / hw_pages;
1354 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1355 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1356 cmd->cmd.pgsz_pgcnt |= hw_pages;
1357 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1358
fe2caefc
PP		 1359 cq->eqn = ocrdma_bind_eq(dev);
1360 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
1361 cqe_count = cq->len / cqe_size;
f99b1649 1362 if (cqe_count > 1024) {
fe2caefc
PP		 1363 /* Set cnt to 3 to indicate more than 1024 cq entries */
1364 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1365 } else {
fe2caefc
PP		 1366 u8 count = 0;
1367 switch (cqe_count) {
1368 case 256:
1369 count = 0;
1370 break;
1371 case 512:
1372 count = 1;
1373 break;
1374 case 1024:
1375 count = 2;
1376 break;
1377 default:
1378 goto mbx_err;
1379 }
1380 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1381 }
1382 /* shared eq between all the consumer cqs. */
1383 cmd->cmd.eqn = cq->eqn;
1384 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1385 if (dpp_cq)
1386 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1387 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1388 cq->phase_change = false;
1389 cmd->cmd.cqe_count = (cq->len / cqe_size);
1390 } else {
1391 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1392 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1393 cq->phase_change = true;
1394 }
1395
1396 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1397 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1398 if (status)
1399 goto mbx_err;
1400
1401 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1402 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1403 kfree(cmd);
1404 return 0;
1405mbx_err:
1406 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1407 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1408mem_err:
1409 kfree(cmd);
1410 return status;
1411}
1412
1413int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1414{
1415 int status = -ENOMEM;
1416 struct ocrdma_destroy_cq *cmd;
1417
1418 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1419 if (!cmd)
1420 return status;
1421 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1422 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1423
1424 cmd->bypass_flush_qid |=
1425 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1426 OCRDMA_DESTROY_CQ_QID_MASK;
1427
1428 ocrdma_unbind_eq(dev, cq->eqn);
1429 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1430 if (status)
1431 goto mbx_err;
1432 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1433mbx_err:
1434 kfree(cmd);
1435 return status;
1436}
1437
1438int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1439 u32 pdid, int addr_check)
1440{
1441 int status = -ENOMEM;
1442 struct ocrdma_alloc_lkey *cmd;
1443 struct ocrdma_alloc_lkey_rsp *rsp;
1444
1445 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1446 if (!cmd)
1447 return status;
1448 cmd->pdid = pdid;
1449 cmd->pbl_sz_flags |= addr_check;
1450 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1451 cmd->pbl_sz_flags |=
1452 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1453 cmd->pbl_sz_flags |=
1454 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1455 cmd->pbl_sz_flags |=
1456 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1457 cmd->pbl_sz_flags |=
1458 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1459 cmd->pbl_sz_flags |=
1460 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1461
1462 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1463 if (status)
1464 goto mbx_err;
1465 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1466 hwmr->lkey = rsp->lrkey;
1467mbx_err:
1468 kfree(cmd);
1469 return status;
1470}
1471
1472int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1473{
1474 int status = -ENOMEM;
1475 struct ocrdma_dealloc_lkey *cmd;
1476
1477 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1478 if (!cmd)
1479 return -ENOMEM;
1480 cmd->lkey = lkey;
1481 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1482 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1483 if (status)
1484 goto mbx_err;
1485mbx_err:
1486 kfree(cmd);
1487 return status;
1488}
1489
1490static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1491 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1492{
1493 int status = -ENOMEM;
1494 int i;
1495 struct ocrdma_reg_nsmr *cmd;
1496 struct ocrdma_reg_nsmr_rsp *rsp;
1497
1498 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1499 if (!cmd)
1500 return -ENOMEM;
1501 cmd->num_pbl_pdid =
1502 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
2b51a9b9 1503 cmd->fr_mr = hwmr->fr_mr;
fe2caefc
PP		 1504
1505 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1506 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1507 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1508 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1509 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1510 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1511 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1512 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1513 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1514 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1515 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1516
1517 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1518 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1519 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1520 cmd->totlen_low = hwmr->len;
1521 cmd->totlen_high = upper_32_bits(hwmr->len);
1522 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1523 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1524 cmd->va_loaddr = (u32) hwmr->va;
1525 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1526
1527 for (i = 0; i < pbl_cnt; i++) {
1528 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1529 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1530 }
1531 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1532 if (status)
1533 goto mbx_err;
1534 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1535 hwmr->lkey = rsp->lrkey;
1536mbx_err:
1537 kfree(cmd);
1538 return status;
1539}
1540
1541static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1542 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1543 u32 pbl_offset, u32 last)
1544{
1545 int status = -ENOMEM;
1546 int i;
1547 struct ocrdma_reg_nsmr_cont *cmd;
1548
1549 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1550 if (!cmd)
1551 return -ENOMEM;
1552 cmd->lrkey = hwmr->lkey;
1553 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1554 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1555 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1556
1557 for (i = 0; i < pbl_cnt; i++) {
1558 cmd->pbl[i].lo =
1559 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1560 cmd->pbl[i].hi =
1561 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1562 }
1563 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1564 if (status)
1565 goto mbx_err;
1566mbx_err:
1567 kfree(cmd);
1568 return status;
1569}
1570
1571int ocrdma_reg_mr(struct ocrdma_dev *dev,
1572 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1573{
1574 int status;
1575 u32 last = 0;
1576 u32 cur_pbl_cnt, pbl_offset;
1577 u32 pending_pbl_cnt = hwmr->num_pbls;
1578
1579 pbl_offset = 0;
1580 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1581 if (cur_pbl_cnt == pending_pbl_cnt)
1582 last = 1;
1583
1584 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1585 cur_pbl_cnt, hwmr->pbe_size, last);
1586 if (status) {
ef99c4c2 1587 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 1588 return status;
1589 }
1590 /* if there is no more pbls to register then exit. */
1591 if (last)
1592 return 0;
1593
1594 while (!last) {
1595 pbl_offset += cur_pbl_cnt;
1596 pending_pbl_cnt -= cur_pbl_cnt;
1597 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1598 /* if we reach the end of the pbls, then need to set the last
1599 * bit, indicating no more pbls to register for this memory key.
1600 */
1601 if (cur_pbl_cnt == pending_pbl_cnt)
1602 last = 1;
1603
1604 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1605 pbl_offset, last);
1606 if (status)
1607 break;
1608 }
1609 if (status)
ef99c4c2 1610 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 1611
1612 return status;
1613}
1614
1615bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1616{
1617 struct ocrdma_qp *tmp;
1618 bool found = false;
1619 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1620 if (qp == tmp) {
1621 found = true;
1622 break;
1623 }
1624 }
1625 return found;
1626}
1627
1628bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1629{
1630 struct ocrdma_qp *tmp;
1631 bool found = false;
1632 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1633 if (qp == tmp) {
1634 found = true;
1635 break;
1636 }
1637 }
1638 return found;
1639}
1640
1641void ocrdma_flush_qp(struct ocrdma_qp *qp)
1642{
1643 bool found;
1644 unsigned long flags;
1645
1646 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1647 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1648 if (!found)
1649 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1650 if (!qp->srq) {
1651 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1652 if (!found)
1653 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1654 }
1655 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1656}
1657
f11220ee
NG		 1658static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1659{
1660 qp->sq.head = 0;
1661 qp->sq.tail = 0;
1662 qp->rq.head = 0;
1663 qp->rq.tail = 0;
1664}
1665
057729cb
NG		 1666int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1667 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 1668{
1669 unsigned long flags;
1670 int status = 0;
1671 enum ocrdma_qp_state new_state;
1672 new_state = get_ocrdma_qp_state(new_ib_state);
1673
1674 /* sync with wqe and rqe posting */
1675 spin_lock_irqsave(&qp->q_lock, flags);
1676
1677 if (old_ib_state)
1678 *old_ib_state = get_ibqp_state(qp->state);
1679 if (new_state == qp->state) {
1680 spin_unlock_irqrestore(&qp->q_lock, flags);
1681 return 1;
1682 }
1683
057729cb 1684
f11220ee
NG		 1685 if (new_state == OCRDMA_QPS_INIT) {
1686 ocrdma_init_hwq_ptr(qp);
1687 ocrdma_del_flush_qp(qp);
1688 } else if (new_state == OCRDMA_QPS_ERR) {
057729cb 1689 ocrdma_flush_qp(qp);
f11220ee 1690 }
057729cb
NG		 1691
1692 qp->state = new_state;
fe2caefc
PP		 1693
1694 spin_unlock_irqrestore(&qp->q_lock, flags);
1695 return status;
1696}
1697
1698static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1699{
1700 u32 flags = 0;
1701 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1702 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1703 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1704 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1705 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1706 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1707 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1708 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1709 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1710 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1711 return flags;
1712}
1713
1714static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1715 struct ib_qp_init_attr *attrs,
1716 struct ocrdma_qp *qp)
1717{
1718 int status;
1719 u32 len, hw_pages, hw_page_size;
1720 dma_addr_t pa;
1721 struct ocrdma_dev *dev = qp->dev;
1722 struct pci_dev *pdev = dev->nic_info.pdev;
1723 u32 max_wqe_allocated;
1724 u32 max_sges = attrs->cap.max_send_sge;
1725
43a6b402
NG		 1726 /* QP1 may exceed 127 */
1727 max_wqe_allocated = min_t(int, attrs->cap.max_send_wr + 1,
1728 dev->attr.max_wqe);
fe2caefc
PP		 1729
1730 status = ocrdma_build_q_conf(&max_wqe_allocated,
1731 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1732 if (status) {
ef99c4c2
NG		 1733 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1734 max_wqe_allocated);
fe2caefc
PP		 1735 return -EINVAL;
1736 }
1737 qp->sq.max_cnt = max_wqe_allocated;
1738 len = (hw_pages * hw_page_size);
1739
1740 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1741 if (!qp->sq.va)
1742 return -EINVAL;
1743 memset(qp->sq.va, 0, len);
1744 qp->sq.len = len;
1745 qp->sq.pa = pa;
1746 qp->sq.entry_size = dev->attr.wqe_size;
1747 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1748
1749 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1750 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1751 cmd->num_wq_rq_pages |= (hw_pages <<
1752 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1753 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1754 cmd->max_sge_send_write |= (max_sges <<
1755 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1756 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1757 cmd->max_sge_send_write |= (max_sges <<
1758 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1759 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1760 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1761 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1762 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1763 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1764 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1765 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1766 return 0;
1767}
1768
1769static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1770 struct ib_qp_init_attr *attrs,
1771 struct ocrdma_qp *qp)
1772{
1773 int status;
1774 u32 len, hw_pages, hw_page_size;
1775 dma_addr_t pa = 0;
1776 struct ocrdma_dev *dev = qp->dev;
1777 struct pci_dev *pdev = dev->nic_info.pdev;
1778 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1779
1780 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1781 &hw_pages, &hw_page_size);
1782 if (status) {
ef99c4c2
NG		 1783 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1784 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 1785 return status;
1786 }
1787 qp->rq.max_cnt = max_rqe_allocated;
1788 len = (hw_pages * hw_page_size);
1789
1790 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1791 if (!qp->rq.va)
c94e15c5 1792 return -ENOMEM;
fe2caefc
PP		 1793 memset(qp->rq.va, 0, len);
1794 qp->rq.pa = pa;
1795 qp->rq.len = len;
1796 qp->rq.entry_size = dev->attr.rqe_size;
1797
1798 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1799 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1800 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1801 cmd->num_wq_rq_pages |=
1802 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1803 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1804 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1805 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1806 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1807 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1808 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1809 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1810 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1811 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1812 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1813 return 0;
1814}
1815
1816static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1817 struct ocrdma_pd *pd,
1818 struct ocrdma_qp *qp,
1819 u8 enable_dpp_cq, u16 dpp_cq_id)
1820{
1821 pd->num_dpp_qp--;
1822 qp->dpp_enabled = true;
1823 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1824 if (!enable_dpp_cq)
1825 return;
1826 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1827 cmd->dpp_credits_cqid = dpp_cq_id;
1828 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1829 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1830}
1831
1832static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1833 struct ocrdma_qp *qp)
1834{
1835 struct ocrdma_dev *dev = qp->dev;
1836 struct pci_dev *pdev = dev->nic_info.pdev;
1837 dma_addr_t pa = 0;
1838 int ird_page_size = dev->attr.ird_page_size;
1839 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
43a6b402
NG		 1840 struct ocrdma_hdr_wqe *rqe;
1841 int i = 0;
fe2caefc
PP		 1842
1843 if (dev->attr.ird == 0)
1844 return 0;
1845
1846 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1847 &pa, GFP_KERNEL);
1848 if (!qp->ird_q_va)
1849 return -ENOMEM;
1850 memset(qp->ird_q_va, 0, ird_q_len);
1851 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1852 pa, ird_page_size);
43a6b402
NG		 1853 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
1854 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
1855 (i * dev->attr.rqe_size));
1856 rqe->cw = 0;
1857 rqe->cw |= 2;
1858 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
1859 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
1860 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
1861 }
fe2caefc
PP		 1862 return 0;
1863}
1864
1865static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1866 struct ocrdma_qp *qp,
1867 struct ib_qp_init_attr *attrs,
1868 u16 *dpp_offset, u16 *dpp_credit_lmt)
1869{
1870 u32 max_wqe_allocated, max_rqe_allocated;
1871 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1872 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1873 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1874 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1875 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1876 qp->dpp_enabled = false;
1877 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1878 qp->dpp_enabled = true;
1879 *dpp_credit_lmt = (rsp->dpp_response &
1880 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1881 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1882 *dpp_offset = (rsp->dpp_response &
1883 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1884 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1885 }
1886 max_wqe_allocated =
1887 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1888 max_wqe_allocated = 1 << max_wqe_allocated;
1889 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1890
fe2caefc
PP		 1891 qp->sq.max_cnt = max_wqe_allocated;
1892 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1893
1894 if (!attrs->srq) {
1895 qp->rq.max_cnt = max_rqe_allocated;
1896 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 1897 }
1898}
1899
1900int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1901 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1902 u16 *dpp_credit_lmt)
1903{
1904 int status = -ENOMEM;
1905 u32 flags = 0;
1906 struct ocrdma_dev *dev = qp->dev;
1907 struct ocrdma_pd *pd = qp->pd;
1908 struct pci_dev *pdev = dev->nic_info.pdev;
1909 struct ocrdma_cq *cq;
1910 struct ocrdma_create_qp_req *cmd;
1911 struct ocrdma_create_qp_rsp *rsp;
1912 int qptype;
1913
1914 switch (attrs->qp_type) {
1915 case IB_QPT_GSI:
1916 qptype = OCRDMA_QPT_GSI;
1917 break;
1918 case IB_QPT_RC:
1919 qptype = OCRDMA_QPT_RC;
1920 break;
1921 case IB_QPT_UD:
1922 qptype = OCRDMA_QPT_UD;
1923 break;
1924 default:
1925 return -EINVAL;
1926 };
1927
1928 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
1929 if (!cmd)
1930 return status;
1931 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
1932 OCRDMA_CREATE_QP_REQ_QPT_MASK;
1933 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
1934 if (status)
1935 goto sq_err;
1936
1937 if (attrs->srq) {
1938 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
1939 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
1940 cmd->rq_addr[0].lo = srq->id;
1941 qp->srq = srq;
1942 } else {
1943 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
1944 if (status)
1945 goto rq_err;
1946 }
1947
1948 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
1949 if (status)
1950 goto mbx_err;
1951
1952 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
1953 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
1954
1955 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
1956
1957 cmd->max_sge_recv_flags |= flags;
1958 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
1959 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
1960 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
1961 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
1962 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
1963 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
1964 cq = get_ocrdma_cq(attrs->send_cq);
1965 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
1966 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
1967 qp->sq_cq = cq;
1968 cq = get_ocrdma_cq(attrs->recv_cq);
1969 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
1970 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
1971 qp->rq_cq = cq;
1972
1973 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
f99b1649 1974 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
fe2caefc
PP		 1975 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
1976 dpp_cq_id);
f99b1649 1977 }
fe2caefc
PP		 1978
1979 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1980 if (status)
1981 goto mbx_err;
1982 rsp = (struct ocrdma_create_qp_rsp *)cmd;
1983 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
1984 qp->state = OCRDMA_QPS_RST;
1985 kfree(cmd);
1986 return 0;
1987mbx_err:
1988 if (qp->rq.va)
1989 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
1990rq_err:
ef99c4c2 1991 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 1992 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
1993sq_err:
ef99c4c2 1994 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 1995 kfree(cmd);
1996 return status;
1997}
1998
1999int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2000 struct ocrdma_qp_params *param)
2001{
2002 int status = -ENOMEM;
2003 struct ocrdma_query_qp *cmd;
2004 struct ocrdma_query_qp_rsp *rsp;
2005
2006 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2007 if (!cmd)
2008 return status;
2009 cmd->qp_id = qp->id;
2010 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2011 if (status)
2012 goto mbx_err;
2013 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2014 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2015mbx_err:
2016 kfree(cmd);
2017 return status;
2018}
2019
2020int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid,
2021 u8 *mac_addr)
2022{
2023 struct in6_addr in6;
2024
2025 memcpy(&in6, dgid, sizeof in6);
f99b1649 2026 if (rdma_is_multicast_addr(&in6)) {
fe2caefc 2027 rdma_get_mcast_mac(&in6, mac_addr);
f99b1649 2028 } else if (rdma_link_local_addr(&in6)) {
fe2caefc 2029 rdma_get_ll_mac(&in6, mac_addr);
f99b1649 2030 } else {
ef99c4c2 2031 pr_err("%s() fail to resolve mac_addr.\n", __func__);
fe2caefc
PP		 2032 return -EINVAL;
2033 }
2034 return 0;
2035}
2036
f99b1649 2037static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc
PP		 2038 struct ocrdma_modify_qp *cmd,
2039 struct ib_qp_attr *attrs)
2040{
f99b1649 2041 int status;
fe2caefc 2042 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2043 union ib_gid sgid, zgid;
fe2caefc
PP		 2044 u32 vlan_id;
2045 u8 mac_addr[6];
9c58726b 2046
fe2caefc 2047 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
f99b1649 2048 return -EINVAL;
fe2caefc
PP		 2049 cmd->params.tclass_sq_psn |=
2050 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2051 cmd->params.rnt_rc_sl_fl |=
2052 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2b51a9b9 2053 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
fe2caefc
PP		 2054 cmd->params.hop_lmt_rq_psn |=
2055 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2056 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2057 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2058 sizeof(cmd->params.dgid));
f99b1649 2059 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
fe2caefc 2060 ah_attr->grh.sgid_index, &sgid);
f99b1649
NG		 2061 if (status)
2062 return status;
9c58726b
NG		 2063
2064 memset(&zgid, 0, sizeof(zgid));
2065 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2066 return -EINVAL;
2067
fe2caefc
PP		 2068 qp->sgid_idx = ah_attr->grh.sgid_index;
2069 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2070 ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]);
2071 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2072 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2073 /* convert them to LE format. */
2074 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2075 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2076 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2077 vlan_id = rdma_get_vlan_id(&sgid);
2078 if (vlan_id && (vlan_id < 0x1000)) {
2079 cmd->params.vlan_dmac_b4_to_b5 |=
2080 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2081 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2082 }
f99b1649 2083 return 0;
fe2caefc
PP		 2084}
2085
2086static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2087 struct ocrdma_modify_qp *cmd,
2088 struct ib_qp_attr *attrs, int attr_mask,
2089 enum ib_qp_state old_qps)
2090{
2091 int status = 0;
fe2caefc
PP		 2092
2093 if (attr_mask & IB_QP_PKEY_INDEX) {
2094 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2095 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2096 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2097 }
2098 if (attr_mask & IB_QP_QKEY) {
2099 qp->qkey = attrs->qkey;
2100 cmd->params.qkey = attrs->qkey;
2101 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2102 }
f99b1649
NG		 2103 if (attr_mask & IB_QP_AV) {
2104 status = ocrdma_set_av_params(qp, cmd, attrs);
2105 if (status)
2106 return status;
2107 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc
PP		 2108 /* set the default mac address for UD, GSI QPs */
2109 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2110 (qp->dev->nic_info.mac_addr[1] << 8) |
2111 (qp->dev->nic_info.mac_addr[2] << 16) |
2112 (qp->dev->nic_info.mac_addr[3] << 24);
2113 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2114 (qp->dev->nic_info.mac_addr[5] << 8);
2115 }
2116 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2117 attrs->en_sqd_async_notify) {
2118 cmd->params.max_sge_recv_flags |=
2119 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2120 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2121 }
2122 if (attr_mask & IB_QP_DEST_QPN) {
2123 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2124 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2125 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2126 }
2127 if (attr_mask & IB_QP_PATH_MTU) {
d3cb6c0b
NG		 2128 if (attrs->path_mtu < IB_MTU_256 ||
2129 attrs->path_mtu > IB_MTU_4096) {
fe2caefc
PP		 2130 status = -EINVAL;
2131 goto pmtu_err;
2132 }
2133 cmd->params.path_mtu_pkey_indx |=
2134 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2135 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2136 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2137 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2138 }
2139 if (attr_mask & IB_QP_TIMEOUT) {
2140 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2141 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2142 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2143 }
2144 if (attr_mask & IB_QP_RETRY_CNT) {
2145 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2146 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2147 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2148 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2149 }
2150 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2151 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2152 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2153 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2154 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2155 }
2156 if (attr_mask & IB_QP_RNR_RETRY) {
2157 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2158 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2159 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2160 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2161 }
2162 if (attr_mask & IB_QP_SQ_PSN) {
2163 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2164 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2165 }
2166 if (attr_mask & IB_QP_RQ_PSN) {
2167 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2168 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2169 }
2170 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2171 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2172 status = -EINVAL;
2173 goto pmtu_err;
2174 }
2175 qp->max_ord = attrs->max_rd_atomic;
2176 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2177 }
2178 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2179 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2180 status = -EINVAL;
2181 goto pmtu_err;
2182 }
2183 qp->max_ird = attrs->max_dest_rd_atomic;
2184 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2185 }
2186 cmd->params.max_ord_ird = (qp->max_ord <<
2187 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2188 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2189pmtu_err:
2190 return status;
2191}
2192
2193int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2194 struct ib_qp_attr *attrs, int attr_mask,
2195 enum ib_qp_state old_qps)
2196{
2197 int status = -ENOMEM;
2198 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2199
2200 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2201 if (!cmd)
2202 return status;
2203
2204 cmd->params.id = qp->id;
2205 cmd->flags = 0;
2206 if (attr_mask & IB_QP_STATE) {
2207 cmd->params.max_sge_recv_flags |=
2208 (get_ocrdma_qp_state(attrs->qp_state) <<
2209 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2210 OCRDMA_QP_PARAMS_STATE_MASK;
2211 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2212 } else {
fe2caefc
PP		 2213 cmd->params.max_sge_recv_flags |=
2214 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2215 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2216 }
2217
fe2caefc
PP		 2218 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps);
2219 if (status)
2220 goto mbx_err;
2221 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2222 if (status)
2223 goto mbx_err;
c592c423 2224
fe2caefc
PP		 2225mbx_err:
2226 kfree(cmd);
2227 return status;
2228}
2229
2230int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2231{
2232 int status = -ENOMEM;
2233 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2234 struct pci_dev *pdev = dev->nic_info.pdev;
2235
2236 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2237 if (!cmd)
2238 return status;
2239 cmd->qp_id = qp->id;
2240 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2241 if (status)
2242 goto mbx_err;
c592c423 2243
fe2caefc
PP		 2244mbx_err:
2245 kfree(cmd);
2246 if (qp->sq.va)
2247 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2248 if (!qp->srq && qp->rq.va)
2249 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2250 if (qp->dpp_enabled)
2251 qp->pd->num_dpp_qp++;
2252 return status;
2253}
2254
1afc0454 2255int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2256 struct ib_srq_init_attr *srq_attr,
2257 struct ocrdma_pd *pd)
2258{
2259 int status = -ENOMEM;
2260 int hw_pages, hw_page_size;
2261 int len;
2262 struct ocrdma_create_srq_rsp *rsp;
2263 struct ocrdma_create_srq *cmd;
2264 dma_addr_t pa;
fe2caefc
PP		 2265 struct pci_dev *pdev = dev->nic_info.pdev;
2266 u32 max_rqe_allocated;
2267
2268 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2269 if (!cmd)
2270 return status;
2271
2272 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2273 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2274 status = ocrdma_build_q_conf(&max_rqe_allocated,
2275 dev->attr.rqe_size,
2276 &hw_pages, &hw_page_size);
2277 if (status) {
ef99c4c2
NG		 2278 pr_err("%s() req. max_wr=0x%x\n", __func__,
2279 srq_attr->attr.max_wr);
fe2caefc
PP		 2280 status = -EINVAL;
2281 goto ret;
2282 }
2283 len = hw_pages * hw_page_size;
2284 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2285 if (!srq->rq.va) {
2286 status = -ENOMEM;
2287 goto ret;
2288 }
2289 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2290
2291 srq->rq.entry_size = dev->attr.rqe_size;
2292 srq->rq.pa = pa;
2293 srq->rq.len = len;
2294 srq->rq.max_cnt = max_rqe_allocated;
2295
2296 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2297 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2298 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2299
2300 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2301 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2302 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2303 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2304 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2305 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2306
2307 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2308 if (status)
2309 goto mbx_err;
2310 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2311 srq->id = rsp->id;
2312 srq->rq.dbid = rsp->id;
2313 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2314 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2315 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2316 max_rqe_allocated = (1 << max_rqe_allocated);
2317 srq->rq.max_cnt = max_rqe_allocated;
2318 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2319 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2320 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2321 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2322 goto ret;
2323mbx_err:
2324 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2325ret:
2326 kfree(cmd);
2327 return status;
2328}
2329
2330int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2331{
2332 int status = -ENOMEM;
2333 struct ocrdma_modify_srq *cmd;
f11220ee
NG		 2334 struct ocrdma_pd *pd = srq->pd;
2335 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
1afc0454 2336
fe2caefc
PP		 2337 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2338 if (!cmd)
2339 return status;
2340 cmd->id = srq->id;
2341 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2342 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2343 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2344 kfree(cmd);
2345 return status;
2346}
2347
2348int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2349{
2350 int status = -ENOMEM;
2351 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2352 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2353
fe2caefc
PP		 2354 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2355 if (!cmd)
2356 return status;
2357 cmd->id = srq->rq.dbid;
1afc0454 2358 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2359 if (status == 0) {
2360 struct ocrdma_query_srq_rsp *rsp =
2361 (struct ocrdma_query_srq_rsp *)cmd;
2362 srq_attr->max_sge =
2363 rsp->srq_lmt_max_sge &
2364 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2365 srq_attr->max_wr =
2366 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2367 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2368 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2369 }
2370 kfree(cmd);
2371 return status;
2372}
2373
2374int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2375{
2376 int status = -ENOMEM;
2377 struct ocrdma_destroy_srq *cmd;
2378 struct pci_dev *pdev = dev->nic_info.pdev;
2379 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2380 if (!cmd)
2381 return status;
2382 cmd->id = srq->id;
1afc0454 2383 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2384 if (srq->rq.va)
2385 dma_free_coherent(&pdev->dev, srq->rq.len,
2386 srq->rq.va, srq->rq.pa);
2387 kfree(cmd);
2388 return status;
2389}
2390
2391int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2392{
2393 int i;
2394 int status = -EINVAL;
2395 struct ocrdma_av *av;
2396 unsigned long flags;
2397
2398 av = dev->av_tbl.va;
2399 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2400 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2401 if (av->valid == 0) {
2402 av->valid = OCRDMA_AV_VALID;
2403 ah->av = av;
2404 ah->id = i;
2405 status = 0;
2406 break;
2407 }
2408 av++;
2409 }
2410 if (i == dev->av_tbl.num_ah)
2411 status = -EAGAIN;
2412 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2413 return status;
2414}
2415
2416int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2417{
2418 unsigned long flags;
2419 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2420 ah->av->valid = 0;
2421 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2422 return 0;
2423}
2424
c88bd03f 2425static int ocrdma_create_eqs(struct ocrdma_dev *dev)
fe2caefc 2426{
da496438 2427 int num_eq, i, status = 0;
fe2caefc
PP		 2428 int irq;
2429 unsigned long flags = 0;
2430
2431 num_eq = dev->nic_info.msix.num_vectors -
2432 dev->nic_info.msix.start_vector;
2433 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2434 num_eq = 1;
2435 flags = IRQF_SHARED;
f99b1649 2436 } else {
fe2caefc 2437 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 2438 }
2439
c88bd03f
NG		 2440 if (!num_eq)
2441 return -EINVAL;
2442
2443 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2444 if (!dev->eq_tbl)
fe2caefc
PP		 2445 return -ENOMEM;
2446
2447 for (i = 0; i < num_eq; i++) {
c88bd03f 2448 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
fe2caefc
PP		 2449 OCRDMA_EQ_LEN);
2450 if (status) {
2451 status = -EINVAL;
2452 break;
2453 }
c88bd03f 2454 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
fe2caefc 2455 dev->id, i);
c88bd03f 2456 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
fe2caefc 2457 status = request_irq(irq, ocrdma_irq_handler, flags,
c88bd03f
NG		 2458 dev->eq_tbl[i].irq_name,
2459 &dev->eq_tbl[i]);
2460 if (status)
2461 goto done;
fe2caefc
PP		 2462 dev->eq_cnt += 1;
2463 }
2464 /* one eq is sufficient for data path to work */
c88bd03f
NG		 2465 return 0;
2466done:
2467 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2468 return status;
2469}
2470
2471int ocrdma_init_hw(struct ocrdma_dev *dev)
2472{
2473 int status;
c88bd03f
NG		 2474
2475 /* create the eqs */
2476 status = ocrdma_create_eqs(dev);
fe2caefc
PP		 2477 if (status)
2478 goto qpeq_err;
2479 status = ocrdma_create_mq(dev);
2480 if (status)
2481 goto mq_err;
2482 status = ocrdma_mbx_query_fw_config(dev);
2483 if (status)
2484 goto conf_err;
2485 status = ocrdma_mbx_query_dev(dev);
2486 if (status)
2487 goto conf_err;
2488 status = ocrdma_mbx_query_fw_ver(dev);
2489 if (status)
2490 goto conf_err;
2491 status = ocrdma_mbx_create_ah_tbl(dev);
2492 if (status)
2493 goto conf_err;
2494 return 0;
2495
2496conf_err:
2497 ocrdma_destroy_mq(dev);
2498mq_err:
c88bd03f 2499 ocrdma_destroy_eqs(dev);
fe2caefc 2500qpeq_err:
ef99c4c2 2501 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2502 return status;
2503}
2504
2505void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2506{
2507 ocrdma_mbx_delete_ah_tbl(dev);
2508
c88bd03f
NG		 2509 /* cleanup the eqs */
2510 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2511
2512 /* cleanup the control path */
2513 ocrdma_destroy_mq(dev);
fe2caefc 2514}
Linux kernel - Deliverables
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