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RDMA/ocrdma: Do proper cleanup even if FW is in error state
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
fe2caefc
PP		 35
36#include "ocrdma.h"
37#include "ocrdma_hw.h"
38#include "ocrdma_verbs.h"
39#include "ocrdma_ah.h"
40
41enum mbx_status {
42 OCRDMA_MBX_STATUS_FAILED = 1,
43 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
44 OCRDMA_MBX_STATUS_OOR = 100,
45 OCRDMA_MBX_STATUS_INVALID_PD = 101,
46 OCRDMA_MBX_STATUS_PD_INUSE = 102,
47 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
48 OCRDMA_MBX_STATUS_INVALID_QP = 104,
49 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
50 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
51 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
52 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
53 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
54 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
55 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
56 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
57 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
58 OCRDMA_MBX_STATUS_MW_BOUND = 114,
59 OCRDMA_MBX_STATUS_INVALID_VA = 115,
60 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
61 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
62 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
63 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
64 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
65 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
66 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
67 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
68 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
69 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
70 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
71 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
72 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
73 OCRDMA_MBX_STATUS_QP_BOUND = 130,
74 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
75 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
76 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
77 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
78 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
80};
81
82enum additional_status {
83 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
84};
85
86enum cqe_status {
87 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
88 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
89 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
90 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
91 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
92};
93
94static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
95{
f99b1649 96 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 97}
98
99static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
100{
101 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
102}
103
104static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
105{
106 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 107 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 108
109 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
110 return NULL;
111 return cqe;
112}
113
114static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
115{
116 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
117}
118
119static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
120{
f99b1649 121 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 122}
123
124static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
125{
126 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 127}
128
129static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
130{
f99b1649 131 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 132}
133
134enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
135{
136 switch (qps) {
137 case OCRDMA_QPS_RST:
138 return IB_QPS_RESET;
139 case OCRDMA_QPS_INIT:
140 return IB_QPS_INIT;
141 case OCRDMA_QPS_RTR:
142 return IB_QPS_RTR;
143 case OCRDMA_QPS_RTS:
144 return IB_QPS_RTS;
145 case OCRDMA_QPS_SQD:
146 case OCRDMA_QPS_SQ_DRAINING:
147 return IB_QPS_SQD;
148 case OCRDMA_QPS_SQE:
149 return IB_QPS_SQE;
150 case OCRDMA_QPS_ERR:
151 return IB_QPS_ERR;
2b50176d 152 }
fe2caefc
PP		 153 return IB_QPS_ERR;
154}
155
abe3afac 156static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 157{
158 switch (qps) {
159 case IB_QPS_RESET:
160 return OCRDMA_QPS_RST;
161 case IB_QPS_INIT:
162 return OCRDMA_QPS_INIT;
163 case IB_QPS_RTR:
164 return OCRDMA_QPS_RTR;
165 case IB_QPS_RTS:
166 return OCRDMA_QPS_RTS;
167 case IB_QPS_SQD:
168 return OCRDMA_QPS_SQD;
169 case IB_QPS_SQE:
170 return OCRDMA_QPS_SQE;
171 case IB_QPS_ERR:
172 return OCRDMA_QPS_ERR;
2b50176d 173 }
fe2caefc
PP		 174 return OCRDMA_QPS_ERR;
175}
176
177static int ocrdma_get_mbx_errno(u32 status)
178{
f99b1649 179 int err_num;
fe2caefc
PP		 180 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
181 OCRDMA_MBX_RSP_STATUS_SHIFT;
182 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
183 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
184
185 switch (mbox_status) {
186 case OCRDMA_MBX_STATUS_OOR:
187 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
188 err_num = -EAGAIN;
189 break;
190
191 case OCRDMA_MBX_STATUS_INVALID_PD:
192 case OCRDMA_MBX_STATUS_INVALID_CQ:
193 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
194 case OCRDMA_MBX_STATUS_INVALID_QP:
195 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
196 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
197 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
198 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
200 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
201 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
202 case OCRDMA_MBX_STATUS_INVALID_LKEY:
203 case OCRDMA_MBX_STATUS_INVALID_VA:
204 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
205 case OCRDMA_MBX_STATUS_INVALID_FBO:
206 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
207 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
208 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
209 case OCRDMA_MBX_STATUS_SRQ_ERROR:
210 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
211 err_num = -EINVAL;
212 break;
213
214 case OCRDMA_MBX_STATUS_PD_INUSE:
215 case OCRDMA_MBX_STATUS_QP_BOUND:
216 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
217 case OCRDMA_MBX_STATUS_MW_BOUND:
218 err_num = -EBUSY;
219 break;
220
221 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
222 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
223 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
224 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
225 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
226 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
230 err_num = -ENOBUFS;
231 break;
232
233 case OCRDMA_MBX_STATUS_FAILED:
234 switch (add_status) {
235 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
236 err_num = -EAGAIN;
237 break;
238 }
239 default:
240 err_num = -EFAULT;
241 }
242 return err_num;
243}
244
a51f06e1
SX		 245char *port_speed_string(struct ocrdma_dev *dev)
246{
247 char *str = "";
248 u16 speeds_supported;
249
250 speeds_supported = dev->phy.fixed_speeds_supported |
251 dev->phy.auto_speeds_supported;
252 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
253 str = "40Gbps ";
254 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
255 str = "10Gbps ";
256 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
257 str = "1Gbps ";
258
259 return str;
260}
261
fe2caefc
PP		 262static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
263{
264 int err_num = -EINVAL;
265
266 switch (cqe_status) {
267 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
268 err_num = -EPERM;
269 break;
270 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
271 err_num = -EINVAL;
272 break;
273 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
274 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
f11220ee 275 err_num = -EINVAL;
fe2caefc
PP		 276 break;
277 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
43a6b402 278 default:
f11220ee 279 err_num = -EINVAL;
fe2caefc
PP		 280 break;
281 }
282 return err_num;
283}
284
285void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
286 bool solicited, u16 cqe_popped)
287{
288 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
289
290 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
291 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
292
293 if (armed)
294 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
295 if (solicited)
296 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
297 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
298 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
299}
300
301static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
302{
303 u32 val = 0;
304
305 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
306 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
308}
309
310static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
311 bool arm, bool clear_int, u16 num_eqe)
312{
313 u32 val = 0;
314
315 val |= eq_id & OCRDMA_EQ_ID_MASK;
316 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
317 if (arm)
318 val |= (1 << OCRDMA_REARM_SHIFT);
319 if (clear_int)
320 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
321 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
322 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
323 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
324}
325
326static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
327 u8 opcode, u8 subsys, u32 cmd_len)
328{
329 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
330 cmd_hdr->timeout = 20; /* seconds */
331 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
332}
333
334static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
335{
336 struct ocrdma_mqe *mqe;
337
338 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
339 if (!mqe)
340 return NULL;
341 mqe->hdr.spcl_sge_cnt_emb |=
342 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
343 OCRDMA_MQE_HDR_EMB_MASK;
344 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
345
346 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
347 mqe->hdr.pyld_len);
348 return mqe;
349}
350
a51f06e1
SX		 351static void *ocrdma_alloc_mqe(void)
352{
353 return kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
354}
355
fe2caefc
PP		 356static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
357{
358 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
359}
360
361static int ocrdma_alloc_q(struct ocrdma_dev *dev,
362 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
363{
364 memset(q, 0, sizeof(*q));
365 q->len = len;
366 q->entry_size = entry_size;
367 q->size = len * entry_size;
368 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
369 &q->dma, GFP_KERNEL);
370 if (!q->va)
371 return -ENOMEM;
372 memset(q->va, 0, q->size);
373 return 0;
374}
375
376static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
377 dma_addr_t host_pa, int hw_page_size)
378{
379 int i;
380
381 for (i = 0; i < cnt; i++) {
382 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
383 q_pa[i].hi = (u32) upper_32_bits(host_pa);
384 host_pa += hw_page_size;
385 }
386}
387
fad51b7d
DS		 388static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
389 struct ocrdma_queue_info *q, int queue_type)
fe2caefc
PP		 390{
391 u8 opcode = 0;
392 int status;
393 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
394
395 switch (queue_type) {
396 case QTYPE_MCCQ:
397 opcode = OCRDMA_CMD_DELETE_MQ;
398 break;
399 case QTYPE_CQ:
400 opcode = OCRDMA_CMD_DELETE_CQ;
401 break;
402 case QTYPE_EQ:
403 opcode = OCRDMA_CMD_DELETE_EQ;
404 break;
405 default:
406 BUG();
407 }
408 memset(cmd, 0, sizeof(*cmd));
409 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
410 cmd->id = q->id;
411
412 status = be_roce_mcc_cmd(dev->nic_info.netdev,
413 cmd, sizeof(*cmd), NULL, NULL);
414 if (!status)
415 q->created = false;
416 return status;
417}
418
419static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
420{
421 int status;
422 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
423 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
424
425 memset(cmd, 0, sizeof(*cmd));
426 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
427 sizeof(*cmd));
fe2caefc 428
c88bd03f 429 cmd->req.rsvd_version = 2;
fe2caefc
PP		 430 cmd->num_pages = 4;
431 cmd->valid = OCRDMA_CREATE_EQ_VALID;
432 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
433
434 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
435 PAGE_SIZE_4K);
436 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
437 NULL);
438 if (!status) {
439 eq->q.id = rsp->vector_eqid & 0xffff;
c88bd03f 440 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
fe2caefc
PP		 441 eq->q.created = true;
442 }
443 return status;
444}
445
446static int ocrdma_create_eq(struct ocrdma_dev *dev,
447 struct ocrdma_eq *eq, u16 q_len)
448{
449 int status;
450
451 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
452 sizeof(struct ocrdma_eqe));
453 if (status)
454 return status;
455
456 status = ocrdma_mbx_create_eq(dev, eq);
457 if (status)
458 goto mbx_err;
459 eq->dev = dev;
460 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
461
462 return 0;
463mbx_err:
464 ocrdma_free_q(dev, &eq->q);
465 return status;
466}
467
ea617626 468int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
fe2caefc
PP		 469{
470 int irq;
471
472 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
473 irq = dev->nic_info.pdev->irq;
474 else
475 irq = dev->nic_info.msix.vector_list[eq->vector];
476 return irq;
477}
478
479static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
480{
481 if (eq->q.created) {
482 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
fe2caefc
PP		 483 ocrdma_free_q(dev, &eq->q);
484 }
485}
486
487static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
488{
489 int irq;
490
491 /* disarm EQ so that interrupts are not generated
492 * during freeing and EQ delete is in progress.
493 */
494 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
495
496 irq = ocrdma_get_irq(dev, eq);
497 free_irq(irq, eq);
498 _ocrdma_destroy_eq(dev, eq);
499}
500
c88bd03f 501static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
fe2caefc
PP		 502{
503 int i;
504
fe2caefc 505 for (i = 0; i < dev->eq_cnt; i++)
c88bd03f 506 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
fe2caefc
PP		 507}
508
abe3afac
RD		 509static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
510 struct ocrdma_queue_info *cq,
511 struct ocrdma_queue_info *eq)
fe2caefc
PP		 512{
513 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
514 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
515 int status;
516
517 memset(cmd, 0, sizeof(*cmd));
518 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
519 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
520
1afc0454
NG		 521 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
522 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
523 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
524 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
525
fe2caefc 526 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454
NG		 527 cmd->eqn = eq->id;
528 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 529
1afc0454 530 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 531 cq->dma, PAGE_SIZE_4K);
532 status = be_roce_mcc_cmd(dev->nic_info.netdev,
533 cmd, sizeof(*cmd), NULL, NULL);
534 if (!status) {
1afc0454 535 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 536 cq->created = true;
537 }
538 return status;
539}
540
541static u32 ocrdma_encoded_q_len(int q_len)
542{
543 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
544
545 if (len_encoded == 16)
546 len_encoded = 0;
547 return len_encoded;
548}
549
550static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
551 struct ocrdma_queue_info *mq,
552 struct ocrdma_queue_info *cq)
553{
554 int num_pages, status;
555 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
556 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
557 struct ocrdma_pa *pa;
558
559 memset(cmd, 0, sizeof(*cmd));
560 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
561
b1d58b99
NG		 562 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
563 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
564 cmd->req.rsvd_version = 1;
565 cmd->cqid_pages = num_pages;
566 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
567 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
84b105db
NG		 568
569 cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
570 cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
571
b1d58b99
NG		 572 cmd->async_cqid_ringsize = cq->id;
573 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
574 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
575 cmd->valid = OCRDMA_CREATE_MQ_VALID;
576 pa = &cmd->pa[0];
577
fe2caefc
PP		 578 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
579 status = be_roce_mcc_cmd(dev->nic_info.netdev,
580 cmd, sizeof(*cmd), NULL, NULL);
581 if (!status) {
582 mq->id = rsp->id;
583 mq->created = true;
584 }
585 return status;
586}
587
588static int ocrdma_create_mq(struct ocrdma_dev *dev)
589{
590 int status;
591
592 /* Alloc completion queue for Mailbox queue */
593 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
594 sizeof(struct ocrdma_mcqe));
595 if (status)
596 goto alloc_err;
597
ea617626 598 dev->eq_tbl[0].cq_cnt++;
c88bd03f 599 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
fe2caefc
PP		 600 if (status)
601 goto mbx_cq_free;
602
603 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
604 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
605 mutex_init(&dev->mqe_ctx.lock);
606
607 /* Alloc Mailbox queue */
608 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
609 sizeof(struct ocrdma_mqe));
610 if (status)
611 goto mbx_cq_destroy;
612 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
613 if (status)
614 goto mbx_q_free;
615 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
616 return 0;
617
618mbx_q_free:
619 ocrdma_free_q(dev, &dev->mq.sq);
620mbx_cq_destroy:
621 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
622mbx_cq_free:
623 ocrdma_free_q(dev, &dev->mq.cq);
624alloc_err:
625 return status;
626}
627
628static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
629{
630 struct ocrdma_queue_info *mbxq, *cq;
631
632 /* mqe_ctx lock synchronizes with any other pending cmds. */
633 mutex_lock(&dev->mqe_ctx.lock);
634 mbxq = &dev->mq.sq;
635 if (mbxq->created) {
636 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
637 ocrdma_free_q(dev, mbxq);
638 }
639 mutex_unlock(&dev->mqe_ctx.lock);
640
641 cq = &dev->mq.cq;
642 if (cq->created) {
643 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
644 ocrdma_free_q(dev, cq);
645 }
646}
647
648static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
649 struct ocrdma_qp *qp)
650{
651 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
652 enum ib_qp_state old_ib_qps;
653
654 if (qp == NULL)
655 BUG();
057729cb 656 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 657}
658
659static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
660 struct ocrdma_ae_mcqe *cqe)
661{
662 struct ocrdma_qp *qp = NULL;
663 struct ocrdma_cq *cq = NULL;
1228056b 664 struct ib_event ib_evt = { 0 };
fe2caefc
PP		 665 int cq_event = 0;
666 int qp_event = 1;
667 int srq_event = 0;
668 int dev_event = 0;
669 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
670 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
671
672 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
673 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
674 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
675 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
676
e9db2953
RD		 677 ib_evt.device = &dev->ibdev;
678
fe2caefc
PP		 679 switch (type) {
680 case OCRDMA_CQ_ERROR:
681 ib_evt.element.cq = &cq->ibcq;
682 ib_evt.event = IB_EVENT_CQ_ERR;
683 cq_event = 1;
684 qp_event = 0;
685 break;
686 case OCRDMA_CQ_OVERRUN_ERROR:
687 ib_evt.element.cq = &cq->ibcq;
688 ib_evt.event = IB_EVENT_CQ_ERR;
1228056b
SX		 689 cq_event = 1;
690 qp_event = 0;
fe2caefc
PP		 691 break;
692 case OCRDMA_CQ_QPCAT_ERROR:
693 ib_evt.element.qp = &qp->ibqp;
694 ib_evt.event = IB_EVENT_QP_FATAL;
695 ocrdma_process_qpcat_error(dev, qp);
696 break;
697 case OCRDMA_QP_ACCESS_ERROR:
698 ib_evt.element.qp = &qp->ibqp;
699 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
700 break;
701 case OCRDMA_QP_COMM_EST_EVENT:
702 ib_evt.element.qp = &qp->ibqp;
703 ib_evt.event = IB_EVENT_COMM_EST;
704 break;
705 case OCRDMA_SQ_DRAINED_EVENT:
706 ib_evt.element.qp = &qp->ibqp;
707 ib_evt.event = IB_EVENT_SQ_DRAINED;
708 break;
709 case OCRDMA_DEVICE_FATAL_EVENT:
710 ib_evt.element.port_num = 1;
711 ib_evt.event = IB_EVENT_DEVICE_FATAL;
712 qp_event = 0;
713 dev_event = 1;
714 break;
715 case OCRDMA_SRQCAT_ERROR:
716 ib_evt.element.srq = &qp->srq->ibsrq;
717 ib_evt.event = IB_EVENT_SRQ_ERR;
718 srq_event = 1;
719 qp_event = 0;
720 break;
721 case OCRDMA_SRQ_LIMIT_EVENT:
722 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 723 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 724 srq_event = 1;
725 qp_event = 0;
726 break;
727 case OCRDMA_QP_LAST_WQE_EVENT:
728 ib_evt.element.qp = &qp->ibqp;
729 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
730 break;
731 default:
732 cq_event = 0;
733 qp_event = 0;
734 srq_event = 0;
735 dev_event = 0;
ef99c4c2 736 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 737 break;
738 }
739
740 if (qp_event) {
741 if (qp->ibqp.event_handler)
742 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
743 } else if (cq_event) {
744 if (cq->ibcq.event_handler)
745 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
746 } else if (srq_event) {
747 if (qp->srq->ibsrq.event_handler)
748 qp->srq->ibsrq.event_handler(&ib_evt,
749 qp->srq->ibsrq.
750 srq_context);
f99b1649 751 } else if (dev_event) {
1228056b 752 pr_err("%s: Fatal event received\n", dev->ibdev.name);
fe2caefc 753 ib_dispatch_event(&ib_evt);
f99b1649 754 }
fe2caefc
PP		 755
756}
757
84b105db
NG		 758static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
759 struct ocrdma_ae_mcqe *cqe)
760{
761 struct ocrdma_ae_pvid_mcqe *evt;
762 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
763 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
764
765 switch (type) {
766 case OCRDMA_ASYNC_EVENT_PVID_STATE:
767 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
768 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
769 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
770 dev->pvid = ((evt->tag_enabled &
771 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
772 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
773 break;
31dbdd9a
SX		 774
775 case OCRDMA_ASYNC_EVENT_COS_VALUE:
776 atomic_set(&dev->update_sl, 1);
777 break;
84b105db
NG		 778 default:
779 /* Not interested evts. */
780 break;
781 }
782}
783
fe2caefc
PP		 784static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
785{
786 /* async CQE processing */
787 struct ocrdma_ae_mcqe *cqe = ae_cqe;
788 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
789 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
790
84b105db 791 if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
fe2caefc 792 ocrdma_dispatch_ibevent(dev, cqe);
84b105db
NG		 793 else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
794 ocrdma_process_grp5_aync(dev, cqe);
fe2caefc 795 else
ef99c4c2
NG		 796 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
797 dev->id, evt_code);
fe2caefc
PP		 798}
799
800static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
801{
802 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
803 dev->mqe_ctx.cqe_status = (cqe->status &
804 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
805 dev->mqe_ctx.ext_status =
806 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
807 >> OCRDMA_MCQE_ESTATUS_SHIFT;
808 dev->mqe_ctx.cmd_done = true;
809 wake_up(&dev->mqe_ctx.cmd_wait);
810 } else
ef99c4c2
NG		 811 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
812 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 813}
814
815static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
816{
817 u16 cqe_popped = 0;
818 struct ocrdma_mcqe *cqe;
819
820 while (1) {
821 cqe = ocrdma_get_mcqe(dev);
822 if (cqe == NULL)
823 break;
824 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
825 cqe_popped += 1;
826 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
827 ocrdma_process_acqe(dev, cqe);
828 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
829 ocrdma_process_mcqe(dev, cqe);
fe2caefc
PP		 830 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
831 ocrdma_mcq_inc_tail(dev);
832 }
833 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
834 return 0;
835}
836
837static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
838 struct ocrdma_cq *cq)
839{
840 unsigned long flags;
841 struct ocrdma_qp *qp;
842 bool buddy_cq_found = false;
843 /* Go through list of QPs in error state which are using this CQ
844 * and invoke its callback handler to trigger CQE processing for
845 * error/flushed CQE. It is rare to find more than few entries in
846 * this list as most consumers stops after getting error CQE.
847 * List is traversed only once when a matching buddy cq found for a QP.
848 */
849 spin_lock_irqsave(&dev->flush_q_lock, flags);
850 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
851 if (qp->srq)
852 continue;
853 /* if wq and rq share the same cq, than comp_handler
854 * is already invoked.
855 */
856 if (qp->sq_cq == qp->rq_cq)
857 continue;
858 /* if completion came on sq, rq's cq is buddy cq.
859 * if completion came on rq, sq's cq is buddy cq.
860 */
861 if (qp->sq_cq == cq)
862 cq = qp->rq_cq;
863 else
864 cq = qp->sq_cq;
865 buddy_cq_found = true;
866 break;
867 }
868 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
869 if (buddy_cq_found == false)
870 return;
871 if (cq->ibcq.comp_handler) {
872 spin_lock_irqsave(&cq->comp_handler_lock, flags);
873 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
874 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
875 }
876}
877
878static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
879{
880 unsigned long flags;
881 struct ocrdma_cq *cq;
882
883 if (cq_idx >= OCRDMA_MAX_CQ)
884 BUG();
885
886 cq = dev->cq_tbl[cq_idx];
ea617626 887 if (cq == NULL)
fe2caefc 888 return;
fe2caefc
PP		 889
890 if (cq->ibcq.comp_handler) {
891 spin_lock_irqsave(&cq->comp_handler_lock, flags);
892 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
893 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
894 }
895 ocrdma_qp_buddy_cq_handler(dev, cq);
896}
897
898static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
899{
900 /* process the MQ-CQE. */
901 if (cq_id == dev->mq.cq.id)
902 ocrdma_mq_cq_handler(dev, cq_id);
903 else
904 ocrdma_qp_cq_handler(dev, cq_id);
905}
906
907static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
908{
909 struct ocrdma_eq *eq = handle;
910 struct ocrdma_dev *dev = eq->dev;
911 struct ocrdma_eqe eqe;
912 struct ocrdma_eqe *ptr;
fe2caefc 913 u16 cq_id;
ea617626
DS		 914 int budget = eq->cq_cnt;
915
916 do {
fe2caefc
PP		 917 ptr = ocrdma_get_eqe(eq);
918 eqe = *ptr;
919 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
920 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
921 break;
ea617626 922
fe2caefc 923 ptr->id_valid = 0;
ea617626
DS		 924 /* ring eq doorbell as soon as its consumed. */
925 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
fe2caefc
PP		 926 /* check whether its CQE or not. */
927 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
928 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
929 ocrdma_cq_handler(dev, cq_id);
930 }
931 ocrdma_eq_inc_tail(eq);
ea617626
DS		 932
933 /* There can be a stale EQE after the last bound CQ is
934 * destroyed. EQE valid and budget == 0 implies this.
935 */
936 if (budget)
937 budget--;
938
939 } while (budget);
940
941 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
fe2caefc
PP		 942 return IRQ_HANDLED;
943}
944
945static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
946{
947 struct ocrdma_mqe *mqe;
948
949 dev->mqe_ctx.tag = dev->mq.sq.head;
950 dev->mqe_ctx.cmd_done = false;
951 mqe = ocrdma_get_mqe(dev);
952 cmd->hdr.tag_lo = dev->mq.sq.head;
953 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
954 /* make sure descriptor is written before ringing doorbell */
955 wmb();
956 ocrdma_mq_inc_head(dev);
957 ocrdma_ring_mq_db(dev);
958}
959
960static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
961{
962 long status;
963 /* 30 sec timeout */
964 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
965 (dev->mqe_ctx.cmd_done != false),
966 msecs_to_jiffies(30000));
967 if (status)
968 return 0;
6dab0264
MA		 969 else {
970 dev->mqe_ctx.fw_error_state = true;
971 pr_err("%s(%d) mailbox timeout: fw not responding\n",
972 __func__, dev->id);
fe2caefc 973 return -1;
6dab0264 974 }
fe2caefc
PP		 975}
976
977/* issue a mailbox command on the MQ */
978static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
979{
980 int status = 0;
981 u16 cqe_status, ext_status;
bbc5ec52
SX		 982 struct ocrdma_mqe *rsp_mqe;
983 struct ocrdma_mbx_rsp *rsp = NULL;
fe2caefc
PP		 984
985 mutex_lock(&dev->mqe_ctx.lock);
6dab0264
MA		 986 if (dev->mqe_ctx.fw_error_state)
987 goto mbx_err;
fe2caefc
PP		 988 ocrdma_post_mqe(dev, mqe);
989 status = ocrdma_wait_mqe_cmpl(dev);
990 if (status)
991 goto mbx_err;
992 cqe_status = dev->mqe_ctx.cqe_status;
993 ext_status = dev->mqe_ctx.ext_status;
bbc5ec52
SX		 994 rsp_mqe = ocrdma_get_mqe_rsp(dev);
995 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
996 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
997 OCRDMA_MQE_HDR_EMB_SHIFT)
998 rsp = &mqe->u.rsp;
999
fe2caefc 1000 if (cqe_status || ext_status) {
bbc5ec52
SX		 1001 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1002 __func__, cqe_status, ext_status);
1003 if (rsp) {
1004 /* This is for embedded cmds. */
1005 pr_err("opcode=0x%x, subsystem=0x%x\n",
1006 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1007 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1008 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1009 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1010 }
fe2caefc
PP		 1011 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1012 goto mbx_err;
1013 }
bbc5ec52
SX		 1014 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1015 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
fe2caefc
PP		 1016 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1017mbx_err:
1018 mutex_unlock(&dev->mqe_ctx.lock);
1019 return status;
1020}
1021
bbc5ec52
SX		 1022static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1023 void *payload_va)
1024{
1025 int status = 0;
1026 struct ocrdma_mbx_rsp *rsp = payload_va;
1027
1028 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1029 OCRDMA_MQE_HDR_EMB_SHIFT)
1030 BUG();
1031
1032 status = ocrdma_mbx_cmd(dev, mqe);
1033 if (!status)
1034 /* For non embedded, only CQE failures are handled in
1035 * ocrdma_mbx_cmd. We need to check for RSP errors.
1036 */
1037 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1038 status = ocrdma_get_mbx_errno(rsp->status);
1039
1040 if (status)
1041 pr_err("opcode=0x%x, subsystem=0x%x\n",
1042 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1043 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1044 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1045 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1046 return status;
1047}
1048
fe2caefc
PP		 1049static void ocrdma_get_attr(struct ocrdma_dev *dev,
1050 struct ocrdma_dev_attr *attr,
1051 struct ocrdma_mbx_query_config *rsp)
1052{
fe2caefc
PP		 1053 attr->max_pd =
1054 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1055 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1056 attr->max_qp =
1057 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1058 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
fad51b7d
DS		 1059 attr->max_srq =
1060 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1061 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
fe2caefc
PP		 1062 attr->max_send_sge = ((rsp->max_write_send_sge &
1063 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1064 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1065 attr->max_recv_sge = (rsp->max_write_send_sge &
1066 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1067 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 1068 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1069 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1070 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
45e86b33
NG		 1071 attr->max_rdma_sge = (rsp->max_write_send_sge &
1072 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1073 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
fe2caefc
PP		 1074 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1075 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1076 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1077 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1078 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1079 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1080 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1081 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1082 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1083 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1084 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1085 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1086 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1087 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1088 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
ac578aef 1089 attr->max_mw = rsp->max_mw;
fe2caefc
PP		 1090 attr->max_mr = rsp->max_mr;
1091 attr->max_mr_size = ~0ull;
1092 attr->max_fmr = 0;
1093 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1094 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1095 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1096 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
c43e9ab8
NG		 1097 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1098 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1099 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
fe2caefc
PP		 1100 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1101 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1102 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1103 OCRDMA_WQE_STRIDE;
1104 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1105 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1106 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1107 OCRDMA_WQE_STRIDE;
1108 attr->max_inline_data =
1109 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1110 sizeof(struct ocrdma_sge));
21c3391a 1111 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1112 attr->ird = 1;
1113 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1114 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1115 }
1116 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1117 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1118 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1119 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1120}
1121
1122static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1123 struct ocrdma_fw_conf_rsp *conf)
1124{
1125 u32 fn_mode;
1126
1127 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1128 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1129 return -EINVAL;
1130 dev->base_eqid = conf->base_eqid;
1131 dev->max_eq = conf->max_eq;
fe2caefc
PP		 1132 return 0;
1133}
1134
1135/* can be issued only during init time. */
1136static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1137{
1138 int status = -ENOMEM;
1139 struct ocrdma_mqe *cmd;
1140 struct ocrdma_fw_ver_rsp *rsp;
1141
1142 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1143 if (!cmd)
1144 return -ENOMEM;
1145 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1146 OCRDMA_CMD_GET_FW_VER,
1147 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1148
1149 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1150 if (status)
1151 goto mbx_err;
1152 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1153 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1154 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1155 sizeof(rsp->running_ver));
1156 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1157mbx_err:
1158 kfree(cmd);
1159 return status;
1160}
1161
1162/* can be issued only during init time. */
1163static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1164{
1165 int status = -ENOMEM;
1166 struct ocrdma_mqe *cmd;
1167 struct ocrdma_fw_conf_rsp *rsp;
1168
1169 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1170 if (!cmd)
1171 return -ENOMEM;
1172 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1173 OCRDMA_CMD_GET_FW_CONFIG,
1174 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1175 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1176 if (status)
1177 goto mbx_err;
1178 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1179 status = ocrdma_check_fw_config(dev, rsp);
1180mbx_err:
1181 kfree(cmd);
1182 return status;
1183}
1184
a51f06e1
SX		 1185int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1186{
1187 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1188 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1189 struct ocrdma_rdma_stats_resp *old_stats = NULL;
1190 int status;
1191
1192 old_stats = kzalloc(sizeof(*old_stats), GFP_KERNEL);
1193 if (old_stats == NULL)
1194 return -ENOMEM;
1195
1196 memset(mqe, 0, sizeof(*mqe));
1197 mqe->hdr.pyld_len = dev->stats_mem.size;
1198 mqe->hdr.spcl_sge_cnt_emb |=
1199 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1200 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1201 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1202 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1203 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1204
1205 /* Cache the old stats */
1206 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1207 memset(req, 0, dev->stats_mem.size);
1208
1209 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1210 OCRDMA_CMD_GET_RDMA_STATS,
1211 OCRDMA_SUBSYS_ROCE,
1212 dev->stats_mem.size);
1213 if (reset)
1214 req->reset_stats = reset;
1215
1216 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1217 if (status)
1218 /* Copy from cache, if mbox fails */
1219 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1220 else
1221 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1222
1223 kfree(old_stats);
1224 return status;
1225}
1226
1227static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1228{
1229 int status = -ENOMEM;
1230 struct ocrdma_dma_mem dma;
1231 struct ocrdma_mqe *mqe;
1232 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1233 struct mgmt_hba_attribs *hba_attribs;
1234
1235 mqe = ocrdma_alloc_mqe();
1236 if (!mqe)
1237 return status;
1238 memset(mqe, 0, sizeof(*mqe));
1239
1240 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1241 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1242 dma.size, &dma.pa, GFP_KERNEL);
1243 if (!dma.va)
1244 goto free_mqe;
1245
1246 mqe->hdr.pyld_len = dma.size;
1247 mqe->hdr.spcl_sge_cnt_emb |=
1248 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1249 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1250 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1251 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1252 mqe->u.nonemb_req.sge[0].len = dma.size;
1253
1254 memset(dma.va, 0, dma.size);
1255 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1256 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1257 OCRDMA_SUBSYS_COMMON,
1258 dma.size);
1259
1260 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1261 if (!status) {
1262 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1263 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1264
1265 dev->hba_port_num = hba_attribs->phy_port;
1266 strncpy(dev->model_number,
1267 hba_attribs->controller_model_number, 31);
1268 }
1269 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1270free_mqe:
1271 kfree(mqe);
1272 return status;
1273}
1274
fe2caefc
PP		 1275static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1276{
1277 int status = -ENOMEM;
1278 struct ocrdma_mbx_query_config *rsp;
1279 struct ocrdma_mqe *cmd;
1280
1281 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1282 if (!cmd)
1283 return status;
1284 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1285 if (status)
1286 goto mbx_err;
1287 rsp = (struct ocrdma_mbx_query_config *)cmd;
1288 ocrdma_get_attr(dev, &dev->attr, rsp);
1289mbx_err:
1290 kfree(cmd);
1291 return status;
1292}
1293
f24ceba6
NG		 1294int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1295{
1296 int status = -ENOMEM;
1297 struct ocrdma_get_link_speed_rsp *rsp;
1298 struct ocrdma_mqe *cmd;
1299
1300 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1301 sizeof(*cmd));
1302 if (!cmd)
1303 return status;
1304 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1305 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1306 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1307
1308 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1309
1310 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1311 if (status)
1312 goto mbx_err;
1313
1314 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1315 *lnk_speed = rsp->phys_port_speed;
1316
1317mbx_err:
1318 kfree(cmd);
1319 return status;
1320}
1321
a51f06e1
SX		 1322static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1323{
1324 int status = -ENOMEM;
1325 struct ocrdma_mqe *cmd;
1326 struct ocrdma_get_phy_info_rsp *rsp;
1327
1328 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1329 if (!cmd)
1330 return status;
1331
1332 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1333 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1334 sizeof(*cmd));
1335
1336 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1337 if (status)
1338 goto mbx_err;
1339
1340 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1341 dev->phy.phy_type = le16_to_cpu(rsp->phy_type);
1342 dev->phy.auto_speeds_supported =
1343 le16_to_cpu(rsp->auto_speeds_supported);
1344 dev->phy.fixed_speeds_supported =
1345 le16_to_cpu(rsp->fixed_speeds_supported);
1346mbx_err:
1347 kfree(cmd);
1348 return status;
1349}
1350
fe2caefc
PP		 1351int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1352{
1353 int status = -ENOMEM;
1354 struct ocrdma_alloc_pd *cmd;
1355 struct ocrdma_alloc_pd_rsp *rsp;
1356
1357 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1358 if (!cmd)
1359 return status;
1360 if (pd->dpp_enabled)
1361 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1362 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1363 if (status)
1364 goto mbx_err;
1365 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1366 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1367 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1368 pd->dpp_enabled = true;
1369 pd->dpp_page = rsp->dpp_page_pdid >>
1370 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1371 } else {
1372 pd->dpp_enabled = false;
1373 pd->num_dpp_qp = 0;
1374 }
1375mbx_err:
1376 kfree(cmd);
1377 return status;
1378}
1379
1380int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1381{
1382 int status = -ENOMEM;
1383 struct ocrdma_dealloc_pd *cmd;
1384
1385 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1386 if (!cmd)
1387 return status;
1388 cmd->id = pd->id;
1389 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1390 kfree(cmd);
1391 return status;
1392}
1393
1394static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1395 int *num_pages, int *page_size)
1396{
1397 int i;
1398 int mem_size;
1399
1400 *num_entries = roundup_pow_of_two(*num_entries);
1401 mem_size = *num_entries * entry_size;
1402 /* find the possible lowest possible multiplier */
1403 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1404 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1405 break;
1406 }
1407 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1408 return -EINVAL;
1409 mem_size = roundup(mem_size,
1410 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1411 *num_pages =
1412 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1413 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1414 *num_entries = mem_size / entry_size;
1415 return 0;
1416}
1417
1418static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1419{
fad51b7d 1420 int i;
fe2caefc
PP		 1421 int status = 0;
1422 int max_ah;
1423 struct ocrdma_create_ah_tbl *cmd;
1424 struct ocrdma_create_ah_tbl_rsp *rsp;
1425 struct pci_dev *pdev = dev->nic_info.pdev;
1426 dma_addr_t pa;
1427 struct ocrdma_pbe *pbes;
1428
1429 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1430 if (!cmd)
1431 return status;
1432
1433 max_ah = OCRDMA_MAX_AH;
1434 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1435
1436 /* number of PBEs in PBL */
1437 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1438 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1439 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1440
1441 /* page size */
1442 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1443 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1444 break;
1445 }
1446 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1447 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1448
1449 /* ah_entry size */
1450 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1451 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1452 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1453
1454 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1455 &dev->av_tbl.pbl.pa,
1456 GFP_KERNEL);
1457 if (dev->av_tbl.pbl.va == NULL)
1458 goto mem_err;
1459
1460 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1461 &pa, GFP_KERNEL);
1462 if (dev->av_tbl.va == NULL)
1463 goto mem_err_ah;
1464 dev->av_tbl.pa = pa;
1465 dev->av_tbl.num_ah = max_ah;
1466 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1467
1468 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1469 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1470 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1471 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1472 pa += PAGE_SIZE;
1473 }
1474 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1475 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1476 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1477 if (status)
1478 goto mbx_err;
1479 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1480 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1481 kfree(cmd);
1482 return 0;
1483
1484mbx_err:
1485 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1486 dev->av_tbl.pa);
1487 dev->av_tbl.va = NULL;
1488mem_err_ah:
1489 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1490 dev->av_tbl.pbl.pa);
1491 dev->av_tbl.pbl.va = NULL;
1492 dev->av_tbl.size = 0;
1493mem_err:
1494 kfree(cmd);
1495 return status;
1496}
1497
1498static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1499{
1500 struct ocrdma_delete_ah_tbl *cmd;
1501 struct pci_dev *pdev = dev->nic_info.pdev;
1502
1503 if (dev->av_tbl.va == NULL)
1504 return;
1505
1506 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1507 if (!cmd)
1508 return;
1509 cmd->ahid = dev->av_tbl.ahid;
1510
1511 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1512 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1513 dev->av_tbl.pa);
daac9681 1514 dev->av_tbl.va = NULL;
fe2caefc
PP		 1515 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1516 dev->av_tbl.pbl.pa);
1517 kfree(cmd);
1518}
1519
1520/* Multiple CQs uses the EQ. This routine returns least used
1521 * EQ to associate with CQ. This will distributes the interrupt
1522 * processing and CPU load to associated EQ, vector and so to that CPU.
1523 */
1524static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1525{
1526 int i, selected_eq = 0, cq_cnt = 0;
1527 u16 eq_id;
1528
1529 mutex_lock(&dev->dev_lock);
c88bd03f
NG		 1530 cq_cnt = dev->eq_tbl[0].cq_cnt;
1531 eq_id = dev->eq_tbl[0].q.id;
fe2caefc
PP		 1532 /* find the EQ which is has the least number of
1533 * CQs associated with it.
1534 */
1535 for (i = 0; i < dev->eq_cnt; i++) {
c88bd03f
NG		 1536 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1537 cq_cnt = dev->eq_tbl[i].cq_cnt;
1538 eq_id = dev->eq_tbl[i].q.id;
fe2caefc
PP		 1539 selected_eq = i;
1540 }
1541 }
c88bd03f 1542 dev->eq_tbl[selected_eq].cq_cnt += 1;
fe2caefc
PP		 1543 mutex_unlock(&dev->dev_lock);
1544 return eq_id;
1545}
1546
1547static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1548{
1549 int i;
1550
1551 mutex_lock(&dev->dev_lock);
ea617626
DS		 1552 i = ocrdma_get_eq_table_index(dev, eq_id);
1553 if (i == -EINVAL)
1554 BUG();
1555 dev->eq_tbl[i].cq_cnt -= 1;
fe2caefc
PP		 1556 mutex_unlock(&dev->dev_lock);
1557}
1558
1559int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
cffce990 1560 int entries, int dpp_cq, u16 pd_id)
fe2caefc
PP		 1561{
1562 int status = -ENOMEM; int max_hw_cqe;
1563 struct pci_dev *pdev = dev->nic_info.pdev;
1564 struct ocrdma_create_cq *cmd;
1565 struct ocrdma_create_cq_rsp *rsp;
1566 u32 hw_pages, cqe_size, page_size, cqe_count;
1567
fe2caefc 1568 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1569 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1570 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1571 return -EINVAL;
1572 }
21c3391a 1573 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
fe2caefc
PP		 1574 return -EINVAL;
1575
1576 if (dpp_cq) {
1577 cq->max_hw_cqe = 1;
1578 max_hw_cqe = 1;
1579 cqe_size = OCRDMA_DPP_CQE_SIZE;
1580 hw_pages = 1;
1581 } else {
1582 cq->max_hw_cqe = dev->attr.max_cqe;
1583 max_hw_cqe = dev->attr.max_cqe;
1584 cqe_size = sizeof(struct ocrdma_cqe);
1585 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1586 }
1587
1588 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1589
1590 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1591 if (!cmd)
1592 return -ENOMEM;
1593 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1594 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1595 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1596 if (!cq->va) {
1597 status = -ENOMEM;
1598 goto mem_err;
1599 }
1600 memset(cq->va, 0, cq->len);
1601 page_size = cq->len / hw_pages;
1602 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1603 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1604 cmd->cmd.pgsz_pgcnt |= hw_pages;
1605 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1606
fe2caefc 1607 cq->eqn = ocrdma_bind_eq(dev);
cffce990 1608 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
fe2caefc 1609 cqe_count = cq->len / cqe_size;
ea617626 1610 cq->cqe_cnt = cqe_count;
f99b1649 1611 if (cqe_count > 1024) {
fe2caefc
PP		 1612 /* Set cnt to 3 to indicate more than 1024 cq entries */
1613 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1614 } else {
fe2caefc
PP		 1615 u8 count = 0;
1616 switch (cqe_count) {
1617 case 256:
1618 count = 0;
1619 break;
1620 case 512:
1621 count = 1;
1622 break;
1623 case 1024:
1624 count = 2;
1625 break;
1626 default:
1627 goto mbx_err;
1628 }
1629 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1630 }
1631 /* shared eq between all the consumer cqs. */
1632 cmd->cmd.eqn = cq->eqn;
21c3391a 1633 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
fe2caefc
PP		 1634 if (dpp_cq)
1635 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1636 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1637 cq->phase_change = false;
1638 cmd->cmd.cqe_count = (cq->len / cqe_size);
1639 } else {
1640 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1641 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1642 cq->phase_change = true;
1643 }
1644
cffce990 1645 cmd->cmd.pd_id = pd_id; /* valid only for v3 */
fe2caefc
PP		 1646 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1647 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1648 if (status)
1649 goto mbx_err;
1650
1651 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1652 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1653 kfree(cmd);
1654 return 0;
1655mbx_err:
1656 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1657 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1658mem_err:
1659 kfree(cmd);
1660 return status;
1661}
1662
1663int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1664{
1665 int status = -ENOMEM;
1666 struct ocrdma_destroy_cq *cmd;
1667
1668 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1669 if (!cmd)
1670 return status;
1671 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1672 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1673
1674 cmd->bypass_flush_qid |=
1675 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1676 OCRDMA_DESTROY_CQ_QID_MASK;
1677
fe2caefc 1678 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
ea617626 1679 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc 1680 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
fe2caefc
PP		 1681 kfree(cmd);
1682 return status;
1683}
1684
1685int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1686 u32 pdid, int addr_check)
1687{
1688 int status = -ENOMEM;
1689 struct ocrdma_alloc_lkey *cmd;
1690 struct ocrdma_alloc_lkey_rsp *rsp;
1691
1692 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1693 if (!cmd)
1694 return status;
1695 cmd->pdid = pdid;
1696 cmd->pbl_sz_flags |= addr_check;
1697 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1698 cmd->pbl_sz_flags |=
1699 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1700 cmd->pbl_sz_flags |=
1701 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1702 cmd->pbl_sz_flags |=
1703 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1704 cmd->pbl_sz_flags |=
1705 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1706 cmd->pbl_sz_flags |=
1707 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1708
1709 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1710 if (status)
1711 goto mbx_err;
1712 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1713 hwmr->lkey = rsp->lrkey;
1714mbx_err:
1715 kfree(cmd);
1716 return status;
1717}
1718
1719int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1720{
1721 int status = -ENOMEM;
1722 struct ocrdma_dealloc_lkey *cmd;
1723
1724 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1725 if (!cmd)
1726 return -ENOMEM;
1727 cmd->lkey = lkey;
1728 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1729 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1730 if (status)
1731 goto mbx_err;
1732mbx_err:
1733 kfree(cmd);
1734 return status;
1735}
1736
1737static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1738 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1739{
1740 int status = -ENOMEM;
1741 int i;
1742 struct ocrdma_reg_nsmr *cmd;
1743 struct ocrdma_reg_nsmr_rsp *rsp;
1744
1745 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1746 if (!cmd)
1747 return -ENOMEM;
1748 cmd->num_pbl_pdid =
1749 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
2b51a9b9 1750 cmd->fr_mr = hwmr->fr_mr;
fe2caefc
PP		 1751
1752 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1753 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1754 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1755 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1756 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1757 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1758 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1759 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1760 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1761 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1762 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1763
1764 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1765 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1766 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1767 cmd->totlen_low = hwmr->len;
1768 cmd->totlen_high = upper_32_bits(hwmr->len);
1769 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1770 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1771 cmd->va_loaddr = (u32) hwmr->va;
1772 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1773
1774 for (i = 0; i < pbl_cnt; i++) {
1775 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1776 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1777 }
1778 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1779 if (status)
1780 goto mbx_err;
1781 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1782 hwmr->lkey = rsp->lrkey;
1783mbx_err:
1784 kfree(cmd);
1785 return status;
1786}
1787
1788static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1789 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1790 u32 pbl_offset, u32 last)
1791{
1792 int status = -ENOMEM;
1793 int i;
1794 struct ocrdma_reg_nsmr_cont *cmd;
1795
1796 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1797 if (!cmd)
1798 return -ENOMEM;
1799 cmd->lrkey = hwmr->lkey;
1800 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1801 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1802 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1803
1804 for (i = 0; i < pbl_cnt; i++) {
1805 cmd->pbl[i].lo =
1806 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1807 cmd->pbl[i].hi =
1808 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1809 }
1810 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1811 if (status)
1812 goto mbx_err;
1813mbx_err:
1814 kfree(cmd);
1815 return status;
1816}
1817
1818int ocrdma_reg_mr(struct ocrdma_dev *dev,
1819 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1820{
1821 int status;
1822 u32 last = 0;
1823 u32 cur_pbl_cnt, pbl_offset;
1824 u32 pending_pbl_cnt = hwmr->num_pbls;
1825
1826 pbl_offset = 0;
1827 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1828 if (cur_pbl_cnt == pending_pbl_cnt)
1829 last = 1;
1830
1831 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1832 cur_pbl_cnt, hwmr->pbe_size, last);
1833 if (status) {
ef99c4c2 1834 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 1835 return status;
1836 }
1837 /* if there is no more pbls to register then exit. */
1838 if (last)
1839 return 0;
1840
1841 while (!last) {
1842 pbl_offset += cur_pbl_cnt;
1843 pending_pbl_cnt -= cur_pbl_cnt;
1844 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1845 /* if we reach the end of the pbls, then need to set the last
1846 * bit, indicating no more pbls to register for this memory key.
1847 */
1848 if (cur_pbl_cnt == pending_pbl_cnt)
1849 last = 1;
1850
1851 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1852 pbl_offset, last);
1853 if (status)
1854 break;
1855 }
1856 if (status)
ef99c4c2 1857 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 1858
1859 return status;
1860}
1861
1862bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1863{
1864 struct ocrdma_qp *tmp;
1865 bool found = false;
1866 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1867 if (qp == tmp) {
1868 found = true;
1869 break;
1870 }
1871 }
1872 return found;
1873}
1874
1875bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1876{
1877 struct ocrdma_qp *tmp;
1878 bool found = false;
1879 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1880 if (qp == tmp) {
1881 found = true;
1882 break;
1883 }
1884 }
1885 return found;
1886}
1887
1888void ocrdma_flush_qp(struct ocrdma_qp *qp)
1889{
1890 bool found;
1891 unsigned long flags;
1892
1893 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1894 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1895 if (!found)
1896 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1897 if (!qp->srq) {
1898 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1899 if (!found)
1900 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1901 }
1902 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1903}
1904
f11220ee
NG		 1905static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1906{
1907 qp->sq.head = 0;
1908 qp->sq.tail = 0;
1909 qp->rq.head = 0;
1910 qp->rq.tail = 0;
1911}
1912
057729cb
NG		 1913int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1914 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 1915{
1916 unsigned long flags;
1917 int status = 0;
1918 enum ocrdma_qp_state new_state;
1919 new_state = get_ocrdma_qp_state(new_ib_state);
1920
1921 /* sync with wqe and rqe posting */
1922 spin_lock_irqsave(&qp->q_lock, flags);
1923
1924 if (old_ib_state)
1925 *old_ib_state = get_ibqp_state(qp->state);
1926 if (new_state == qp->state) {
1927 spin_unlock_irqrestore(&qp->q_lock, flags);
1928 return 1;
1929 }
1930
057729cb 1931
f11220ee
NG		 1932 if (new_state == OCRDMA_QPS_INIT) {
1933 ocrdma_init_hwq_ptr(qp);
1934 ocrdma_del_flush_qp(qp);
1935 } else if (new_state == OCRDMA_QPS_ERR) {
057729cb 1936 ocrdma_flush_qp(qp);
f11220ee 1937 }
057729cb
NG		 1938
1939 qp->state = new_state;
fe2caefc
PP		 1940
1941 spin_unlock_irqrestore(&qp->q_lock, flags);
1942 return status;
1943}
1944
1945static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1946{
1947 u32 flags = 0;
1948 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1949 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1950 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1951 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1952 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1953 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1954 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1955 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1956 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1957 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1958 return flags;
1959}
1960
1961static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1962 struct ib_qp_init_attr *attrs,
1963 struct ocrdma_qp *qp)
1964{
1965 int status;
1966 u32 len, hw_pages, hw_page_size;
1967 dma_addr_t pa;
1968 struct ocrdma_dev *dev = qp->dev;
1969 struct pci_dev *pdev = dev->nic_info.pdev;
1970 u32 max_wqe_allocated;
1971 u32 max_sges = attrs->cap.max_send_sge;
1972
43a6b402 1973 /* QP1 may exceed 127 */
6ebacdfc 1974 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
43a6b402 1975 dev->attr.max_wqe);
fe2caefc
PP		 1976
1977 status = ocrdma_build_q_conf(&max_wqe_allocated,
1978 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1979 if (status) {
ef99c4c2
NG		 1980 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1981 max_wqe_allocated);
fe2caefc
PP		 1982 return -EINVAL;
1983 }
1984 qp->sq.max_cnt = max_wqe_allocated;
1985 len = (hw_pages * hw_page_size);
1986
1987 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1988 if (!qp->sq.va)
1989 return -EINVAL;
1990 memset(qp->sq.va, 0, len);
1991 qp->sq.len = len;
1992 qp->sq.pa = pa;
1993 qp->sq.entry_size = dev->attr.wqe_size;
1994 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1995
1996 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1997 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1998 cmd->num_wq_rq_pages |= (hw_pages <<
1999 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2000 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2001 cmd->max_sge_send_write |= (max_sges <<
2002 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2003 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2004 cmd->max_sge_send_write |= (max_sges <<
2005 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2006 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2007 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2008 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2009 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2010 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2011 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2012 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2013 return 0;
2014}
2015
2016static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2017 struct ib_qp_init_attr *attrs,
2018 struct ocrdma_qp *qp)
2019{
2020 int status;
2021 u32 len, hw_pages, hw_page_size;
2022 dma_addr_t pa = 0;
2023 struct ocrdma_dev *dev = qp->dev;
2024 struct pci_dev *pdev = dev->nic_info.pdev;
2025 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2026
2027 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2028 &hw_pages, &hw_page_size);
2029 if (status) {
ef99c4c2
NG		 2030 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2031 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 2032 return status;
2033 }
2034 qp->rq.max_cnt = max_rqe_allocated;
2035 len = (hw_pages * hw_page_size);
2036
2037 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2038 if (!qp->rq.va)
c94e15c5 2039 return -ENOMEM;
fe2caefc
PP		 2040 memset(qp->rq.va, 0, len);
2041 qp->rq.pa = pa;
2042 qp->rq.len = len;
2043 qp->rq.entry_size = dev->attr.rqe_size;
2044
2045 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2046 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2047 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2048 cmd->num_wq_rq_pages |=
2049 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2050 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2051 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2052 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2053 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2054 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2055 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2056 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2057 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2058 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2059 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2060 return 0;
2061}
2062
2063static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2064 struct ocrdma_pd *pd,
2065 struct ocrdma_qp *qp,
2066 u8 enable_dpp_cq, u16 dpp_cq_id)
2067{
2068 pd->num_dpp_qp--;
2069 qp->dpp_enabled = true;
2070 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2071 if (!enable_dpp_cq)
2072 return;
2073 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2074 cmd->dpp_credits_cqid = dpp_cq_id;
2075 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2076 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2077}
2078
2079static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2080 struct ocrdma_qp *qp)
2081{
2082 struct ocrdma_dev *dev = qp->dev;
2083 struct pci_dev *pdev = dev->nic_info.pdev;
2084 dma_addr_t pa = 0;
2085 int ird_page_size = dev->attr.ird_page_size;
2086 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
43a6b402
NG		 2087 struct ocrdma_hdr_wqe *rqe;
2088 int i = 0;
fe2caefc
PP		 2089
2090 if (dev->attr.ird == 0)
2091 return 0;
2092
2093 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2094 &pa, GFP_KERNEL);
2095 if (!qp->ird_q_va)
2096 return -ENOMEM;
2097 memset(qp->ird_q_va, 0, ird_q_len);
2098 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2099 pa, ird_page_size);
43a6b402
NG		 2100 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2101 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2102 (i * dev->attr.rqe_size));
2103 rqe->cw = 0;
2104 rqe->cw |= 2;
2105 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2106 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2107 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2108 }
fe2caefc
PP		 2109 return 0;
2110}
2111
2112static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2113 struct ocrdma_qp *qp,
2114 struct ib_qp_init_attr *attrs,
2115 u16 *dpp_offset, u16 *dpp_credit_lmt)
2116{
2117 u32 max_wqe_allocated, max_rqe_allocated;
2118 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2119 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2120 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2121 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2122 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2123 qp->dpp_enabled = false;
2124 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2125 qp->dpp_enabled = true;
2126 *dpp_credit_lmt = (rsp->dpp_response &
2127 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2128 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2129 *dpp_offset = (rsp->dpp_response &
2130 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2131 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2132 }
2133 max_wqe_allocated =
2134 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2135 max_wqe_allocated = 1 << max_wqe_allocated;
2136 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2137
fe2caefc
PP		 2138 qp->sq.max_cnt = max_wqe_allocated;
2139 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2140
2141 if (!attrs->srq) {
2142 qp->rq.max_cnt = max_rqe_allocated;
2143 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 2144 }
2145}
2146
2147int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2148 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2149 u16 *dpp_credit_lmt)
2150{
2151 int status = -ENOMEM;
2152 u32 flags = 0;
2153 struct ocrdma_dev *dev = qp->dev;
2154 struct ocrdma_pd *pd = qp->pd;
2155 struct pci_dev *pdev = dev->nic_info.pdev;
2156 struct ocrdma_cq *cq;
2157 struct ocrdma_create_qp_req *cmd;
2158 struct ocrdma_create_qp_rsp *rsp;
2159 int qptype;
2160
2161 switch (attrs->qp_type) {
2162 case IB_QPT_GSI:
2163 qptype = OCRDMA_QPT_GSI;
2164 break;
2165 case IB_QPT_RC:
2166 qptype = OCRDMA_QPT_RC;
2167 break;
2168 case IB_QPT_UD:
2169 qptype = OCRDMA_QPT_UD;
2170 break;
2171 default:
2172 return -EINVAL;
2b50176d 2173 }
fe2caefc
PP		 2174
2175 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2176 if (!cmd)
2177 return status;
2178 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2179 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2180 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2181 if (status)
2182 goto sq_err;
2183
2184 if (attrs->srq) {
2185 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2186 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2187 cmd->rq_addr[0].lo = srq->id;
2188 qp->srq = srq;
2189 } else {
2190 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2191 if (status)
2192 goto rq_err;
2193 }
2194
2195 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2196 if (status)
2197 goto mbx_err;
2198
2199 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2200 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2201
2202 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2203
2204 cmd->max_sge_recv_flags |= flags;
2205 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2206 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2207 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2208 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2209 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2210 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2211 cq = get_ocrdma_cq(attrs->send_cq);
2212 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2213 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2214 qp->sq_cq = cq;
2215 cq = get_ocrdma_cq(attrs->recv_cq);
2216 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2217 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2218 qp->rq_cq = cq;
2219
f50f31e4
DS		 2220 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2221 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
fe2caefc
PP		 2222 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2223 dpp_cq_id);
f99b1649 2224 }
fe2caefc
PP		 2225
2226 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2227 if (status)
2228 goto mbx_err;
2229 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2230 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2231 qp->state = OCRDMA_QPS_RST;
2232 kfree(cmd);
2233 return 0;
2234mbx_err:
2235 if (qp->rq.va)
2236 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2237rq_err:
ef99c4c2 2238 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 2239 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2240sq_err:
ef99c4c2 2241 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 2242 kfree(cmd);
2243 return status;
2244}
2245
2246int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2247 struct ocrdma_qp_params *param)
2248{
2249 int status = -ENOMEM;
2250 struct ocrdma_query_qp *cmd;
2251 struct ocrdma_query_qp_rsp *rsp;
2252
2253 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2254 if (!cmd)
2255 return status;
2256 cmd->qp_id = qp->id;
2257 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2258 if (status)
2259 goto mbx_err;
2260 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2261 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2262mbx_err:
2263 kfree(cmd);
2264 return status;
2265}
2266
f99b1649 2267static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc
PP		 2268 struct ocrdma_modify_qp *cmd,
2269 struct ib_qp_attr *attrs)
2270{
f99b1649 2271 int status;
fe2caefc 2272 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2273 union ib_gid sgid, zgid;
fe2caefc
PP		 2274 u32 vlan_id;
2275 u8 mac_addr[6];
9c58726b 2276
fe2caefc 2277 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
f99b1649 2278 return -EINVAL;
31dbdd9a
SX		 2279 if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2280 ocrdma_init_service_level(qp->dev);
fe2caefc
PP		 2281 cmd->params.tclass_sq_psn |=
2282 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2283 cmd->params.rnt_rc_sl_fl |=
2284 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2b51a9b9 2285 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
fe2caefc
PP		 2286 cmd->params.hop_lmt_rq_psn |=
2287 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2288 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2289 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2290 sizeof(cmd->params.dgid));
f99b1649 2291 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
fad51b7d 2292 ah_attr->grh.sgid_index, &sgid);
f99b1649
NG		 2293 if (status)
2294 return status;
9c58726b
NG		 2295
2296 memset(&zgid, 0, sizeof(zgid));
2297 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2298 return -EINVAL;
2299
fe2caefc
PP		 2300 qp->sgid_idx = ah_attr->grh.sgid_index;
2301 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
40aca6ff 2302 ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
fe2caefc
PP		 2303 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2304 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2305 /* convert them to LE format. */
2306 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2307 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2308 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
40aca6ff 2309 vlan_id = ah_attr->vlan_id;
fe2caefc
PP		 2310 if (vlan_id && (vlan_id < 0x1000)) {
2311 cmd->params.vlan_dmac_b4_to_b5 |=
2312 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2313 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
31dbdd9a
SX		 2314 /* override the sl with default priority if 0 */
2315 cmd->params.rnt_rc_sl_fl |=
2316 (ah_attr->sl ? ah_attr->sl :
2317 qp->dev->sl) << OCRDMA_QP_PARAMS_SL_SHIFT;
fe2caefc 2318 }
f99b1649 2319 return 0;
fe2caefc
PP		 2320}
2321
2322static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2323 struct ocrdma_modify_qp *cmd,
bc1b04ab 2324 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2325{
2326 int status = 0;
fe2caefc
PP		 2327
2328 if (attr_mask & IB_QP_PKEY_INDEX) {
2329 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2330 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2331 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2332 }
2333 if (attr_mask & IB_QP_QKEY) {
2334 qp->qkey = attrs->qkey;
2335 cmd->params.qkey = attrs->qkey;
2336 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2337 }
f99b1649
NG		 2338 if (attr_mask & IB_QP_AV) {
2339 status = ocrdma_set_av_params(qp, cmd, attrs);
2340 if (status)
2341 return status;
2342 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc
PP		 2343 /* set the default mac address for UD, GSI QPs */
2344 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2345 (qp->dev->nic_info.mac_addr[1] << 8) |
2346 (qp->dev->nic_info.mac_addr[2] << 16) |
2347 (qp->dev->nic_info.mac_addr[3] << 24);
2348 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2349 (qp->dev->nic_info.mac_addr[5] << 8);
2350 }
2351 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2352 attrs->en_sqd_async_notify) {
2353 cmd->params.max_sge_recv_flags |=
2354 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2355 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2356 }
2357 if (attr_mask & IB_QP_DEST_QPN) {
2358 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2359 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2360 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2361 }
2362 if (attr_mask & IB_QP_PATH_MTU) {
d3cb6c0b
NG		 2363 if (attrs->path_mtu < IB_MTU_256 ||
2364 attrs->path_mtu > IB_MTU_4096) {
fe2caefc
PP		 2365 status = -EINVAL;
2366 goto pmtu_err;
2367 }
2368 cmd->params.path_mtu_pkey_indx |=
2369 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2370 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2371 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2372 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2373 }
2374 if (attr_mask & IB_QP_TIMEOUT) {
2375 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2376 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2377 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2378 }
2379 if (attr_mask & IB_QP_RETRY_CNT) {
2380 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2381 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2382 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2383 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2384 }
2385 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2386 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2387 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2388 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2389 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2390 }
2391 if (attr_mask & IB_QP_RNR_RETRY) {
2392 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2393 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2394 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2395 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2396 }
2397 if (attr_mask & IB_QP_SQ_PSN) {
2398 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2399 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2400 }
2401 if (attr_mask & IB_QP_RQ_PSN) {
2402 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2403 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2404 }
2405 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2406 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2407 status = -EINVAL;
2408 goto pmtu_err;
2409 }
2410 qp->max_ord = attrs->max_rd_atomic;
2411 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2412 }
2413 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2414 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2415 status = -EINVAL;
2416 goto pmtu_err;
2417 }
2418 qp->max_ird = attrs->max_dest_rd_atomic;
2419 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2420 }
2421 cmd->params.max_ord_ird = (qp->max_ord <<
2422 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2423 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2424pmtu_err:
2425 return status;
2426}
2427
2428int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
bc1b04ab 2429 struct ib_qp_attr *attrs, int attr_mask)
fe2caefc
PP		 2430{
2431 int status = -ENOMEM;
2432 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2433
2434 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2435 if (!cmd)
2436 return status;
2437
2438 cmd->params.id = qp->id;
2439 cmd->flags = 0;
2440 if (attr_mask & IB_QP_STATE) {
2441 cmd->params.max_sge_recv_flags |=
2442 (get_ocrdma_qp_state(attrs->qp_state) <<
2443 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2444 OCRDMA_QP_PARAMS_STATE_MASK;
2445 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2446 } else {
fe2caefc
PP		 2447 cmd->params.max_sge_recv_flags |=
2448 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2449 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2450 }
2451
bc1b04ab 2452 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
fe2caefc
PP		 2453 if (status)
2454 goto mbx_err;
2455 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2456 if (status)
2457 goto mbx_err;
c592c423 2458
fe2caefc
PP		 2459mbx_err:
2460 kfree(cmd);
2461 return status;
2462}
2463
2464int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2465{
2466 int status = -ENOMEM;
2467 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2468 struct pci_dev *pdev = dev->nic_info.pdev;
2469
2470 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2471 if (!cmd)
2472 return status;
2473 cmd->qp_id = qp->id;
2474 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2475 if (status)
2476 goto mbx_err;
c592c423 2477
fe2caefc
PP		 2478mbx_err:
2479 kfree(cmd);
2480 if (qp->sq.va)
2481 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2482 if (!qp->srq && qp->rq.va)
2483 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2484 if (qp->dpp_enabled)
2485 qp->pd->num_dpp_qp++;
2486 return status;
2487}
2488
1afc0454 2489int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2490 struct ib_srq_init_attr *srq_attr,
2491 struct ocrdma_pd *pd)
2492{
2493 int status = -ENOMEM;
2494 int hw_pages, hw_page_size;
2495 int len;
2496 struct ocrdma_create_srq_rsp *rsp;
2497 struct ocrdma_create_srq *cmd;
2498 dma_addr_t pa;
fe2caefc
PP		 2499 struct pci_dev *pdev = dev->nic_info.pdev;
2500 u32 max_rqe_allocated;
2501
2502 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2503 if (!cmd)
2504 return status;
2505
2506 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2507 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2508 status = ocrdma_build_q_conf(&max_rqe_allocated,
2509 dev->attr.rqe_size,
2510 &hw_pages, &hw_page_size);
2511 if (status) {
ef99c4c2
NG		 2512 pr_err("%s() req. max_wr=0x%x\n", __func__,
2513 srq_attr->attr.max_wr);
fe2caefc
PP		 2514 status = -EINVAL;
2515 goto ret;
2516 }
2517 len = hw_pages * hw_page_size;
2518 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2519 if (!srq->rq.va) {
2520 status = -ENOMEM;
2521 goto ret;
2522 }
2523 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2524
2525 srq->rq.entry_size = dev->attr.rqe_size;
2526 srq->rq.pa = pa;
2527 srq->rq.len = len;
2528 srq->rq.max_cnt = max_rqe_allocated;
2529
2530 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2531 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2532 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2533
2534 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2535 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2536 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2537 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2538 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2539 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2540
2541 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2542 if (status)
2543 goto mbx_err;
2544 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2545 srq->id = rsp->id;
2546 srq->rq.dbid = rsp->id;
2547 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2548 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2549 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2550 max_rqe_allocated = (1 << max_rqe_allocated);
2551 srq->rq.max_cnt = max_rqe_allocated;
2552 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2553 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2554 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2555 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2556 goto ret;
2557mbx_err:
2558 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2559ret:
2560 kfree(cmd);
2561 return status;
2562}
2563
2564int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2565{
2566 int status = -ENOMEM;
2567 struct ocrdma_modify_srq *cmd;
f11220ee
NG		 2568 struct ocrdma_pd *pd = srq->pd;
2569 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
1afc0454 2570
d7e19c0a 2571 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2572 if (!cmd)
2573 return status;
2574 cmd->id = srq->id;
2575 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2576 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2577 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2578 kfree(cmd);
2579 return status;
2580}
2581
2582int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2583{
2584 int status = -ENOMEM;
2585 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2586 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2587
d7e19c0a 2588 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
fe2caefc
PP		 2589 if (!cmd)
2590 return status;
2591 cmd->id = srq->rq.dbid;
1afc0454 2592 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2593 if (status == 0) {
2594 struct ocrdma_query_srq_rsp *rsp =
2595 (struct ocrdma_query_srq_rsp *)cmd;
2596 srq_attr->max_sge =
2597 rsp->srq_lmt_max_sge &
2598 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2599 srq_attr->max_wr =
2600 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2601 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2602 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2603 }
2604 kfree(cmd);
2605 return status;
2606}
2607
2608int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2609{
2610 int status = -ENOMEM;
2611 struct ocrdma_destroy_srq *cmd;
2612 struct pci_dev *pdev = dev->nic_info.pdev;
2613 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2614 if (!cmd)
2615 return status;
2616 cmd->id = srq->id;
1afc0454 2617 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2618 if (srq->rq.va)
2619 dma_free_coherent(&pdev->dev, srq->rq.len,
2620 srq->rq.va, srq->rq.pa);
2621 kfree(cmd);
2622 return status;
2623}
2624
31dbdd9a
SX		 2625static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2626 struct ocrdma_dcbx_cfg *dcbxcfg)
2627{
2628 int status = 0;
2629 dma_addr_t pa;
2630 struct ocrdma_mqe cmd;
2631
2632 struct ocrdma_get_dcbx_cfg_req *req = NULL;
2633 struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2634 struct pci_dev *pdev = dev->nic_info.pdev;
2635 struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2636
2637 memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2638 cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2639 sizeof(struct ocrdma_get_dcbx_cfg_req));
2640 req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2641 if (!req) {
2642 status = -ENOMEM;
2643 goto mem_err;
2644 }
2645
2646 cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2647 OCRDMA_MQE_HDR_SGE_CNT_MASK;
2648 mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2649 mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2650 mqe_sge->len = cmd.hdr.pyld_len;
2651
2652 memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2653 ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2654 OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2655 req->param_type = ptype;
2656
2657 status = ocrdma_mbx_cmd(dev, &cmd);
2658 if (status)
2659 goto mbx_err;
2660
2661 rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2662 ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2663 memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2664
2665mbx_err:
2666 dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2667mem_err:
2668 return status;
2669}
2670
2671#define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2672#define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2673
2674static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2675 struct ocrdma_dcbx_cfg *dcbxcfg,
2676 u8 *srvc_lvl)
2677{
2678 int status = -EINVAL, indx, slindx;
2679 int ventry_cnt;
2680 struct ocrdma_app_parameter *app_param;
2681 u8 valid, proto_sel;
2682 u8 app_prio, pfc_prio;
2683 u16 proto;
2684
2685 if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2686 pr_info("%s ocrdma%d DCBX is disabled\n",
2687 dev_name(&dev->nic_info.pdev->dev), dev->id);
2688 goto out;
2689 }
2690
2691 if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2692 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2693 dev_name(&dev->nic_info.pdev->dev), dev->id,
2694 (ptype > 0 ? "operational" : "admin"),
2695 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2696 "enabled" : "disabled",
2697 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2698 "" : ", not sync'ed");
2699 goto out;
2700 } else {
2701 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2702 dev_name(&dev->nic_info.pdev->dev), dev->id);
2703 }
2704
2705 ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2706 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2707 & OCRDMA_DCBX_STATE_MASK;
2708
2709 for (indx = 0; indx < ventry_cnt; indx++) {
2710 app_param = &dcbxcfg->app_param[indx];
2711 valid = (app_param->valid_proto_app >>
2712 OCRDMA_APP_PARAM_VALID_SHIFT)
2713 & OCRDMA_APP_PARAM_VALID_MASK;
2714 proto_sel = (app_param->valid_proto_app
2715 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2716 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2717 proto = app_param->valid_proto_app &
2718 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2719
2720 if (
2721 valid && proto == OCRDMA_APP_PROTO_ROCE &&
2722 proto_sel == OCRDMA_PROTO_SELECT_L2) {
2723 for (slindx = 0; slindx <
2724 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2725 app_prio = ocrdma_get_app_prio(
2726 (u8 *)app_param->app_prio,
2727 slindx);
2728 pfc_prio = ocrdma_get_pfc_prio(
2729 (u8 *)dcbxcfg->pfc_prio,
2730 slindx);
2731
2732 if (app_prio && pfc_prio) {
2733 *srvc_lvl = slindx;
2734 status = 0;
2735 goto out;
2736 }
2737 }
2738 if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2739 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2740 dev_name(&dev->nic_info.pdev->dev),
2741 dev->id, proto);
2742 }
2743 }
2744 }
2745
2746out:
2747 return status;
2748}
2749
2750void ocrdma_init_service_level(struct ocrdma_dev *dev)
2751{
2752 int status = 0, indx;
2753 struct ocrdma_dcbx_cfg dcbxcfg;
2754 u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2755 int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2756
2757 for (indx = 0; indx < 2; indx++) {
2758 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2759 if (status) {
2760 pr_err("%s(): status=%d\n", __func__, status);
2761 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2762 continue;
2763 }
2764
2765 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2766 &dcbxcfg, &srvc_lvl);
2767 if (status) {
2768 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2769 continue;
2770 }
2771
2772 break;
2773 }
2774
2775 if (status)
2776 pr_info("%s ocrdma%d service level default\n",
2777 dev_name(&dev->nic_info.pdev->dev), dev->id);
2778 else
2779 pr_info("%s ocrdma%d service level %d\n",
2780 dev_name(&dev->nic_info.pdev->dev), dev->id,
2781 srvc_lvl);
2782
2783 dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2784 dev->sl = srvc_lvl;
2785}
2786
fe2caefc
PP		 2787int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2788{
2789 int i;
2790 int status = -EINVAL;
2791 struct ocrdma_av *av;
2792 unsigned long flags;
2793
2794 av = dev->av_tbl.va;
2795 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2796 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2797 if (av->valid == 0) {
2798 av->valid = OCRDMA_AV_VALID;
2799 ah->av = av;
2800 ah->id = i;
2801 status = 0;
2802 break;
2803 }
2804 av++;
2805 }
2806 if (i == dev->av_tbl.num_ah)
2807 status = -EAGAIN;
2808 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2809 return status;
2810}
2811
2812int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2813{
2814 unsigned long flags;
2815 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2816 ah->av->valid = 0;
2817 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2818 return 0;
2819}
2820
c88bd03f 2821static int ocrdma_create_eqs(struct ocrdma_dev *dev)
fe2caefc 2822{
da496438 2823 int num_eq, i, status = 0;
fe2caefc
PP		 2824 int irq;
2825 unsigned long flags = 0;
2826
2827 num_eq = dev->nic_info.msix.num_vectors -
2828 dev->nic_info.msix.start_vector;
2829 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2830 num_eq = 1;
2831 flags = IRQF_SHARED;
f99b1649 2832 } else {
fe2caefc 2833 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 2834 }
2835
c88bd03f
NG		 2836 if (!num_eq)
2837 return -EINVAL;
2838
2839 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2840 if (!dev->eq_tbl)
fe2caefc
PP		 2841 return -ENOMEM;
2842
2843 for (i = 0; i < num_eq; i++) {
c88bd03f 2844 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
fad51b7d 2845 OCRDMA_EQ_LEN);
fe2caefc
PP		 2846 if (status) {
2847 status = -EINVAL;
2848 break;
2849 }
c88bd03f 2850 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
fe2caefc 2851 dev->id, i);
c88bd03f 2852 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
fe2caefc 2853 status = request_irq(irq, ocrdma_irq_handler, flags,
c88bd03f
NG		 2854 dev->eq_tbl[i].irq_name,
2855 &dev->eq_tbl[i]);
2856 if (status)
2857 goto done;
fe2caefc
PP		 2858 dev->eq_cnt += 1;
2859 }
2860 /* one eq is sufficient for data path to work */
c88bd03f
NG		 2861 return 0;
2862done:
2863 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2864 return status;
2865}
2866
2867int ocrdma_init_hw(struct ocrdma_dev *dev)
2868{
2869 int status;
c88bd03f
NG		 2870
2871 /* create the eqs */
2872 status = ocrdma_create_eqs(dev);
fe2caefc
PP		 2873 if (status)
2874 goto qpeq_err;
2875 status = ocrdma_create_mq(dev);
2876 if (status)
2877 goto mq_err;
2878 status = ocrdma_mbx_query_fw_config(dev);
2879 if (status)
2880 goto conf_err;
2881 status = ocrdma_mbx_query_dev(dev);
2882 if (status)
2883 goto conf_err;
2884 status = ocrdma_mbx_query_fw_ver(dev);
2885 if (status)
2886 goto conf_err;
2887 status = ocrdma_mbx_create_ah_tbl(dev);
2888 if (status)
2889 goto conf_err;
a51f06e1
SX		 2890 status = ocrdma_mbx_get_phy_info(dev);
2891 if (status)
daac9681 2892 goto info_attrb_err;
a51f06e1
SX		 2893 status = ocrdma_mbx_get_ctrl_attribs(dev);
2894 if (status)
daac9681 2895 goto info_attrb_err;
a51f06e1 2896
fe2caefc
PP		 2897 return 0;
2898
daac9681
DS		 2899info_attrb_err:
2900 ocrdma_mbx_delete_ah_tbl(dev);
fe2caefc
PP		 2901conf_err:
2902 ocrdma_destroy_mq(dev);
2903mq_err:
c88bd03f 2904 ocrdma_destroy_eqs(dev);
fe2caefc 2905qpeq_err:
ef99c4c2 2906 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2907 return status;
2908}
2909
2910void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2911{
2912 ocrdma_mbx_delete_ah_tbl(dev);
2913
c88bd03f
NG		 2914 /* cleanup the eqs */
2915 ocrdma_destroy_eqs(dev);
fe2caefc
PP		 2916
2917 /* cleanup the control path */
2918 ocrdma_destroy_mq(dev);
fe2caefc 2919}
Linux kernel - Deliverables
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