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f931551b RC |
1 | /* |
2 | * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved. | |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/spinlock.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/io.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/vmalloc.h> | |
e4dd23d7 | 40 | #include <linux/module.h> |
f931551b RC |
41 | |
42 | #include "qib.h" | |
43 | ||
44 | /* | |
45 | * The size has to be longer than this string, so we can append | |
46 | * board/chip information to it in the init code. | |
47 | */ | |
48 | const char ib_qib_version[] = QIB_IDSTR "\n"; | |
49 | ||
50 | DEFINE_SPINLOCK(qib_devs_lock); | |
51 | LIST_HEAD(qib_dev_list); | |
52 | DEFINE_MUTEX(qib_mutex); /* general driver use */ | |
53 | ||
54 | unsigned qib_ibmtu; | |
55 | module_param_named(ibmtu, qib_ibmtu, uint, S_IRUGO); | |
56 | MODULE_PARM_DESC(ibmtu, "Set max IB MTU (0=2KB, 1=256, 2=512, ... 5=4096"); | |
57 | ||
58 | unsigned qib_compat_ddr_negotiate = 1; | |
59 | module_param_named(compat_ddr_negotiate, qib_compat_ddr_negotiate, uint, | |
60 | S_IWUSR | S_IRUGO); | |
61 | MODULE_PARM_DESC(compat_ddr_negotiate, | |
62 | "Attempt pre-IBTA 1.2 DDR speed negotiation"); | |
63 | ||
64 | MODULE_LICENSE("Dual BSD/GPL"); | |
65 | MODULE_AUTHOR("QLogic <support@qlogic.com>"); | |
66 | MODULE_DESCRIPTION("QLogic IB driver"); | |
67 | ||
68 | /* | |
69 | * QIB_PIO_MAXIBHDR is the max IB header size allowed for in our | |
70 | * PIO send buffers. This is well beyond anything currently | |
71 | * defined in the InfiniBand spec. | |
72 | */ | |
73 | #define QIB_PIO_MAXIBHDR 128 | |
74 | ||
aa7374ac MM |
75 | /* |
76 | * QIB_MAX_PKT_RCV is the max # if packets processed per receive interrupt. | |
77 | */ | |
78 | #define QIB_MAX_PKT_RECV 64 | |
79 | ||
f931551b RC |
80 | struct qlogic_ib_stats qib_stats; |
81 | ||
82 | const char *qib_get_unit_name(int unit) | |
83 | { | |
84 | static char iname[16]; | |
85 | ||
86 | snprintf(iname, sizeof iname, "infinipath%u", unit); | |
87 | return iname; | |
88 | } | |
89 | ||
90 | /* | |
91 | * Return count of units with at least one port ACTIVE. | |
92 | */ | |
93 | int qib_count_active_units(void) | |
94 | { | |
95 | struct qib_devdata *dd; | |
96 | struct qib_pportdata *ppd; | |
97 | unsigned long flags; | |
98 | int pidx, nunits_active = 0; | |
99 | ||
100 | spin_lock_irqsave(&qib_devs_lock, flags); | |
101 | list_for_each_entry(dd, &qib_dev_list, list) { | |
102 | if (!(dd->flags & QIB_PRESENT) || !dd->kregbase) | |
103 | continue; | |
104 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
105 | ppd = dd->pport + pidx; | |
106 | if (ppd->lid && (ppd->lflags & (QIBL_LINKINIT | | |
107 | QIBL_LINKARMED | QIBL_LINKACTIVE))) { | |
108 | nunits_active++; | |
109 | break; | |
110 | } | |
111 | } | |
112 | } | |
113 | spin_unlock_irqrestore(&qib_devs_lock, flags); | |
114 | return nunits_active; | |
115 | } | |
116 | ||
117 | /* | |
118 | * Return count of all units, optionally return in arguments | |
119 | * the number of usable (present) units, and the number of | |
120 | * ports that are up. | |
121 | */ | |
122 | int qib_count_units(int *npresentp, int *nupp) | |
123 | { | |
124 | int nunits = 0, npresent = 0, nup = 0; | |
125 | struct qib_devdata *dd; | |
126 | unsigned long flags; | |
127 | int pidx; | |
128 | struct qib_pportdata *ppd; | |
129 | ||
130 | spin_lock_irqsave(&qib_devs_lock, flags); | |
131 | ||
132 | list_for_each_entry(dd, &qib_dev_list, list) { | |
133 | nunits++; | |
134 | if ((dd->flags & QIB_PRESENT) && dd->kregbase) | |
135 | npresent++; | |
136 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
137 | ppd = dd->pport + pidx; | |
138 | if (ppd->lid && (ppd->lflags & (QIBL_LINKINIT | | |
139 | QIBL_LINKARMED | QIBL_LINKACTIVE))) | |
140 | nup++; | |
141 | } | |
142 | } | |
143 | ||
144 | spin_unlock_irqrestore(&qib_devs_lock, flags); | |
145 | ||
146 | if (npresentp) | |
147 | *npresentp = npresent; | |
148 | if (nupp) | |
149 | *nupp = nup; | |
150 | ||
151 | return nunits; | |
152 | } | |
153 | ||
154 | /** | |
155 | * qib_wait_linkstate - wait for an IB link state change to occur | |
156 | * @dd: the qlogic_ib device | |
157 | * @state: the state to wait for | |
158 | * @msecs: the number of milliseconds to wait | |
159 | * | |
160 | * wait up to msecs milliseconds for IB link state change to occur for | |
161 | * now, take the easy polling route. Currently used only by | |
162 | * qib_set_linkstate. Returns 0 if state reached, otherwise | |
163 | * -ETIMEDOUT state can have multiple states set, for any of several | |
164 | * transitions. | |
165 | */ | |
166 | int qib_wait_linkstate(struct qib_pportdata *ppd, u32 state, int msecs) | |
167 | { | |
168 | int ret; | |
169 | unsigned long flags; | |
170 | ||
171 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
172 | if (ppd->state_wanted) { | |
173 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
174 | ret = -EBUSY; | |
175 | goto bail; | |
176 | } | |
177 | ppd->state_wanted = state; | |
178 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
179 | wait_event_interruptible_timeout(ppd->state_wait, | |
180 | (ppd->lflags & state), | |
181 | msecs_to_jiffies(msecs)); | |
182 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
183 | ppd->state_wanted = 0; | |
184 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
185 | ||
186 | if (!(ppd->lflags & state)) | |
187 | ret = -ETIMEDOUT; | |
188 | else | |
189 | ret = 0; | |
190 | bail: | |
191 | return ret; | |
192 | } | |
193 | ||
194 | int qib_set_linkstate(struct qib_pportdata *ppd, u8 newstate) | |
195 | { | |
196 | u32 lstate; | |
197 | int ret; | |
198 | struct qib_devdata *dd = ppd->dd; | |
199 | unsigned long flags; | |
200 | ||
201 | switch (newstate) { | |
202 | case QIB_IB_LINKDOWN_ONLY: | |
203 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, | |
204 | IB_LINKCMD_DOWN | IB_LINKINITCMD_NOP); | |
205 | /* don't wait */ | |
206 | ret = 0; | |
207 | goto bail; | |
208 | ||
209 | case QIB_IB_LINKDOWN: | |
210 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, | |
211 | IB_LINKCMD_DOWN | IB_LINKINITCMD_POLL); | |
212 | /* don't wait */ | |
213 | ret = 0; | |
214 | goto bail; | |
215 | ||
216 | case QIB_IB_LINKDOWN_SLEEP: | |
217 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, | |
218 | IB_LINKCMD_DOWN | IB_LINKINITCMD_SLEEP); | |
219 | /* don't wait */ | |
220 | ret = 0; | |
221 | goto bail; | |
222 | ||
223 | case QIB_IB_LINKDOWN_DISABLE: | |
224 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, | |
225 | IB_LINKCMD_DOWN | IB_LINKINITCMD_DISABLE); | |
226 | /* don't wait */ | |
227 | ret = 0; | |
228 | goto bail; | |
229 | ||
230 | case QIB_IB_LINKARM: | |
231 | if (ppd->lflags & QIBL_LINKARMED) { | |
232 | ret = 0; | |
233 | goto bail; | |
234 | } | |
235 | if (!(ppd->lflags & (QIBL_LINKINIT | QIBL_LINKACTIVE))) { | |
236 | ret = -EINVAL; | |
237 | goto bail; | |
238 | } | |
239 | /* | |
240 | * Since the port can be ACTIVE when we ask for ARMED, | |
241 | * clear QIBL_LINKV so we can wait for a transition. | |
242 | * If the link isn't ARMED, then something else happened | |
243 | * and there is no point waiting for ARMED. | |
244 | */ | |
245 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
246 | ppd->lflags &= ~QIBL_LINKV; | |
247 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
248 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, | |
249 | IB_LINKCMD_ARMED | IB_LINKINITCMD_NOP); | |
250 | lstate = QIBL_LINKV; | |
251 | break; | |
252 | ||
253 | case QIB_IB_LINKACTIVE: | |
254 | if (ppd->lflags & QIBL_LINKACTIVE) { | |
255 | ret = 0; | |
256 | goto bail; | |
257 | } | |
258 | if (!(ppd->lflags & QIBL_LINKARMED)) { | |
259 | ret = -EINVAL; | |
260 | goto bail; | |
261 | } | |
262 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, | |
263 | IB_LINKCMD_ACTIVE | IB_LINKINITCMD_NOP); | |
264 | lstate = QIBL_LINKACTIVE; | |
265 | break; | |
266 | ||
267 | default: | |
268 | ret = -EINVAL; | |
269 | goto bail; | |
270 | } | |
271 | ret = qib_wait_linkstate(ppd, lstate, 10); | |
272 | ||
273 | bail: | |
274 | return ret; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Get address of eager buffer from it's index (allocated in chunks, not | |
279 | * contiguous). | |
280 | */ | |
281 | static inline void *qib_get_egrbuf(const struct qib_ctxtdata *rcd, u32 etail) | |
282 | { | |
9e1c0e43 MM |
283 | const u32 chunk = etail >> rcd->rcvegrbufs_perchunk_shift; |
284 | const u32 idx = etail & ((u32)rcd->rcvegrbufs_perchunk - 1); | |
f931551b | 285 | |
9e1c0e43 | 286 | return rcd->rcvegrbuf[chunk] + (idx << rcd->dd->rcvegrbufsize_shift); |
f931551b RC |
287 | } |
288 | ||
289 | /* | |
290 | * Returns 1 if error was a CRC, else 0. | |
291 | * Needed for some chip's synthesized error counters. | |
292 | */ | |
994bcd28 MM |
293 | static u32 qib_rcv_hdrerr(struct qib_ctxtdata *rcd, struct qib_pportdata *ppd, |
294 | u32 ctxt, u32 eflags, u32 l, u32 etail, | |
295 | __le32 *rhf_addr, struct qib_message_header *rhdr) | |
f931551b RC |
296 | { |
297 | u32 ret = 0; | |
298 | ||
299 | if (eflags & (QLOGIC_IB_RHF_H_ICRCERR | QLOGIC_IB_RHF_H_VCRCERR)) | |
300 | ret = 1; | |
994bcd28 MM |
301 | else if (eflags == QLOGIC_IB_RHF_H_TIDERR) { |
302 | /* For TIDERR and RC QPs premptively schedule a NAK */ | |
303 | struct qib_ib_header *hdr = (struct qib_ib_header *) rhdr; | |
304 | struct qib_other_headers *ohdr = NULL; | |
305 | struct qib_ibport *ibp = &ppd->ibport_data; | |
306 | struct qib_qp *qp = NULL; | |
307 | u32 tlen = qib_hdrget_length_in_bytes(rhf_addr); | |
308 | u16 lid = be16_to_cpu(hdr->lrh[1]); | |
309 | int lnh = be16_to_cpu(hdr->lrh[0]) & 3; | |
310 | u32 qp_num; | |
311 | u32 opcode; | |
312 | u32 psn; | |
313 | int diff; | |
994bcd28 MM |
314 | |
315 | /* Sanity check packet */ | |
316 | if (tlen < 24) | |
317 | goto drop; | |
318 | ||
319 | if (lid < QIB_MULTICAST_LID_BASE) { | |
320 | lid &= ~((1 << ppd->lmc) - 1); | |
321 | if (unlikely(lid != ppd->lid)) | |
322 | goto drop; | |
323 | } | |
324 | ||
325 | /* Check for GRH */ | |
326 | if (lnh == QIB_LRH_BTH) | |
327 | ohdr = &hdr->u.oth; | |
328 | else if (lnh == QIB_LRH_GRH) { | |
329 | u32 vtf; | |
330 | ||
331 | ohdr = &hdr->u.l.oth; | |
332 | if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR) | |
333 | goto drop; | |
334 | vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow); | |
335 | if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION) | |
336 | goto drop; | |
337 | } else | |
338 | goto drop; | |
339 | ||
340 | /* Get opcode and PSN from packet */ | |
341 | opcode = be32_to_cpu(ohdr->bth[0]); | |
342 | opcode >>= 24; | |
343 | psn = be32_to_cpu(ohdr->bth[2]); | |
344 | ||
345 | /* Get the destination QP number. */ | |
346 | qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK; | |
347 | if (qp_num != QIB_MULTICAST_QPN) { | |
348 | int ruc_res; | |
349 | qp = qib_lookup_qpn(ibp, qp_num); | |
350 | if (!qp) | |
351 | goto drop; | |
352 | ||
353 | /* | |
354 | * Handle only RC QPs - for other QP types drop error | |
355 | * packet. | |
356 | */ | |
357 | spin_lock(&qp->r_lock); | |
358 | ||
359 | /* Check for valid receive state. */ | |
360 | if (!(ib_qib_state_ops[qp->state] & | |
361 | QIB_PROCESS_RECV_OK)) { | |
362 | ibp->n_pkt_drops++; | |
363 | goto unlock; | |
364 | } | |
365 | ||
366 | switch (qp->ibqp.qp_type) { | |
367 | case IB_QPT_RC: | |
994bcd28 MM |
368 | ruc_res = |
369 | qib_ruc_check_hdr( | |
370 | ibp, hdr, | |
371 | lnh == QIB_LRH_GRH, | |
372 | qp, | |
373 | be32_to_cpu(ohdr->bth[0])); | |
865b64be | 374 | if (ruc_res) |
994bcd28 | 375 | goto unlock; |
994bcd28 MM |
376 | |
377 | /* Only deal with RDMA Writes for now */ | |
378 | if (opcode < | |
379 | IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) { | |
380 | diff = qib_cmp24(psn, qp->r_psn); | |
381 | if (!qp->r_nak_state && diff >= 0) { | |
382 | ibp->n_rc_seqnak++; | |
383 | qp->r_nak_state = | |
384 | IB_NAK_PSN_ERROR; | |
385 | /* Use the expected PSN. */ | |
386 | qp->r_ack_psn = qp->r_psn; | |
387 | /* | |
388 | * Wait to send the sequence | |
389 | * NAK until all packets | |
390 | * in the receive queue have | |
391 | * been processed. | |
392 | * Otherwise, we end up | |
393 | * propagating congestion. | |
394 | */ | |
395 | if (list_empty(&qp->rspwait)) { | |
396 | qp->r_flags |= | |
397 | QIB_R_RSP_NAK; | |
398 | atomic_inc( | |
399 | &qp->refcount); | |
400 | list_add_tail( | |
401 | &qp->rspwait, | |
402 | &rcd->qp_wait_list); | |
403 | } | |
404 | } /* Out of sequence NAK */ | |
405 | } /* QP Request NAKs */ | |
406 | break; | |
407 | case IB_QPT_SMI: | |
408 | case IB_QPT_GSI: | |
409 | case IB_QPT_UD: | |
410 | case IB_QPT_UC: | |
411 | default: | |
412 | /* For now don't handle any other QP types */ | |
413 | break; | |
414 | } | |
415 | ||
416 | unlock: | |
417 | spin_unlock(&qp->r_lock); | |
418 | /* | |
419 | * Notify qib_destroy_qp() if it is waiting | |
420 | * for us to finish. | |
421 | */ | |
422 | if (atomic_dec_and_test(&qp->refcount)) | |
423 | wake_up(&qp->wait); | |
424 | } /* Unicast QP */ | |
425 | } /* Valid packet with TIDErr */ | |
426 | ||
427 | drop: | |
f931551b RC |
428 | return ret; |
429 | } | |
430 | ||
431 | /* | |
432 | * qib_kreceive - receive a packet | |
433 | * @rcd: the qlogic_ib context | |
434 | * @llic: gets count of good packets needed to clear lli, | |
435 | * (used with chips that need need to track crcs for lli) | |
436 | * | |
437 | * called from interrupt handler for errors or receive interrupt | |
438 | * Returns number of CRC error packets, needed by some chips for | |
439 | * local link integrity tracking. crcs are adjusted down by following | |
440 | * good packets, if any, and count of good packets is also tracked. | |
441 | */ | |
442 | u32 qib_kreceive(struct qib_ctxtdata *rcd, u32 *llic, u32 *npkts) | |
443 | { | |
444 | struct qib_devdata *dd = rcd->dd; | |
445 | struct qib_pportdata *ppd = rcd->ppd; | |
446 | __le32 *rhf_addr; | |
447 | void *ebuf; | |
448 | const u32 rsize = dd->rcvhdrentsize; /* words */ | |
449 | const u32 maxcnt = dd->rcvhdrcnt * rsize; /* words */ | |
450 | u32 etail = -1, l, hdrqtail; | |
451 | struct qib_message_header *hdr; | |
452 | u32 eflags, etype, tlen, i = 0, updegr = 0, crcs = 0; | |
453 | int last; | |
454 | u64 lval; | |
455 | struct qib_qp *qp, *nqp; | |
456 | ||
457 | l = rcd->head; | |
458 | rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset; | |
459 | if (dd->flags & QIB_NODMA_RTAIL) { | |
460 | u32 seq = qib_hdrget_seq(rhf_addr); | |
461 | if (seq != rcd->seq_cnt) | |
462 | goto bail; | |
463 | hdrqtail = 0; | |
464 | } else { | |
465 | hdrqtail = qib_get_rcvhdrtail(rcd); | |
466 | if (l == hdrqtail) | |
467 | goto bail; | |
468 | smp_rmb(); /* prevent speculative reads of dma'ed hdrq */ | |
469 | } | |
470 | ||
aa7374ac | 471 | for (last = 0, i = 1; !last; i += !last) { |
f931551b RC |
472 | hdr = dd->f_get_msgheader(dd, rhf_addr); |
473 | eflags = qib_hdrget_err_flags(rhf_addr); | |
474 | etype = qib_hdrget_rcv_type(rhf_addr); | |
475 | /* total length */ | |
476 | tlen = qib_hdrget_length_in_bytes(rhf_addr); | |
477 | ebuf = NULL; | |
478 | if ((dd->flags & QIB_NODMA_RTAIL) ? | |
479 | qib_hdrget_use_egr_buf(rhf_addr) : | |
480 | (etype != RCVHQ_RCV_TYPE_EXPECTED)) { | |
481 | etail = qib_hdrget_index(rhf_addr); | |
482 | updegr = 1; | |
483 | if (tlen > sizeof(*hdr) || | |
484 | etype >= RCVHQ_RCV_TYPE_NON_KD) | |
485 | ebuf = qib_get_egrbuf(rcd, etail); | |
486 | } | |
487 | if (!eflags) { | |
488 | u16 lrh_len = be16_to_cpu(hdr->lrh[2]) << 2; | |
489 | ||
490 | if (lrh_len != tlen) { | |
491 | qib_stats.sps_lenerrs++; | |
492 | goto move_along; | |
493 | } | |
494 | } | |
495 | if (etype == RCVHQ_RCV_TYPE_NON_KD && !eflags && | |
496 | ebuf == NULL && | |
497 | tlen > (dd->rcvhdrentsize - 2 + 1 - | |
498 | qib_hdrget_offset(rhf_addr)) << 2) { | |
499 | goto move_along; | |
500 | } | |
501 | ||
502 | /* | |
503 | * Both tiderr and qibhdrerr are set for all plain IB | |
504 | * packets; only qibhdrerr should be set. | |
505 | */ | |
506 | if (unlikely(eflags)) | |
994bcd28 | 507 | crcs += qib_rcv_hdrerr(rcd, ppd, rcd->ctxt, eflags, l, |
f931551b RC |
508 | etail, rhf_addr, hdr); |
509 | else if (etype == RCVHQ_RCV_TYPE_NON_KD) { | |
510 | qib_ib_rcv(rcd, hdr, ebuf, tlen); | |
511 | if (crcs) | |
512 | crcs--; | |
513 | else if (llic && *llic) | |
514 | --*llic; | |
515 | } | |
516 | move_along: | |
517 | l += rsize; | |
518 | if (l >= maxcnt) | |
519 | l = 0; | |
aa7374ac MM |
520 | if (i == QIB_MAX_PKT_RECV) |
521 | last = 1; | |
522 | ||
f931551b RC |
523 | rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset; |
524 | if (dd->flags & QIB_NODMA_RTAIL) { | |
525 | u32 seq = qib_hdrget_seq(rhf_addr); | |
526 | ||
527 | if (++rcd->seq_cnt > 13) | |
528 | rcd->seq_cnt = 1; | |
529 | if (seq != rcd->seq_cnt) | |
530 | last = 1; | |
531 | } else if (l == hdrqtail) | |
532 | last = 1; | |
533 | /* | |
534 | * Update head regs etc., every 16 packets, if not last pkt, | |
535 | * to help prevent rcvhdrq overflows, when many packets | |
536 | * are processed and queue is nearly full. | |
537 | * Don't request an interrupt for intermediate updates. | |
538 | */ | |
539 | lval = l; | |
540 | if (!last && !(i & 0xf)) { | |
19ede2e4 | 541 | dd->f_update_usrhead(rcd, lval, updegr, etail, i); |
f931551b RC |
542 | updegr = 0; |
543 | } | |
544 | } | |
af061a64 MM |
545 | /* |
546 | * Notify qib_destroy_qp() if it is waiting | |
547 | * for lookaside_qp to finish. | |
548 | */ | |
549 | if (rcd->lookaside_qp) { | |
550 | if (atomic_dec_and_test(&rcd->lookaside_qp->refcount)) | |
551 | wake_up(&rcd->lookaside_qp->wait); | |
552 | rcd->lookaside_qp = NULL; | |
553 | } | |
f931551b RC |
554 | |
555 | rcd->head = l; | |
556 | rcd->pkt_count += i; | |
557 | ||
558 | /* | |
559 | * Iterate over all QPs waiting to respond. | |
560 | * The list won't change since the IRQ is only run on one CPU. | |
561 | */ | |
562 | list_for_each_entry_safe(qp, nqp, &rcd->qp_wait_list, rspwait) { | |
563 | list_del_init(&qp->rspwait); | |
564 | if (qp->r_flags & QIB_R_RSP_NAK) { | |
565 | qp->r_flags &= ~QIB_R_RSP_NAK; | |
566 | qib_send_rc_ack(qp); | |
567 | } | |
568 | if (qp->r_flags & QIB_R_RSP_SEND) { | |
569 | unsigned long flags; | |
570 | ||
571 | qp->r_flags &= ~QIB_R_RSP_SEND; | |
572 | spin_lock_irqsave(&qp->s_lock, flags); | |
573 | if (ib_qib_state_ops[qp->state] & | |
574 | QIB_PROCESS_OR_FLUSH_SEND) | |
575 | qib_schedule_send(qp); | |
576 | spin_unlock_irqrestore(&qp->s_lock, flags); | |
577 | } | |
578 | if (atomic_dec_and_test(&qp->refcount)) | |
579 | wake_up(&qp->wait); | |
580 | } | |
581 | ||
582 | bail: | |
583 | /* Report number of packets consumed */ | |
584 | if (npkts) | |
585 | *npkts = i; | |
586 | ||
587 | /* | |
588 | * Always write head at end, and setup rcv interrupt, even | |
589 | * if no packets were processed. | |
590 | */ | |
591 | lval = (u64)rcd->head | dd->rhdrhead_intr_off; | |
19ede2e4 | 592 | dd->f_update_usrhead(rcd, lval, updegr, etail, i); |
f931551b RC |
593 | return crcs; |
594 | } | |
595 | ||
596 | /** | |
597 | * qib_set_mtu - set the MTU | |
598 | * @ppd: the perport data | |
599 | * @arg: the new MTU | |
600 | * | |
601 | * We can handle "any" incoming size, the issue here is whether we | |
602 | * need to restrict our outgoing size. For now, we don't do any | |
603 | * sanity checking on this, and we don't deal with what happens to | |
604 | * programs that are already running when the size changes. | |
605 | * NOTE: changing the MTU will usually cause the IBC to go back to | |
606 | * link INIT state... | |
607 | */ | |
608 | int qib_set_mtu(struct qib_pportdata *ppd, u16 arg) | |
609 | { | |
610 | u32 piosize; | |
611 | int ret, chk; | |
612 | ||
613 | if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 && | |
614 | arg != 4096) { | |
615 | ret = -EINVAL; | |
616 | goto bail; | |
617 | } | |
618 | chk = ib_mtu_enum_to_int(qib_ibmtu); | |
619 | if (chk > 0 && arg > chk) { | |
620 | ret = -EINVAL; | |
621 | goto bail; | |
622 | } | |
623 | ||
624 | piosize = ppd->ibmaxlen; | |
625 | ppd->ibmtu = arg; | |
626 | ||
627 | if (arg >= (piosize - QIB_PIO_MAXIBHDR)) { | |
628 | /* Only if it's not the initial value (or reset to it) */ | |
629 | if (piosize != ppd->init_ibmaxlen) { | |
630 | if (arg > piosize && arg <= ppd->init_ibmaxlen) | |
631 | piosize = ppd->init_ibmaxlen - 2 * sizeof(u32); | |
632 | ppd->ibmaxlen = piosize; | |
633 | } | |
634 | } else if ((arg + QIB_PIO_MAXIBHDR) != ppd->ibmaxlen) { | |
635 | piosize = arg + QIB_PIO_MAXIBHDR - 2 * sizeof(u32); | |
636 | ppd->ibmaxlen = piosize; | |
637 | } | |
638 | ||
639 | ppd->dd->f_set_ib_cfg(ppd, QIB_IB_CFG_MTU, 0); | |
640 | ||
641 | ret = 0; | |
642 | ||
643 | bail: | |
644 | return ret; | |
645 | } | |
646 | ||
647 | int qib_set_lid(struct qib_pportdata *ppd, u32 lid, u8 lmc) | |
648 | { | |
649 | struct qib_devdata *dd = ppd->dd; | |
650 | ppd->lid = lid; | |
651 | ppd->lmc = lmc; | |
652 | ||
653 | dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LIDLMC, | |
654 | lid | (~((1U << lmc) - 1)) << 16); | |
655 | ||
656 | qib_devinfo(dd->pcidev, "IB%u:%u got a lid: 0x%x\n", | |
657 | dd->unit, ppd->port, lid); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | /* | |
663 | * Following deal with the "obviously simple" task of overriding the state | |
664 | * of the LEDS, which normally indicate link physical and logical status. | |
665 | * The complications arise in dealing with different hardware mappings | |
666 | * and the board-dependent routine being called from interrupts. | |
667 | * and then there's the requirement to _flash_ them. | |
668 | */ | |
669 | #define LED_OVER_FREQ_SHIFT 8 | |
670 | #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT) | |
671 | /* Below is "non-zero" to force override, but both actual LEDs are off */ | |
672 | #define LED_OVER_BOTH_OFF (8) | |
673 | ||
674 | static void qib_run_led_override(unsigned long opaque) | |
675 | { | |
676 | struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; | |
677 | struct qib_devdata *dd = ppd->dd; | |
678 | int timeoff; | |
679 | int ph_idx; | |
680 | ||
681 | if (!(dd->flags & QIB_INITTED)) | |
682 | return; | |
683 | ||
684 | ph_idx = ppd->led_override_phase++ & 1; | |
685 | ppd->led_override = ppd->led_override_vals[ph_idx]; | |
686 | timeoff = ppd->led_override_timeoff; | |
687 | ||
688 | dd->f_setextled(ppd, 1); | |
689 | /* | |
690 | * don't re-fire the timer if user asked for it to be off; we let | |
691 | * it fire one more time after they turn it off to simplify | |
692 | */ | |
693 | if (ppd->led_override_vals[0] || ppd->led_override_vals[1]) | |
694 | mod_timer(&ppd->led_override_timer, jiffies + timeoff); | |
695 | } | |
696 | ||
697 | void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val) | |
698 | { | |
699 | struct qib_devdata *dd = ppd->dd; | |
700 | int timeoff, freq; | |
701 | ||
702 | if (!(dd->flags & QIB_INITTED)) | |
703 | return; | |
704 | ||
705 | /* First check if we are blinking. If not, use 1HZ polling */ | |
706 | timeoff = HZ; | |
707 | freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT; | |
708 | ||
709 | if (freq) { | |
710 | /* For blink, set each phase from one nybble of val */ | |
711 | ppd->led_override_vals[0] = val & 0xF; | |
712 | ppd->led_override_vals[1] = (val >> 4) & 0xF; | |
713 | timeoff = (HZ << 4)/freq; | |
714 | } else { | |
715 | /* Non-blink set both phases the same. */ | |
716 | ppd->led_override_vals[0] = val & 0xF; | |
717 | ppd->led_override_vals[1] = val & 0xF; | |
718 | } | |
719 | ppd->led_override_timeoff = timeoff; | |
720 | ||
721 | /* | |
722 | * If the timer has not already been started, do so. Use a "quick" | |
723 | * timeout so the function will be called soon, to look at our request. | |
724 | */ | |
725 | if (atomic_inc_return(&ppd->led_override_timer_active) == 1) { | |
726 | /* Need to start timer */ | |
727 | init_timer(&ppd->led_override_timer); | |
728 | ppd->led_override_timer.function = qib_run_led_override; | |
729 | ppd->led_override_timer.data = (unsigned long) ppd; | |
730 | ppd->led_override_timer.expires = jiffies + 1; | |
731 | add_timer(&ppd->led_override_timer); | |
732 | } else { | |
733 | if (ppd->led_override_vals[0] || ppd->led_override_vals[1]) | |
734 | mod_timer(&ppd->led_override_timer, jiffies + 1); | |
735 | atomic_dec(&ppd->led_override_timer_active); | |
736 | } | |
737 | } | |
738 | ||
739 | /** | |
740 | * qib_reset_device - reset the chip if possible | |
741 | * @unit: the device to reset | |
742 | * | |
743 | * Whether or not reset is successful, we attempt to re-initialize the chip | |
744 | * (that is, much like a driver unload/reload). We clear the INITTED flag | |
745 | * so that the various entry points will fail until we reinitialize. For | |
746 | * now, we only allow this if no user contexts are open that use chip resources | |
747 | */ | |
748 | int qib_reset_device(int unit) | |
749 | { | |
750 | int ret, i; | |
751 | struct qib_devdata *dd = qib_lookup(unit); | |
752 | struct qib_pportdata *ppd; | |
753 | unsigned long flags; | |
754 | int pidx; | |
755 | ||
756 | if (!dd) { | |
757 | ret = -ENODEV; | |
758 | goto bail; | |
759 | } | |
760 | ||
761 | qib_devinfo(dd->pcidev, "Reset on unit %u requested\n", unit); | |
762 | ||
763 | if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) { | |
764 | qib_devinfo(dd->pcidev, "Invalid unit number %u or " | |
765 | "not initialized or not present\n", unit); | |
766 | ret = -ENXIO; | |
767 | goto bail; | |
768 | } | |
769 | ||
770 | spin_lock_irqsave(&dd->uctxt_lock, flags); | |
771 | if (dd->rcd) | |
772 | for (i = dd->first_user_ctxt; i < dd->cfgctxts; i++) { | |
773 | if (!dd->rcd[i] || !dd->rcd[i]->cnt) | |
774 | continue; | |
775 | spin_unlock_irqrestore(&dd->uctxt_lock, flags); | |
776 | ret = -EBUSY; | |
777 | goto bail; | |
778 | } | |
779 | spin_unlock_irqrestore(&dd->uctxt_lock, flags); | |
780 | ||
781 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
782 | ppd = dd->pport + pidx; | |
783 | if (atomic_read(&ppd->led_override_timer_active)) { | |
784 | /* Need to stop LED timer, _then_ shut off LEDs */ | |
785 | del_timer_sync(&ppd->led_override_timer); | |
786 | atomic_set(&ppd->led_override_timer_active, 0); | |
787 | } | |
788 | ||
789 | /* Shut off LEDs after we are sure timer is not running */ | |
790 | ppd->led_override = LED_OVER_BOTH_OFF; | |
791 | dd->f_setextled(ppd, 0); | |
792 | if (dd->flags & QIB_HAS_SEND_DMA) | |
793 | qib_teardown_sdma(ppd); | |
794 | } | |
795 | ||
796 | ret = dd->f_reset(dd); | |
797 | if (ret == 1) | |
798 | ret = qib_init(dd, 1); | |
799 | else | |
800 | ret = -EAGAIN; | |
801 | if (ret) | |
802 | qib_dev_err(dd, "Reinitialize unit %u after " | |
803 | "reset failed with %d\n", unit, ret); | |
804 | else | |
805 | qib_devinfo(dd->pcidev, "Reinitialized unit %u after " | |
806 | "resetting\n", unit); | |
807 | ||
808 | bail: | |
809 | return ret; | |
810 | } |