Commit | Line | Data |
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f931551b | 1 | /* |
e2eed58b | 2 | * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved. |
551ace12 | 3 | * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. |
f931551b RC |
4 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/pci.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/vmalloc.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/idr.h> | |
e4dd23d7 | 40 | #include <linux/module.h> |
7fac3301 | 41 | #include <linux/printk.h> |
8469ba39 MM |
42 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
43 | #include <linux/dca.h> | |
44 | #endif | |
f931551b RC |
45 | |
46 | #include "qib.h" | |
47 | #include "qib_common.h" | |
36a8f01c | 48 | #include "qib_mad.h" |
f931551b | 49 | |
7fac3301 MM |
50 | #undef pr_fmt |
51 | #define pr_fmt(fmt) QIB_DRV_NAME ": " fmt | |
52 | ||
f931551b RC |
53 | /* |
54 | * min buffers we want to have per context, after driver | |
55 | */ | |
56 | #define QIB_MIN_USER_CTXT_BUFCNT 7 | |
57 | ||
58 | #define QLOGIC_IB_R_SOFTWARE_MASK 0xFF | |
59 | #define QLOGIC_IB_R_SOFTWARE_SHIFT 24 | |
60 | #define QLOGIC_IB_R_EMULATOR_MASK (1ULL<<62) | |
61 | ||
62 | /* | |
63 | * Number of ctxts we are configured to use (to allow for more pio | |
64 | * buffers per ctxt, etc.) Zero means use chip value. | |
65 | */ | |
66 | ushort qib_cfgctxts; | |
67 | module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO); | |
68 | MODULE_PARM_DESC(cfgctxts, "Set max number of contexts to use"); | |
69 | ||
e0f30bac RV |
70 | unsigned qib_numa_aware; |
71 | module_param_named(numa_aware, qib_numa_aware, uint, S_IRUGO); | |
72 | MODULE_PARM_DESC(numa_aware, | |
73 | "0 -> PSM allocation close to HCA, 1 -> PSM allocation local to process"); | |
74 | ||
f931551b RC |
75 | /* |
76 | * If set, do not write to any regs if avoidable, hack to allow | |
77 | * check for deranged default register values. | |
78 | */ | |
79 | ushort qib_mini_init; | |
80 | module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO); | |
81 | MODULE_PARM_DESC(mini_init, "If set, do minimal diag init"); | |
82 | ||
83 | unsigned qib_n_krcv_queues; | |
84 | module_param_named(krcvqs, qib_n_krcv_queues, uint, S_IRUGO); | |
85 | MODULE_PARM_DESC(krcvqs, "number of kernel receive queues per IB port"); | |
86 | ||
36a8f01c MM |
87 | unsigned qib_cc_table_size; |
88 | module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO); | |
89 | MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984"); | |
f931551b RC |
90 | /* |
91 | * qib_wc_pat parameter: | |
92 | * 0 is WC via MTRR | |
93 | * 1 is WC via PAT | |
94 | * If PAT initialization fails, code reverts back to MTRR | |
95 | */ | |
96 | unsigned qib_wc_pat = 1; /* default (1) is to use PAT, not MTRR */ | |
97 | module_param_named(wc_pat, qib_wc_pat, uint, S_IRUGO); | |
98 | MODULE_PARM_DESC(wc_pat, "enable write-combining via PAT mechanism"); | |
99 | ||
f931551b RC |
100 | struct workqueue_struct *qib_cq_wq; |
101 | ||
102 | static void verify_interrupt(unsigned long); | |
103 | ||
104 | static struct idr qib_unit_table; | |
105 | u32 qib_cpulist_count; | |
106 | unsigned long *qib_cpulist; | |
107 | ||
108 | /* set number of contexts we'll actually use */ | |
109 | void qib_set_ctxtcnt(struct qib_devdata *dd) | |
110 | { | |
5dbbcb97 | 111 | if (!qib_cfgctxts) { |
0502f94c | 112 | dd->cfgctxts = dd->first_user_ctxt + num_online_cpus(); |
5dbbcb97 MM |
113 | if (dd->cfgctxts > dd->ctxtcnt) |
114 | dd->cfgctxts = dd->ctxtcnt; | |
115 | } else if (qib_cfgctxts < dd->num_pports) | |
f931551b RC |
116 | dd->cfgctxts = dd->ctxtcnt; |
117 | else if (qib_cfgctxts <= dd->ctxtcnt) | |
118 | dd->cfgctxts = qib_cfgctxts; | |
119 | else | |
120 | dd->cfgctxts = dd->ctxtcnt; | |
6ceaadee MH |
121 | dd->freectxts = (dd->first_user_ctxt > dd->cfgctxts) ? 0 : |
122 | dd->cfgctxts - dd->first_user_ctxt; | |
f931551b RC |
123 | } |
124 | ||
125 | /* | |
126 | * Common code for creating the receive context array. | |
127 | */ | |
128 | int qib_create_ctxts(struct qib_devdata *dd) | |
129 | { | |
130 | unsigned i; | |
131 | int ret; | |
e0f30bac RV |
132 | int local_node_id = pcibus_to_node(dd->pcidev->bus); |
133 | ||
134 | if (local_node_id < 0) | |
135 | local_node_id = numa_node_id(); | |
136 | dd->assigned_node_id = local_node_id; | |
f931551b RC |
137 | |
138 | /* | |
139 | * Allocate full ctxtcnt array, rather than just cfgctxts, because | |
140 | * cleanup iterates across all possible ctxts. | |
141 | */ | |
142 | dd->rcd = kzalloc(sizeof(*dd->rcd) * dd->ctxtcnt, GFP_KERNEL); | |
143 | if (!dd->rcd) { | |
7fac3301 MM |
144 | qib_dev_err(dd, |
145 | "Unable to allocate ctxtdata array, failing\n"); | |
f931551b RC |
146 | ret = -ENOMEM; |
147 | goto done; | |
148 | } | |
149 | ||
150 | /* create (one or more) kctxt */ | |
151 | for (i = 0; i < dd->first_user_ctxt; ++i) { | |
152 | struct qib_pportdata *ppd; | |
153 | struct qib_ctxtdata *rcd; | |
154 | ||
155 | if (dd->skip_kctxt_mask & (1 << i)) | |
156 | continue; | |
157 | ||
158 | ppd = dd->pport + (i % dd->num_pports); | |
e0f30bac RV |
159 | |
160 | rcd = qib_create_ctxtdata(ppd, i, dd->assigned_node_id); | |
f931551b | 161 | if (!rcd) { |
7fac3301 MM |
162 | qib_dev_err(dd, |
163 | "Unable to allocate ctxtdata for Kernel ctxt, failing\n"); | |
f931551b RC |
164 | ret = -ENOMEM; |
165 | goto done; | |
166 | } | |
167 | rcd->pkeys[0] = QIB_DEFAULT_P_KEY; | |
168 | rcd->seq_cnt = 1; | |
169 | } | |
170 | ret = 0; | |
171 | done: | |
172 | return ret; | |
173 | } | |
174 | ||
175 | /* | |
176 | * Common code for user and kernel context setup. | |
177 | */ | |
e0f30bac RV |
178 | struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *ppd, u32 ctxt, |
179 | int node_id) | |
f931551b RC |
180 | { |
181 | struct qib_devdata *dd = ppd->dd; | |
182 | struct qib_ctxtdata *rcd; | |
183 | ||
e0f30bac | 184 | rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, node_id); |
f931551b RC |
185 | if (rcd) { |
186 | INIT_LIST_HEAD(&rcd->qp_wait_list); | |
e0f30bac | 187 | rcd->node_id = node_id; |
f931551b RC |
188 | rcd->ppd = ppd; |
189 | rcd->dd = dd; | |
190 | rcd->cnt = 1; | |
191 | rcd->ctxt = ctxt; | |
192 | dd->rcd[ctxt] = rcd; | |
193 | ||
194 | dd->f_init_ctxt(rcd); | |
195 | ||
196 | /* | |
197 | * To avoid wasting a lot of memory, we allocate 32KB chunks | |
198 | * of physically contiguous memory, advance through it until | |
199 | * used up and then allocate more. Of course, we need | |
200 | * memory to store those extra pointers, now. 32KB seems to | |
201 | * be the most that is "safe" under memory pressure | |
202 | * (creating large files and then copying them over | |
203 | * NFS while doing lots of MPI jobs). The OOM killer can | |
204 | * get invoked, even though we say we can sleep and this can | |
205 | * cause significant system problems.... | |
206 | */ | |
207 | rcd->rcvegrbuf_size = 0x8000; | |
208 | rcd->rcvegrbufs_perchunk = | |
209 | rcd->rcvegrbuf_size / dd->rcvegrbufsize; | |
210 | rcd->rcvegrbuf_chunks = (rcd->rcvegrcnt + | |
211 | rcd->rcvegrbufs_perchunk - 1) / | |
212 | rcd->rcvegrbufs_perchunk; | |
9e1c0e43 MM |
213 | BUG_ON(!is_power_of_2(rcd->rcvegrbufs_perchunk)); |
214 | rcd->rcvegrbufs_perchunk_shift = | |
215 | ilog2(rcd->rcvegrbufs_perchunk); | |
f931551b RC |
216 | } |
217 | return rcd; | |
218 | } | |
219 | ||
220 | /* | |
221 | * Common code for initializing the physical port structure. | |
222 | */ | |
223 | void qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd, | |
224 | u8 hw_pidx, u8 port) | |
225 | { | |
36a8f01c | 226 | int size; |
f931551b RC |
227 | ppd->dd = dd; |
228 | ppd->hw_pidx = hw_pidx; | |
229 | ppd->port = port; /* IB port number, not index */ | |
230 | ||
231 | spin_lock_init(&ppd->sdma_lock); | |
232 | spin_lock_init(&ppd->lflags_lock); | |
233 | init_waitqueue_head(&ppd->state_wait); | |
234 | ||
235 | init_timer(&ppd->symerr_clear_timer); | |
236 | ppd->symerr_clear_timer.function = qib_clear_symerror_on_linkup; | |
237 | ppd->symerr_clear_timer.data = (unsigned long)ppd; | |
551ace12 MM |
238 | |
239 | ppd->qib_wq = NULL; | |
36a8f01c MM |
240 | |
241 | spin_lock_init(&ppd->cc_shadow_lock); | |
242 | ||
243 | if (qib_cc_table_size < IB_CCT_MIN_ENTRIES) | |
244 | goto bail; | |
245 | ||
246 | ppd->cc_supported_table_entries = min(max_t(int, qib_cc_table_size, | |
247 | IB_CCT_MIN_ENTRIES), IB_CCT_ENTRIES*IB_CC_TABLE_CAP_DEFAULT); | |
248 | ||
249 | ppd->cc_max_table_entries = | |
250 | ppd->cc_supported_table_entries/IB_CCT_ENTRIES; | |
251 | ||
252 | size = IB_CC_TABLE_CAP_DEFAULT * sizeof(struct ib_cc_table_entry) | |
253 | * IB_CCT_ENTRIES; | |
254 | ppd->ccti_entries = kzalloc(size, GFP_KERNEL); | |
255 | if (!ppd->ccti_entries) { | |
256 | qib_dev_err(dd, | |
257 | "failed to allocate congestion control table for port %d!\n", | |
258 | port); | |
259 | goto bail; | |
260 | } | |
261 | ||
262 | size = IB_CC_CCS_ENTRIES * sizeof(struct ib_cc_congestion_entry); | |
263 | ppd->congestion_entries = kzalloc(size, GFP_KERNEL); | |
264 | if (!ppd->congestion_entries) { | |
265 | qib_dev_err(dd, | |
266 | "failed to allocate congestion setting list for port %d!\n", | |
267 | port); | |
268 | goto bail_1; | |
269 | } | |
270 | ||
271 | size = sizeof(struct cc_table_shadow); | |
272 | ppd->ccti_entries_shadow = kzalloc(size, GFP_KERNEL); | |
273 | if (!ppd->ccti_entries_shadow) { | |
274 | qib_dev_err(dd, | |
275 | "failed to allocate shadow ccti list for port %d!\n", | |
276 | port); | |
277 | goto bail_2; | |
278 | } | |
279 | ||
280 | size = sizeof(struct ib_cc_congestion_setting_attr); | |
281 | ppd->congestion_entries_shadow = kzalloc(size, GFP_KERNEL); | |
282 | if (!ppd->congestion_entries_shadow) { | |
283 | qib_dev_err(dd, | |
284 | "failed to allocate shadow congestion setting list for port %d!\n", | |
285 | port); | |
286 | goto bail_3; | |
287 | } | |
288 | ||
289 | return; | |
290 | ||
291 | bail_3: | |
292 | kfree(ppd->ccti_entries_shadow); | |
293 | ppd->ccti_entries_shadow = NULL; | |
294 | bail_2: | |
295 | kfree(ppd->congestion_entries); | |
296 | ppd->congestion_entries = NULL; | |
297 | bail_1: | |
298 | kfree(ppd->ccti_entries); | |
299 | ppd->ccti_entries = NULL; | |
300 | bail: | |
301 | /* User is intentionally disabling the congestion control agent */ | |
302 | if (!qib_cc_table_size) | |
303 | return; | |
304 | ||
305 | if (qib_cc_table_size < IB_CCT_MIN_ENTRIES) { | |
306 | qib_cc_table_size = 0; | |
307 | qib_dev_err(dd, | |
308 | "Congestion Control table size %d less than minimum %d for port %d\n", | |
309 | qib_cc_table_size, IB_CCT_MIN_ENTRIES, port); | |
310 | } | |
311 | ||
312 | qib_dev_err(dd, "Congestion Control Agent disabled for port %d\n", | |
313 | port); | |
314 | return; | |
f931551b RC |
315 | } |
316 | ||
317 | static int init_pioavailregs(struct qib_devdata *dd) | |
318 | { | |
319 | int ret, pidx; | |
320 | u64 *status_page; | |
321 | ||
322 | dd->pioavailregs_dma = dma_alloc_coherent( | |
323 | &dd->pcidev->dev, PAGE_SIZE, &dd->pioavailregs_phys, | |
324 | GFP_KERNEL); | |
325 | if (!dd->pioavailregs_dma) { | |
7fac3301 MM |
326 | qib_dev_err(dd, |
327 | "failed to allocate PIOavail reg area in memory\n"); | |
f931551b RC |
328 | ret = -ENOMEM; |
329 | goto done; | |
330 | } | |
331 | ||
332 | /* | |
333 | * We really want L2 cache aligned, but for current CPUs of | |
334 | * interest, they are the same. | |
335 | */ | |
336 | status_page = (u64 *) | |
337 | ((char *) dd->pioavailregs_dma + | |
338 | ((2 * L1_CACHE_BYTES + | |
339 | dd->pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES)); | |
340 | /* device status comes first, for backwards compatibility */ | |
341 | dd->devstatusp = status_page; | |
342 | *status_page++ = 0; | |
343 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
344 | dd->pport[pidx].statusp = status_page; | |
345 | *status_page++ = 0; | |
346 | } | |
347 | ||
348 | /* | |
349 | * Setup buffer to hold freeze and other messages, accessible to | |
350 | * apps, following statusp. This is per-unit, not per port. | |
351 | */ | |
352 | dd->freezemsg = (char *) status_page; | |
353 | *dd->freezemsg = 0; | |
354 | /* length of msg buffer is "whatever is left" */ | |
355 | ret = (char *) status_page - (char *) dd->pioavailregs_dma; | |
356 | dd->freezelen = PAGE_SIZE - ret; | |
357 | ||
358 | ret = 0; | |
359 | ||
360 | done: | |
361 | return ret; | |
362 | } | |
363 | ||
364 | /** | |
365 | * init_shadow_tids - allocate the shadow TID array | |
366 | * @dd: the qlogic_ib device | |
367 | * | |
368 | * allocate the shadow TID array, so we can qib_munlock previous | |
369 | * entries. It may make more sense to move the pageshadow to the | |
370 | * ctxt data structure, so we only allocate memory for ctxts actually | |
371 | * in use, since we at 8k per ctxt, now. | |
372 | * We don't want failures here to prevent use of the driver/chip, | |
373 | * so no return value. | |
374 | */ | |
375 | static void init_shadow_tids(struct qib_devdata *dd) | |
376 | { | |
377 | struct page **pages; | |
378 | dma_addr_t *addrs; | |
379 | ||
948579cd | 380 | pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *)); |
f931551b | 381 | if (!pages) { |
7fac3301 MM |
382 | qib_dev_err(dd, |
383 | "failed to allocate shadow page * array, no expected sends!\n"); | |
f931551b RC |
384 | goto bail; |
385 | } | |
386 | ||
948579cd | 387 | addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t)); |
f931551b | 388 | if (!addrs) { |
7fac3301 MM |
389 | qib_dev_err(dd, |
390 | "failed to allocate shadow dma handle array, no expected sends!\n"); | |
f931551b RC |
391 | goto bail_free; |
392 | } | |
393 | ||
f931551b RC |
394 | dd->pageshadow = pages; |
395 | dd->physshadow = addrs; | |
396 | return; | |
397 | ||
398 | bail_free: | |
399 | vfree(pages); | |
400 | bail: | |
401 | dd->pageshadow = NULL; | |
402 | } | |
403 | ||
404 | /* | |
405 | * Do initialization for device that is only needed on | |
406 | * first detect, not on resets. | |
407 | */ | |
408 | static int loadtime_init(struct qib_devdata *dd) | |
409 | { | |
410 | int ret = 0; | |
411 | ||
412 | if (((dd->revision >> QLOGIC_IB_R_SOFTWARE_SHIFT) & | |
413 | QLOGIC_IB_R_SOFTWARE_MASK) != QIB_CHIP_SWVERSION) { | |
7fac3301 MM |
414 | qib_dev_err(dd, |
415 | "Driver only handles version %d, chip swversion is %d (%llx), failng\n", | |
416 | QIB_CHIP_SWVERSION, | |
417 | (int)(dd->revision >> | |
f931551b | 418 | QLOGIC_IB_R_SOFTWARE_SHIFT) & |
7fac3301 MM |
419 | QLOGIC_IB_R_SOFTWARE_MASK, |
420 | (unsigned long long) dd->revision); | |
f931551b RC |
421 | ret = -ENOSYS; |
422 | goto done; | |
423 | } | |
424 | ||
425 | if (dd->revision & QLOGIC_IB_R_EMULATOR_MASK) | |
426 | qib_devinfo(dd->pcidev, "%s", dd->boardversion); | |
427 | ||
428 | spin_lock_init(&dd->pioavail_lock); | |
429 | spin_lock_init(&dd->sendctrl_lock); | |
430 | spin_lock_init(&dd->uctxt_lock); | |
431 | spin_lock_init(&dd->qib_diag_trans_lock); | |
432 | spin_lock_init(&dd->eep_st_lock); | |
433 | mutex_init(&dd->eep_lock); | |
434 | ||
435 | if (qib_mini_init) | |
436 | goto done; | |
437 | ||
438 | ret = init_pioavailregs(dd); | |
439 | init_shadow_tids(dd); | |
440 | ||
441 | qib_get_eeprom_info(dd); | |
442 | ||
443 | /* setup time (don't start yet) to verify we got interrupt */ | |
444 | init_timer(&dd->intrchk_timer); | |
445 | dd->intrchk_timer.function = verify_interrupt; | |
446 | dd->intrchk_timer.data = (unsigned long) dd; | |
447 | ||
448 | done: | |
449 | return ret; | |
450 | } | |
451 | ||
452 | /** | |
453 | * init_after_reset - re-initialize after a reset | |
454 | * @dd: the qlogic_ib device | |
455 | * | |
456 | * sanity check at least some of the values after reset, and | |
25985edc | 457 | * ensure no receive or transmit (explicitly, in case reset |
f931551b RC |
458 | * failed |
459 | */ | |
460 | static int init_after_reset(struct qib_devdata *dd) | |
461 | { | |
462 | int i; | |
463 | ||
464 | /* | |
465 | * Ensure chip does no sends or receives, tail updates, or | |
466 | * pioavail updates while we re-initialize. This is mostly | |
467 | * for the driver data structures, not chip registers. | |
468 | */ | |
469 | for (i = 0; i < dd->num_pports; ++i) { | |
470 | /* | |
471 | * ctxt == -1 means "all contexts". Only really safe for | |
472 | * _dis_abling things, as here. | |
473 | */ | |
474 | dd->f_rcvctrl(dd->pport + i, QIB_RCVCTRL_CTXT_DIS | | |
475 | QIB_RCVCTRL_INTRAVAIL_DIS | | |
476 | QIB_RCVCTRL_TAILUPD_DIS, -1); | |
477 | /* Redundant across ports for some, but no big deal. */ | |
478 | dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_DIS | | |
479 | QIB_SENDCTRL_AVAIL_DIS); | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static void enable_chip(struct qib_devdata *dd) | |
486 | { | |
487 | u64 rcvmask; | |
488 | int i; | |
489 | ||
490 | /* | |
491 | * Enable PIO send, and update of PIOavail regs to memory. | |
492 | */ | |
493 | for (i = 0; i < dd->num_pports; ++i) | |
494 | dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_ENB | | |
495 | QIB_SENDCTRL_AVAIL_ENB); | |
496 | /* | |
497 | * Enable kernel ctxts' receive and receive interrupt. | |
498 | * Other ctxts done as user opens and inits them. | |
499 | */ | |
500 | rcvmask = QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_INTRAVAIL_ENB; | |
501 | rcvmask |= (dd->flags & QIB_NODMA_RTAIL) ? | |
502 | QIB_RCVCTRL_TAILUPD_DIS : QIB_RCVCTRL_TAILUPD_ENB; | |
503 | for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) { | |
504 | struct qib_ctxtdata *rcd = dd->rcd[i]; | |
505 | ||
506 | if (rcd) | |
507 | dd->f_rcvctrl(rcd->ppd, rcvmask, i); | |
508 | } | |
509 | } | |
510 | ||
511 | static void verify_interrupt(unsigned long opaque) | |
512 | { | |
513 | struct qib_devdata *dd = (struct qib_devdata *) opaque; | |
514 | ||
515 | if (!dd) | |
516 | return; /* being torn down */ | |
517 | ||
518 | /* | |
519 | * If we don't have a lid or any interrupts, let the user know and | |
520 | * don't bother checking again. | |
521 | */ | |
522 | if (dd->int_counter == 0) { | |
523 | if (!dd->f_intr_fallback(dd)) | |
7fac3301 MM |
524 | dev_err(&dd->pcidev->dev, |
525 | "No interrupts detected, not usable.\n"); | |
f931551b RC |
526 | else /* re-arm the timer to see if fallback works */ |
527 | mod_timer(&dd->intrchk_timer, jiffies + HZ/2); | |
528 | } | |
529 | } | |
530 | ||
531 | static void init_piobuf_state(struct qib_devdata *dd) | |
532 | { | |
533 | int i, pidx; | |
534 | u32 uctxts; | |
535 | ||
536 | /* | |
537 | * Ensure all buffers are free, and fifos empty. Buffers | |
538 | * are common, so only do once for port 0. | |
539 | * | |
540 | * After enable and qib_chg_pioavailkernel so we can safely | |
541 | * enable pioavail updates and PIOENABLE. After this, packets | |
542 | * are ready and able to go out. | |
543 | */ | |
544 | dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_ALL); | |
545 | for (pidx = 0; pidx < dd->num_pports; ++pidx) | |
546 | dd->f_sendctrl(dd->pport + pidx, QIB_SENDCTRL_FLUSH); | |
547 | ||
548 | /* | |
549 | * If not all sendbufs are used, add the one to each of the lower | |
550 | * numbered contexts. pbufsctxt and lastctxt_piobuf are | |
551 | * calculated in chip-specific code because it may cause some | |
552 | * chip-specific adjustments to be made. | |
553 | */ | |
554 | uctxts = dd->cfgctxts - dd->first_user_ctxt; | |
555 | dd->ctxts_extrabuf = dd->pbufsctxt ? | |
556 | dd->lastctxt_piobuf - (dd->pbufsctxt * uctxts) : 0; | |
557 | ||
558 | /* | |
559 | * Set up the shadow copies of the piobufavail registers, | |
560 | * which we compare against the chip registers for now, and | |
561 | * the in memory DMA'ed copies of the registers. | |
562 | * By now pioavail updates to memory should have occurred, so | |
563 | * copy them into our working/shadow registers; this is in | |
564 | * case something went wrong with abort, but mostly to get the | |
565 | * initial values of the generation bit correct. | |
566 | */ | |
567 | for (i = 0; i < dd->pioavregs; i++) { | |
568 | __le64 tmp; | |
569 | ||
570 | tmp = dd->pioavailregs_dma[i]; | |
571 | /* | |
572 | * Don't need to worry about pioavailkernel here | |
573 | * because we will call qib_chg_pioavailkernel() later | |
574 | * in initialization, to busy out buffers as needed. | |
575 | */ | |
576 | dd->pioavailshadow[i] = le64_to_cpu(tmp); | |
577 | } | |
578 | while (i < ARRAY_SIZE(dd->pioavailshadow)) | |
579 | dd->pioavailshadow[i++] = 0; /* for debugging sanity */ | |
580 | ||
581 | /* after pioavailshadow is setup */ | |
582 | qib_chg_pioavailkernel(dd, 0, dd->piobcnt2k + dd->piobcnt4k, | |
583 | TXCHK_CHG_TYPE_KERN, NULL); | |
584 | dd->f_initvl15_bufs(dd); | |
585 | } | |
586 | ||
551ace12 MM |
587 | /** |
588 | * qib_create_workqueues - create per port workqueues | |
589 | * @dd: the qlogic_ib device | |
590 | */ | |
591 | static int qib_create_workqueues(struct qib_devdata *dd) | |
592 | { | |
593 | int pidx; | |
594 | struct qib_pportdata *ppd; | |
595 | ||
596 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
597 | ppd = dd->pport + pidx; | |
598 | if (!ppd->qib_wq) { | |
599 | char wq_name[8]; /* 3 + 2 + 1 + 1 + 1 */ | |
600 | snprintf(wq_name, sizeof(wq_name), "qib%d_%d", | |
601 | dd->unit, pidx); | |
602 | ppd->qib_wq = | |
603 | create_singlethread_workqueue(wq_name); | |
604 | if (!ppd->qib_wq) | |
605 | goto wq_error; | |
606 | } | |
607 | } | |
608 | return 0; | |
609 | wq_error: | |
7fac3301 MM |
610 | pr_err("create_singlethread_workqueue failed for port %d\n", |
611 | pidx + 1); | |
551ace12 MM |
612 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { |
613 | ppd = dd->pport + pidx; | |
614 | if (ppd->qib_wq) { | |
615 | destroy_workqueue(ppd->qib_wq); | |
616 | ppd->qib_wq = NULL; | |
617 | } | |
618 | } | |
619 | return -ENOMEM; | |
620 | } | |
621 | ||
f931551b RC |
622 | /** |
623 | * qib_init - do the actual initialization sequence on the chip | |
624 | * @dd: the qlogic_ib device | |
625 | * @reinit: reinitializing, so don't allocate new memory | |
626 | * | |
627 | * Do the actual initialization sequence on the chip. This is done | |
628 | * both from the init routine called from the PCI infrastructure, and | |
629 | * when we reset the chip, or detect that it was reset internally, | |
630 | * or it's administratively re-enabled. | |
631 | * | |
632 | * Memory allocation here and in called routines is only done in | |
633 | * the first case (reinit == 0). We have to be careful, because even | |
634 | * without memory allocation, we need to re-write all the chip registers | |
635 | * TIDs, etc. after the reset or enable has completed. | |
636 | */ | |
637 | int qib_init(struct qib_devdata *dd, int reinit) | |
638 | { | |
639 | int ret = 0, pidx, lastfail = 0; | |
640 | u32 portok = 0; | |
641 | unsigned i; | |
642 | struct qib_ctxtdata *rcd; | |
643 | struct qib_pportdata *ppd; | |
644 | unsigned long flags; | |
645 | ||
646 | /* Set linkstate to unknown, so we can watch for a transition. */ | |
647 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
648 | ppd = dd->pport + pidx; | |
649 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
650 | ppd->lflags &= ~(QIBL_LINKACTIVE | QIBL_LINKARMED | | |
651 | QIBL_LINKDOWN | QIBL_LINKINIT | | |
652 | QIBL_LINKV); | |
653 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
654 | } | |
655 | ||
656 | if (reinit) | |
657 | ret = init_after_reset(dd); | |
658 | else | |
659 | ret = loadtime_init(dd); | |
660 | if (ret) | |
661 | goto done; | |
662 | ||
663 | /* Bypass most chip-init, to get to device creation */ | |
664 | if (qib_mini_init) | |
665 | return 0; | |
666 | ||
667 | ret = dd->f_late_initreg(dd); | |
668 | if (ret) | |
669 | goto done; | |
670 | ||
671 | /* dd->rcd can be NULL if early init failed */ | |
672 | for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) { | |
673 | /* | |
674 | * Set up the (kernel) rcvhdr queue and egr TIDs. If doing | |
675 | * re-init, the simplest way to handle this is to free | |
676 | * existing, and re-allocate. | |
677 | * Need to re-create rest of ctxt 0 ctxtdata as well. | |
678 | */ | |
679 | rcd = dd->rcd[i]; | |
680 | if (!rcd) | |
681 | continue; | |
682 | ||
683 | lastfail = qib_create_rcvhdrq(dd, rcd); | |
684 | if (!lastfail) | |
685 | lastfail = qib_setup_eagerbufs(rcd); | |
686 | if (lastfail) { | |
7fac3301 MM |
687 | qib_dev_err(dd, |
688 | "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n"); | |
f931551b RC |
689 | continue; |
690 | } | |
691 | } | |
692 | ||
693 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
694 | int mtu; | |
695 | if (lastfail) | |
696 | ret = lastfail; | |
697 | ppd = dd->pport + pidx; | |
698 | mtu = ib_mtu_enum_to_int(qib_ibmtu); | |
699 | if (mtu == -1) { | |
700 | mtu = QIB_DEFAULT_MTU; | |
701 | qib_ibmtu = 0; /* don't leave invalid value */ | |
702 | } | |
703 | /* set max we can ever have for this driver load */ | |
704 | ppd->init_ibmaxlen = min(mtu > 2048 ? | |
705 | dd->piosize4k : dd->piosize2k, | |
706 | dd->rcvegrbufsize + | |
707 | (dd->rcvhdrentsize << 2)); | |
708 | /* | |
709 | * Have to initialize ibmaxlen, but this will normally | |
710 | * change immediately in qib_set_mtu(). | |
711 | */ | |
712 | ppd->ibmaxlen = ppd->init_ibmaxlen; | |
713 | qib_set_mtu(ppd, mtu); | |
714 | ||
715 | spin_lock_irqsave(&ppd->lflags_lock, flags); | |
716 | ppd->lflags |= QIBL_IB_LINK_DISABLED; | |
717 | spin_unlock_irqrestore(&ppd->lflags_lock, flags); | |
718 | ||
719 | lastfail = dd->f_bringup_serdes(ppd); | |
720 | if (lastfail) { | |
721 | qib_devinfo(dd->pcidev, | |
722 | "Failed to bringup IB port %u\n", ppd->port); | |
723 | lastfail = -ENETDOWN; | |
724 | continue; | |
725 | } | |
726 | ||
f931551b RC |
727 | portok++; |
728 | } | |
729 | ||
730 | if (!portok) { | |
731 | /* none of the ports initialized */ | |
732 | if (!ret && lastfail) | |
733 | ret = lastfail; | |
734 | else if (!ret) | |
735 | ret = -ENETDOWN; | |
736 | /* but continue on, so we can debug cause */ | |
737 | } | |
738 | ||
739 | enable_chip(dd); | |
740 | ||
741 | init_piobuf_state(dd); | |
742 | ||
743 | done: | |
744 | if (!ret) { | |
745 | /* chip is OK for user apps; mark it as initialized */ | |
746 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
747 | ppd = dd->pport + pidx; | |
748 | /* | |
749 | * Set status even if port serdes is not initialized | |
750 | * so that diags will work. | |
751 | */ | |
752 | *ppd->statusp |= QIB_STATUS_CHIP_PRESENT | | |
753 | QIB_STATUS_INITTED; | |
754 | if (!ppd->link_speed_enabled) | |
755 | continue; | |
756 | if (dd->flags & QIB_HAS_SEND_DMA) | |
757 | ret = qib_setup_sdma(ppd); | |
758 | init_timer(&ppd->hol_timer); | |
759 | ppd->hol_timer.function = qib_hol_event; | |
760 | ppd->hol_timer.data = (unsigned long)ppd; | |
761 | ppd->hol_state = QIB_HOL_UP; | |
762 | } | |
763 | ||
764 | /* now we can enable all interrupts from the chip */ | |
765 | dd->f_set_intr_state(dd, 1); | |
766 | ||
767 | /* | |
768 | * Setup to verify we get an interrupt, and fallback | |
769 | * to an alternate if necessary and possible. | |
770 | */ | |
771 | mod_timer(&dd->intrchk_timer, jiffies + HZ/2); | |
772 | /* start stats retrieval timer */ | |
773 | mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); | |
774 | } | |
775 | ||
776 | /* if ret is non-zero, we probably should do some cleanup here... */ | |
777 | return ret; | |
778 | } | |
779 | ||
780 | /* | |
781 | * These next two routines are placeholders in case we don't have per-arch | |
782 | * code for controlling write combining. If explicit control of write | |
783 | * combining is not available, performance will probably be awful. | |
784 | */ | |
785 | ||
786 | int __attribute__((weak)) qib_enable_wc(struct qib_devdata *dd) | |
787 | { | |
788 | return -EOPNOTSUPP; | |
789 | } | |
790 | ||
791 | void __attribute__((weak)) qib_disable_wc(struct qib_devdata *dd) | |
792 | { | |
793 | } | |
794 | ||
795 | static inline struct qib_devdata *__qib_lookup(int unit) | |
796 | { | |
797 | return idr_find(&qib_unit_table, unit); | |
798 | } | |
799 | ||
800 | struct qib_devdata *qib_lookup(int unit) | |
801 | { | |
802 | struct qib_devdata *dd; | |
803 | unsigned long flags; | |
804 | ||
805 | spin_lock_irqsave(&qib_devs_lock, flags); | |
806 | dd = __qib_lookup(unit); | |
807 | spin_unlock_irqrestore(&qib_devs_lock, flags); | |
808 | ||
809 | return dd; | |
810 | } | |
811 | ||
812 | /* | |
813 | * Stop the timers during unit shutdown, or after an error late | |
814 | * in initialization. | |
815 | */ | |
816 | static void qib_stop_timers(struct qib_devdata *dd) | |
817 | { | |
818 | struct qib_pportdata *ppd; | |
819 | int pidx; | |
820 | ||
821 | if (dd->stats_timer.data) { | |
822 | del_timer_sync(&dd->stats_timer); | |
823 | dd->stats_timer.data = 0; | |
824 | } | |
825 | if (dd->intrchk_timer.data) { | |
826 | del_timer_sync(&dd->intrchk_timer); | |
827 | dd->intrchk_timer.data = 0; | |
828 | } | |
829 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
830 | ppd = dd->pport + pidx; | |
831 | if (ppd->hol_timer.data) | |
832 | del_timer_sync(&ppd->hol_timer); | |
833 | if (ppd->led_override_timer.data) { | |
834 | del_timer_sync(&ppd->led_override_timer); | |
835 | atomic_set(&ppd->led_override_timer_active, 0); | |
836 | } | |
837 | if (ppd->symerr_clear_timer.data) | |
838 | del_timer_sync(&ppd->symerr_clear_timer); | |
839 | } | |
840 | } | |
841 | ||
842 | /** | |
843 | * qib_shutdown_device - shut down a device | |
844 | * @dd: the qlogic_ib device | |
845 | * | |
846 | * This is called to make the device quiet when we are about to | |
847 | * unload the driver, and also when the device is administratively | |
848 | * disabled. It does not free any data structures. | |
849 | * Everything it does has to be setup again by qib_init(dd, 1) | |
850 | */ | |
851 | static void qib_shutdown_device(struct qib_devdata *dd) | |
852 | { | |
853 | struct qib_pportdata *ppd; | |
854 | unsigned pidx; | |
855 | ||
856 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
857 | ppd = dd->pport + pidx; | |
858 | ||
859 | spin_lock_irq(&ppd->lflags_lock); | |
860 | ppd->lflags &= ~(QIBL_LINKDOWN | QIBL_LINKINIT | | |
861 | QIBL_LINKARMED | QIBL_LINKACTIVE | | |
862 | QIBL_LINKV); | |
863 | spin_unlock_irq(&ppd->lflags_lock); | |
864 | *ppd->statusp &= ~(QIB_STATUS_IB_CONF | QIB_STATUS_IB_READY); | |
865 | } | |
866 | dd->flags &= ~QIB_INITTED; | |
867 | ||
868 | /* mask interrupts, but not errors */ | |
869 | dd->f_set_intr_state(dd, 0); | |
870 | ||
871 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
872 | ppd = dd->pport + pidx; | |
873 | dd->f_rcvctrl(ppd, QIB_RCVCTRL_TAILUPD_DIS | | |
874 | QIB_RCVCTRL_CTXT_DIS | | |
875 | QIB_RCVCTRL_INTRAVAIL_DIS | | |
876 | QIB_RCVCTRL_PKEY_ENB, -1); | |
877 | /* | |
878 | * Gracefully stop all sends allowing any in progress to | |
879 | * trickle out first. | |
880 | */ | |
881 | dd->f_sendctrl(ppd, QIB_SENDCTRL_CLEAR); | |
882 | } | |
883 | ||
884 | /* | |
885 | * Enough for anything that's going to trickle out to have actually | |
886 | * done so. | |
887 | */ | |
888 | udelay(20); | |
889 | ||
890 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
891 | ppd = dd->pport + pidx; | |
892 | dd->f_setextled(ppd, 0); /* make sure LEDs are off */ | |
893 | ||
894 | if (dd->flags & QIB_HAS_SEND_DMA) | |
895 | qib_teardown_sdma(ppd); | |
896 | ||
897 | dd->f_sendctrl(ppd, QIB_SENDCTRL_AVAIL_DIS | | |
898 | QIB_SENDCTRL_SEND_DIS); | |
899 | /* | |
900 | * Clear SerdesEnable. | |
901 | * We can't count on interrupts since we are stopping. | |
902 | */ | |
903 | dd->f_quiet_serdes(ppd); | |
551ace12 MM |
904 | |
905 | if (ppd->qib_wq) { | |
906 | destroy_workqueue(ppd->qib_wq); | |
907 | ppd->qib_wq = NULL; | |
908 | } | |
f931551b RC |
909 | } |
910 | ||
911 | qib_update_eeprom_log(dd); | |
912 | } | |
913 | ||
914 | /** | |
915 | * qib_free_ctxtdata - free a context's allocated data | |
916 | * @dd: the qlogic_ib device | |
917 | * @rcd: the ctxtdata structure | |
918 | * | |
919 | * free up any allocated data for a context | |
920 | * This should not touch anything that would affect a simultaneous | |
921 | * re-allocation of context data, because it is called after qib_mutex | |
922 | * is released (and can be called from reinit as well). | |
923 | * It should never change any chip state, or global driver state. | |
924 | */ | |
925 | void qib_free_ctxtdata(struct qib_devdata *dd, struct qib_ctxtdata *rcd) | |
926 | { | |
927 | if (!rcd) | |
928 | return; | |
929 | ||
930 | if (rcd->rcvhdrq) { | |
931 | dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size, | |
932 | rcd->rcvhdrq, rcd->rcvhdrq_phys); | |
933 | rcd->rcvhdrq = NULL; | |
934 | if (rcd->rcvhdrtail_kvaddr) { | |
935 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
936 | rcd->rcvhdrtail_kvaddr, | |
937 | rcd->rcvhdrqtailaddr_phys); | |
938 | rcd->rcvhdrtail_kvaddr = NULL; | |
939 | } | |
940 | } | |
941 | if (rcd->rcvegrbuf) { | |
942 | unsigned e; | |
943 | ||
944 | for (e = 0; e < rcd->rcvegrbuf_chunks; e++) { | |
945 | void *base = rcd->rcvegrbuf[e]; | |
946 | size_t size = rcd->rcvegrbuf_size; | |
947 | ||
948 | dma_free_coherent(&dd->pcidev->dev, size, | |
949 | base, rcd->rcvegrbuf_phys[e]); | |
950 | } | |
951 | kfree(rcd->rcvegrbuf); | |
952 | rcd->rcvegrbuf = NULL; | |
953 | kfree(rcd->rcvegrbuf_phys); | |
954 | rcd->rcvegrbuf_phys = NULL; | |
955 | rcd->rcvegrbuf_chunks = 0; | |
956 | } | |
957 | ||
958 | kfree(rcd->tid_pg_list); | |
959 | vfree(rcd->user_event_mask); | |
960 | vfree(rcd->subctxt_uregbase); | |
961 | vfree(rcd->subctxt_rcvegrbuf); | |
962 | vfree(rcd->subctxt_rcvhdr_base); | |
963 | kfree(rcd); | |
964 | } | |
965 | ||
966 | /* | |
967 | * Perform a PIO buffer bandwidth write test, to verify proper system | |
968 | * configuration. Even when all the setup calls work, occasionally | |
969 | * BIOS or other issues can prevent write combining from working, or | |
970 | * can cause other bandwidth problems to the chip. | |
971 | * | |
972 | * This test simply writes the same buffer over and over again, and | |
973 | * measures close to the peak bandwidth to the chip (not testing | |
974 | * data bandwidth to the wire). On chips that use an address-based | |
975 | * trigger to send packets to the wire, this is easy. On chips that | |
976 | * use a count to trigger, we want to make sure that the packet doesn't | |
977 | * go out on the wire, or trigger flow control checks. | |
978 | */ | |
979 | static void qib_verify_pioperf(struct qib_devdata *dd) | |
980 | { | |
981 | u32 pbnum, cnt, lcnt; | |
982 | u32 __iomem *piobuf; | |
983 | u32 *addr; | |
984 | u64 msecs, emsecs; | |
985 | ||
986 | piobuf = dd->f_getsendbuf(dd->pport, 0ULL, &pbnum); | |
987 | if (!piobuf) { | |
988 | qib_devinfo(dd->pcidev, | |
989 | "No PIObufs for checking perf, skipping\n"); | |
990 | return; | |
991 | } | |
992 | ||
993 | /* | |
994 | * Enough to give us a reasonable test, less than piobuf size, and | |
995 | * likely multiple of store buffer length. | |
996 | */ | |
997 | cnt = 1024; | |
998 | ||
999 | addr = vmalloc(cnt); | |
1000 | if (!addr) { | |
1001 | qib_devinfo(dd->pcidev, | |
1002 | "Couldn't get memory for checking PIO perf," | |
1003 | " skipping\n"); | |
1004 | goto done; | |
1005 | } | |
1006 | ||
1007 | preempt_disable(); /* we want reasonably accurate elapsed time */ | |
1008 | msecs = 1 + jiffies_to_msecs(jiffies); | |
1009 | for (lcnt = 0; lcnt < 10000U; lcnt++) { | |
1010 | /* wait until we cross msec boundary */ | |
1011 | if (jiffies_to_msecs(jiffies) >= msecs) | |
1012 | break; | |
1013 | udelay(1); | |
1014 | } | |
1015 | ||
1016 | dd->f_set_armlaunch(dd, 0); | |
1017 | ||
1018 | /* | |
1019 | * length 0, no dwords actually sent | |
1020 | */ | |
1021 | writeq(0, piobuf); | |
1022 | qib_flush_wc(); | |
1023 | ||
1024 | /* | |
1025 | * This is only roughly accurate, since even with preempt we | |
1026 | * still take interrupts that could take a while. Running for | |
1027 | * >= 5 msec seems to get us "close enough" to accurate values. | |
1028 | */ | |
1029 | msecs = jiffies_to_msecs(jiffies); | |
1030 | for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) { | |
1031 | qib_pio_copy(piobuf + 64, addr, cnt >> 2); | |
1032 | emsecs = jiffies_to_msecs(jiffies) - msecs; | |
1033 | } | |
1034 | ||
1035 | /* 1 GiB/sec, slightly over IB SDR line rate */ | |
1036 | if (lcnt < (emsecs * 1024U)) | |
1037 | qib_dev_err(dd, | |
7fac3301 | 1038 | "Performance problem: bandwidth to PIO buffers is only %u MiB/sec\n", |
f931551b RC |
1039 | lcnt / (u32) emsecs); |
1040 | ||
1041 | preempt_enable(); | |
1042 | ||
1043 | vfree(addr); | |
1044 | ||
1045 | done: | |
1046 | /* disarm piobuf, so it's available again */ | |
1047 | dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbnum)); | |
1048 | qib_sendbuf_done(dd, pbnum); | |
1049 | dd->f_set_armlaunch(dd, 1); | |
1050 | } | |
1051 | ||
1052 | ||
1053 | void qib_free_devdata(struct qib_devdata *dd) | |
1054 | { | |
1055 | unsigned long flags; | |
1056 | ||
1057 | spin_lock_irqsave(&qib_devs_lock, flags); | |
1058 | idr_remove(&qib_unit_table, dd->unit); | |
1059 | list_del(&dd->list); | |
1060 | spin_unlock_irqrestore(&qib_devs_lock, flags); | |
1061 | ||
1062 | ib_dealloc_device(&dd->verbs_dev.ibdev); | |
1063 | } | |
1064 | ||
1065 | /* | |
1066 | * Allocate our primary per-unit data structure. Must be done via verbs | |
1067 | * allocator, because the verbs cleanup process both does cleanup and | |
1068 | * free of the data structure. | |
1069 | * "extra" is for chip-specific data. | |
1070 | * | |
1071 | * Use the idr mechanism to get a unit number for this unit. | |
1072 | */ | |
1073 | struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra) | |
1074 | { | |
1075 | unsigned long flags; | |
1076 | struct qib_devdata *dd; | |
1077 | int ret; | |
1078 | ||
f931551b RC |
1079 | dd = (struct qib_devdata *) ib_alloc_device(sizeof(*dd) + extra); |
1080 | if (!dd) { | |
1081 | dd = ERR_PTR(-ENOMEM); | |
1082 | goto bail; | |
1083 | } | |
1084 | ||
80f22b44 | 1085 | idr_preload(GFP_KERNEL); |
f931551b | 1086 | spin_lock_irqsave(&qib_devs_lock, flags); |
80f22b44 TH |
1087 | |
1088 | ret = idr_alloc(&qib_unit_table, dd, 0, 0, GFP_NOWAIT); | |
1089 | if (ret >= 0) { | |
1090 | dd->unit = ret; | |
f931551b | 1091 | list_add(&dd->list, &qib_dev_list); |
80f22b44 TH |
1092 | } |
1093 | ||
f931551b | 1094 | spin_unlock_irqrestore(&qib_devs_lock, flags); |
80f22b44 | 1095 | idr_preload_end(); |
f931551b RC |
1096 | |
1097 | if (ret < 0) { | |
1098 | qib_early_err(&pdev->dev, | |
1099 | "Could not allocate unit ID: error %d\n", -ret); | |
1100 | ib_dealloc_device(&dd->verbs_dev.ibdev); | |
1101 | dd = ERR_PTR(ret); | |
1102 | goto bail; | |
1103 | } | |
1104 | ||
1105 | if (!qib_cpulist_count) { | |
1106 | u32 count = num_online_cpus(); | |
1107 | qib_cpulist = kzalloc(BITS_TO_LONGS(count) * | |
1108 | sizeof(long), GFP_KERNEL); | |
1109 | if (qib_cpulist) | |
1110 | qib_cpulist_count = count; | |
1111 | else | |
7fac3301 MM |
1112 | qib_early_err(&pdev->dev, |
1113 | "Could not alloc cpulist info, cpu affinity might be wrong\n"); | |
f931551b RC |
1114 | } |
1115 | ||
1116 | bail: | |
1117 | return dd; | |
1118 | } | |
1119 | ||
1120 | /* | |
1121 | * Called from freeze mode handlers, and from PCI error | |
1122 | * reporting code. Should be paranoid about state of | |
1123 | * system and data structures. | |
1124 | */ | |
1125 | void qib_disable_after_error(struct qib_devdata *dd) | |
1126 | { | |
1127 | if (dd->flags & QIB_INITTED) { | |
1128 | u32 pidx; | |
1129 | ||
1130 | dd->flags &= ~QIB_INITTED; | |
1131 | if (dd->pport) | |
1132 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
1133 | struct qib_pportdata *ppd; | |
1134 | ||
1135 | ppd = dd->pport + pidx; | |
1136 | if (dd->flags & QIB_PRESENT) { | |
1137 | qib_set_linkstate(ppd, | |
1138 | QIB_IB_LINKDOWN_DISABLE); | |
1139 | dd->f_setextled(ppd, 0); | |
1140 | } | |
1141 | *ppd->statusp &= ~QIB_STATUS_IB_READY; | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /* | |
1146 | * Mark as having had an error for driver, and also | |
1147 | * for /sys and status word mapped to user programs. | |
1148 | * This marks unit as not usable, until reset. | |
1149 | */ | |
1150 | if (dd->devstatusp) | |
1151 | *dd->devstatusp |= QIB_STATUS_HWERROR; | |
1152 | } | |
1153 | ||
1e6d9abe GKH |
1154 | static void qib_remove_one(struct pci_dev *); |
1155 | static int qib_init_one(struct pci_dev *, const struct pci_device_id *); | |
f931551b | 1156 | |
e2eed58b | 1157 | #define DRIVER_LOAD_MSG "Intel " QIB_DRV_NAME " loaded: " |
f931551b RC |
1158 | #define PFX QIB_DRV_NAME ": " |
1159 | ||
865b64be | 1160 | static DEFINE_PCI_DEVICE_TABLE(qib_pci_tbl) = { |
f931551b RC |
1161 | { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_QLOGIC_IB_6120) }, |
1162 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7220) }, | |
1163 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7322) }, | |
1164 | { 0, } | |
1165 | }; | |
1166 | ||
1167 | MODULE_DEVICE_TABLE(pci, qib_pci_tbl); | |
1168 | ||
1169 | struct pci_driver qib_driver = { | |
1170 | .name = QIB_DRV_NAME, | |
1171 | .probe = qib_init_one, | |
1e6d9abe | 1172 | .remove = qib_remove_one, |
f931551b RC |
1173 | .id_table = qib_pci_tbl, |
1174 | .err_handler = &qib_pci_err_handler, | |
1175 | }; | |
1176 | ||
8469ba39 MM |
1177 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
1178 | ||
1179 | static int qib_notify_dca(struct notifier_block *, unsigned long, void *); | |
1180 | static struct notifier_block dca_notifier = { | |
1181 | .notifier_call = qib_notify_dca, | |
1182 | .next = NULL, | |
1183 | .priority = 0 | |
1184 | }; | |
1185 | ||
1186 | static int qib_notify_dca_device(struct device *device, void *data) | |
1187 | { | |
1188 | struct qib_devdata *dd = dev_get_drvdata(device); | |
1189 | unsigned long event = *(unsigned long *)data; | |
1190 | ||
1191 | return dd->f_notify_dca(dd, event); | |
1192 | } | |
1193 | ||
1194 | static int qib_notify_dca(struct notifier_block *nb, unsigned long event, | |
1195 | void *p) | |
1196 | { | |
1197 | int rval; | |
1198 | ||
1199 | rval = driver_for_each_device(&qib_driver.driver, NULL, | |
1200 | &event, qib_notify_dca_device); | |
1201 | return rval ? NOTIFY_BAD : NOTIFY_DONE; | |
1202 | } | |
1203 | ||
1204 | #endif | |
1205 | ||
f931551b RC |
1206 | /* |
1207 | * Do all the generic driver unit- and chip-independent memory | |
1208 | * allocation and initialization. | |
1209 | */ | |
1210 | static int __init qlogic_ib_init(void) | |
1211 | { | |
1212 | int ret; | |
1213 | ||
1214 | ret = qib_dev_init(); | |
1215 | if (ret) | |
1216 | goto bail; | |
1217 | ||
950aff53 | 1218 | qib_cq_wq = create_singlethread_workqueue("qib_cq"); |
f931551b RC |
1219 | if (!qib_cq_wq) { |
1220 | ret = -ENOMEM; | |
f0626710 | 1221 | goto bail_dev; |
f931551b RC |
1222 | } |
1223 | ||
1224 | /* | |
1225 | * These must be called before the driver is registered with | |
1226 | * the PCI subsystem. | |
1227 | */ | |
1228 | idr_init(&qib_unit_table); | |
f931551b | 1229 | |
8469ba39 MM |
1230 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
1231 | dca_register_notify(&dca_notifier); | |
1232 | #endif | |
f931551b RC |
1233 | ret = pci_register_driver(&qib_driver); |
1234 | if (ret < 0) { | |
7fac3301 | 1235 | pr_err("Unable to register driver: error %d\n", -ret); |
f931551b RC |
1236 | goto bail_unit; |
1237 | } | |
1238 | ||
1239 | /* not fatal if it doesn't work */ | |
1240 | if (qib_init_qibfs()) | |
7fac3301 | 1241 | pr_err("Unable to register ipathfs\n"); |
f931551b RC |
1242 | goto bail; /* all OK */ |
1243 | ||
1244 | bail_unit: | |
8469ba39 MM |
1245 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
1246 | dca_unregister_notify(&dca_notifier); | |
1247 | #endif | |
f931551b | 1248 | idr_destroy(&qib_unit_table); |
f931551b | 1249 | destroy_workqueue(qib_cq_wq); |
f931551b RC |
1250 | bail_dev: |
1251 | qib_dev_cleanup(); | |
1252 | bail: | |
1253 | return ret; | |
1254 | } | |
1255 | ||
1256 | module_init(qlogic_ib_init); | |
1257 | ||
1258 | /* | |
1259 | * Do the non-unit driver cleanup, memory free, etc. at unload. | |
1260 | */ | |
1261 | static void __exit qlogic_ib_cleanup(void) | |
1262 | { | |
1263 | int ret; | |
1264 | ||
1265 | ret = qib_exit_qibfs(); | |
1266 | if (ret) | |
7fac3301 MM |
1267 | pr_err( |
1268 | "Unable to cleanup counter filesystem: error %d\n", | |
1269 | -ret); | |
f931551b | 1270 | |
8469ba39 MM |
1271 | #ifdef CONFIG_INFINIBAND_QIB_DCA |
1272 | dca_unregister_notify(&dca_notifier); | |
1273 | #endif | |
f931551b RC |
1274 | pci_unregister_driver(&qib_driver); |
1275 | ||
f931551b RC |
1276 | destroy_workqueue(qib_cq_wq); |
1277 | ||
1278 | qib_cpulist_count = 0; | |
1279 | kfree(qib_cpulist); | |
1280 | ||
1281 | idr_destroy(&qib_unit_table); | |
1282 | qib_dev_cleanup(); | |
1283 | } | |
1284 | ||
1285 | module_exit(qlogic_ib_cleanup); | |
1286 | ||
1287 | /* this can only be called after a successful initialization */ | |
1288 | static void cleanup_device_data(struct qib_devdata *dd) | |
1289 | { | |
1290 | int ctxt; | |
1291 | int pidx; | |
1292 | struct qib_ctxtdata **tmp; | |
1293 | unsigned long flags; | |
1294 | ||
1295 | /* users can't do anything more with chip */ | |
36a8f01c | 1296 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { |
f931551b RC |
1297 | if (dd->pport[pidx].statusp) |
1298 | *dd->pport[pidx].statusp &= ~QIB_STATUS_CHIP_PRESENT; | |
1299 | ||
36a8f01c MM |
1300 | spin_lock(&dd->pport[pidx].cc_shadow_lock); |
1301 | ||
1302 | kfree(dd->pport[pidx].congestion_entries); | |
1303 | dd->pport[pidx].congestion_entries = NULL; | |
1304 | kfree(dd->pport[pidx].ccti_entries); | |
1305 | dd->pport[pidx].ccti_entries = NULL; | |
1306 | kfree(dd->pport[pidx].ccti_entries_shadow); | |
1307 | dd->pport[pidx].ccti_entries_shadow = NULL; | |
1308 | kfree(dd->pport[pidx].congestion_entries_shadow); | |
1309 | dd->pport[pidx].congestion_entries_shadow = NULL; | |
1310 | ||
1311 | spin_unlock(&dd->pport[pidx].cc_shadow_lock); | |
1312 | } | |
1313 | ||
f931551b RC |
1314 | if (!qib_wc_pat) |
1315 | qib_disable_wc(dd); | |
1316 | ||
1317 | if (dd->pioavailregs_dma) { | |
1318 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
1319 | (void *) dd->pioavailregs_dma, | |
1320 | dd->pioavailregs_phys); | |
1321 | dd->pioavailregs_dma = NULL; | |
1322 | } | |
1323 | ||
1324 | if (dd->pageshadow) { | |
1325 | struct page **tmpp = dd->pageshadow; | |
1326 | dma_addr_t *tmpd = dd->physshadow; | |
1327 | int i, cnt = 0; | |
1328 | ||
1329 | for (ctxt = 0; ctxt < dd->cfgctxts; ctxt++) { | |
1330 | int ctxt_tidbase = ctxt * dd->rcvtidcnt; | |
1331 | int maxtid = ctxt_tidbase + dd->rcvtidcnt; | |
1332 | ||
1333 | for (i = ctxt_tidbase; i < maxtid; i++) { | |
1334 | if (!tmpp[i]) | |
1335 | continue; | |
1336 | pci_unmap_page(dd->pcidev, tmpd[i], | |
1337 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | |
1338 | qib_release_user_pages(&tmpp[i], 1); | |
1339 | tmpp[i] = NULL; | |
1340 | cnt++; | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | tmpp = dd->pageshadow; | |
1345 | dd->pageshadow = NULL; | |
1346 | vfree(tmpp); | |
1347 | } | |
1348 | ||
1349 | /* | |
1350 | * Free any resources still in use (usually just kernel contexts) | |
1351 | * at unload; we do for ctxtcnt, because that's what we allocate. | |
1352 | * We acquire lock to be really paranoid that rcd isn't being | |
1353 | * accessed from some interrupt-related code (that should not happen, | |
1354 | * but best to be sure). | |
1355 | */ | |
1356 | spin_lock_irqsave(&dd->uctxt_lock, flags); | |
1357 | tmp = dd->rcd; | |
1358 | dd->rcd = NULL; | |
1359 | spin_unlock_irqrestore(&dd->uctxt_lock, flags); | |
1360 | for (ctxt = 0; tmp && ctxt < dd->ctxtcnt; ctxt++) { | |
1361 | struct qib_ctxtdata *rcd = tmp[ctxt]; | |
1362 | ||
1363 | tmp[ctxt] = NULL; /* debugging paranoia */ | |
1364 | qib_free_ctxtdata(dd, rcd); | |
1365 | } | |
1366 | kfree(tmp); | |
1367 | kfree(dd->boardname); | |
1368 | } | |
1369 | ||
1370 | /* | |
1371 | * Clean up on unit shutdown, or error during unit load after | |
1372 | * successful initialization. | |
1373 | */ | |
1374 | static void qib_postinit_cleanup(struct qib_devdata *dd) | |
1375 | { | |
1376 | /* | |
1377 | * Clean up chip-specific stuff. | |
1378 | * We check for NULL here, because it's outside | |
1379 | * the kregbase check, and we need to call it | |
1380 | * after the free_irq. Thus it's possible that | |
1381 | * the function pointers were never initialized. | |
1382 | */ | |
1383 | if (dd->f_cleanup) | |
1384 | dd->f_cleanup(dd); | |
1385 | ||
1386 | qib_pcie_ddcleanup(dd); | |
1387 | ||
1388 | cleanup_device_data(dd); | |
1389 | ||
1390 | qib_free_devdata(dd); | |
1391 | } | |
1392 | ||
1e6d9abe | 1393 | static int qib_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
f931551b RC |
1394 | { |
1395 | int ret, j, pidx, initfail; | |
1396 | struct qib_devdata *dd = NULL; | |
1397 | ||
1398 | ret = qib_pcie_init(pdev, ent); | |
1399 | if (ret) | |
1400 | goto bail; | |
1401 | ||
1402 | /* | |
1403 | * Do device-specific initialiation, function table setup, dd | |
1404 | * allocation, etc. | |
1405 | */ | |
1406 | switch (ent->device) { | |
1407 | case PCI_DEVICE_ID_QLOGIC_IB_6120: | |
7e3a1f4a | 1408 | #ifdef CONFIG_PCI_MSI |
f931551b | 1409 | dd = qib_init_iba6120_funcs(pdev, ent); |
7e3a1f4a | 1410 | #else |
7fac3301 | 1411 | qib_early_err(&pdev->dev, |
e2eed58b | 1412 | "Intel PCIE device 0x%x cannot work if CONFIG_PCI_MSI is not enabled\n", |
7fac3301 | 1413 | ent->device); |
9e43e010 | 1414 | dd = ERR_PTR(-ENODEV); |
7e3a1f4a | 1415 | #endif |
f931551b RC |
1416 | break; |
1417 | ||
1418 | case PCI_DEVICE_ID_QLOGIC_IB_7220: | |
1419 | dd = qib_init_iba7220_funcs(pdev, ent); | |
1420 | break; | |
1421 | ||
1422 | case PCI_DEVICE_ID_QLOGIC_IB_7322: | |
1423 | dd = qib_init_iba7322_funcs(pdev, ent); | |
1424 | break; | |
1425 | ||
1426 | default: | |
7fac3301 | 1427 | qib_early_err(&pdev->dev, |
e2eed58b | 1428 | "Failing on unknown Intel deviceid 0x%x\n", |
7fac3301 | 1429 | ent->device); |
f931551b RC |
1430 | ret = -ENODEV; |
1431 | } | |
1432 | ||
1433 | if (IS_ERR(dd)) | |
1434 | ret = PTR_ERR(dd); | |
1435 | if (ret) | |
1436 | goto bail; /* error already printed */ | |
1437 | ||
551ace12 MM |
1438 | ret = qib_create_workqueues(dd); |
1439 | if (ret) | |
1440 | goto bail; | |
1441 | ||
f931551b RC |
1442 | /* do the generic initialization */ |
1443 | initfail = qib_init(dd, 0); | |
1444 | ||
1445 | ret = qib_register_ib_device(dd); | |
1446 | ||
1447 | /* | |
1448 | * Now ready for use. this should be cleared whenever we | |
1449 | * detect a reset, or initiate one. If earlier failure, | |
1450 | * we still create devices, so diags, etc. can be used | |
1451 | * to determine cause of problem. | |
1452 | */ | |
1453 | if (!qib_mini_init && !initfail && !ret) | |
1454 | dd->flags |= QIB_INITTED; | |
1455 | ||
1456 | j = qib_device_create(dd); | |
1457 | if (j) | |
1458 | qib_dev_err(dd, "Failed to create /dev devices: %d\n", -j); | |
1459 | j = qibfs_add(dd); | |
1460 | if (j) | |
1461 | qib_dev_err(dd, "Failed filesystem setup for counters: %d\n", | |
1462 | -j); | |
1463 | ||
1464 | if (qib_mini_init || initfail || ret) { | |
1465 | qib_stop_timers(dd); | |
f0626710 | 1466 | flush_workqueue(ib_wq); |
f931551b RC |
1467 | for (pidx = 0; pidx < dd->num_pports; ++pidx) |
1468 | dd->f_quiet_serdes(dd->pport + pidx); | |
756a33b8 RC |
1469 | if (qib_mini_init) |
1470 | goto bail; | |
1471 | if (!j) { | |
1472 | (void) qibfs_remove(dd); | |
1473 | qib_device_remove(dd); | |
1474 | } | |
1475 | if (!ret) | |
1476 | qib_unregister_ib_device(dd); | |
1477 | qib_postinit_cleanup(dd); | |
f931551b RC |
1478 | if (initfail) |
1479 | ret = initfail; | |
1480 | goto bail; | |
1481 | } | |
1482 | ||
1483 | if (!qib_wc_pat) { | |
1484 | ret = qib_enable_wc(dd); | |
1485 | if (ret) { | |
7fac3301 MM |
1486 | qib_dev_err(dd, |
1487 | "Write combining not enabled (err %d): performance may be poor\n", | |
1488 | -ret); | |
f931551b RC |
1489 | ret = 0; |
1490 | } | |
1491 | } | |
1492 | ||
1493 | qib_verify_pioperf(dd); | |
1494 | bail: | |
1495 | return ret; | |
1496 | } | |
1497 | ||
1e6d9abe | 1498 | static void qib_remove_one(struct pci_dev *pdev) |
f931551b RC |
1499 | { |
1500 | struct qib_devdata *dd = pci_get_drvdata(pdev); | |
1501 | int ret; | |
1502 | ||
1503 | /* unregister from IB core */ | |
1504 | qib_unregister_ib_device(dd); | |
1505 | ||
1506 | /* | |
1507 | * Disable the IB link, disable interrupts on the device, | |
1508 | * clear dma engines, etc. | |
1509 | */ | |
1510 | if (!qib_mini_init) | |
1511 | qib_shutdown_device(dd); | |
1512 | ||
1513 | qib_stop_timers(dd); | |
1514 | ||
f0626710 TH |
1515 | /* wait until all of our (qsfp) queue_work() calls complete */ |
1516 | flush_workqueue(ib_wq); | |
f931551b RC |
1517 | |
1518 | ret = qibfs_remove(dd); | |
1519 | if (ret) | |
1520 | qib_dev_err(dd, "Failed counters filesystem cleanup: %d\n", | |
1521 | -ret); | |
1522 | ||
1523 | qib_device_remove(dd); | |
1524 | ||
1525 | qib_postinit_cleanup(dd); | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * qib_create_rcvhdrq - create a receive header queue | |
1530 | * @dd: the qlogic_ib device | |
1531 | * @rcd: the context data | |
1532 | * | |
1533 | * This must be contiguous memory (from an i/o perspective), and must be | |
1534 | * DMA'able (which means for some systems, it will go through an IOMMU, | |
1535 | * or be forced into a low address range). | |
1536 | */ | |
1537 | int qib_create_rcvhdrq(struct qib_devdata *dd, struct qib_ctxtdata *rcd) | |
1538 | { | |
1539 | unsigned amt; | |
e0f30bac | 1540 | int old_node_id; |
f931551b RC |
1541 | |
1542 | if (!rcd->rcvhdrq) { | |
1543 | dma_addr_t phys_hdrqtail; | |
1544 | gfp_t gfp_flags; | |
1545 | ||
1546 | amt = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize * | |
1547 | sizeof(u32), PAGE_SIZE); | |
1548 | gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ? | |
1549 | GFP_USER : GFP_KERNEL; | |
e0f30bac RV |
1550 | |
1551 | old_node_id = dev_to_node(&dd->pcidev->dev); | |
1552 | set_dev_node(&dd->pcidev->dev, rcd->node_id); | |
f931551b RC |
1553 | rcd->rcvhdrq = dma_alloc_coherent( |
1554 | &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys, | |
1555 | gfp_flags | __GFP_COMP); | |
e0f30bac | 1556 | set_dev_node(&dd->pcidev->dev, old_node_id); |
f931551b RC |
1557 | |
1558 | if (!rcd->rcvhdrq) { | |
7fac3301 MM |
1559 | qib_dev_err(dd, |
1560 | "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n", | |
1561 | amt, rcd->ctxt); | |
f931551b RC |
1562 | goto bail; |
1563 | } | |
1564 | ||
1565 | if (rcd->ctxt >= dd->first_user_ctxt) { | |
1566 | rcd->user_event_mask = vmalloc_user(PAGE_SIZE); | |
1567 | if (!rcd->user_event_mask) | |
1568 | goto bail_free_hdrq; | |
1569 | } | |
1570 | ||
1571 | if (!(dd->flags & QIB_NODMA_RTAIL)) { | |
e0f30bac | 1572 | set_dev_node(&dd->pcidev->dev, rcd->node_id); |
f931551b RC |
1573 | rcd->rcvhdrtail_kvaddr = dma_alloc_coherent( |
1574 | &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, | |
1575 | gfp_flags); | |
e0f30bac | 1576 | set_dev_node(&dd->pcidev->dev, old_node_id); |
f931551b RC |
1577 | if (!rcd->rcvhdrtail_kvaddr) |
1578 | goto bail_free; | |
1579 | rcd->rcvhdrqtailaddr_phys = phys_hdrqtail; | |
1580 | } | |
1581 | ||
1582 | rcd->rcvhdrq_size = amt; | |
1583 | } | |
1584 | ||
1585 | /* clear for security and sanity on each use */ | |
1586 | memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size); | |
1587 | if (rcd->rcvhdrtail_kvaddr) | |
1588 | memset(rcd->rcvhdrtail_kvaddr, 0, PAGE_SIZE); | |
1589 | return 0; | |
1590 | ||
1591 | bail_free: | |
7fac3301 MM |
1592 | qib_dev_err(dd, |
1593 | "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n", | |
1594 | rcd->ctxt); | |
f931551b RC |
1595 | vfree(rcd->user_event_mask); |
1596 | rcd->user_event_mask = NULL; | |
1597 | bail_free_hdrq: | |
1598 | dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq, | |
1599 | rcd->rcvhdrq_phys); | |
1600 | rcd->rcvhdrq = NULL; | |
1601 | bail: | |
1602 | return -ENOMEM; | |
1603 | } | |
1604 | ||
1605 | /** | |
1606 | * allocate eager buffers, both kernel and user contexts. | |
1607 | * @rcd: the context we are setting up. | |
1608 | * | |
1609 | * Allocate the eager TID buffers and program them into hip. | |
1610 | * They are no longer completely contiguous, we do multiple allocation | |
1611 | * calls. Otherwise we get the OOM code involved, by asking for too | |
1612 | * much per call, with disastrous results on some kernels. | |
1613 | */ | |
1614 | int qib_setup_eagerbufs(struct qib_ctxtdata *rcd) | |
1615 | { | |
1616 | struct qib_devdata *dd = rcd->dd; | |
1617 | unsigned e, egrcnt, egrperchunk, chunk, egrsize, egroff; | |
1618 | size_t size; | |
1619 | gfp_t gfp_flags; | |
e0f30bac | 1620 | int old_node_id; |
f931551b RC |
1621 | |
1622 | /* | |
1623 | * GFP_USER, but without GFP_FS, so buffer cache can be | |
1624 | * coalesced (we hope); otherwise, even at order 4, | |
1625 | * heavy filesystem activity makes these fail, and we can | |
1626 | * use compound pages. | |
1627 | */ | |
1628 | gfp_flags = __GFP_WAIT | __GFP_IO | __GFP_COMP; | |
1629 | ||
1630 | egrcnt = rcd->rcvegrcnt; | |
1631 | egroff = rcd->rcvegr_tid_base; | |
1632 | egrsize = dd->rcvegrbufsize; | |
1633 | ||
1634 | chunk = rcd->rcvegrbuf_chunks; | |
1635 | egrperchunk = rcd->rcvegrbufs_perchunk; | |
1636 | size = rcd->rcvegrbuf_size; | |
1637 | if (!rcd->rcvegrbuf) { | |
1638 | rcd->rcvegrbuf = | |
e0f30bac RV |
1639 | kzalloc_node(chunk * sizeof(rcd->rcvegrbuf[0]), |
1640 | GFP_KERNEL, rcd->node_id); | |
f931551b RC |
1641 | if (!rcd->rcvegrbuf) |
1642 | goto bail; | |
1643 | } | |
1644 | if (!rcd->rcvegrbuf_phys) { | |
1645 | rcd->rcvegrbuf_phys = | |
e0f30bac RV |
1646 | kmalloc_node(chunk * sizeof(rcd->rcvegrbuf_phys[0]), |
1647 | GFP_KERNEL, rcd->node_id); | |
f931551b RC |
1648 | if (!rcd->rcvegrbuf_phys) |
1649 | goto bail_rcvegrbuf; | |
1650 | } | |
1651 | for (e = 0; e < rcd->rcvegrbuf_chunks; e++) { | |
1652 | if (rcd->rcvegrbuf[e]) | |
1653 | continue; | |
e0f30bac RV |
1654 | |
1655 | old_node_id = dev_to_node(&dd->pcidev->dev); | |
1656 | set_dev_node(&dd->pcidev->dev, rcd->node_id); | |
f931551b RC |
1657 | rcd->rcvegrbuf[e] = |
1658 | dma_alloc_coherent(&dd->pcidev->dev, size, | |
1659 | &rcd->rcvegrbuf_phys[e], | |
1660 | gfp_flags); | |
e0f30bac | 1661 | set_dev_node(&dd->pcidev->dev, old_node_id); |
f931551b RC |
1662 | if (!rcd->rcvegrbuf[e]) |
1663 | goto bail_rcvegrbuf_phys; | |
1664 | } | |
1665 | ||
1666 | rcd->rcvegr_phys = rcd->rcvegrbuf_phys[0]; | |
1667 | ||
1668 | for (e = chunk = 0; chunk < rcd->rcvegrbuf_chunks; chunk++) { | |
1669 | dma_addr_t pa = rcd->rcvegrbuf_phys[chunk]; | |
1670 | unsigned i; | |
1671 | ||
5df4223a RC |
1672 | /* clear for security and sanity on each use */ |
1673 | memset(rcd->rcvegrbuf[chunk], 0, size); | |
1674 | ||
f931551b RC |
1675 | for (i = 0; e < egrcnt && i < egrperchunk; e++, i++) { |
1676 | dd->f_put_tid(dd, e + egroff + | |
1677 | (u64 __iomem *) | |
1678 | ((char __iomem *) | |
1679 | dd->kregbase + | |
1680 | dd->rcvegrbase), | |
1681 | RCVHQ_RCV_TYPE_EAGER, pa); | |
1682 | pa += egrsize; | |
1683 | } | |
1684 | cond_resched(); /* don't hog the cpu */ | |
1685 | } | |
1686 | ||
1687 | return 0; | |
1688 | ||
1689 | bail_rcvegrbuf_phys: | |
1690 | for (e = 0; e < rcd->rcvegrbuf_chunks && rcd->rcvegrbuf[e]; e++) | |
1691 | dma_free_coherent(&dd->pcidev->dev, size, | |
1692 | rcd->rcvegrbuf[e], rcd->rcvegrbuf_phys[e]); | |
1693 | kfree(rcd->rcvegrbuf_phys); | |
1694 | rcd->rcvegrbuf_phys = NULL; | |
1695 | bail_rcvegrbuf: | |
1696 | kfree(rcd->rcvegrbuf); | |
1697 | rcd->rcvegrbuf = NULL; | |
1698 | bail: | |
1699 | return -ENOMEM; | |
1700 | } | |
1701 | ||
fce24a9d DO |
1702 | /* |
1703 | * Note: Changes to this routine should be mirrored | |
1704 | * for the diagnostics routine qib_remap_ioaddr32(). | |
1705 | * There is also related code for VL15 buffers in qib_init_7322_variables(). | |
1706 | * The teardown code that unmaps is in qib_pcie_ddcleanup() | |
1707 | */ | |
f931551b RC |
1708 | int init_chip_wc_pat(struct qib_devdata *dd, u32 vl15buflen) |
1709 | { | |
1710 | u64 __iomem *qib_kregbase = NULL; | |
1711 | void __iomem *qib_piobase = NULL; | |
1712 | u64 __iomem *qib_userbase = NULL; | |
1713 | u64 qib_kreglen; | |
1714 | u64 qib_pio2koffset = dd->piobufbase & 0xffffffff; | |
1715 | u64 qib_pio4koffset = dd->piobufbase >> 32; | |
1716 | u64 qib_pio2klen = dd->piobcnt2k * dd->palign; | |
1717 | u64 qib_pio4klen = dd->piobcnt4k * dd->align4k; | |
1718 | u64 qib_physaddr = dd->physaddr; | |
1719 | u64 qib_piolen; | |
1720 | u64 qib_userlen = 0; | |
1721 | ||
1722 | /* | |
1723 | * Free the old mapping because the kernel will try to reuse the | |
1724 | * old mapping and not create a new mapping with the | |
1725 | * write combining attribute. | |
1726 | */ | |
1727 | iounmap(dd->kregbase); | |
1728 | dd->kregbase = NULL; | |
1729 | ||
1730 | /* | |
1731 | * Assumes chip address space looks like: | |
1732 | * - kregs + sregs + cregs + uregs (in any order) | |
1733 | * - piobufs (2K and 4K bufs in either order) | |
1734 | * or: | |
1735 | * - kregs + sregs + cregs (in any order) | |
1736 | * - piobufs (2K and 4K bufs in either order) | |
1737 | * - uregs | |
1738 | */ | |
1739 | if (dd->piobcnt4k == 0) { | |
1740 | qib_kreglen = qib_pio2koffset; | |
1741 | qib_piolen = qib_pio2klen; | |
1742 | } else if (qib_pio2koffset < qib_pio4koffset) { | |
1743 | qib_kreglen = qib_pio2koffset; | |
1744 | qib_piolen = qib_pio4koffset + qib_pio4klen - qib_kreglen; | |
1745 | } else { | |
1746 | qib_kreglen = qib_pio4koffset; | |
1747 | qib_piolen = qib_pio2koffset + qib_pio2klen - qib_kreglen; | |
1748 | } | |
1749 | qib_piolen += vl15buflen; | |
1750 | /* Map just the configured ports (not all hw ports) */ | |
1751 | if (dd->uregbase > qib_kreglen) | |
1752 | qib_userlen = dd->ureg_align * dd->cfgctxts; | |
1753 | ||
1754 | /* Sanity checks passed, now create the new mappings */ | |
1755 | qib_kregbase = ioremap_nocache(qib_physaddr, qib_kreglen); | |
1756 | if (!qib_kregbase) | |
1757 | goto bail; | |
1758 | ||
1759 | qib_piobase = ioremap_wc(qib_physaddr + qib_kreglen, qib_piolen); | |
1760 | if (!qib_piobase) | |
1761 | goto bail_kregbase; | |
1762 | ||
1763 | if (qib_userlen) { | |
1764 | qib_userbase = ioremap_nocache(qib_physaddr + dd->uregbase, | |
1765 | qib_userlen); | |
1766 | if (!qib_userbase) | |
1767 | goto bail_piobase; | |
1768 | } | |
1769 | ||
1770 | dd->kregbase = qib_kregbase; | |
1771 | dd->kregend = (u64 __iomem *) | |
1772 | ((char __iomem *) qib_kregbase + qib_kreglen); | |
1773 | dd->piobase = qib_piobase; | |
1774 | dd->pio2kbase = (void __iomem *) | |
1775 | (((char __iomem *) dd->piobase) + | |
1776 | qib_pio2koffset - qib_kreglen); | |
1777 | if (dd->piobcnt4k) | |
1778 | dd->pio4kbase = (void __iomem *) | |
1779 | (((char __iomem *) dd->piobase) + | |
1780 | qib_pio4koffset - qib_kreglen); | |
1781 | if (qib_userlen) | |
1782 | /* ureg will now be accessed relative to dd->userbase */ | |
1783 | dd->userbase = qib_userbase; | |
1784 | return 0; | |
1785 | ||
1786 | bail_piobase: | |
1787 | iounmap(qib_piobase); | |
1788 | bail_kregbase: | |
1789 | iounmap(qib_kregbase); | |
1790 | bail: | |
1791 | return -ENOMEM; | |
1792 | } |