[deliverable/linux.git] / drivers / input / keyboard / tegra-kbc.c

/*
 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
 * keyboard controller
 *
 * Copyright (c) 2009-2011, NVIDIA Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <linux/module.h>
#include <linux/input.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <mach/clk.h>
#include <mach/kbc.h>

#define KBC_MAX_DEBOUNCE_CNT	0x3ffu

/* KBC row scan time and delay for beginning the row scan. */
#define KBC_ROW_SCAN_TIME	16
#define KBC_ROW_SCAN_DLY	5

/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
#define KBC_CYCLE_USEC	32

/* KBC Registers */

/* KBC Control Register */
#define KBC_CONTROL_0	0x0
#define KBC_FIFO_TH_CNT_SHIFT(cnt)	(cnt << 14)
#define KBC_DEBOUNCE_CNT_SHIFT(cnt)	(cnt << 4)
#define KBC_CONTROL_FIFO_CNT_INT_EN	(1 << 3)
#define KBC_CONTROL_KBC_EN		(1 << 0)

/* KBC Interrupt Register */
#define KBC_INT_0	0x4
#define KBC_INT_FIFO_CNT_INT_STATUS	(1 << 2)

#define KBC_ROW_CFG0_0	0x8
#define KBC_COL_CFG0_0	0x18
#define KBC_INIT_DLY_0	0x28
#define KBC_RPT_DLY_0	0x2c
#define KBC_KP_ENT0_0	0x30
#define KBC_KP_ENT1_0	0x34
#define KBC_ROW0_MASK_0	0x38

#define KBC_ROW_SHIFT	3

struct tegra_kbc {
	void __iomem *mmio;
	struct input_dev *idev;
	unsigned int irq;
	unsigned int wake_enable_rows;
	unsigned int wake_enable_cols;
	spinlock_t lock;
	unsigned int repoll_dly;
	unsigned long cp_dly_jiffies;
	const struct tegra_kbc_platform_data *pdata;
	unsigned short keycode[KBC_MAX_KEY];
	unsigned short current_keys[KBC_MAX_KPENT];
	unsigned int num_pressed_keys;
	struct timer_list timer;
	struct clk *clk;
};

static const u32 tegra_kbc_default_keymap[] = {
	KEY(0, 2, KEY_W),
	KEY(0, 3, KEY_S),
	KEY(0, 4, KEY_A),
	KEY(0, 5, KEY_Z),
	KEY(0, 7, KEY_FN),

	KEY(1, 7, KEY_MENU),

	KEY(2, 6, KEY_RIGHTALT),
	KEY(2, 7, KEY_LEFTALT),

	KEY(3, 0, KEY_5),
	KEY(3, 1, KEY_4),
	KEY(3, 2, KEY_R),
	KEY(3, 3, KEY_E),
	KEY(3, 4, KEY_F),
	KEY(3, 5, KEY_D),
	KEY(3, 6, KEY_X),

	KEY(4, 0, KEY_7),
	KEY(4, 1, KEY_6),
	KEY(4, 2, KEY_T),
	KEY(4, 3, KEY_H),
	KEY(4, 4, KEY_G),
	KEY(4, 5, KEY_V),
	KEY(4, 6, KEY_C),
	KEY(4, 7, KEY_SPACE),

	KEY(5, 0, KEY_9),
	KEY(5, 1, KEY_8),
	KEY(5, 2, KEY_U),
	KEY(5, 3, KEY_Y),
	KEY(5, 4, KEY_J),
	KEY(5, 5, KEY_N),
	KEY(5, 6, KEY_B),
	KEY(5, 7, KEY_BACKSLASH),

	KEY(6, 0, KEY_MINUS),
	KEY(6, 1, KEY_0),
	KEY(6, 2, KEY_O),
	KEY(6, 3, KEY_I),
	KEY(6, 4, KEY_L),
	KEY(6, 5, KEY_K),
	KEY(6, 6, KEY_COMMA),
	KEY(6, 7, KEY_M),

	KEY(7, 1, KEY_EQUAL),
	KEY(7, 2, KEY_RIGHTBRACE),
	KEY(7, 3, KEY_ENTER),
	KEY(7, 7, KEY_MENU),

	KEY(8, 4, KEY_RIGHTSHIFT),
	KEY(8, 5, KEY_LEFTSHIFT),

	KEY(9, 5, KEY_RIGHTCTRL),
	KEY(9, 7, KEY_LEFTCTRL),

	KEY(11, 0, KEY_LEFTBRACE),
	KEY(11, 1, KEY_P),
	KEY(11, 2, KEY_APOSTROPHE),
	KEY(11, 3, KEY_SEMICOLON),
	KEY(11, 4, KEY_SLASH),
	KEY(11, 5, KEY_DOT),

	KEY(12, 0, KEY_F10),
	KEY(12, 1, KEY_F9),
	KEY(12, 2, KEY_BACKSPACE),
	KEY(12, 3, KEY_3),
	KEY(12, 4, KEY_2),
	KEY(12, 5, KEY_UP),
	KEY(12, 6, KEY_PRINT),
	KEY(12, 7, KEY_PAUSE),

	KEY(13, 0, KEY_INSERT),
	KEY(13, 1, KEY_DELETE),
	KEY(13, 3, KEY_PAGEUP),
	KEY(13, 4, KEY_PAGEDOWN),
	KEY(13, 5, KEY_RIGHT),
	KEY(13, 6, KEY_DOWN),
	KEY(13, 7, KEY_LEFT),

	KEY(14, 0, KEY_F11),
	KEY(14, 1, KEY_F12),
	KEY(14, 2, KEY_F8),
	KEY(14, 3, KEY_Q),
	KEY(14, 4, KEY_F4),
	KEY(14, 5, KEY_F3),
	KEY(14, 6, KEY_1),
	KEY(14, 7, KEY_F7),

	KEY(15, 0, KEY_ESC),
	KEY(15, 1, KEY_GRAVE),
	KEY(15, 2, KEY_F5),
	KEY(15, 3, KEY_TAB),
	KEY(15, 4, KEY_F1),
	KEY(15, 5, KEY_F2),
	KEY(15, 6, KEY_CAPSLOCK),
	KEY(15, 7, KEY_F6),
};

static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
	.keymap		= tegra_kbc_default_keymap,
	.keymap_size	= ARRAY_SIZE(tegra_kbc_default_keymap),
};

static void tegra_kbc_report_released_keys(struct input_dev *input,
					   unsigned short old_keycodes[],
					   unsigned int old_num_keys,
					   unsigned short new_keycodes[],
					   unsigned int new_num_keys)
{
	unsigned int i, j;

	for (i = 0; i < old_num_keys; i++) {
		for (j = 0; j < new_num_keys; j++)
			if (old_keycodes[i] == new_keycodes[j])
				break;

		if (j == new_num_keys)
			input_report_key(input, old_keycodes[i], 0);
	}
}

static void tegra_kbc_report_pressed_keys(struct input_dev *input,
					  unsigned char scancodes[],
					  unsigned short keycodes[],
					  unsigned int num_pressed_keys)
{
	unsigned int i;

	for (i = 0; i < num_pressed_keys; i++) {
		input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
		input_report_key(input, keycodes[i], 1);
	}
}

static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
{
	unsigned char scancodes[KBC_MAX_KPENT];
	unsigned short keycodes[KBC_MAX_KPENT];
	u32 val = 0;
	unsigned int i;
	unsigned int num_down = 0;
	unsigned long flags;

	spin_lock_irqsave(&kbc->lock, flags);
	for (i = 0; i < KBC_MAX_KPENT; i++) {
		if ((i % 4) == 0)
			val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);

		if (val & 0x80) {
			unsigned int col = val & 0x07;
			unsigned int row = (val >> 3) & 0x0f;
			unsigned char scancode =
				MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);

			scancodes[num_down] = scancode;
			keycodes[num_down++] = kbc->keycode[scancode];
		}

		val >>= 8;
	}
	spin_unlock_irqrestore(&kbc->lock, flags);

	tegra_kbc_report_released_keys(kbc->idev,
				       kbc->current_keys, kbc->num_pressed_keys,
				       keycodes, num_down);
	tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
	input_sync(kbc->idev);

	memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
	kbc->num_pressed_keys = num_down;
}

static void tegra_kbc_keypress_timer(unsigned long data)
{
	struct tegra_kbc *kbc = (struct tegra_kbc *)data;
	unsigned long flags;
	u32 val;
	unsigned int i;

	val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
	if (val) {
		unsigned long dly;

		tegra_kbc_report_keys(kbc);

		/*
		 * If more than one keys are pressed we need not wait
		 * for the repoll delay.
		 */
		dly = (val == 1) ? kbc->repoll_dly : 1;
		mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
	} else {
		/* Release any pressed keys and exit the polling loop */
		for (i = 0; i < kbc->num_pressed_keys; i++)
			input_report_key(kbc->idev, kbc->current_keys[i], 0);
		input_sync(kbc->idev);

		kbc->num_pressed_keys = 0;

		/* All keys are released so enable the keypress interrupt */
		spin_lock_irqsave(&kbc->lock, flags);
		val = readl(kbc->mmio + KBC_CONTROL_0);
		val |= KBC_CONTROL_FIFO_CNT_INT_EN;
		writel(val, kbc->mmio + KBC_CONTROL_0);
		spin_unlock_irqrestore(&kbc->lock, flags);
	}
}

static irqreturn_t tegra_kbc_isr(int irq, void *args)
{
	struct tegra_kbc *kbc = args;
	u32 val, ctl;

	/*
	 * Until all keys are released, defer further processing to
	 * the polling loop in tegra_kbc_keypress_timer
	 */
	ctl = readl(kbc->mmio + KBC_CONTROL_0);
	ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
	writel(ctl, kbc->mmio + KBC_CONTROL_0);

	/*
	 * Quickly bail out & reenable interrupts if the fifo threshold
	 * count interrupt wasn't the interrupt source
	 */
	val = readl(kbc->mmio + KBC_INT_0);
	writel(val, kbc->mmio + KBC_INT_0);

	if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
		/*
		 * Schedule timer to run when hardware is in continuous
		 * polling mode.
		 */
		mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
	} else {
		ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
		writel(ctl, kbc->mmio + KBC_CONTROL_0);
	}

	return IRQ_HANDLED;
}

static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
{
	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
	int i;
	unsigned int rst_val;

	BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
	rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;

	for (i = 0; i < KBC_MAX_ROW; i++)
		writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);

	if (filter) {
		for (i = 0; i < pdata->wake_cnt; i++) {
			u32 val, addr;
			addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
			val = readl(kbc->mmio + addr);
			val &= ~(1 << pdata->wake_cfg[i].col);
			writel(val, kbc->mmio + addr);
		}
	}
}

static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
{
	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
	int i;

	for (i = 0; i < KBC_MAX_GPIO; i++) {
		u32 r_shft = 5 * (i % 6);
		u32 c_shft = 4 * (i % 8);
		u32 r_mask = 0x1f << r_shift;
		u32 c_mask = 0x0f << c_shift;
		u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
		u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
		u32 row_cfg = readl(kbc->mmio + r_offs);
		u32 col_cfg = readl(kbc->mmio + c_offs);

		row_cfg &= ~r_mask;
		col_cfg &= ~c_mask;

		if (pdata->pin_cfg[i].is_row)
			row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
		else
			col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;

		writel(row_cfg, kbc->mmio + r_offs);
		writel(col_cfg, kbc->mmio + c_offs);
	}
}

static int tegra_kbc_start(struct tegra_kbc *kbc)
{
	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
	unsigned long flags;
	unsigned int debounce_cnt;
	u32 val = 0;

	clk_enable(kbc->clk);

	/* Reset the KBC controller to clear all previous status.*/
	tegra_periph_reset_assert(kbc->clk);
	udelay(100);
	tegra_periph_reset_deassert(kbc->clk);
	udelay(100);

	tegra_kbc_config_pins(kbc);
	tegra_kbc_setup_wakekeys(kbc, false);

	writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);

	/* Keyboard debounce count is maximum of 12 bits. */
	debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
	val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
	val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
	val |= KBC_CONTROL_FIFO_CNT_INT_EN;  /* interrupt on FIFO threshold */
	val |= KBC_CONTROL_KBC_EN;     /* enable */
	writel(val, kbc->mmio + KBC_CONTROL_0);

	/*
	 * Compute the delay(ns) from interrupt mode to continuous polling
	 * mode so the timer routine is scheduled appropriately.
	 */
	val = readl(kbc->mmio + KBC_INIT_DLY_0);
	kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);

	kbc->num_pressed_keys = 0;

	/*
	 * Atomically clear out any remaining entries in the key FIFO
	 * and enable keyboard interrupts.
	 */
	spin_lock_irqsave(&kbc->lock, flags);
	while (1) {
		val = readl(kbc->mmio + KBC_INT_0);
		val >>= 4;
		if (!val)
			break;

		val = readl(kbc->mmio + KBC_KP_ENT0_0);
		val = readl(kbc->mmio + KBC_KP_ENT1_0);
	}
	writel(0x7, kbc->mmio + KBC_INT_0);
	spin_unlock_irqrestore(&kbc->lock, flags);

	enable_irq(kbc->irq);

	return 0;
}

static void tegra_kbc_stop(struct tegra_kbc *kbc)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&kbc->lock, flags);
	val = readl(kbc->mmio + KBC_CONTROL_0);
	val &= ~1;
	writel(val, kbc->mmio + KBC_CONTROL_0);
	spin_unlock_irqrestore(&kbc->lock, flags);

	disable_irq(kbc->irq);
	del_timer_sync(&kbc->timer);

	clk_disable(kbc->clk);
}

static int tegra_kbc_open(struct input_dev *dev)
{
	struct tegra_kbc *kbc = input_get_drvdata(dev);

	return tegra_kbc_start(kbc);
}

static void tegra_kbc_close(struct input_dev *dev)
{
	struct tegra_kbc *kbc = input_get_drvdata(dev);

	return tegra_kbc_stop(kbc);
}

static bool __devinit
tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
			struct device *dev, unsigned int *num_rows)
{
	int i;

	*num_rows = 0;

	for (i = 0; i < KBC_MAX_GPIO; i++) {
		const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];

		if (pin_cfg->is_row) {
			if (pin_cfg->num >= KBC_MAX_ROW) {
				dev_err(dev,
					"pin_cfg[%d]: invalid row number %d\n",
					i, pin_cfg->num);
				return false;
			}
			(*num_rows)++;
		} else {
			if (pin_cfg->num >= KBC_MAX_COL) {
				dev_err(dev,
					"pin_cfg[%d]: invalid column number %d\n",
					i, pin_cfg->num);
				return false;
			}
		}
	}

	return true;
}

static int __devinit tegra_kbc_probe(struct platform_device *pdev)
{
	const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
	const struct matrix_keymap_data *keymap_data;
	struct tegra_kbc *kbc;
	struct input_dev *input_dev;
	struct resource *res;
	int irq;
	int err;
	int i;
	int num_rows = 0;
	unsigned int debounce_cnt;
	unsigned int scan_time_rows;

	if (!pdata)
		return -EINVAL;

	if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
		return -EINVAL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "failed to get I/O memory\n");
		return -ENXIO;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
		return -ENXIO;
	}

	kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
	input_dev = input_allocate_device();
	if (!kbc || !input_dev) {
		err = -ENOMEM;
		goto err_free_mem;
	}

	kbc->pdata = pdata;
	kbc->idev = input_dev;
	kbc->irq = irq;
	spin_lock_init(&kbc->lock);
	setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);

	res = request_mem_region(res->start, resource_size(res), pdev->name);
	if (!res) {
		dev_err(&pdev->dev, "failed to request I/O memory\n");
		err = -EBUSY;
		goto err_free_mem;
	}

	kbc->mmio = ioremap(res->start, resource_size(res));
	if (!kbc->mmio) {
		dev_err(&pdev->dev, "failed to remap I/O memory\n");
		err = -ENXIO;
		goto err_free_mem_region;
	}

	kbc->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(kbc->clk)) {
		dev_err(&pdev->dev, "failed to get keyboard clock\n");
		err = PTR_ERR(kbc->clk);
		goto err_iounmap;
	}

	kbc->wake_enable_rows = 0;
	kbc->wake_enable_cols = 0;
	for (i = 0; i < pdata->wake_cnt; i++) {
		kbc->wake_enable_rows |= (1 << pdata->wake_cfg[i].row);
		kbc->wake_enable_cols |= (1 << pdata->wake_cfg[i].col);
	}

	/*
	 * The time delay between two consecutive reads of the FIFO is
	 * the sum of the repeat time and the time taken for scanning
	 * the rows. There is an additional delay before the row scanning
	 * starts. The repoll delay is computed in milliseconds.
	 */
	debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
	scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
	kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
	kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;

	input_dev->name = pdev->name;
	input_dev->id.bustype = BUS_HOST;
	input_dev->dev.parent = &pdev->dev;
	input_dev->open = tegra_kbc_open;
	input_dev->close = tegra_kbc_close;

	input_set_drvdata(input_dev, kbc);

	input_dev->evbit[0] = BIT_MASK(EV_KEY);
	input_set_capability(input_dev, EV_MSC, MSC_SCAN);

	input_dev->keycode = kbc->keycode;
	input_dev->keycodesize = sizeof(kbc->keycode[0]);
	input_dev->keycodemax = ARRAY_SIZE(kbc->keycode);

	keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
	matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
				   input_dev->keycode, input_dev->keybit);

	err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
			  pdev->name, kbc);
	if (err) {
		dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
		goto err_put_clk;
	}

	disable_irq(kbc->irq);

	err = input_register_device(kbc->idev);
	if (err) {
		dev_err(&pdev->dev, "failed to register input device\n");
		goto err_free_irq;
	}

	platform_set_drvdata(pdev, kbc);
	device_init_wakeup(&pdev->dev, pdata->wakeup);

	return 0;

err_free_irq:
	free_irq(kbc->irq, pdev);
err_put_clk:
	clk_put(kbc->clk);
err_iounmap:
	iounmap(kbc->mmio);
err_free_mem_region:
	release_mem_region(res->start, resource_size(res));
err_free_mem:
	input_free_device(kbc->idev);
	kfree(kbc);

	return err;
}

static int __devexit tegra_kbc_remove(struct platform_device *pdev)
{
	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
	struct resource *res;

	free_irq(kbc->irq, pdev);
	clk_put(kbc->clk);

	input_unregister_device(kbc->idev);
	iounmap(kbc->mmio);
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, resource_size(res));

	kfree(kbc);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tegra_kbc_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct tegra_kbc *kbc = platform_get_drvdata(pdev);

	if (device_may_wakeup(&pdev->dev)) {
		tegra_kbc_setup_wakekeys(kbc, true);
		enable_irq_wake(kbc->irq);
		/* Forcefully clear the interrupt status */
		writel(0x7, kbc->mmio + KBC_INT_0);
		msleep(30);
	} else {
		mutex_lock(&kbc->idev->mutex);
		if (kbc->idev->users)
			tegra_kbc_stop(kbc);
		mutex_unlock(&kbc->idev->mutex);
	}

	return 0;
}

static int tegra_kbc_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
	int err = 0;

	if (device_may_wakeup(&pdev->dev)) {
		disable_irq_wake(kbc->irq);
		tegra_kbc_setup_wakekeys(kbc, false);
	} else {
		mutex_lock(&kbc->idev->mutex);
		if (kbc->idev->users)
			err = tegra_kbc_start(kbc);
		mutex_unlock(&kbc->idev->mutex);
	}

	return err;
}
#endif

static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);

static struct platform_driver tegra_kbc_driver = {
	.probe		= tegra_kbc_probe,
	.remove		= __devexit_p(tegra_kbc_remove),
	.driver	= {
		.name	= "tegra-kbc",
		.owner  = THIS_MODULE,
		.pm	= &tegra_kbc_pm_ops,
	},
};

static void __exit tegra_kbc_exit(void)
{
	platform_driver_unregister(&tegra_kbc_driver);
}
module_exit(tegra_kbc_exit);

static int __init tegra_kbc_init(void)
{
	return platform_driver_register(&tegra_kbc_driver);
}
module_init(tegra_kbc_init);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
MODULE_ALIAS("platform:tegra-kbc");
Commit	Line	Data
11f5b30d RI	1	/*
	2	* Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
	3	* keyboard controller
	4	*
	5	* Copyright (c) 2009-2011, NVIDIA Corporation.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*/
	21
	22	#include <linux/module.h>
	23	#include <linux/input.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/delay.h>
	26	#include <linux/io.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/clk.h>
	29	#include <linux/slab.h>
	30	#include <mach/clk.h>
	31	#include <mach/kbc.h>
	32
	33	#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
	34
	35	/* KBC row scan time and delay for beginning the row scan. */
	36	#define KBC_ROW_SCAN_TIME 16
	37	#define KBC_ROW_SCAN_DLY 5
	38
	39	/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
	40	#define KBC_CYCLE_USEC 32
	41
	42	/* KBC Registers */
	43
	44	/* KBC Control Register */
	45	#define KBC_CONTROL_0 0x0
	46	#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
	47	#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
	48	#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
	49	#define KBC_CONTROL_KBC_EN (1 << 0)
	50
	51	/* KBC Interrupt Register */
	52	#define KBC_INT_0 0x4
	53	#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
	54
	55	#define KBC_ROW_CFG0_0 0x8
	56	#define KBC_COL_CFG0_0 0x18
	57	#define KBC_INIT_DLY_0 0x28
	58	#define KBC_RPT_DLY_0 0x2c
	59	#define KBC_KP_ENT0_0 0x30
	60	#define KBC_KP_ENT1_0 0x34
	61	#define KBC_ROW0_MASK_0 0x38
	62
	63	#define KBC_ROW_SHIFT 3
	64
65	struct tegra_kbc {
66	void __iomem *mmio;
67	struct input_dev *idev;
68	unsigned int irq;
69	unsigned int wake_enable_rows;
70	unsigned int wake_enable_cols;
71	spinlock_t lock;
72	unsigned int repoll_dly;
73	unsigned long cp_dly_jiffies;
74	const struct tegra_kbc_platform_data *pdata;
75	unsigned short keycode[KBC_MAX_KEY];
76	unsigned short current_keys[KBC_MAX_KPENT];
77	unsigned int num_pressed_keys;
78	struct timer_list timer;
79	struct clk *clk;
80	};
81
82	static const u32 tegra_kbc_default_keymap[] = {
83	KEY(0, 2, KEY_W),
84	KEY(0, 3, KEY_S),
85	KEY(0, 4, KEY_A),
86	KEY(0, 5, KEY_Z),
87	KEY(0, 7, KEY_FN),
88
89	KEY(1, 7, KEY_MENU),
90
91	KEY(2, 6, KEY_RIGHTALT),
92	KEY(2, 7, KEY_LEFTALT),
93
94	KEY(3, 0, KEY_5),
95	KEY(3, 1, KEY_4),
96	KEY(3, 2, KEY_R),
97	KEY(3, 3, KEY_E),
98	KEY(3, 4, KEY_F),
99	KEY(3, 5, KEY_D),
100	KEY(3, 6, KEY_X),
101
102	KEY(4, 0, KEY_7),
103	KEY(4, 1, KEY_6),
104	KEY(4, 2, KEY_T),
105	KEY(4, 3, KEY_H),
106	KEY(4, 4, KEY_G),
107	KEY(4, 5, KEY_V),
108	KEY(4, 6, KEY_C),
109	KEY(4, 7, KEY_SPACE),
110
111	KEY(5, 0, KEY_9),
112	KEY(5, 1, KEY_8),
113	KEY(5, 2, KEY_U),
114	KEY(5, 3, KEY_Y),
115	KEY(5, 4, KEY_J),
116	KEY(5, 5, KEY_N),
117	KEY(5, 6, KEY_B),
118	KEY(5, 7, KEY_BACKSLASH),
119
120	KEY(6, 0, KEY_MINUS),
121	KEY(6, 1, KEY_0),
122	KEY(6, 2, KEY_O),
123	KEY(6, 3, KEY_I),
124	KEY(6, 4, KEY_L),
125	KEY(6, 5, KEY_K),
126	KEY(6, 6, KEY_COMMA),
127	KEY(6, 7, KEY_M),
128
129	KEY(7, 1, KEY_EQUAL),
130	KEY(7, 2, KEY_RIGHTBRACE),
131	KEY(7, 3, KEY_ENTER),
132	KEY(7, 7, KEY_MENU),
133
134	KEY(8, 4, KEY_RIGHTSHIFT),
135	KEY(8, 5, KEY_LEFTSHIFT),
136
137	KEY(9, 5, KEY_RIGHTCTRL),
138	KEY(9, 7, KEY_LEFTCTRL),
139
140	KEY(11, 0, KEY_LEFTBRACE),
141	KEY(11, 1, KEY_P),
142	KEY(11, 2, KEY_APOSTROPHE),
143	KEY(11, 3, KEY_SEMICOLON),
144	KEY(11, 4, KEY_SLASH),
145	KEY(11, 5, KEY_DOT),
146
147	KEY(12, 0, KEY_F10),
148	KEY(12, 1, KEY_F9),
149	KEY(12, 2, KEY_BACKSPACE),
150	KEY(12, 3, KEY_3),
151	KEY(12, 4, KEY_2),
152	KEY(12, 5, KEY_UP),
153	KEY(12, 6, KEY_PRINT),
154	KEY(12, 7, KEY_PAUSE),
155
156	KEY(13, 0, KEY_INSERT),
157	KEY(13, 1, KEY_DELETE),
158	KEY(13, 3, KEY_PAGEUP),
159	KEY(13, 4, KEY_PAGEDOWN),
160	KEY(13, 5, KEY_RIGHT),
161	KEY(13, 6, KEY_DOWN),
162	KEY(13, 7, KEY_LEFT),
163
164	KEY(14, 0, KEY_F11),
165	KEY(14, 1, KEY_F12),
166	KEY(14, 2, KEY_F8),
167	KEY(14, 3, KEY_Q),
168	KEY(14, 4, KEY_F4),
169	KEY(14, 5, KEY_F3),
170	KEY(14, 6, KEY_1),
171	KEY(14, 7, KEY_F7),
172
173	KEY(15, 0, KEY_ESC),
174	KEY(15, 1, KEY_GRAVE),
175	KEY(15, 2, KEY_F5),
176	KEY(15, 3, KEY_TAB),
177	KEY(15, 4, KEY_F1),
178	KEY(15, 5, KEY_F2),
179	KEY(15, 6, KEY_CAPSLOCK),
180	KEY(15, 7, KEY_F6),
181	};
182
183	static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
184	.keymap = tegra_kbc_default_keymap,
185	.keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
186	};
187
188	static void tegra_kbc_report_released_keys(struct input_dev *input,
189	unsigned short old_keycodes[],
190	unsigned int old_num_keys,
191	unsigned short new_keycodes[],
192	unsigned int new_num_keys)
193	{
194	unsigned int i, j;
195
196	for (i = 0; i < old_num_keys; i++) {
197	for (j = 0; j < new_num_keys; j++)
198	if (old_keycodes[i] == new_keycodes[j])
199	break;
200
201	if (j == new_num_keys)
202	input_report_key(input, old_keycodes[i], 0);
203	}
204	}
205
206	static void tegra_kbc_report_pressed_keys(struct input_dev *input,
207	unsigned char scancodes[],
208	unsigned short keycodes[],
209	unsigned int num_pressed_keys)
210	{
211	unsigned int i;
212
213	for (i = 0; i < num_pressed_keys; i++) {
214	input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
215	input_report_key(input, keycodes[i], 1);
216	}
217	}
218
219	static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
220	{
221	unsigned char scancodes[KBC_MAX_KPENT];
222	unsigned short keycodes[KBC_MAX_KPENT];
223	u32 val = 0;
224	unsigned int i;
225	unsigned int num_down = 0;
226	unsigned long flags;
227
228	spin_lock_irqsave(&kbc->lock, flags);
229	for (i = 0; i < KBC_MAX_KPENT; i++) {
230	if ((i % 4) == 0)
231	val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
232
233	if (val & 0x80) {
234	unsigned int col = val & 0x07;
235	unsigned int row = (val >> 3) & 0x0f;
236	unsigned char scancode =
237	MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
238
239	scancodes[num_down] = scancode;
240	keycodes[num_down++] = kbc->keycode[scancode];
241	}
242
243	val >>= 8;
244	}
245	spin_unlock_irqrestore(&kbc->lock, flags);
246
247	tegra_kbc_report_released_keys(kbc->idev,
248	kbc->current_keys, kbc->num_pressed_keys,
249	keycodes, num_down);
250	tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
251	input_sync(kbc->idev);
252
253	memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
254	kbc->num_pressed_keys = num_down;
255	}
256
257	static void tegra_kbc_keypress_timer(unsigned long data)
258	{
259	struct tegra_kbc kbc = (struct tegra_kbc )data;
260	unsigned long flags;
261	u32 val;
262	unsigned int i;
263
264	val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
265	if (val) {
266	unsigned long dly;
267
268	tegra_kbc_report_keys(kbc);
269
270	/*
271	* If more than one keys are pressed we need not wait
272	* for the repoll delay.
273	*/
274	dly = (val == 1) ? kbc->repoll_dly : 1;
275	mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
276	} else {
277	/* Release any pressed keys and exit the polling loop */
278	for (i = 0; i < kbc->num_pressed_keys; i++)
279	input_report_key(kbc->idev, kbc->current_keys[i], 0);
280	input_sync(kbc->idev);
281
282	kbc->num_pressed_keys = 0;
283
284	/* All keys are released so enable the keypress interrupt */
285	spin_lock_irqsave(&kbc->lock, flags);
286	val = readl(kbc->mmio + KBC_CONTROL_0);
287	val \|= KBC_CONTROL_FIFO_CNT_INT_EN;
288	writel(val, kbc->mmio + KBC_CONTROL_0);
289	spin_unlock_irqrestore(&kbc->lock, flags);
290	}
291	}
292
293	static irqreturn_t tegra_kbc_isr(int irq, void *args)
294	{
295	struct tegra_kbc *kbc = args;
296	u32 val, ctl;
297
298	/*
299	* Until all keys are released, defer further processing to
300	* the polling loop in tegra_kbc_keypress_timer
301	*/
302	ctl = readl(kbc->mmio + KBC_CONTROL_0);
303	ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
304	writel(ctl, kbc->mmio + KBC_CONTROL_0);
305
306	/*
307	* Quickly bail out & reenable interrupts if the fifo threshold
308	* count interrupt wasn't the interrupt source
309	*/
310	val = readl(kbc->mmio + KBC_INT_0);
311	writel(val, kbc->mmio + KBC_INT_0);
312
313	if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
314	/*
315	* Schedule timer to run when hardware is in continuous
316	* polling mode.
317	*/
318	mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
319	} else {
320	ctl \|= KBC_CONTROL_FIFO_CNT_INT_EN;
321	writel(ctl, kbc->mmio + KBC_CONTROL_0);
322	}
323
324	return IRQ_HANDLED;
325	}
326
327	static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
328	{
329	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
330	int i;
331	unsigned int rst_val;
332
333	BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
334	rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;
335
336	for (i = 0; i < KBC_MAX_ROW; i++)
337	writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
338
339	if (filter) {
340	for (i = 0; i < pdata->wake_cnt; i++) {
341	u32 val, addr;
342	addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
343	val = readl(kbc->mmio + addr);
344	val &= ~(1 << pdata->wake_cfg[i].col);
345	writel(val, kbc->mmio + addr);
346	}
347	}
348	}
349
350	static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
351	{
352	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
353	int i;
354
355	for (i = 0; i < KBC_MAX_GPIO; i++) {
356	u32 r_shft = 5 * (i % 6);
357	u32 c_shft = 4 * (i % 8);
358	u32 r_mask = 0x1f << r_shift;
359	u32 c_mask = 0x0f << c_shift;
360	u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
361	u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
362	u32 row_cfg = readl(kbc->mmio + r_offs);
363	u32 col_cfg = readl(kbc->mmio + c_offs);
364
365	row_cfg &= ~r_mask;
366	col_cfg &= ~c_mask;
367
368	if (pdata->pin_cfg[i].is_row)
369	row_cfg \|= ((pdata->pin_cfg[i].num << 1) \| 1) << r_shft;
370	else
371	col_cfg \|= ((pdata->pin_cfg[i].num << 1) \| 1) << c_shft;
372
373	writel(row_cfg, kbc->mmio + r_offs);
374	writel(col_cfg, kbc->mmio + c_offs);
375	}
376	}
377
378	static int tegra_kbc_start(struct tegra_kbc *kbc)
379	{
380	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
381	unsigned long flags;
382	unsigned int debounce_cnt;
383	u32 val = 0;
384
385	clk_enable(kbc->clk);
386
387	/* Reset the KBC controller to clear all previous status.*/
388	tegra_periph_reset_assert(kbc->clk);
389	udelay(100);
390	tegra_periph_reset_deassert(kbc->clk);
391	udelay(100);
392
393	tegra_kbc_config_pins(kbc);
394	tegra_kbc_setup_wakekeys(kbc, false);
395
396	writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
397
398	/* Keyboard debounce count is maximum of 12 bits. */
399	debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
400	val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
401	val \|= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
402	val \|= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
403	val \|= KBC_CONTROL_KBC_EN; /* enable */
404	writel(val, kbc->mmio + KBC_CONTROL_0);
405
406	/*
407	* Compute the delay(ns) from interrupt mode to continuous polling
408	* mode so the timer routine is scheduled appropriately.
409	*/
410	val = readl(kbc->mmio + KBC_INIT_DLY_0);
411	kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
412
413	kbc->num_pressed_keys = 0;
414
415	/*
416	* Atomically clear out any remaining entries in the key FIFO
417	* and enable keyboard interrupts.
418	*/
419	spin_lock_irqsave(&kbc->lock, flags);
420	while (1) {
421	val = readl(kbc->mmio + KBC_INT_0);
422	val >>= 4;
423	if (!val)
424	break;
425
426	val = readl(kbc->mmio + KBC_KP_ENT0_0);
427	val = readl(kbc->mmio + KBC_KP_ENT1_0);
428	}
429	writel(0x7, kbc->mmio + KBC_INT_0);
430	spin_unlock_irqrestore(&kbc->lock, flags);
431
432	enable_irq(kbc->irq);
433
434	return 0;
435	}
436
437	static void tegra_kbc_stop(struct tegra_kbc *kbc)
438	{
439	unsigned long flags;
440	u32 val;
441
442	spin_lock_irqsave(&kbc->lock, flags);
443	val = readl(kbc->mmio + KBC_CONTROL_0);
444	val &= ~1;
445	writel(val, kbc->mmio + KBC_CONTROL_0);
446	spin_unlock_irqrestore(&kbc->lock, flags);
447
448	disable_irq(kbc->irq);
449	del_timer_sync(&kbc->timer);
450
451	clk_disable(kbc->clk);
452	}
453
454	static int tegra_kbc_open(struct input_dev *dev)
455	{
456	struct tegra_kbc *kbc = input_get_drvdata(dev);
457
458	return tegra_kbc_start(kbc);
459	}
460
461	static void tegra_kbc_close(struct input_dev *dev)
462	{
463	struct tegra_kbc *kbc = input_get_drvdata(dev);
464
465	return tegra_kbc_stop(kbc);
466	}
467
468	static bool __devinit
469	tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
470	struct device dev, unsigned int num_rows)
471	{
472	int i;
473
474	*num_rows = 0;
475
476	for (i = 0; i < KBC_MAX_GPIO; i++) {
477	const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
478
479	if (pin_cfg->is_row) {
480	if (pin_cfg->num >= KBC_MAX_ROW) {
481	dev_err(dev,
482	"pin_cfg[%d]: invalid row number %d\n",
483	i, pin_cfg->num);
484	return false;
485	}
486	(*num_rows)++;
487	} else {
488	if (pin_cfg->num >= KBC_MAX_COL) {
489	dev_err(dev,
490	"pin_cfg[%d]: invalid column number %d\n",
491	i, pin_cfg->num);
492	return false;
493	}
494	}
495	}
496
497	return true;
498	}
499
500	static int __devinit tegra_kbc_probe(struct platform_device *pdev)
501	{
502	const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
503	const struct matrix_keymap_data *keymap_data;
504	struct tegra_kbc *kbc;
505	struct input_dev *input_dev;
506	struct resource *res;
507	int irq;
508	int err;
509	int i;
510	int num_rows = 0;
511	unsigned int debounce_cnt;
512	unsigned int scan_time_rows;
513
514	if (!pdata)
515	return -EINVAL;
516
517	if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
518	return -EINVAL;
519
520	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
521	if (!res) {
522	dev_err(&pdev->dev, "failed to get I/O memory\n");
523	return -ENXIO;
524	}
525
526	irq = platform_get_irq(pdev, 0);
527	if (irq < 0) {
528	dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
529	return -ENXIO;
530	}
531
532	kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
533	input_dev = input_allocate_device();
534	if (!kbc \|\| !input_dev) {
535	err = -ENOMEM;
536	goto err_free_mem;
537	}
538
539	kbc->pdata = pdata;
540	kbc->idev = input_dev;
541	kbc->irq = irq;
542	spin_lock_init(&kbc->lock);
543	setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
544
545	res = request_mem_region(res->start, resource_size(res), pdev->name);
546	if (!res) {
547	dev_err(&pdev->dev, "failed to request I/O memory\n");
548	err = -EBUSY;
549	goto err_free_mem;
550	}
551
552	kbc->mmio = ioremap(res->start, resource_size(res));
553	if (!kbc->mmio) {
554	dev_err(&pdev->dev, "failed to remap I/O memory\n");
555	err = -ENXIO;
556	goto err_free_mem_region;
557	}
558
559	kbc->clk = clk_get(&pdev->dev, NULL);
560	if (IS_ERR(kbc->clk)) {
561	dev_err(&pdev->dev, "failed to get keyboard clock\n");
562	err = PTR_ERR(kbc->clk);
563	goto err_iounmap;
564	}
565
566	kbc->wake_enable_rows = 0;
567	kbc->wake_enable_cols = 0;
568	for (i = 0; i < pdata->wake_cnt; i++) {
569	kbc->wake_enable_rows \|= (1 << pdata->wake_cfg[i].row);
570	kbc->wake_enable_cols \|= (1 << pdata->wake_cfg[i].col);
571	}
572
573	/*
574	* The time delay between two consecutive reads of the FIFO is
575	* the sum of the repeat time and the time taken for scanning
576	* the rows. There is an additional delay before the row scanning
577	* starts. The repoll delay is computed in milliseconds.
578	*/
579	debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
580	scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
581	kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
582	kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;
583
584	input_dev->name = pdev->name;
585	input_dev->id.bustype = BUS_HOST;
586	input_dev->dev.parent = &pdev->dev;
587	input_dev->open = tegra_kbc_open;
588	input_dev->close = tegra_kbc_close;
589
590	input_set_drvdata(input_dev, kbc);
591
592	input_dev->evbit[0] = BIT_MASK(EV_KEY);
593	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
594
595	input_dev->keycode = kbc->keycode;
596	input_dev->keycodesize = sizeof(kbc->keycode[0]);
597	input_dev->keycodemax = ARRAY_SIZE(kbc->keycode);
598
599	keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
600	matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
601	input_dev->keycode, input_dev->keybit);
602
603	err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
604	pdev->name, kbc);
605	if (err) {
606	dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
607	goto err_put_clk;
608	}
609
610	disable_irq(kbc->irq);
611
612	err = input_register_device(kbc->idev);
613	if (err) {
614	dev_err(&pdev->dev, "failed to register input device\n");
615	goto err_free_irq;
616	}
617
618	platform_set_drvdata(pdev, kbc);
619	device_init_wakeup(&pdev->dev, pdata->wakeup);
620
621	return 0;
622
623	err_free_irq:
624	free_irq(kbc->irq, pdev);
625	err_put_clk:
626	clk_put(kbc->clk);
627	err_iounmap:
628	iounmap(kbc->mmio);
629	err_free_mem_region:
630	release_mem_region(res->start, resource_size(res));
631	err_free_mem:
632	input_free_device(kbc->idev);
633	kfree(kbc);
634
635	return err;
636	}
637
638	static int __devexit tegra_kbc_remove(struct platform_device *pdev)
639	{
640	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
641	struct resource *res;
642
643	free_irq(kbc->irq, pdev);
644	clk_put(kbc->clk);
645
646	input_unregister_device(kbc->idev);
647	iounmap(kbc->mmio);
648	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649	release_mem_region(res->start, resource_size(res));
650
651	kfree(kbc);
652
653	platform_set_drvdata(pdev, NULL);
654
655	return 0;
656	}
657
658	#ifdef CONFIG_PM_SLEEP
659	static int tegra_kbc_suspend(struct device *dev)
660	{
661	struct platform_device *pdev = to_platform_device(dev);
662	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
663
664	if (device_may_wakeup(&pdev->dev)) {
665	tegra_kbc_setup_wakekeys(kbc, true);
666	enable_irq_wake(kbc->irq);
667	/* Forcefully clear the interrupt status */
668	writel(0x7, kbc->mmio + KBC_INT_0);
669	msleep(30);
670	} else {
671	mutex_lock(&kbc->idev->mutex);
672	if (kbc->idev->users)
673	tegra_kbc_stop(kbc);
674	mutex_unlock(&kbc->idev->mutex);
675	}
676
677	return 0;
678	}
679
680	static int tegra_kbc_resume(struct device *dev)
681	{
682	struct platform_device *pdev = to_platform_device(dev);
683	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
684	int err = 0;
685
686	if (device_may_wakeup(&pdev->dev)) {
687	disable_irq_wake(kbc->irq);
688	tegra_kbc_setup_wakekeys(kbc, false);
689	} else {
690	mutex_lock(&kbc->idev->mutex);
691	if (kbc->idev->users)
692	err = tegra_kbc_start(kbc);
693	mutex_unlock(&kbc->idev->mutex);
694	}
695
696	return err;
697	}
698	#endif
699
700	static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
701
702	static struct platform_driver tegra_kbc_driver = {
703	.probe = tegra_kbc_probe,
704	.remove = __devexit_p(tegra_kbc_remove),
705	.driver = {
706	.name = "tegra-kbc",
707	.owner = THIS_MODULE,
708	.pm = &tegra_kbc_pm_ops,
709	},
710	};
711
712	static void __exit tegra_kbc_exit(void)
713	{
714	platform_driver_unregister(&tegra_kbc_driver);
715	}
716	module_exit(tegra_kbc_exit);
717
718	static int __init tegra_kbc_init(void)
719	{
720	return platform_driver_register(&tegra_kbc_driver);
721	}
722	module_init(tegra_kbc_init);
723
724	MODULE_LICENSE("GPL");
725	MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
726	MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
727	MODULE_ALIAS("platform:tegra-kbc");