Commit | Line | Data |
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11f5b30d RI |
1 | /* |
2 | * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix | |
3 | * keyboard controller | |
4 | * | |
5 | * Copyright (c) 2009-2011, NVIDIA Corporation. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | */ | |
21 | ||
3f27757a | 22 | #include <linux/kernel.h> |
11f5b30d RI |
23 | #include <linux/module.h> |
24 | #include <linux/input.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/slab.h> | |
31 | #include <mach/clk.h> | |
32 | #include <mach/kbc.h> | |
33 | ||
34 | #define KBC_MAX_DEBOUNCE_CNT 0x3ffu | |
35 | ||
36 | /* KBC row scan time and delay for beginning the row scan. */ | |
37 | #define KBC_ROW_SCAN_TIME 16 | |
38 | #define KBC_ROW_SCAN_DLY 5 | |
39 | ||
40 | /* KBC uses a 32KHz clock so a cycle = 1/32Khz */ | |
3f27757a | 41 | #define KBC_CYCLE_MS 32 |
11f5b30d RI |
42 | |
43 | /* KBC Registers */ | |
44 | ||
45 | /* KBC Control Register */ | |
46 | #define KBC_CONTROL_0 0x0 | |
47 | #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) | |
48 | #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) | |
49 | #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) | |
50 | #define KBC_CONTROL_KBC_EN (1 << 0) | |
51 | ||
52 | /* KBC Interrupt Register */ | |
53 | #define KBC_INT_0 0x4 | |
54 | #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) | |
55 | ||
56 | #define KBC_ROW_CFG0_0 0x8 | |
57 | #define KBC_COL_CFG0_0 0x18 | |
d0d150ec | 58 | #define KBC_TO_CNT_0 0x24 |
11f5b30d RI |
59 | #define KBC_INIT_DLY_0 0x28 |
60 | #define KBC_RPT_DLY_0 0x2c | |
61 | #define KBC_KP_ENT0_0 0x30 | |
62 | #define KBC_KP_ENT1_0 0x34 | |
63 | #define KBC_ROW0_MASK_0 0x38 | |
64 | ||
65 | #define KBC_ROW_SHIFT 3 | |
66 | ||
67 | struct tegra_kbc { | |
68 | void __iomem *mmio; | |
69 | struct input_dev *idev; | |
70 | unsigned int irq; | |
11f5b30d RI |
71 | spinlock_t lock; |
72 | unsigned int repoll_dly; | |
73 | unsigned long cp_dly_jiffies; | |
d0d150ec | 74 | unsigned int cp_to_wkup_dly; |
4e8b65f6 | 75 | bool use_fn_map; |
34abeeb2 | 76 | bool use_ghost_filter; |
11f5b30d | 77 | const struct tegra_kbc_platform_data *pdata; |
4e8b65f6 | 78 | unsigned short keycode[KBC_MAX_KEY * 2]; |
11f5b30d RI |
79 | unsigned short current_keys[KBC_MAX_KPENT]; |
80 | unsigned int num_pressed_keys; | |
81 | struct timer_list timer; | |
82 | struct clk *clk; | |
83 | }; | |
84 | ||
85 | static const u32 tegra_kbc_default_keymap[] = { | |
86 | KEY(0, 2, KEY_W), | |
87 | KEY(0, 3, KEY_S), | |
88 | KEY(0, 4, KEY_A), | |
89 | KEY(0, 5, KEY_Z), | |
90 | KEY(0, 7, KEY_FN), | |
91 | ||
e7acc84a | 92 | KEY(1, 7, KEY_LEFTMETA), |
11f5b30d RI |
93 | |
94 | KEY(2, 6, KEY_RIGHTALT), | |
95 | KEY(2, 7, KEY_LEFTALT), | |
96 | ||
97 | KEY(3, 0, KEY_5), | |
98 | KEY(3, 1, KEY_4), | |
99 | KEY(3, 2, KEY_R), | |
100 | KEY(3, 3, KEY_E), | |
101 | KEY(3, 4, KEY_F), | |
102 | KEY(3, 5, KEY_D), | |
103 | KEY(3, 6, KEY_X), | |
104 | ||
105 | KEY(4, 0, KEY_7), | |
106 | KEY(4, 1, KEY_6), | |
107 | KEY(4, 2, KEY_T), | |
108 | KEY(4, 3, KEY_H), | |
109 | KEY(4, 4, KEY_G), | |
110 | KEY(4, 5, KEY_V), | |
111 | KEY(4, 6, KEY_C), | |
112 | KEY(4, 7, KEY_SPACE), | |
113 | ||
114 | KEY(5, 0, KEY_9), | |
115 | KEY(5, 1, KEY_8), | |
116 | KEY(5, 2, KEY_U), | |
117 | KEY(5, 3, KEY_Y), | |
118 | KEY(5, 4, KEY_J), | |
119 | KEY(5, 5, KEY_N), | |
120 | KEY(5, 6, KEY_B), | |
121 | KEY(5, 7, KEY_BACKSLASH), | |
122 | ||
123 | KEY(6, 0, KEY_MINUS), | |
124 | KEY(6, 1, KEY_0), | |
125 | KEY(6, 2, KEY_O), | |
126 | KEY(6, 3, KEY_I), | |
127 | KEY(6, 4, KEY_L), | |
128 | KEY(6, 5, KEY_K), | |
129 | KEY(6, 6, KEY_COMMA), | |
130 | KEY(6, 7, KEY_M), | |
131 | ||
132 | KEY(7, 1, KEY_EQUAL), | |
133 | KEY(7, 2, KEY_RIGHTBRACE), | |
134 | KEY(7, 3, KEY_ENTER), | |
135 | KEY(7, 7, KEY_MENU), | |
136 | ||
137 | KEY(8, 4, KEY_RIGHTSHIFT), | |
138 | KEY(8, 5, KEY_LEFTSHIFT), | |
139 | ||
140 | KEY(9, 5, KEY_RIGHTCTRL), | |
141 | KEY(9, 7, KEY_LEFTCTRL), | |
142 | ||
143 | KEY(11, 0, KEY_LEFTBRACE), | |
144 | KEY(11, 1, KEY_P), | |
145 | KEY(11, 2, KEY_APOSTROPHE), | |
146 | KEY(11, 3, KEY_SEMICOLON), | |
147 | KEY(11, 4, KEY_SLASH), | |
148 | KEY(11, 5, KEY_DOT), | |
149 | ||
150 | KEY(12, 0, KEY_F10), | |
151 | KEY(12, 1, KEY_F9), | |
152 | KEY(12, 2, KEY_BACKSPACE), | |
153 | KEY(12, 3, KEY_3), | |
154 | KEY(12, 4, KEY_2), | |
155 | KEY(12, 5, KEY_UP), | |
156 | KEY(12, 6, KEY_PRINT), | |
157 | KEY(12, 7, KEY_PAUSE), | |
158 | ||
159 | KEY(13, 0, KEY_INSERT), | |
160 | KEY(13, 1, KEY_DELETE), | |
161 | KEY(13, 3, KEY_PAGEUP), | |
162 | KEY(13, 4, KEY_PAGEDOWN), | |
163 | KEY(13, 5, KEY_RIGHT), | |
164 | KEY(13, 6, KEY_DOWN), | |
165 | KEY(13, 7, KEY_LEFT), | |
166 | ||
167 | KEY(14, 0, KEY_F11), | |
168 | KEY(14, 1, KEY_F12), | |
169 | KEY(14, 2, KEY_F8), | |
170 | KEY(14, 3, KEY_Q), | |
171 | KEY(14, 4, KEY_F4), | |
172 | KEY(14, 5, KEY_F3), | |
173 | KEY(14, 6, KEY_1), | |
174 | KEY(14, 7, KEY_F7), | |
175 | ||
176 | KEY(15, 0, KEY_ESC), | |
177 | KEY(15, 1, KEY_GRAVE), | |
178 | KEY(15, 2, KEY_F5), | |
179 | KEY(15, 3, KEY_TAB), | |
180 | KEY(15, 4, KEY_F1), | |
181 | KEY(15, 5, KEY_F2), | |
182 | KEY(15, 6, KEY_CAPSLOCK), | |
183 | KEY(15, 7, KEY_F6), | |
4e8b65f6 RI |
184 | |
185 | /* Software Handled Function Keys */ | |
186 | KEY(20, 0, KEY_KP7), | |
187 | ||
188 | KEY(21, 0, KEY_KP9), | |
189 | KEY(21, 1, KEY_KP8), | |
190 | KEY(21, 2, KEY_KP4), | |
191 | KEY(21, 4, KEY_KP1), | |
192 | ||
193 | KEY(22, 1, KEY_KPSLASH), | |
194 | KEY(22, 2, KEY_KP6), | |
195 | KEY(22, 3, KEY_KP5), | |
196 | KEY(22, 4, KEY_KP3), | |
197 | KEY(22, 5, KEY_KP2), | |
198 | KEY(22, 7, KEY_KP0), | |
199 | ||
200 | KEY(27, 1, KEY_KPASTERISK), | |
201 | KEY(27, 3, KEY_KPMINUS), | |
202 | KEY(27, 4, KEY_KPPLUS), | |
203 | KEY(27, 5, KEY_KPDOT), | |
204 | ||
205 | KEY(28, 5, KEY_VOLUMEUP), | |
206 | ||
207 | KEY(29, 3, KEY_HOME), | |
208 | KEY(29, 4, KEY_END), | |
209 | KEY(29, 5, KEY_BRIGHTNESSDOWN), | |
210 | KEY(29, 6, KEY_VOLUMEDOWN), | |
211 | KEY(29, 7, KEY_BRIGHTNESSUP), | |
212 | ||
213 | KEY(30, 0, KEY_NUMLOCK), | |
214 | KEY(30, 1, KEY_SCROLLLOCK), | |
215 | KEY(30, 2, KEY_MUTE), | |
216 | ||
217 | KEY(31, 4, KEY_HELP), | |
11f5b30d RI |
218 | }; |
219 | ||
220 | static const struct matrix_keymap_data tegra_kbc_default_keymap_data = { | |
221 | .keymap = tegra_kbc_default_keymap, | |
222 | .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap), | |
223 | }; | |
224 | ||
225 | static void tegra_kbc_report_released_keys(struct input_dev *input, | |
226 | unsigned short old_keycodes[], | |
227 | unsigned int old_num_keys, | |
228 | unsigned short new_keycodes[], | |
229 | unsigned int new_num_keys) | |
230 | { | |
231 | unsigned int i, j; | |
232 | ||
233 | for (i = 0; i < old_num_keys; i++) { | |
234 | for (j = 0; j < new_num_keys; j++) | |
235 | if (old_keycodes[i] == new_keycodes[j]) | |
236 | break; | |
237 | ||
238 | if (j == new_num_keys) | |
239 | input_report_key(input, old_keycodes[i], 0); | |
240 | } | |
241 | } | |
242 | ||
243 | static void tegra_kbc_report_pressed_keys(struct input_dev *input, | |
244 | unsigned char scancodes[], | |
245 | unsigned short keycodes[], | |
246 | unsigned int num_pressed_keys) | |
247 | { | |
248 | unsigned int i; | |
249 | ||
250 | for (i = 0; i < num_pressed_keys; i++) { | |
251 | input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); | |
252 | input_report_key(input, keycodes[i], 1); | |
253 | } | |
254 | } | |
255 | ||
256 | static void tegra_kbc_report_keys(struct tegra_kbc *kbc) | |
257 | { | |
258 | unsigned char scancodes[KBC_MAX_KPENT]; | |
259 | unsigned short keycodes[KBC_MAX_KPENT]; | |
260 | u32 val = 0; | |
261 | unsigned int i; | |
262 | unsigned int num_down = 0; | |
263 | unsigned long flags; | |
4e8b65f6 | 264 | bool fn_keypress = false; |
34abeeb2 RI |
265 | bool key_in_same_row = false; |
266 | bool key_in_same_col = false; | |
11f5b30d RI |
267 | |
268 | spin_lock_irqsave(&kbc->lock, flags); | |
269 | for (i = 0; i < KBC_MAX_KPENT; i++) { | |
270 | if ((i % 4) == 0) | |
271 | val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); | |
272 | ||
273 | if (val & 0x80) { | |
274 | unsigned int col = val & 0x07; | |
275 | unsigned int row = (val >> 3) & 0x0f; | |
276 | unsigned char scancode = | |
277 | MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); | |
278 | ||
279 | scancodes[num_down] = scancode; | |
4e8b65f6 RI |
280 | keycodes[num_down] = kbc->keycode[scancode]; |
281 | /* If driver uses Fn map, do not report the Fn key. */ | |
282 | if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) | |
283 | fn_keypress = true; | |
284 | else | |
285 | num_down++; | |
11f5b30d RI |
286 | } |
287 | ||
288 | val >>= 8; | |
289 | } | |
4e8b65f6 | 290 | |
34abeeb2 RI |
291 | /* |
292 | * Matrix keyboard designs are prone to keyboard ghosting. | |
293 | * Ghosting occurs if there are 3 keys such that - | |
294 | * any 2 of the 3 keys share a row, and any 2 of them share a column. | |
295 | * If so ignore the key presses for this iteration. | |
296 | */ | |
297 | if ((kbc->use_ghost_filter) && (num_down >= 3)) { | |
298 | for (i = 0; i < num_down; i++) { | |
299 | unsigned int j; | |
300 | u8 curr_col = scancodes[i] & 0x07; | |
301 | u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; | |
302 | ||
303 | /* | |
304 | * Find 2 keys such that one key is in the same row | |
305 | * and the other is in the same column as the i-th key. | |
306 | */ | |
307 | for (j = i + 1; j < num_down; j++) { | |
308 | u8 col = scancodes[j] & 0x07; | |
309 | u8 row = scancodes[j] >> KBC_ROW_SHIFT; | |
310 | ||
311 | if (col == curr_col) | |
312 | key_in_same_col = true; | |
313 | if (row == curr_row) | |
314 | key_in_same_row = true; | |
315 | } | |
316 | } | |
317 | } | |
318 | ||
4e8b65f6 RI |
319 | /* |
320 | * If the platform uses Fn keymaps, translate keys on a Fn keypress. | |
321 | * Function keycodes are KBC_MAX_KEY apart from the plain keycodes. | |
322 | */ | |
323 | if (fn_keypress) { | |
324 | for (i = 0; i < num_down; i++) { | |
325 | scancodes[i] += KBC_MAX_KEY; | |
326 | keycodes[i] = kbc->keycode[scancodes[i]]; | |
327 | } | |
328 | } | |
329 | ||
11f5b30d RI |
330 | spin_unlock_irqrestore(&kbc->lock, flags); |
331 | ||
34abeeb2 RI |
332 | /* Ignore the key presses for this iteration? */ |
333 | if (key_in_same_col && key_in_same_row) | |
334 | return; | |
335 | ||
11f5b30d RI |
336 | tegra_kbc_report_released_keys(kbc->idev, |
337 | kbc->current_keys, kbc->num_pressed_keys, | |
338 | keycodes, num_down); | |
339 | tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); | |
340 | input_sync(kbc->idev); | |
341 | ||
342 | memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); | |
343 | kbc->num_pressed_keys = num_down; | |
344 | } | |
345 | ||
d0d150ec RI |
346 | static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) |
347 | { | |
348 | u32 val; | |
349 | ||
350 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
351 | if (enable) | |
352 | val |= KBC_CONTROL_FIFO_CNT_INT_EN; | |
353 | else | |
354 | val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; | |
355 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
356 | } | |
357 | ||
11f5b30d RI |
358 | static void tegra_kbc_keypress_timer(unsigned long data) |
359 | { | |
360 | struct tegra_kbc *kbc = (struct tegra_kbc *)data; | |
361 | unsigned long flags; | |
362 | u32 val; | |
363 | unsigned int i; | |
364 | ||
365 | val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; | |
366 | if (val) { | |
367 | unsigned long dly; | |
368 | ||
369 | tegra_kbc_report_keys(kbc); | |
370 | ||
371 | /* | |
372 | * If more than one keys are pressed we need not wait | |
373 | * for the repoll delay. | |
374 | */ | |
375 | dly = (val == 1) ? kbc->repoll_dly : 1; | |
376 | mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); | |
377 | } else { | |
378 | /* Release any pressed keys and exit the polling loop */ | |
379 | for (i = 0; i < kbc->num_pressed_keys; i++) | |
380 | input_report_key(kbc->idev, kbc->current_keys[i], 0); | |
381 | input_sync(kbc->idev); | |
382 | ||
383 | kbc->num_pressed_keys = 0; | |
384 | ||
385 | /* All keys are released so enable the keypress interrupt */ | |
386 | spin_lock_irqsave(&kbc->lock, flags); | |
d0d150ec | 387 | tegra_kbc_set_fifo_interrupt(kbc, true); |
11f5b30d RI |
388 | spin_unlock_irqrestore(&kbc->lock, flags); |
389 | } | |
390 | } | |
391 | ||
392 | static irqreturn_t tegra_kbc_isr(int irq, void *args) | |
393 | { | |
394 | struct tegra_kbc *kbc = args; | |
d0d150ec | 395 | u32 val; |
11f5b30d RI |
396 | |
397 | /* | |
398 | * Until all keys are released, defer further processing to | |
399 | * the polling loop in tegra_kbc_keypress_timer | |
400 | */ | |
d0d150ec | 401 | tegra_kbc_set_fifo_interrupt(kbc, false); |
11f5b30d RI |
402 | |
403 | /* | |
404 | * Quickly bail out & reenable interrupts if the fifo threshold | |
405 | * count interrupt wasn't the interrupt source | |
406 | */ | |
407 | val = readl(kbc->mmio + KBC_INT_0); | |
408 | writel(val, kbc->mmio + KBC_INT_0); | |
409 | ||
410 | if (val & KBC_INT_FIFO_CNT_INT_STATUS) { | |
411 | /* | |
412 | * Schedule timer to run when hardware is in continuous | |
413 | * polling mode. | |
414 | */ | |
415 | mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); | |
416 | } else { | |
d0d150ec | 417 | tegra_kbc_set_fifo_interrupt(kbc, true); |
11f5b30d RI |
418 | } |
419 | ||
420 | return IRQ_HANDLED; | |
421 | } | |
422 | ||
423 | static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) | |
424 | { | |
425 | const struct tegra_kbc_platform_data *pdata = kbc->pdata; | |
426 | int i; | |
427 | unsigned int rst_val; | |
428 | ||
baafb435 RI |
429 | /* Either mask all keys or none. */ |
430 | rst_val = (filter && !pdata->wakeup) ? ~0 : 0; | |
11f5b30d RI |
431 | |
432 | for (i = 0; i < KBC_MAX_ROW; i++) | |
433 | writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); | |
11f5b30d RI |
434 | } |
435 | ||
436 | static void tegra_kbc_config_pins(struct tegra_kbc *kbc) | |
437 | { | |
438 | const struct tegra_kbc_platform_data *pdata = kbc->pdata; | |
439 | int i; | |
440 | ||
441 | for (i = 0; i < KBC_MAX_GPIO; i++) { | |
442 | u32 r_shft = 5 * (i % 6); | |
443 | u32 c_shft = 4 * (i % 8); | |
7530c4a1 RI |
444 | u32 r_mask = 0x1f << r_shft; |
445 | u32 c_mask = 0x0f << c_shft; | |
11f5b30d RI |
446 | u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; |
447 | u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; | |
448 | u32 row_cfg = readl(kbc->mmio + r_offs); | |
449 | u32 col_cfg = readl(kbc->mmio + c_offs); | |
450 | ||
451 | row_cfg &= ~r_mask; | |
452 | col_cfg &= ~c_mask; | |
453 | ||
454 | if (pdata->pin_cfg[i].is_row) | |
455 | row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft; | |
456 | else | |
457 | col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft; | |
458 | ||
459 | writel(row_cfg, kbc->mmio + r_offs); | |
460 | writel(col_cfg, kbc->mmio + c_offs); | |
461 | } | |
462 | } | |
463 | ||
464 | static int tegra_kbc_start(struct tegra_kbc *kbc) | |
465 | { | |
466 | const struct tegra_kbc_platform_data *pdata = kbc->pdata; | |
467 | unsigned long flags; | |
468 | unsigned int debounce_cnt; | |
469 | u32 val = 0; | |
470 | ||
471 | clk_enable(kbc->clk); | |
472 | ||
473 | /* Reset the KBC controller to clear all previous status.*/ | |
474 | tegra_periph_reset_assert(kbc->clk); | |
475 | udelay(100); | |
476 | tegra_periph_reset_deassert(kbc->clk); | |
477 | udelay(100); | |
478 | ||
479 | tegra_kbc_config_pins(kbc); | |
480 | tegra_kbc_setup_wakekeys(kbc, false); | |
481 | ||
482 | writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); | |
483 | ||
484 | /* Keyboard debounce count is maximum of 12 bits. */ | |
485 | debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); | |
486 | val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); | |
487 | val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ | |
488 | val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ | |
489 | val |= KBC_CONTROL_KBC_EN; /* enable */ | |
490 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
491 | ||
492 | /* | |
493 | * Compute the delay(ns) from interrupt mode to continuous polling | |
494 | * mode so the timer routine is scheduled appropriately. | |
495 | */ | |
496 | val = readl(kbc->mmio + KBC_INIT_DLY_0); | |
497 | kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); | |
498 | ||
499 | kbc->num_pressed_keys = 0; | |
500 | ||
501 | /* | |
502 | * Atomically clear out any remaining entries in the key FIFO | |
503 | * and enable keyboard interrupts. | |
504 | */ | |
505 | spin_lock_irqsave(&kbc->lock, flags); | |
506 | while (1) { | |
507 | val = readl(kbc->mmio + KBC_INT_0); | |
508 | val >>= 4; | |
509 | if (!val) | |
510 | break; | |
511 | ||
512 | val = readl(kbc->mmio + KBC_KP_ENT0_0); | |
513 | val = readl(kbc->mmio + KBC_KP_ENT1_0); | |
514 | } | |
515 | writel(0x7, kbc->mmio + KBC_INT_0); | |
516 | spin_unlock_irqrestore(&kbc->lock, flags); | |
517 | ||
518 | enable_irq(kbc->irq); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | static void tegra_kbc_stop(struct tegra_kbc *kbc) | |
524 | { | |
525 | unsigned long flags; | |
526 | u32 val; | |
527 | ||
528 | spin_lock_irqsave(&kbc->lock, flags); | |
529 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
530 | val &= ~1; | |
531 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
532 | spin_unlock_irqrestore(&kbc->lock, flags); | |
533 | ||
534 | disable_irq(kbc->irq); | |
535 | del_timer_sync(&kbc->timer); | |
536 | ||
537 | clk_disable(kbc->clk); | |
538 | } | |
539 | ||
540 | static int tegra_kbc_open(struct input_dev *dev) | |
541 | { | |
542 | struct tegra_kbc *kbc = input_get_drvdata(dev); | |
543 | ||
544 | return tegra_kbc_start(kbc); | |
545 | } | |
546 | ||
547 | static void tegra_kbc_close(struct input_dev *dev) | |
548 | { | |
549 | struct tegra_kbc *kbc = input_get_drvdata(dev); | |
550 | ||
551 | return tegra_kbc_stop(kbc); | |
552 | } | |
553 | ||
554 | static bool __devinit | |
555 | tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata, | |
556 | struct device *dev, unsigned int *num_rows) | |
557 | { | |
558 | int i; | |
559 | ||
560 | *num_rows = 0; | |
561 | ||
562 | for (i = 0; i < KBC_MAX_GPIO; i++) { | |
563 | const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i]; | |
564 | ||
565 | if (pin_cfg->is_row) { | |
566 | if (pin_cfg->num >= KBC_MAX_ROW) { | |
567 | dev_err(dev, | |
568 | "pin_cfg[%d]: invalid row number %d\n", | |
569 | i, pin_cfg->num); | |
570 | return false; | |
571 | } | |
572 | (*num_rows)++; | |
573 | } else { | |
574 | if (pin_cfg->num >= KBC_MAX_COL) { | |
575 | dev_err(dev, | |
576 | "pin_cfg[%d]: invalid column number %d\n", | |
577 | i, pin_cfg->num); | |
578 | return false; | |
579 | } | |
580 | } | |
581 | } | |
582 | ||
583 | return true; | |
584 | } | |
585 | ||
586 | static int __devinit tegra_kbc_probe(struct platform_device *pdev) | |
587 | { | |
588 | const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data; | |
589 | const struct matrix_keymap_data *keymap_data; | |
590 | struct tegra_kbc *kbc; | |
591 | struct input_dev *input_dev; | |
592 | struct resource *res; | |
593 | int irq; | |
594 | int err; | |
11f5b30d RI |
595 | int num_rows = 0; |
596 | unsigned int debounce_cnt; | |
597 | unsigned int scan_time_rows; | |
598 | ||
599 | if (!pdata) | |
600 | return -EINVAL; | |
601 | ||
602 | if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows)) | |
603 | return -EINVAL; | |
604 | ||
605 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
606 | if (!res) { | |
607 | dev_err(&pdev->dev, "failed to get I/O memory\n"); | |
608 | return -ENXIO; | |
609 | } | |
610 | ||
611 | irq = platform_get_irq(pdev, 0); | |
612 | if (irq < 0) { | |
613 | dev_err(&pdev->dev, "failed to get keyboard IRQ\n"); | |
614 | return -ENXIO; | |
615 | } | |
616 | ||
617 | kbc = kzalloc(sizeof(*kbc), GFP_KERNEL); | |
618 | input_dev = input_allocate_device(); | |
619 | if (!kbc || !input_dev) { | |
620 | err = -ENOMEM; | |
621 | goto err_free_mem; | |
622 | } | |
623 | ||
624 | kbc->pdata = pdata; | |
625 | kbc->idev = input_dev; | |
626 | kbc->irq = irq; | |
627 | spin_lock_init(&kbc->lock); | |
628 | setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc); | |
629 | ||
630 | res = request_mem_region(res->start, resource_size(res), pdev->name); | |
631 | if (!res) { | |
632 | dev_err(&pdev->dev, "failed to request I/O memory\n"); | |
633 | err = -EBUSY; | |
634 | goto err_free_mem; | |
635 | } | |
636 | ||
637 | kbc->mmio = ioremap(res->start, resource_size(res)); | |
638 | if (!kbc->mmio) { | |
639 | dev_err(&pdev->dev, "failed to remap I/O memory\n"); | |
640 | err = -ENXIO; | |
641 | goto err_free_mem_region; | |
642 | } | |
643 | ||
644 | kbc->clk = clk_get(&pdev->dev, NULL); | |
645 | if (IS_ERR(kbc->clk)) { | |
646 | dev_err(&pdev->dev, "failed to get keyboard clock\n"); | |
647 | err = PTR_ERR(kbc->clk); | |
648 | goto err_iounmap; | |
649 | } | |
650 | ||
11f5b30d RI |
651 | /* |
652 | * The time delay between two consecutive reads of the FIFO is | |
653 | * the sum of the repeat time and the time taken for scanning | |
654 | * the rows. There is an additional delay before the row scanning | |
655 | * starts. The repoll delay is computed in milliseconds. | |
656 | */ | |
657 | debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); | |
658 | scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; | |
659 | kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt; | |
3f27757a | 660 | kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); |
11f5b30d RI |
661 | |
662 | input_dev->name = pdev->name; | |
663 | input_dev->id.bustype = BUS_HOST; | |
664 | input_dev->dev.parent = &pdev->dev; | |
665 | input_dev->open = tegra_kbc_open; | |
666 | input_dev->close = tegra_kbc_close; | |
667 | ||
668 | input_set_drvdata(input_dev, kbc); | |
669 | ||
5599d2e6 | 670 | input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP); |
11f5b30d RI |
671 | input_set_capability(input_dev, EV_MSC, MSC_SCAN); |
672 | ||
673 | input_dev->keycode = kbc->keycode; | |
674 | input_dev->keycodesize = sizeof(kbc->keycode[0]); | |
4e8b65f6 RI |
675 | input_dev->keycodemax = KBC_MAX_KEY; |
676 | if (pdata->use_fn_map) | |
677 | input_dev->keycodemax *= 2; | |
11f5b30d | 678 | |
4e8b65f6 | 679 | kbc->use_fn_map = pdata->use_fn_map; |
34abeeb2 | 680 | kbc->use_ghost_filter = pdata->use_ghost_filter; |
11f5b30d RI |
681 | keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data; |
682 | matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT, | |
683 | input_dev->keycode, input_dev->keybit); | |
684 | ||
685 | err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH, | |
686 | pdev->name, kbc); | |
687 | if (err) { | |
688 | dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); | |
689 | goto err_put_clk; | |
690 | } | |
691 | ||
692 | disable_irq(kbc->irq); | |
693 | ||
694 | err = input_register_device(kbc->idev); | |
695 | if (err) { | |
696 | dev_err(&pdev->dev, "failed to register input device\n"); | |
697 | goto err_free_irq; | |
698 | } | |
699 | ||
700 | platform_set_drvdata(pdev, kbc); | |
701 | device_init_wakeup(&pdev->dev, pdata->wakeup); | |
702 | ||
703 | return 0; | |
704 | ||
705 | err_free_irq: | |
706 | free_irq(kbc->irq, pdev); | |
707 | err_put_clk: | |
708 | clk_put(kbc->clk); | |
709 | err_iounmap: | |
710 | iounmap(kbc->mmio); | |
711 | err_free_mem_region: | |
712 | release_mem_region(res->start, resource_size(res)); | |
713 | err_free_mem: | |
22f83205 | 714 | input_free_device(input_dev); |
11f5b30d RI |
715 | kfree(kbc); |
716 | ||
717 | return err; | |
718 | } | |
719 | ||
720 | static int __devexit tegra_kbc_remove(struct platform_device *pdev) | |
721 | { | |
722 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
723 | struct resource *res; | |
724 | ||
725 | free_irq(kbc->irq, pdev); | |
726 | clk_put(kbc->clk); | |
727 | ||
728 | input_unregister_device(kbc->idev); | |
729 | iounmap(kbc->mmio); | |
730 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
731 | release_mem_region(res->start, resource_size(res)); | |
732 | ||
733 | kfree(kbc); | |
734 | ||
735 | platform_set_drvdata(pdev, NULL); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
740 | #ifdef CONFIG_PM_SLEEP | |
741 | static int tegra_kbc_suspend(struct device *dev) | |
742 | { | |
743 | struct platform_device *pdev = to_platform_device(dev); | |
744 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
745 | ||
d0d150ec | 746 | mutex_lock(&kbc->idev->mutex); |
11f5b30d | 747 | if (device_may_wakeup(&pdev->dev)) { |
d0d150ec RI |
748 | disable_irq(kbc->irq); |
749 | del_timer_sync(&kbc->timer); | |
750 | tegra_kbc_set_fifo_interrupt(kbc, false); | |
751 | ||
11f5b30d RI |
752 | /* Forcefully clear the interrupt status */ |
753 | writel(0x7, kbc->mmio + KBC_INT_0); | |
d0d150ec RI |
754 | /* |
755 | * Store the previous resident time of continuous polling mode. | |
756 | * Force the keyboard into interrupt mode. | |
757 | */ | |
758 | kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); | |
759 | writel(0, kbc->mmio + KBC_TO_CNT_0); | |
760 | ||
761 | tegra_kbc_setup_wakekeys(kbc, true); | |
11f5b30d | 762 | msleep(30); |
d0d150ec RI |
763 | |
764 | enable_irq_wake(kbc->irq); | |
11f5b30d | 765 | } else { |
11f5b30d RI |
766 | if (kbc->idev->users) |
767 | tegra_kbc_stop(kbc); | |
11f5b30d | 768 | } |
d0d150ec | 769 | mutex_unlock(&kbc->idev->mutex); |
11f5b30d RI |
770 | |
771 | return 0; | |
772 | } | |
773 | ||
774 | static int tegra_kbc_resume(struct device *dev) | |
775 | { | |
776 | struct platform_device *pdev = to_platform_device(dev); | |
777 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
778 | int err = 0; | |
779 | ||
d0d150ec | 780 | mutex_lock(&kbc->idev->mutex); |
11f5b30d RI |
781 | if (device_may_wakeup(&pdev->dev)) { |
782 | disable_irq_wake(kbc->irq); | |
783 | tegra_kbc_setup_wakekeys(kbc, false); | |
d0d150ec RI |
784 | |
785 | /* Restore the resident time of continuous polling mode. */ | |
786 | writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); | |
787 | ||
788 | tegra_kbc_set_fifo_interrupt(kbc, true); | |
789 | ||
790 | enable_irq(kbc->irq); | |
11f5b30d | 791 | } else { |
11f5b30d RI |
792 | if (kbc->idev->users) |
793 | err = tegra_kbc_start(kbc); | |
11f5b30d | 794 | } |
d0d150ec | 795 | mutex_unlock(&kbc->idev->mutex); |
11f5b30d RI |
796 | |
797 | return err; | |
798 | } | |
799 | #endif | |
800 | ||
801 | static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume); | |
802 | ||
803 | static struct platform_driver tegra_kbc_driver = { | |
804 | .probe = tegra_kbc_probe, | |
805 | .remove = __devexit_p(tegra_kbc_remove), | |
806 | .driver = { | |
807 | .name = "tegra-kbc", | |
808 | .owner = THIS_MODULE, | |
809 | .pm = &tegra_kbc_pm_ops, | |
810 | }, | |
811 | }; | |
812 | ||
813 | static void __exit tegra_kbc_exit(void) | |
814 | { | |
815 | platform_driver_unregister(&tegra_kbc_driver); | |
816 | } | |
817 | module_exit(tegra_kbc_exit); | |
818 | ||
819 | static int __init tegra_kbc_init(void) | |
820 | { | |
821 | return platform_driver_register(&tegra_kbc_driver); | |
822 | } | |
823 | module_init(tegra_kbc_init); | |
824 | ||
825 | MODULE_LICENSE("GPL"); | |
826 | MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); | |
827 | MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); | |
828 | MODULE_ALIAS("platform:tegra-kbc"); |