Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/module.h> | |
1da177e4 LT |
15 | #include <linux/interrupt.h> |
16 | #include <linux/ioport.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/serio.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/rcupdate.h> | |
d052d1be | 21 | #include <linux/platform_device.h> |
553a05b8 | 22 | #include <linux/i8042.h> |
1da177e4 LT |
23 | |
24 | #include <asm/io.h> | |
25 | ||
26 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
27 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
28 | MODULE_LICENSE("GPL"); | |
29 | ||
945ef0d4 DT |
30 | static unsigned int i8042_nokbd; |
31 | module_param_named(nokbd, i8042_nokbd, bool, 0); | |
32 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
33 | ||
1da177e4 LT |
34 | static unsigned int i8042_noaux; |
35 | module_param_named(noaux, i8042_noaux, bool, 0); | |
36 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
37 | ||
38 | static unsigned int i8042_nomux; | |
39 | module_param_named(nomux, i8042_nomux, bool, 0); | |
40 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); | |
41 | ||
42 | static unsigned int i8042_unlock; | |
43 | module_param_named(unlock, i8042_unlock, bool, 0); | |
44 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
45 | ||
46 | static unsigned int i8042_reset; | |
47 | module_param_named(reset, i8042_reset, bool, 0); | |
48 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
49 | ||
50 | static unsigned int i8042_direct; | |
51 | module_param_named(direct, i8042_direct, bool, 0); | |
52 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
53 | ||
54 | static unsigned int i8042_dumbkbd; | |
55 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); | |
56 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
57 | ||
58 | static unsigned int i8042_noloop; | |
59 | module_param_named(noloop, i8042_noloop, bool, 0); | |
60 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
61 | ||
62 | static unsigned int i8042_blink_frequency = 500; | |
63 | module_param_named(panicblink, i8042_blink_frequency, uint, 0600); | |
64 | MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); | |
65 | ||
8987fec0 CC |
66 | #ifdef CONFIG_X86 |
67 | static unsigned int i8042_dritek; | |
68 | module_param_named(dritek, i8042_dritek, bool, 0); | |
69 | MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); | |
70 | #endif | |
71 | ||
1da177e4 LT |
72 | #ifdef CONFIG_PNP |
73 | static int i8042_nopnp; | |
74 | module_param_named(nopnp, i8042_nopnp, bool, 0); | |
75 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
76 | #endif | |
77 | ||
78 | #define DEBUG | |
79 | #ifdef DEBUG | |
80 | static int i8042_debug; | |
81 | module_param_named(debug, i8042_debug, bool, 0600); | |
82 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
83 | #endif | |
84 | ||
1da177e4 LT |
85 | #include "i8042.h" |
86 | ||
87 | static DEFINE_SPINLOCK(i8042_lock); | |
88 | ||
89 | struct i8042_port { | |
90 | struct serio *serio; | |
91 | int irq; | |
1da177e4 LT |
92 | unsigned char exists; |
93 | signed char mux; | |
1da177e4 LT |
94 | }; |
95 | ||
96 | #define I8042_KBD_PORT_NO 0 | |
97 | #define I8042_AUX_PORT_NO 1 | |
98 | #define I8042_MUX_PORT_NO 2 | |
99 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
100 | |
101 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
102 | |
103 | static unsigned char i8042_initial_ctr; | |
104 | static unsigned char i8042_ctr; | |
1da177e4 | 105 | static unsigned char i8042_mux_present; |
de9ce703 DT |
106 | static unsigned char i8042_kbd_irq_registered; |
107 | static unsigned char i8042_aux_irq_registered; | |
817e6ba3 | 108 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 LT |
109 | static struct platform_device *i8042_platform_device; |
110 | ||
7d12e780 | 111 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
1da177e4 LT |
112 | |
113 | /* | |
114 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
115 | * be ready for reading values from it / writing values to it. | |
116 | * Called always with i8042_lock held. | |
117 | */ | |
118 | ||
119 | static int i8042_wait_read(void) | |
120 | { | |
121 | int i = 0; | |
de9ce703 | 122 | |
1da177e4 LT |
123 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
124 | udelay(50); | |
125 | i++; | |
126 | } | |
127 | return -(i == I8042_CTL_TIMEOUT); | |
128 | } | |
129 | ||
130 | static int i8042_wait_write(void) | |
131 | { | |
132 | int i = 0; | |
de9ce703 | 133 | |
1da177e4 LT |
134 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
135 | udelay(50); | |
136 | i++; | |
137 | } | |
138 | return -(i == I8042_CTL_TIMEOUT); | |
139 | } | |
140 | ||
141 | /* | |
142 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
143 | * of the i8042 down the toilet. | |
144 | */ | |
145 | ||
146 | static int i8042_flush(void) | |
147 | { | |
148 | unsigned long flags; | |
149 | unsigned char data, str; | |
150 | int i = 0; | |
151 | ||
152 | spin_lock_irqsave(&i8042_lock, flags); | |
153 | ||
154 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
155 | udelay(50); | |
156 | data = i8042_read_data(); | |
157 | i++; | |
158 | dbg("%02x <- i8042 (flush, %s)", data, | |
159 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
160 | } | |
161 | ||
162 | spin_unlock_irqrestore(&i8042_lock, flags); | |
163 | ||
164 | return i; | |
165 | } | |
166 | ||
167 | /* | |
168 | * i8042_command() executes a command on the i8042. It also sends the input | |
169 | * parameter(s) of the commands to it, and receives the output value(s). The | |
170 | * parameters are to be stored in the param array, and the output is placed | |
171 | * into the same array. The number of the parameters and output values is | |
172 | * encoded in bits 8-11 of the command number. | |
173 | */ | |
174 | ||
de9ce703 | 175 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 176 | { |
de9ce703 | 177 | int i, error; |
1da177e4 LT |
178 | |
179 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
180 | return -1; | |
181 | ||
de9ce703 DT |
182 | error = i8042_wait_write(); |
183 | if (error) | |
184 | return error; | |
463a4f76 DT |
185 | |
186 | dbg("%02x -> i8042 (command)", command & 0xff); | |
187 | i8042_write_command(command & 0xff); | |
188 | ||
189 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 DT |
190 | error = i8042_wait_write(); |
191 | if (error) | |
192 | return error; | |
463a4f76 DT |
193 | dbg("%02x -> i8042 (parameter)", param[i]); |
194 | i8042_write_data(param[i]); | |
1da177e4 LT |
195 | } |
196 | ||
463a4f76 | 197 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
198 | error = i8042_wait_read(); |
199 | if (error) { | |
200 | dbg(" -- i8042 (timeout)"); | |
201 | return error; | |
202 | } | |
1da177e4 | 203 | |
463a4f76 DT |
204 | if (command == I8042_CMD_AUX_LOOP && |
205 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
de9ce703 DT |
206 | dbg(" -- i8042 (auxerr)"); |
207 | return -1; | |
1da177e4 LT |
208 | } |
209 | ||
463a4f76 DT |
210 | param[i] = i8042_read_data(); |
211 | dbg("%02x <- i8042 (return)", param[i]); | |
212 | } | |
1da177e4 | 213 | |
de9ce703 DT |
214 | return 0; |
215 | } | |
1da177e4 | 216 | |
553a05b8 | 217 | int i8042_command(unsigned char *param, int command) |
de9ce703 DT |
218 | { |
219 | unsigned long flags; | |
220 | int retval; | |
221 | ||
222 | spin_lock_irqsave(&i8042_lock, flags); | |
223 | retval = __i8042_command(param, command); | |
463a4f76 | 224 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 225 | |
1da177e4 LT |
226 | return retval; |
227 | } | |
553a05b8 | 228 | EXPORT_SYMBOL(i8042_command); |
1da177e4 LT |
229 | |
230 | /* | |
231 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
232 | */ | |
233 | ||
234 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
235 | { | |
236 | unsigned long flags; | |
237 | int retval = 0; | |
238 | ||
239 | spin_lock_irqsave(&i8042_lock, flags); | |
240 | ||
de9ce703 | 241 | if (!(retval = i8042_wait_write())) { |
1da177e4 LT |
242 | dbg("%02x -> i8042 (kbd-data)", c); |
243 | i8042_write_data(c); | |
244 | } | |
245 | ||
246 | spin_unlock_irqrestore(&i8042_lock, flags); | |
247 | ||
248 | return retval; | |
249 | } | |
250 | ||
251 | /* | |
252 | * i8042_aux_write() sends a byte out through the aux interface. | |
253 | */ | |
254 | ||
255 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
256 | { | |
257 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 258 | |
f4e3c711 DT |
259 | return i8042_command(&c, port->mux == -1 ? |
260 | I8042_CMD_AUX_SEND : | |
261 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
262 | } |
263 | ||
1da177e4 LT |
264 | /* |
265 | * i8042_start() is called by serio core when port is about to finish | |
266 | * registering. It will mark port as existing so i8042_interrupt can | |
267 | * start sending data through it. | |
268 | */ | |
269 | static int i8042_start(struct serio *serio) | |
270 | { | |
271 | struct i8042_port *port = serio->port_data; | |
272 | ||
273 | port->exists = 1; | |
274 | mb(); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /* | |
279 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
280 | * will not try to send data to the port that is about to go away. | |
281 | * The function is called by serio core as part of unregister procedure. | |
282 | */ | |
283 | static void i8042_stop(struct serio *serio) | |
284 | { | |
285 | struct i8042_port *port = serio->port_data; | |
286 | ||
287 | port->exists = 0; | |
a8399c51 DT |
288 | |
289 | /* | |
290 | * We synchronize with both AUX and KBD IRQs because there is | |
291 | * a (very unlikely) chance that AUX IRQ is raised for KBD port | |
292 | * and vice versa. | |
293 | */ | |
294 | synchronize_irq(I8042_AUX_IRQ); | |
295 | synchronize_irq(I8042_KBD_IRQ); | |
1da177e4 LT |
296 | port->serio = NULL; |
297 | } | |
298 | ||
299 | /* | |
300 | * i8042_interrupt() is the most important function in this driver - | |
301 | * it handles the interrupts from the i8042, and sends incoming bytes | |
302 | * to the upper layers. | |
303 | */ | |
304 | ||
7d12e780 | 305 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
306 | { |
307 | struct i8042_port *port; | |
308 | unsigned long flags; | |
309 | unsigned char str, data; | |
310 | unsigned int dfl; | |
311 | unsigned int port_no; | |
817e6ba3 | 312 | int ret = 1; |
1da177e4 | 313 | |
1da177e4 LT |
314 | spin_lock_irqsave(&i8042_lock, flags); |
315 | str = i8042_read_status(); | |
316 | if (unlikely(~str & I8042_STR_OBF)) { | |
317 | spin_unlock_irqrestore(&i8042_lock, flags); | |
318 | if (irq) dbg("Interrupt %d, without any data", irq); | |
319 | ret = 0; | |
320 | goto out; | |
321 | } | |
322 | data = i8042_read_data(); | |
323 | spin_unlock_irqrestore(&i8042_lock, flags); | |
324 | ||
325 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
326 | static unsigned long last_transmit; | |
327 | static unsigned char last_str; | |
328 | ||
329 | dfl = 0; | |
330 | if (str & I8042_STR_MUXERR) { | |
331 | dbg("MUX error, status is %02x, data is %02x", str, data); | |
1da177e4 LT |
332 | /* |
333 | * When MUXERR condition is signalled the data register can only contain | |
334 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
335 | * it is not always the case. Some KBCs also report 0xfc when there is |
336 | * nothing connected to the port while others sometimes get confused which | |
337 | * port the data came from and signal error leaving the data intact. They | |
338 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
339 | * to legacy mode yet, when we see one we'll add proper handling). | |
340 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
341 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
342 | * was transmitted (if transmission happened not too long ago). |
343 | */ | |
a216a4b6 DT |
344 | |
345 | switch (data) { | |
346 | default: | |
1da177e4 LT |
347 | if (time_before(jiffies, last_transmit + HZ/10)) { |
348 | str = last_str; | |
349 | break; | |
350 | } | |
351 | /* fall through - report timeout */ | |
a216a4b6 | 352 | case 0xfc: |
1da177e4 LT |
353 | case 0xfd: |
354 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
355 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
356 | } | |
357 | } | |
358 | ||
359 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
360 | last_str = str; | |
361 | last_transmit = jiffies; | |
362 | } else { | |
363 | ||
364 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
365 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
366 | ||
367 | port_no = (str & I8042_STR_AUXDATA) ? | |
368 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
369 | } | |
370 | ||
371 | port = &i8042_ports[port_no]; | |
372 | ||
de9ce703 DT |
373 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", |
374 | data, port_no, irq, | |
1da177e4 LT |
375 | dfl & SERIO_PARITY ? ", bad parity" : "", |
376 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
377 | ||
817e6ba3 DT |
378 | if (unlikely(i8042_suppress_kbd_ack)) |
379 | if (port_no == I8042_KBD_PORT_NO && | |
380 | (data == 0xfa || data == 0xfe)) { | |
19f3c3e3 | 381 | i8042_suppress_kbd_ack--; |
817e6ba3 DT |
382 | goto out; |
383 | } | |
384 | ||
1da177e4 | 385 | if (likely(port->exists)) |
7d12e780 | 386 | serio_interrupt(port->serio, data, dfl); |
1da177e4 | 387 | |
0854e52d | 388 | out: |
1da177e4 LT |
389 | return IRQ_RETVAL(ret); |
390 | } | |
391 | ||
de9ce703 DT |
392 | /* |
393 | * i8042_enable_kbd_port enables keybaord port on chip | |
394 | */ | |
395 | ||
396 | static int i8042_enable_kbd_port(void) | |
397 | { | |
398 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
399 | i8042_ctr |= I8042_CTR_KBDINT; | |
400 | ||
401 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
402 | i8042_ctr &= ~I8042_CTR_KBDINT; |
403 | i8042_ctr |= I8042_CTR_KBDDIS; | |
de9ce703 DT |
404 | printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); |
405 | return -EIO; | |
406 | } | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | /* | |
412 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
413 | */ | |
414 | ||
415 | static int i8042_enable_aux_port(void) | |
416 | { | |
417 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
418 | i8042_ctr |= I8042_CTR_AUXINT; | |
419 | ||
420 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
421 | i8042_ctr &= ~I8042_CTR_AUXINT; |
422 | i8042_ctr |= I8042_CTR_AUXDIS; | |
de9ce703 DT |
423 | printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); |
424 | return -EIO; | |
425 | } | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | /* | |
431 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
432 | * the controller has been switched into Multiplexed mode | |
433 | */ | |
434 | ||
435 | static int i8042_enable_mux_ports(void) | |
436 | { | |
437 | unsigned char param; | |
438 | int i; | |
439 | ||
440 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
441 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
442 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
443 | } | |
444 | ||
445 | return i8042_enable_aux_port(); | |
446 | } | |
447 | ||
1da177e4 LT |
448 | /* |
449 | * i8042_set_mux_mode checks whether the controller has an active | |
450 | * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode. | |
451 | */ | |
452 | ||
453 | static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version) | |
454 | { | |
455 | ||
456 | unsigned char param; | |
457 | /* | |
458 | * Get rid of bytes in the queue. | |
459 | */ | |
460 | ||
461 | i8042_flush(); | |
462 | ||
463 | /* | |
464 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 465 | * mouse interface, the last should be version. |
1da177e4 LT |
466 | */ |
467 | ||
468 | param = 0xf0; | |
463a4f76 | 469 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xf0) |
1da177e4 LT |
470 | return -1; |
471 | param = mode ? 0x56 : 0xf6; | |
463a4f76 | 472 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6)) |
1da177e4 LT |
473 | return -1; |
474 | param = mode ? 0xa4 : 0xa5; | |
463a4f76 | 475 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5)) |
1da177e4 LT |
476 | return -1; |
477 | ||
478 | if (mux_version) | |
463a4f76 | 479 | *mux_version = param; |
1da177e4 LT |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
1da177e4 | 484 | /* |
de9ce703 DT |
485 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
486 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
487 | * LCS/Telegraphics. | |
1da177e4 LT |
488 | */ |
489 | ||
de9ce703 | 490 | static int __devinit i8042_check_mux(void) |
1da177e4 | 491 | { |
de9ce703 DT |
492 | unsigned char mux_version; |
493 | ||
494 | if (i8042_set_mux_mode(1, &mux_version)) | |
495 | return -1; | |
496 | ||
1da177e4 | 497 | /* |
de9ce703 DT |
498 | * Workaround for interference with USB Legacy emulation |
499 | * that causes a v10.12 MUX to be found. | |
1da177e4 | 500 | */ |
de9ce703 DT |
501 | if (mux_version == 0xAC) |
502 | return -1; | |
503 | ||
504 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | |
505 | (mux_version >> 4) & 0xf, mux_version & 0xf); | |
1da177e4 | 506 | |
de9ce703 DT |
507 | /* |
508 | * Disable all muxed ports by disabling AUX. | |
509 | */ | |
1da177e4 LT |
510 | i8042_ctr |= I8042_CTR_AUXDIS; |
511 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
512 | ||
513 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
514 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | |
de9ce703 | 515 | return -EIO; |
1da177e4 LT |
516 | } |
517 | ||
de9ce703 | 518 | i8042_mux_present = 1; |
1da177e4 LT |
519 | |
520 | return 0; | |
521 | } | |
522 | ||
1da177e4 | 523 | /* |
de9ce703 | 524 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 525 | */ |
de9ce703 DT |
526 | static struct completion i8042_aux_irq_delivered __devinitdata; |
527 | static int i8042_irq_being_tested __devinitdata; | |
1da177e4 | 528 | |
7d12e780 | 529 | static irqreturn_t __devinit i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 530 | { |
de9ce703 DT |
531 | unsigned long flags; |
532 | unsigned char str, data; | |
e3758b2a | 533 | int ret = 0; |
1da177e4 | 534 | |
de9ce703 DT |
535 | spin_lock_irqsave(&i8042_lock, flags); |
536 | str = i8042_read_status(); | |
537 | if (str & I8042_STR_OBF) { | |
538 | data = i8042_read_data(); | |
539 | if (i8042_irq_being_tested && | |
540 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
541 | complete(&i8042_aux_irq_delivered); | |
e3758b2a | 542 | ret = 1; |
de9ce703 DT |
543 | } |
544 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 545 | |
e3758b2a | 546 | return IRQ_RETVAL(ret); |
1da177e4 LT |
547 | } |
548 | ||
d2ada559 RS |
549 | /* |
550 | * i8042_toggle_aux - enables or disables AUX port on i8042 via command and | |
551 | * verifies success by readinng CTR. Used when testing for presence of AUX | |
552 | * port. | |
553 | */ | |
554 | static int __devinit i8042_toggle_aux(int on) | |
555 | { | |
556 | unsigned char param; | |
557 | int i; | |
558 | ||
559 | if (i8042_command(¶m, | |
560 | on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) | |
561 | return -1; | |
562 | ||
563 | /* some chips need some time to set the I8042_CTR_AUXDIS bit */ | |
564 | for (i = 0; i < 100; i++) { | |
565 | udelay(50); | |
566 | ||
567 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) | |
568 | return -1; | |
569 | ||
570 | if (!(param & I8042_CTR_AUXDIS) == on) | |
571 | return 0; | |
572 | } | |
573 | ||
574 | return -1; | |
575 | } | |
1da177e4 LT |
576 | |
577 | /* | |
578 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
579 | * the presence of an AUX interface. | |
580 | */ | |
581 | ||
87fd6318 | 582 | static int __devinit i8042_check_aux(void) |
1da177e4 | 583 | { |
de9ce703 DT |
584 | int retval = -1; |
585 | int irq_registered = 0; | |
1e4865f8 | 586 | int aux_loop_broken = 0; |
de9ce703 | 587 | unsigned long flags; |
1da177e4 | 588 | unsigned char param; |
1da177e4 LT |
589 | |
590 | /* | |
591 | * Get rid of bytes in the queue. | |
592 | */ | |
593 | ||
594 | i8042_flush(); | |
595 | ||
596 | /* | |
597 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
598 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
599 | * though it has an AUX port. | |
600 | */ | |
601 | ||
602 | param = 0x5a; | |
3ca5de6d DT |
603 | retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); |
604 | if (retval || param != 0x5a) { | |
1da177e4 LT |
605 | |
606 | /* | |
607 | * External connection test - filters out AT-soldered PS/2 i8042's | |
608 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
609 | * 0xfa - no error on some notebooks which ignore the spec | |
610 | * Because it's common for chipsets to return error on perfectly functioning | |
611 | * AUX ports, we test for this only when the LOOP command failed. | |
612 | */ | |
613 | ||
de9ce703 DT |
614 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
615 | (param && param != 0xfa && param != 0xff)) | |
616 | return -1; | |
1e4865f8 | 617 | |
3ca5de6d DT |
618 | /* |
619 | * If AUX_LOOP completed without error but returned unexpected data | |
620 | * mark it as broken | |
621 | */ | |
622 | if (!retval) | |
623 | aux_loop_broken = 1; | |
1da177e4 LT |
624 | } |
625 | ||
626 | /* | |
627 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
628 | */ | |
629 | ||
d2ada559 | 630 | if (i8042_toggle_aux(0)) { |
1da177e4 LT |
631 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
632 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | |
633 | } | |
634 | ||
d2ada559 | 635 | if (i8042_toggle_aux(1)) |
1da177e4 LT |
636 | return -1; |
637 | ||
638 | /* | |
de9ce703 DT |
639 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
640 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
641 | */ |
642 | ||
1e4865f8 | 643 | if (i8042_noloop || aux_loop_broken) { |
de9ce703 DT |
644 | /* |
645 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
646 | * is working and hope we are right. | |
647 | */ | |
648 | retval = 0; | |
649 | goto out; | |
650 | } | |
1da177e4 | 651 | |
de9ce703 DT |
652 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
653 | "i8042", i8042_platform_device)) | |
654 | goto out; | |
1da177e4 | 655 | |
de9ce703 DT |
656 | irq_registered = 1; |
657 | ||
658 | if (i8042_enable_aux_port()) | |
659 | goto out; | |
660 | ||
661 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 662 | |
de9ce703 DT |
663 | init_completion(&i8042_aux_irq_delivered); |
664 | i8042_irq_being_tested = 1; | |
665 | ||
666 | param = 0xa5; | |
667 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
668 | ||
669 | spin_unlock_irqrestore(&i8042_lock, flags); | |
670 | ||
671 | if (retval) | |
672 | goto out; | |
1da177e4 | 673 | |
de9ce703 DT |
674 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
675 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 676 | /* |
de9ce703 DT |
677 | * AUX IRQ was never delivered so we need to flush the controller to |
678 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 679 | */ |
de9ce703 DT |
680 | i8042_flush(); |
681 | retval = -1; | |
682 | } | |
1da177e4 | 683 | |
de9ce703 | 684 | out: |
1da177e4 | 685 | |
de9ce703 DT |
686 | /* |
687 | * Disable the interface. | |
688 | */ | |
1da177e4 | 689 | |
de9ce703 DT |
690 | i8042_ctr |= I8042_CTR_AUXDIS; |
691 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 692 | |
de9ce703 DT |
693 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
694 | retval = -1; | |
1da177e4 | 695 | |
de9ce703 DT |
696 | if (irq_registered) |
697 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 698 | |
de9ce703 DT |
699 | return retval; |
700 | } | |
1da177e4 | 701 | |
de9ce703 | 702 | static int i8042_controller_check(void) |
1da177e4 | 703 | { |
de9ce703 DT |
704 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
705 | printk(KERN_ERR "i8042.c: No controller found.\n"); | |
706 | return -ENODEV; | |
707 | } | |
708 | ||
709 | return 0; | |
1da177e4 LT |
710 | } |
711 | ||
de9ce703 | 712 | static int i8042_controller_selftest(void) |
2673c836 VP |
713 | { |
714 | unsigned char param; | |
715 | ||
716 | if (!i8042_reset) | |
717 | return 0; | |
718 | ||
719 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
720 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | |
de9ce703 | 721 | return -ENODEV; |
2673c836 VP |
722 | } |
723 | ||
724 | if (param != I8042_RET_CTL_TEST) { | |
725 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | |
726 | param, I8042_RET_CTL_TEST); | |
de9ce703 | 727 | return -EIO; |
2673c836 VP |
728 | } |
729 | ||
730 | return 0; | |
731 | } | |
1da177e4 LT |
732 | |
733 | /* | |
734 | * i8042_controller init initializes the i8042 controller, and, | |
735 | * most importantly, sets it into non-xlated mode if that's | |
736 | * desired. | |
737 | */ | |
738 | ||
739 | static int i8042_controller_init(void) | |
740 | { | |
741 | unsigned long flags; | |
742 | ||
1da177e4 LT |
743 | /* |
744 | * Save the CTR for restoral on unload / reboot. | |
745 | */ | |
746 | ||
747 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { | |
748 | printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); | |
de9ce703 | 749 | return -EIO; |
1da177e4 LT |
750 | } |
751 | ||
752 | i8042_initial_ctr = i8042_ctr; | |
753 | ||
754 | /* | |
755 | * Disable the keyboard interface and interrupt. | |
756 | */ | |
757 | ||
758 | i8042_ctr |= I8042_CTR_KBDDIS; | |
759 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
760 | ||
761 | /* | |
762 | * Handle keylock. | |
763 | */ | |
764 | ||
765 | spin_lock_irqsave(&i8042_lock, flags); | |
766 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
767 | if (i8042_unlock) | |
768 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
82dd9eff | 769 | else |
1da177e4 LT |
770 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); |
771 | } | |
772 | spin_unlock_irqrestore(&i8042_lock, flags); | |
773 | ||
774 | /* | |
775 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
776 | * bother enabling translating and be happy. | |
777 | */ | |
778 | ||
779 | if (~i8042_ctr & I8042_CTR_XLATE) | |
780 | i8042_direct = 1; | |
781 | ||
782 | /* | |
783 | * Set nontranslated mode for the kbd interface if requested by an option. | |
784 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
785 | * interface is. We don't do this by default, since it can confuse notebook | |
786 | * BIOSes. | |
787 | */ | |
788 | ||
789 | if (i8042_direct) | |
790 | i8042_ctr &= ~I8042_CTR_XLATE; | |
791 | ||
792 | /* | |
793 | * Write CTR back. | |
794 | */ | |
795 | ||
796 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
797 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | |
de9ce703 | 798 | return -EIO; |
1da177e4 LT |
799 | } |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | ||
805 | /* | |
de9ce703 | 806 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 807 | */ |
de9ce703 | 808 | |
1da177e4 LT |
809 | static void i8042_controller_reset(void) |
810 | { | |
de9ce703 | 811 | i8042_flush(); |
1da177e4 | 812 | |
8d04ddb6 DT |
813 | /* |
814 | * Disable both KBD and AUX interfaces so they don't get in the way | |
815 | */ | |
816 | ||
817 | i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; | |
818 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | |
819 | ||
1da177e4 LT |
820 | /* |
821 | * Disable MUX mode if present. | |
822 | */ | |
823 | ||
824 | if (i8042_mux_present) | |
825 | i8042_set_mux_mode(0, NULL); | |
826 | ||
827 | /* | |
de9ce703 | 828 | * Reset the controller if requested. |
1da177e4 LT |
829 | */ |
830 | ||
de9ce703 | 831 | i8042_controller_selftest(); |
1da177e4 | 832 | |
de9ce703 DT |
833 | /* |
834 | * Restore the original control register setting. | |
835 | */ | |
836 | ||
837 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
1da177e4 LT |
838 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); |
839 | } | |
840 | ||
841 | ||
1da177e4 LT |
842 | /* |
843 | * i8042_panic_blink() will flash the keyboard LEDs and is called when | |
844 | * kernel panics. Flashing LEDs is useful for users running X who may | |
845 | * not see the console and will help distingushing panics from "real" | |
846 | * lockups. | |
847 | * | |
848 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
849 | * waiting for KBC to free up even if KBD interrupt is off | |
850 | */ | |
851 | ||
852 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
853 | ||
854 | static long i8042_panic_blink(long count) | |
855 | { | |
856 | long delay = 0; | |
857 | static long last_blink; | |
858 | static char led; | |
859 | ||
860 | /* | |
861 | * We expect frequency to be about 1/2s. KDB uses about 1s. | |
862 | * Make sure they are different. | |
863 | */ | |
864 | if (!i8042_blink_frequency) | |
865 | return 0; | |
866 | if (count - last_blink < i8042_blink_frequency) | |
867 | return 0; | |
868 | ||
869 | led ^= 0x01 | 0x04; | |
870 | while (i8042_read_status() & I8042_STR_IBF) | |
871 | DELAY; | |
19f3c3e3 DT |
872 | dbg("%02x -> i8042 (panic blink)", 0xed); |
873 | i8042_suppress_kbd_ack = 2; | |
1da177e4 LT |
874 | i8042_write_data(0xed); /* set leds */ |
875 | DELAY; | |
876 | while (i8042_read_status() & I8042_STR_IBF) | |
877 | DELAY; | |
878 | DELAY; | |
19f3c3e3 | 879 | dbg("%02x -> i8042 (panic blink)", led); |
1da177e4 LT |
880 | i8042_write_data(led); |
881 | DELAY; | |
882 | last_blink = count; | |
883 | return delay; | |
884 | } | |
885 | ||
886 | #undef DELAY | |
887 | ||
d35895db BP |
888 | #ifdef CONFIG_X86 |
889 | static void i8042_dritek_enable(void) | |
890 | { | |
891 | char param = 0x90; | |
892 | int error; | |
893 | ||
894 | error = i8042_command(¶m, 0x1059); | |
895 | if (error) | |
896 | printk(KERN_WARNING | |
897 | "Failed to enable DRITEK extension: %d\n", | |
898 | error); | |
899 | } | |
900 | #endif | |
901 | ||
82dd9eff | 902 | #ifdef CONFIG_PM |
1da177e4 | 903 | /* |
82dd9eff DT |
904 | * Here we try to restore the original BIOS settings. We only want to |
905 | * do that once, when we really suspend, not when we taking memory | |
906 | * snapshot for swsusp (in this case we'll perform required cleanup | |
907 | * as part of shutdown process). | |
1da177e4 LT |
908 | */ |
909 | ||
3ae5eaec | 910 | static int i8042_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 911 | { |
82dd9eff DT |
912 | if (dev->dev.power.power_state.event != state.event) { |
913 | if (state.event == PM_EVENT_SUSPEND) | |
914 | i8042_controller_reset(); | |
915 | ||
916 | dev->dev.power.power_state = state; | |
917 | } | |
1da177e4 LT |
918 | |
919 | return 0; | |
920 | } | |
921 | ||
922 | ||
923 | /* | |
924 | * Here we try to reset everything back to a state in which suspended | |
925 | */ | |
926 | ||
3ae5eaec | 927 | static int i8042_resume(struct platform_device *dev) |
1da177e4 | 928 | { |
de9ce703 | 929 | int error; |
1da177e4 | 930 | |
82dd9eff DT |
931 | /* |
932 | * Do not bother with restoring state if we haven't suspened yet | |
933 | */ | |
934 | if (dev->dev.power.power_state.event == PM_EVENT_ON) | |
935 | return 0; | |
936 | ||
de9ce703 DT |
937 | error = i8042_controller_check(); |
938 | if (error) | |
939 | return error; | |
2673c836 | 940 | |
de9ce703 DT |
941 | error = i8042_controller_selftest(); |
942 | if (error) | |
943 | return error; | |
1da177e4 LT |
944 | |
945 | /* | |
82dd9eff | 946 | * Restore original CTR value and disable all ports |
1da177e4 LT |
947 | */ |
948 | ||
82dd9eff DT |
949 | i8042_ctr = i8042_initial_ctr; |
950 | if (i8042_direct) | |
951 | i8042_ctr &= ~I8042_CTR_XLATE; | |
de9ce703 DT |
952 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
953 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
954 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
2f6a77d5 JK |
955 | printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); |
956 | msleep(50); | |
957 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
958 | printk(KERN_ERR "i8042: CTR write retry failed\n"); | |
959 | return -EIO; | |
960 | } | |
de9ce703 | 961 | } |
1da177e4 | 962 | |
d35895db BP |
963 | |
964 | #ifdef CONFIG_X86 | |
965 | if (i8042_dritek) | |
966 | i8042_dritek_enable(); | |
967 | #endif | |
968 | ||
de9ce703 DT |
969 | if (i8042_mux_present) { |
970 | if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports()) | |
971 | printk(KERN_WARNING | |
972 | "i8042: failed to resume active multiplexor, " | |
973 | "mouse won't work.\n"); | |
974 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) | |
975 | i8042_enable_aux_port(); | |
1da177e4 | 976 | |
de9ce703 DT |
977 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
978 | i8042_enable_kbd_port(); | |
979 | ||
7d12e780 | 980 | i8042_interrupt(0, NULL); |
1da177e4 | 981 | |
82dd9eff DT |
982 | dev->dev.power.power_state = PMSG_ON; |
983 | ||
1da177e4 | 984 | return 0; |
1da177e4 | 985 | } |
82dd9eff | 986 | #endif /* CONFIG_PM */ |
1da177e4 LT |
987 | |
988 | /* | |
989 | * We need to reset the 8042 back to original mode on system shutdown, | |
990 | * because otherwise BIOSes will be confused. | |
991 | */ | |
992 | ||
3ae5eaec | 993 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 | 994 | { |
82dd9eff | 995 | i8042_controller_reset(); |
1da177e4 LT |
996 | } |
997 | ||
87fd6318 | 998 | static int __devinit i8042_create_kbd_port(void) |
1da177e4 LT |
999 | { |
1000 | struct serio *serio; | |
1001 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
1002 | ||
d39969de | 1003 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1004 | if (!serio) |
1005 | return -ENOMEM; | |
1006 | ||
1007 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
1008 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
1009 | serio->start = i8042_start; |
1010 | serio->stop = i8042_stop; | |
1011 | serio->port_data = port; | |
1012 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 1013 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d DT |
1014 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
1015 | ||
1016 | port->serio = serio; | |
de9ce703 | 1017 | port->irq = I8042_KBD_IRQ; |
0854e52d | 1018 | |
de9ce703 | 1019 | return 0; |
1da177e4 LT |
1020 | } |
1021 | ||
de9ce703 | 1022 | static int __devinit i8042_create_aux_port(int idx) |
1da177e4 LT |
1023 | { |
1024 | struct serio *serio; | |
de9ce703 DT |
1025 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
1026 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 1027 | |
d39969de | 1028 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1029 | if (!serio) |
1030 | return -ENOMEM; | |
1031 | ||
1032 | serio->id.type = SERIO_8042; | |
1033 | serio->write = i8042_aux_write; | |
0854e52d DT |
1034 | serio->start = i8042_start; |
1035 | serio->stop = i8042_stop; | |
1036 | serio->port_data = port; | |
1037 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
1038 | if (idx < 0) { |
1039 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
1040 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
1041 | } else { | |
1042 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
1043 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
1044 | } | |
0854e52d DT |
1045 | |
1046 | port->serio = serio; | |
de9ce703 DT |
1047 | port->mux = idx; |
1048 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 1049 | |
de9ce703 | 1050 | return 0; |
1da177e4 LT |
1051 | } |
1052 | ||
de9ce703 | 1053 | static void __devinit i8042_free_kbd_port(void) |
1da177e4 | 1054 | { |
de9ce703 DT |
1055 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
1056 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
1057 | } | |
1da177e4 | 1058 | |
de9ce703 DT |
1059 | static void __devinit i8042_free_aux_ports(void) |
1060 | { | |
1061 | int i; | |
0854e52d | 1062 | |
de9ce703 DT |
1063 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
1064 | kfree(i8042_ports[i].serio); | |
1065 | i8042_ports[i].serio = NULL; | |
1066 | } | |
1067 | } | |
0854e52d | 1068 | |
de9ce703 DT |
1069 | static void __devinit i8042_register_ports(void) |
1070 | { | |
1071 | int i; | |
0854e52d | 1072 | |
de9ce703 DT |
1073 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1074 | if (i8042_ports[i].serio) { | |
1075 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", | |
1076 | i8042_ports[i].serio->name, | |
1077 | (unsigned long) I8042_DATA_REG, | |
1078 | (unsigned long) I8042_COMMAND_REG, | |
1079 | i8042_ports[i].irq); | |
1080 | serio_register_port(i8042_ports[i].serio); | |
1081 | } | |
1082 | } | |
1da177e4 LT |
1083 | } |
1084 | ||
7a1904c3 | 1085 | static void __devexit i8042_unregister_ports(void) |
1da177e4 | 1086 | { |
de9ce703 | 1087 | int i; |
1da177e4 | 1088 | |
de9ce703 DT |
1089 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1090 | if (i8042_ports[i].serio) { | |
1091 | serio_unregister_port(i8042_ports[i].serio); | |
1092 | i8042_ports[i].serio = NULL; | |
1093 | } | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | static void i8042_free_irqs(void) | |
1098 | { | |
1099 | if (i8042_aux_irq_registered) | |
1100 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1101 | if (i8042_kbd_irq_registered) | |
1102 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1103 | ||
1104 | i8042_aux_irq_registered = i8042_kbd_irq_registered = 0; | |
1105 | } | |
1106 | ||
1107 | static int __devinit i8042_setup_aux(void) | |
1108 | { | |
1109 | int (*aux_enable)(void); | |
1110 | int error; | |
1111 | int i; | |
1da177e4 | 1112 | |
de9ce703 | 1113 | if (i8042_check_aux()) |
87fd6318 | 1114 | return -ENODEV; |
1da177e4 | 1115 | |
de9ce703 DT |
1116 | if (i8042_nomux || i8042_check_mux()) { |
1117 | error = i8042_create_aux_port(-1); | |
1118 | if (error) | |
1119 | goto err_free_ports; | |
1120 | aux_enable = i8042_enable_aux_port; | |
1121 | } else { | |
1122 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1123 | error = i8042_create_aux_port(i); | |
1124 | if (error) | |
1125 | goto err_free_ports; | |
0854e52d | 1126 | } |
de9ce703 | 1127 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1128 | } |
1129 | ||
de9ce703 DT |
1130 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1131 | "i8042", i8042_platform_device); | |
1132 | if (error) | |
1133 | goto err_free_ports; | |
945ef0d4 | 1134 | |
de9ce703 DT |
1135 | if (aux_enable()) |
1136 | goto err_free_irq; | |
1da177e4 | 1137 | |
de9ce703 | 1138 | i8042_aux_irq_registered = 1; |
1da177e4 | 1139 | return 0; |
0854e52d | 1140 | |
de9ce703 DT |
1141 | err_free_irq: |
1142 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1143 | err_free_ports: | |
1144 | i8042_free_aux_ports(); | |
1145 | return error; | |
1146 | } | |
0854e52d | 1147 | |
de9ce703 DT |
1148 | static int __devinit i8042_setup_kbd(void) |
1149 | { | |
1150 | int error; | |
1151 | ||
1152 | error = i8042_create_kbd_port(); | |
1153 | if (error) | |
1154 | return error; | |
1155 | ||
1156 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1157 | "i8042", i8042_platform_device); | |
1158 | if (error) | |
1159 | goto err_free_port; | |
1160 | ||
1161 | error = i8042_enable_kbd_port(); | |
1162 | if (error) | |
1163 | goto err_free_irq; | |
1164 | ||
1165 | i8042_kbd_irq_registered = 1; | |
1166 | return 0; | |
1167 | ||
1168 | err_free_irq: | |
1169 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1170 | err_free_port: | |
1171 | i8042_free_kbd_port(); | |
1172 | return error; | |
1da177e4 LT |
1173 | } |
1174 | ||
de9ce703 | 1175 | static int __devinit i8042_probe(struct platform_device *dev) |
1da177e4 | 1176 | { |
de9ce703 | 1177 | int error; |
1da177e4 | 1178 | |
de9ce703 DT |
1179 | error = i8042_controller_selftest(); |
1180 | if (error) | |
1181 | return error; | |
1da177e4 | 1182 | |
de9ce703 DT |
1183 | error = i8042_controller_init(); |
1184 | if (error) | |
1185 | return error; | |
1186 | ||
d35895db BP |
1187 | #ifdef CONFIG_X86 |
1188 | if (i8042_dritek) | |
1189 | i8042_dritek_enable(); | |
1190 | #endif | |
1191 | ||
de9ce703 DT |
1192 | if (!i8042_noaux) { |
1193 | error = i8042_setup_aux(); | |
1194 | if (error && error != -ENODEV && error != -EBUSY) | |
1195 | goto out_fail; | |
1196 | } | |
1197 | ||
1198 | if (!i8042_nokbd) { | |
1199 | error = i8042_setup_kbd(); | |
1200 | if (error) | |
1201 | goto out_fail; | |
1202 | } | |
de9ce703 DT |
1203 | /* |
1204 | * Ok, everything is ready, let's register all serio ports | |
1205 | */ | |
1206 | i8042_register_ports(); | |
1207 | ||
1208 | return 0; | |
1209 | ||
1210 | out_fail: | |
1211 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1212 | i8042_free_irqs(); | |
1213 | i8042_controller_reset(); | |
1214 | ||
1215 | return error; | |
1216 | } | |
1217 | ||
1218 | static int __devexit i8042_remove(struct platform_device *dev) | |
1219 | { | |
1220 | i8042_unregister_ports(); | |
1221 | i8042_free_irqs(); | |
1222 | i8042_controller_reset(); | |
1da177e4 | 1223 | |
87fd6318 DT |
1224 | return 0; |
1225 | } | |
1226 | ||
1227 | static struct platform_driver i8042_driver = { | |
1228 | .driver = { | |
1229 | .name = "i8042", | |
1230 | .owner = THIS_MODULE, | |
1231 | }, | |
1232 | .probe = i8042_probe, | |
1233 | .remove = __devexit_p(i8042_remove), | |
82dd9eff DT |
1234 | .shutdown = i8042_shutdown, |
1235 | #ifdef CONFIG_PM | |
87fd6318 DT |
1236 | .suspend = i8042_suspend, |
1237 | .resume = i8042_resume, | |
82dd9eff | 1238 | #endif |
87fd6318 DT |
1239 | }; |
1240 | ||
1241 | static int __init i8042_init(void) | |
1242 | { | |
1243 | int err; | |
1244 | ||
1245 | dbg_init(); | |
1246 | ||
1247 | err = i8042_platform_init(); | |
1248 | if (err) | |
1249 | return err; | |
1250 | ||
de9ce703 DT |
1251 | err = i8042_controller_check(); |
1252 | if (err) | |
1253 | goto err_platform_exit; | |
87fd6318 DT |
1254 | |
1255 | err = platform_driver_register(&i8042_driver); | |
1256 | if (err) | |
1257 | goto err_platform_exit; | |
1258 | ||
1259 | i8042_platform_device = platform_device_alloc("i8042", -1); | |
1260 | if (!i8042_platform_device) { | |
1261 | err = -ENOMEM; | |
1262 | goto err_unregister_driver; | |
1263 | } | |
1264 | ||
1265 | err = platform_device_add(i8042_platform_device); | |
1266 | if (err) | |
1267 | goto err_free_device; | |
1268 | ||
de9ce703 DT |
1269 | panic_blink = i8042_panic_blink; |
1270 | ||
87fd6318 DT |
1271 | return 0; |
1272 | ||
1273 | err_free_device: | |
1274 | platform_device_put(i8042_platform_device); | |
1275 | err_unregister_driver: | |
1276 | platform_driver_unregister(&i8042_driver); | |
1277 | err_platform_exit: | |
1278 | i8042_platform_exit(); | |
1279 | ||
1280 | return err; | |
1281 | } | |
1282 | ||
1283 | static void __exit i8042_exit(void) | |
1284 | { | |
1da177e4 | 1285 | platform_device_unregister(i8042_platform_device); |
3ae5eaec | 1286 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1287 | i8042_platform_exit(); |
1288 | ||
1289 | panic_blink = NULL; | |
1290 | } | |
1291 | ||
1292 | module_init(i8042_init); | |
1293 | module_exit(i8042_exit); |