Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ioport.h> | |
1da177e4 LT |
18 | #include <linux/init.h> |
19 | #include <linux/serio.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/rcupdate.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | |
24 | #include <asm/io.h> | |
25 | ||
26 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
27 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
28 | MODULE_LICENSE("GPL"); | |
29 | ||
945ef0d4 DT |
30 | static unsigned int i8042_nokbd; |
31 | module_param_named(nokbd, i8042_nokbd, bool, 0); | |
32 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
33 | ||
1da177e4 LT |
34 | static unsigned int i8042_noaux; |
35 | module_param_named(noaux, i8042_noaux, bool, 0); | |
36 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
37 | ||
38 | static unsigned int i8042_nomux; | |
39 | module_param_named(nomux, i8042_nomux, bool, 0); | |
40 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); | |
41 | ||
42 | static unsigned int i8042_unlock; | |
43 | module_param_named(unlock, i8042_unlock, bool, 0); | |
44 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
45 | ||
46 | static unsigned int i8042_reset; | |
47 | module_param_named(reset, i8042_reset, bool, 0); | |
48 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
49 | ||
50 | static unsigned int i8042_direct; | |
51 | module_param_named(direct, i8042_direct, bool, 0); | |
52 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
53 | ||
54 | static unsigned int i8042_dumbkbd; | |
55 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); | |
56 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
57 | ||
58 | static unsigned int i8042_noloop; | |
59 | module_param_named(noloop, i8042_noloop, bool, 0); | |
60 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
61 | ||
62 | static unsigned int i8042_blink_frequency = 500; | |
63 | module_param_named(panicblink, i8042_blink_frequency, uint, 0600); | |
64 | MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); | |
65 | ||
66 | #ifdef CONFIG_PNP | |
67 | static int i8042_nopnp; | |
68 | module_param_named(nopnp, i8042_nopnp, bool, 0); | |
69 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
70 | #endif | |
71 | ||
72 | #define DEBUG | |
73 | #ifdef DEBUG | |
74 | static int i8042_debug; | |
75 | module_param_named(debug, i8042_debug, bool, 0600); | |
76 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
77 | #endif | |
78 | ||
79 | __obsolete_setup("i8042_noaux"); | |
80 | __obsolete_setup("i8042_nomux"); | |
81 | __obsolete_setup("i8042_unlock"); | |
82 | __obsolete_setup("i8042_reset"); | |
83 | __obsolete_setup("i8042_direct"); | |
84 | __obsolete_setup("i8042_dumbkbd"); | |
85 | ||
86 | #include "i8042.h" | |
87 | ||
88 | static DEFINE_SPINLOCK(i8042_lock); | |
89 | ||
90 | struct i8042_port { | |
91 | struct serio *serio; | |
92 | int irq; | |
1da177e4 LT |
93 | unsigned char exists; |
94 | signed char mux; | |
1da177e4 LT |
95 | }; |
96 | ||
97 | #define I8042_KBD_PORT_NO 0 | |
98 | #define I8042_AUX_PORT_NO 1 | |
99 | #define I8042_MUX_PORT_NO 2 | |
100 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
101 | |
102 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
103 | |
104 | static unsigned char i8042_initial_ctr; | |
105 | static unsigned char i8042_ctr; | |
1da177e4 | 106 | static unsigned char i8042_mux_present; |
de9ce703 DT |
107 | static unsigned char i8042_kbd_irq_registered; |
108 | static unsigned char i8042_aux_irq_registered; | |
817e6ba3 | 109 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 LT |
110 | static struct platform_device *i8042_platform_device; |
111 | ||
7d12e780 | 112 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
1da177e4 LT |
113 | |
114 | /* | |
115 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
116 | * be ready for reading values from it / writing values to it. | |
117 | * Called always with i8042_lock held. | |
118 | */ | |
119 | ||
120 | static int i8042_wait_read(void) | |
121 | { | |
122 | int i = 0; | |
de9ce703 | 123 | |
1da177e4 LT |
124 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
125 | udelay(50); | |
126 | i++; | |
127 | } | |
128 | return -(i == I8042_CTL_TIMEOUT); | |
129 | } | |
130 | ||
131 | static int i8042_wait_write(void) | |
132 | { | |
133 | int i = 0; | |
de9ce703 | 134 | |
1da177e4 LT |
135 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
136 | udelay(50); | |
137 | i++; | |
138 | } | |
139 | return -(i == I8042_CTL_TIMEOUT); | |
140 | } | |
141 | ||
142 | /* | |
143 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
144 | * of the i8042 down the toilet. | |
145 | */ | |
146 | ||
147 | static int i8042_flush(void) | |
148 | { | |
149 | unsigned long flags; | |
150 | unsigned char data, str; | |
151 | int i = 0; | |
152 | ||
153 | spin_lock_irqsave(&i8042_lock, flags); | |
154 | ||
155 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
156 | udelay(50); | |
157 | data = i8042_read_data(); | |
158 | i++; | |
159 | dbg("%02x <- i8042 (flush, %s)", data, | |
160 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
161 | } | |
162 | ||
163 | spin_unlock_irqrestore(&i8042_lock, flags); | |
164 | ||
165 | return i; | |
166 | } | |
167 | ||
168 | /* | |
169 | * i8042_command() executes a command on the i8042. It also sends the input | |
170 | * parameter(s) of the commands to it, and receives the output value(s). The | |
171 | * parameters are to be stored in the param array, and the output is placed | |
172 | * into the same array. The number of the parameters and output values is | |
173 | * encoded in bits 8-11 of the command number. | |
174 | */ | |
175 | ||
de9ce703 | 176 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 177 | { |
de9ce703 | 178 | int i, error; |
1da177e4 LT |
179 | |
180 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
181 | return -1; | |
182 | ||
de9ce703 DT |
183 | error = i8042_wait_write(); |
184 | if (error) | |
185 | return error; | |
463a4f76 DT |
186 | |
187 | dbg("%02x -> i8042 (command)", command & 0xff); | |
188 | i8042_write_command(command & 0xff); | |
189 | ||
190 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 DT |
191 | error = i8042_wait_write(); |
192 | if (error) | |
193 | return error; | |
463a4f76 DT |
194 | dbg("%02x -> i8042 (parameter)", param[i]); |
195 | i8042_write_data(param[i]); | |
1da177e4 LT |
196 | } |
197 | ||
463a4f76 | 198 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
199 | error = i8042_wait_read(); |
200 | if (error) { | |
201 | dbg(" -- i8042 (timeout)"); | |
202 | return error; | |
203 | } | |
1da177e4 | 204 | |
463a4f76 DT |
205 | if (command == I8042_CMD_AUX_LOOP && |
206 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
de9ce703 DT |
207 | dbg(" -- i8042 (auxerr)"); |
208 | return -1; | |
1da177e4 LT |
209 | } |
210 | ||
463a4f76 DT |
211 | param[i] = i8042_read_data(); |
212 | dbg("%02x <- i8042 (return)", param[i]); | |
213 | } | |
1da177e4 | 214 | |
de9ce703 DT |
215 | return 0; |
216 | } | |
1da177e4 | 217 | |
de9ce703 DT |
218 | static int i8042_command(unsigned char *param, int command) |
219 | { | |
220 | unsigned long flags; | |
221 | int retval; | |
222 | ||
223 | spin_lock_irqsave(&i8042_lock, flags); | |
224 | retval = __i8042_command(param, command); | |
463a4f76 | 225 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 226 | |
1da177e4 LT |
227 | return retval; |
228 | } | |
229 | ||
230 | /* | |
231 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
232 | */ | |
233 | ||
234 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
235 | { | |
236 | unsigned long flags; | |
237 | int retval = 0; | |
238 | ||
239 | spin_lock_irqsave(&i8042_lock, flags); | |
240 | ||
de9ce703 | 241 | if (!(retval = i8042_wait_write())) { |
1da177e4 LT |
242 | dbg("%02x -> i8042 (kbd-data)", c); |
243 | i8042_write_data(c); | |
244 | } | |
245 | ||
246 | spin_unlock_irqrestore(&i8042_lock, flags); | |
247 | ||
248 | return retval; | |
249 | } | |
250 | ||
251 | /* | |
252 | * i8042_aux_write() sends a byte out through the aux interface. | |
253 | */ | |
254 | ||
255 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
256 | { | |
257 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 258 | |
f4e3c711 DT |
259 | return i8042_command(&c, port->mux == -1 ? |
260 | I8042_CMD_AUX_SEND : | |
261 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
262 | } |
263 | ||
1da177e4 LT |
264 | /* |
265 | * i8042_start() is called by serio core when port is about to finish | |
266 | * registering. It will mark port as existing so i8042_interrupt can | |
267 | * start sending data through it. | |
268 | */ | |
269 | static int i8042_start(struct serio *serio) | |
270 | { | |
271 | struct i8042_port *port = serio->port_data; | |
272 | ||
273 | port->exists = 1; | |
274 | mb(); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /* | |
279 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
280 | * will not try to send data to the port that is about to go away. | |
281 | * The function is called by serio core as part of unregister procedure. | |
282 | */ | |
283 | static void i8042_stop(struct serio *serio) | |
284 | { | |
285 | struct i8042_port *port = serio->port_data; | |
286 | ||
287 | port->exists = 0; | |
b2b18660 | 288 | synchronize_sched(); |
1da177e4 LT |
289 | port->serio = NULL; |
290 | } | |
291 | ||
292 | /* | |
293 | * i8042_interrupt() is the most important function in this driver - | |
294 | * it handles the interrupts from the i8042, and sends incoming bytes | |
295 | * to the upper layers. | |
296 | */ | |
297 | ||
7d12e780 | 298 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
299 | { |
300 | struct i8042_port *port; | |
301 | unsigned long flags; | |
302 | unsigned char str, data; | |
303 | unsigned int dfl; | |
304 | unsigned int port_no; | |
817e6ba3 | 305 | int ret = 1; |
1da177e4 | 306 | |
1da177e4 LT |
307 | spin_lock_irqsave(&i8042_lock, flags); |
308 | str = i8042_read_status(); | |
309 | if (unlikely(~str & I8042_STR_OBF)) { | |
310 | spin_unlock_irqrestore(&i8042_lock, flags); | |
311 | if (irq) dbg("Interrupt %d, without any data", irq); | |
312 | ret = 0; | |
313 | goto out; | |
314 | } | |
315 | data = i8042_read_data(); | |
316 | spin_unlock_irqrestore(&i8042_lock, flags); | |
317 | ||
318 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
319 | static unsigned long last_transmit; | |
320 | static unsigned char last_str; | |
321 | ||
322 | dfl = 0; | |
323 | if (str & I8042_STR_MUXERR) { | |
324 | dbg("MUX error, status is %02x, data is %02x", str, data); | |
1da177e4 LT |
325 | /* |
326 | * When MUXERR condition is signalled the data register can only contain | |
327 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
328 | * it is not always the case. Some KBCs also report 0xfc when there is |
329 | * nothing connected to the port while others sometimes get confused which | |
330 | * port the data came from and signal error leaving the data intact. They | |
331 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
332 | * to legacy mode yet, when we see one we'll add proper handling). | |
333 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
334 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
335 | * was transmitted (if transmission happened not too long ago). |
336 | */ | |
a216a4b6 DT |
337 | |
338 | switch (data) { | |
339 | default: | |
1da177e4 LT |
340 | if (time_before(jiffies, last_transmit + HZ/10)) { |
341 | str = last_str; | |
342 | break; | |
343 | } | |
344 | /* fall through - report timeout */ | |
a216a4b6 | 345 | case 0xfc: |
1da177e4 LT |
346 | case 0xfd: |
347 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
348 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
349 | } | |
350 | } | |
351 | ||
352 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
353 | last_str = str; | |
354 | last_transmit = jiffies; | |
355 | } else { | |
356 | ||
357 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
358 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
359 | ||
360 | port_no = (str & I8042_STR_AUXDATA) ? | |
361 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
362 | } | |
363 | ||
364 | port = &i8042_ports[port_no]; | |
365 | ||
de9ce703 DT |
366 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", |
367 | data, port_no, irq, | |
1da177e4 LT |
368 | dfl & SERIO_PARITY ? ", bad parity" : "", |
369 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
370 | ||
817e6ba3 DT |
371 | if (unlikely(i8042_suppress_kbd_ack)) |
372 | if (port_no == I8042_KBD_PORT_NO && | |
373 | (data == 0xfa || data == 0xfe)) { | |
374 | i8042_suppress_kbd_ack = 0; | |
375 | goto out; | |
376 | } | |
377 | ||
1da177e4 | 378 | if (likely(port->exists)) |
7d12e780 | 379 | serio_interrupt(port->serio, data, dfl); |
1da177e4 | 380 | |
0854e52d | 381 | out: |
1da177e4 LT |
382 | return IRQ_RETVAL(ret); |
383 | } | |
384 | ||
de9ce703 DT |
385 | /* |
386 | * i8042_enable_kbd_port enables keybaord port on chip | |
387 | */ | |
388 | ||
389 | static int i8042_enable_kbd_port(void) | |
390 | { | |
391 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
392 | i8042_ctr |= I8042_CTR_KBDINT; | |
393 | ||
394 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
395 | printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); | |
396 | return -EIO; | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | /* | |
403 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
404 | */ | |
405 | ||
406 | static int i8042_enable_aux_port(void) | |
407 | { | |
408 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
409 | i8042_ctr |= I8042_CTR_AUXINT; | |
410 | ||
411 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
412 | printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); | |
413 | return -EIO; | |
414 | } | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | /* | |
420 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
421 | * the controller has been switched into Multiplexed mode | |
422 | */ | |
423 | ||
424 | static int i8042_enable_mux_ports(void) | |
425 | { | |
426 | unsigned char param; | |
427 | int i; | |
428 | ||
429 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
430 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
431 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
432 | } | |
433 | ||
434 | return i8042_enable_aux_port(); | |
435 | } | |
436 | ||
1da177e4 LT |
437 | /* |
438 | * i8042_set_mux_mode checks whether the controller has an active | |
439 | * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode. | |
440 | */ | |
441 | ||
442 | static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version) | |
443 | { | |
444 | ||
445 | unsigned char param; | |
446 | /* | |
447 | * Get rid of bytes in the queue. | |
448 | */ | |
449 | ||
450 | i8042_flush(); | |
451 | ||
452 | /* | |
453 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 454 | * mouse interface, the last should be version. |
1da177e4 LT |
455 | */ |
456 | ||
457 | param = 0xf0; | |
463a4f76 | 458 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xf0) |
1da177e4 LT |
459 | return -1; |
460 | param = mode ? 0x56 : 0xf6; | |
463a4f76 | 461 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6)) |
1da177e4 LT |
462 | return -1; |
463 | param = mode ? 0xa4 : 0xa5; | |
463a4f76 | 464 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5)) |
1da177e4 LT |
465 | return -1; |
466 | ||
467 | if (mux_version) | |
463a4f76 | 468 | *mux_version = param; |
1da177e4 LT |
469 | |
470 | return 0; | |
471 | } | |
472 | ||
1da177e4 | 473 | /* |
de9ce703 DT |
474 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
475 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
476 | * LCS/Telegraphics. | |
1da177e4 LT |
477 | */ |
478 | ||
de9ce703 | 479 | static int __devinit i8042_check_mux(void) |
1da177e4 | 480 | { |
de9ce703 DT |
481 | unsigned char mux_version; |
482 | ||
483 | if (i8042_set_mux_mode(1, &mux_version)) | |
484 | return -1; | |
485 | ||
1da177e4 | 486 | /* |
de9ce703 DT |
487 | * Workaround for interference with USB Legacy emulation |
488 | * that causes a v10.12 MUX to be found. | |
1da177e4 | 489 | */ |
de9ce703 DT |
490 | if (mux_version == 0xAC) |
491 | return -1; | |
492 | ||
493 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | |
494 | (mux_version >> 4) & 0xf, mux_version & 0xf); | |
1da177e4 | 495 | |
de9ce703 DT |
496 | /* |
497 | * Disable all muxed ports by disabling AUX. | |
498 | */ | |
1da177e4 LT |
499 | i8042_ctr |= I8042_CTR_AUXDIS; |
500 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
501 | ||
502 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
503 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | |
de9ce703 | 504 | return -EIO; |
1da177e4 LT |
505 | } |
506 | ||
de9ce703 | 507 | i8042_mux_present = 1; |
1da177e4 LT |
508 | |
509 | return 0; | |
510 | } | |
511 | ||
1da177e4 | 512 | /* |
de9ce703 | 513 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 514 | */ |
de9ce703 DT |
515 | static struct completion i8042_aux_irq_delivered __devinitdata; |
516 | static int i8042_irq_being_tested __devinitdata; | |
1da177e4 | 517 | |
7d12e780 | 518 | static irqreturn_t __devinit i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 519 | { |
de9ce703 DT |
520 | unsigned long flags; |
521 | unsigned char str, data; | |
1da177e4 | 522 | |
de9ce703 DT |
523 | spin_lock_irqsave(&i8042_lock, flags); |
524 | str = i8042_read_status(); | |
525 | if (str & I8042_STR_OBF) { | |
526 | data = i8042_read_data(); | |
527 | if (i8042_irq_being_tested && | |
528 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
529 | complete(&i8042_aux_irq_delivered); | |
530 | } | |
531 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 532 | |
de9ce703 | 533 | return IRQ_HANDLED; |
1da177e4 LT |
534 | } |
535 | ||
536 | ||
537 | /* | |
538 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
539 | * the presence of an AUX interface. | |
540 | */ | |
541 | ||
87fd6318 | 542 | static int __devinit i8042_check_aux(void) |
1da177e4 | 543 | { |
de9ce703 DT |
544 | int retval = -1; |
545 | int irq_registered = 0; | |
546 | unsigned long flags; | |
1da177e4 | 547 | unsigned char param; |
1da177e4 LT |
548 | |
549 | /* | |
550 | * Get rid of bytes in the queue. | |
551 | */ | |
552 | ||
553 | i8042_flush(); | |
554 | ||
555 | /* | |
556 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
557 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
558 | * though it has an AUX port. | |
559 | */ | |
560 | ||
561 | param = 0x5a; | |
463a4f76 | 562 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x5a) { |
1da177e4 LT |
563 | |
564 | /* | |
565 | * External connection test - filters out AT-soldered PS/2 i8042's | |
566 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
567 | * 0xfa - no error on some notebooks which ignore the spec | |
568 | * Because it's common for chipsets to return error on perfectly functioning | |
569 | * AUX ports, we test for this only when the LOOP command failed. | |
570 | */ | |
571 | ||
de9ce703 DT |
572 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
573 | (param && param != 0xfa && param != 0xff)) | |
574 | return -1; | |
1da177e4 LT |
575 | } |
576 | ||
577 | /* | |
578 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
579 | */ | |
580 | ||
581 | if (i8042_command(¶m, I8042_CMD_AUX_DISABLE)) | |
582 | return -1; | |
583 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) { | |
584 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); | |
585 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | |
586 | } | |
587 | ||
588 | if (i8042_command(¶m, I8042_CMD_AUX_ENABLE)) | |
589 | return -1; | |
590 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS)) | |
591 | return -1; | |
592 | ||
593 | /* | |
de9ce703 DT |
594 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
595 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
596 | */ |
597 | ||
de9ce703 DT |
598 | if (i8042_noloop) { |
599 | /* | |
600 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
601 | * is working and hope we are right. | |
602 | */ | |
603 | retval = 0; | |
604 | goto out; | |
605 | } | |
1da177e4 | 606 | |
de9ce703 DT |
607 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
608 | "i8042", i8042_platform_device)) | |
609 | goto out; | |
1da177e4 | 610 | |
de9ce703 DT |
611 | irq_registered = 1; |
612 | ||
613 | if (i8042_enable_aux_port()) | |
614 | goto out; | |
615 | ||
616 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 617 | |
de9ce703 DT |
618 | init_completion(&i8042_aux_irq_delivered); |
619 | i8042_irq_being_tested = 1; | |
620 | ||
621 | param = 0xa5; | |
622 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
623 | ||
624 | spin_unlock_irqrestore(&i8042_lock, flags); | |
625 | ||
626 | if (retval) | |
627 | goto out; | |
1da177e4 | 628 | |
de9ce703 DT |
629 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
630 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 631 | /* |
de9ce703 DT |
632 | * AUX IRQ was never delivered so we need to flush the controller to |
633 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 634 | */ |
de9ce703 DT |
635 | i8042_flush(); |
636 | retval = -1; | |
637 | } | |
1da177e4 | 638 | |
de9ce703 | 639 | out: |
1da177e4 | 640 | |
de9ce703 DT |
641 | /* |
642 | * Disable the interface. | |
643 | */ | |
1da177e4 | 644 | |
de9ce703 DT |
645 | i8042_ctr |= I8042_CTR_AUXDIS; |
646 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 647 | |
de9ce703 DT |
648 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
649 | retval = -1; | |
1da177e4 | 650 | |
de9ce703 DT |
651 | if (irq_registered) |
652 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 653 | |
de9ce703 DT |
654 | return retval; |
655 | } | |
1da177e4 | 656 | |
de9ce703 | 657 | static int i8042_controller_check(void) |
1da177e4 | 658 | { |
de9ce703 DT |
659 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
660 | printk(KERN_ERR "i8042.c: No controller found.\n"); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | return 0; | |
1da177e4 LT |
665 | } |
666 | ||
de9ce703 | 667 | static int i8042_controller_selftest(void) |
2673c836 VP |
668 | { |
669 | unsigned char param; | |
670 | ||
671 | if (!i8042_reset) | |
672 | return 0; | |
673 | ||
674 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
675 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | |
de9ce703 | 676 | return -ENODEV; |
2673c836 VP |
677 | } |
678 | ||
679 | if (param != I8042_RET_CTL_TEST) { | |
680 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | |
681 | param, I8042_RET_CTL_TEST); | |
de9ce703 | 682 | return -EIO; |
2673c836 VP |
683 | } |
684 | ||
685 | return 0; | |
686 | } | |
1da177e4 LT |
687 | |
688 | /* | |
689 | * i8042_controller init initializes the i8042 controller, and, | |
690 | * most importantly, sets it into non-xlated mode if that's | |
691 | * desired. | |
692 | */ | |
693 | ||
694 | static int i8042_controller_init(void) | |
695 | { | |
696 | unsigned long flags; | |
697 | ||
1da177e4 LT |
698 | /* |
699 | * Save the CTR for restoral on unload / reboot. | |
700 | */ | |
701 | ||
702 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { | |
703 | printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); | |
de9ce703 | 704 | return -EIO; |
1da177e4 LT |
705 | } |
706 | ||
707 | i8042_initial_ctr = i8042_ctr; | |
708 | ||
709 | /* | |
710 | * Disable the keyboard interface and interrupt. | |
711 | */ | |
712 | ||
713 | i8042_ctr |= I8042_CTR_KBDDIS; | |
714 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
715 | ||
716 | /* | |
717 | * Handle keylock. | |
718 | */ | |
719 | ||
720 | spin_lock_irqsave(&i8042_lock, flags); | |
721 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
722 | if (i8042_unlock) | |
723 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
724 | else | |
725 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); | |
726 | } | |
727 | spin_unlock_irqrestore(&i8042_lock, flags); | |
728 | ||
729 | /* | |
730 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
731 | * bother enabling translating and be happy. | |
732 | */ | |
733 | ||
734 | if (~i8042_ctr & I8042_CTR_XLATE) | |
735 | i8042_direct = 1; | |
736 | ||
737 | /* | |
738 | * Set nontranslated mode for the kbd interface if requested by an option. | |
739 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
740 | * interface is. We don't do this by default, since it can confuse notebook | |
741 | * BIOSes. | |
742 | */ | |
743 | ||
744 | if (i8042_direct) | |
745 | i8042_ctr &= ~I8042_CTR_XLATE; | |
746 | ||
747 | /* | |
748 | * Write CTR back. | |
749 | */ | |
750 | ||
751 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
752 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | |
de9ce703 | 753 | return -EIO; |
1da177e4 LT |
754 | } |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
759 | ||
760 | /* | |
de9ce703 | 761 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 762 | */ |
de9ce703 | 763 | |
1da177e4 LT |
764 | static void i8042_controller_reset(void) |
765 | { | |
de9ce703 | 766 | i8042_flush(); |
1da177e4 LT |
767 | |
768 | /* | |
769 | * Disable MUX mode if present. | |
770 | */ | |
771 | ||
772 | if (i8042_mux_present) | |
773 | i8042_set_mux_mode(0, NULL); | |
774 | ||
775 | /* | |
de9ce703 | 776 | * Reset the controller if requested. |
1da177e4 LT |
777 | */ |
778 | ||
de9ce703 | 779 | i8042_controller_selftest(); |
1da177e4 | 780 | |
de9ce703 DT |
781 | /* |
782 | * Restore the original control register setting. | |
783 | */ | |
784 | ||
785 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
1da177e4 LT |
786 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); |
787 | } | |
788 | ||
789 | ||
790 | /* | |
791 | * Here we try to reset everything back to a state in which the BIOS will be | |
792 | * able to talk to the hardware when rebooting. | |
793 | */ | |
794 | ||
795 | static void i8042_controller_cleanup(void) | |
796 | { | |
797 | int i; | |
798 | ||
1da177e4 LT |
799 | /* |
800 | * Reset anything that is connected to the ports. | |
801 | */ | |
802 | ||
803 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
de9ce703 | 804 | if (i8042_ports[i].serio) |
1da177e4 LT |
805 | serio_cleanup(i8042_ports[i].serio); |
806 | ||
807 | i8042_controller_reset(); | |
808 | } | |
809 | ||
810 | ||
811 | /* | |
812 | * i8042_panic_blink() will flash the keyboard LEDs and is called when | |
813 | * kernel panics. Flashing LEDs is useful for users running X who may | |
814 | * not see the console and will help distingushing panics from "real" | |
815 | * lockups. | |
816 | * | |
817 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
818 | * waiting for KBC to free up even if KBD interrupt is off | |
819 | */ | |
820 | ||
821 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
822 | ||
823 | static long i8042_panic_blink(long count) | |
824 | { | |
825 | long delay = 0; | |
826 | static long last_blink; | |
827 | static char led; | |
828 | ||
829 | /* | |
830 | * We expect frequency to be about 1/2s. KDB uses about 1s. | |
831 | * Make sure they are different. | |
832 | */ | |
833 | if (!i8042_blink_frequency) | |
834 | return 0; | |
835 | if (count - last_blink < i8042_blink_frequency) | |
836 | return 0; | |
837 | ||
838 | led ^= 0x01 | 0x04; | |
839 | while (i8042_read_status() & I8042_STR_IBF) | |
840 | DELAY; | |
817e6ba3 | 841 | i8042_suppress_kbd_ack = 1; |
1da177e4 LT |
842 | i8042_write_data(0xed); /* set leds */ |
843 | DELAY; | |
844 | while (i8042_read_status() & I8042_STR_IBF) | |
845 | DELAY; | |
846 | DELAY; | |
817e6ba3 | 847 | i8042_suppress_kbd_ack = 1; |
1da177e4 LT |
848 | i8042_write_data(led); |
849 | DELAY; | |
850 | last_blink = count; | |
851 | return delay; | |
852 | } | |
853 | ||
854 | #undef DELAY | |
855 | ||
856 | /* | |
857 | * Here we try to restore the original BIOS settings | |
858 | */ | |
859 | ||
3ae5eaec | 860 | static int i8042_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 861 | { |
de9ce703 | 862 | i8042_controller_cleanup(); |
1da177e4 LT |
863 | |
864 | return 0; | |
865 | } | |
866 | ||
867 | ||
868 | /* | |
869 | * Here we try to reset everything back to a state in which suspended | |
870 | */ | |
871 | ||
3ae5eaec | 872 | static int i8042_resume(struct platform_device *dev) |
1da177e4 | 873 | { |
de9ce703 | 874 | int error; |
1da177e4 | 875 | |
de9ce703 DT |
876 | error = i8042_controller_check(); |
877 | if (error) | |
878 | return error; | |
2673c836 | 879 | |
de9ce703 DT |
880 | error = i8042_controller_selftest(); |
881 | if (error) | |
882 | return error; | |
1da177e4 LT |
883 | |
884 | /* | |
de9ce703 | 885 | * Restore pre-resume CTR value and disable all ports |
1da177e4 LT |
886 | */ |
887 | ||
de9ce703 DT |
888 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
889 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
890 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
891 | printk(KERN_ERR "i8042: Can't write CTR to resume\n"); | |
892 | return -EIO; | |
893 | } | |
1da177e4 | 894 | |
de9ce703 DT |
895 | if (i8042_mux_present) { |
896 | if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports()) | |
897 | printk(KERN_WARNING | |
898 | "i8042: failed to resume active multiplexor, " | |
899 | "mouse won't work.\n"); | |
900 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) | |
901 | i8042_enable_aux_port(); | |
1da177e4 | 902 | |
de9ce703 DT |
903 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
904 | i8042_enable_kbd_port(); | |
905 | ||
7d12e780 | 906 | i8042_interrupt(0, NULL); |
1da177e4 LT |
907 | |
908 | return 0; | |
1da177e4 LT |
909 | } |
910 | ||
911 | /* | |
912 | * We need to reset the 8042 back to original mode on system shutdown, | |
913 | * because otherwise BIOSes will be confused. | |
914 | */ | |
915 | ||
3ae5eaec | 916 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 LT |
917 | { |
918 | i8042_controller_cleanup(); | |
919 | } | |
920 | ||
87fd6318 | 921 | static int __devinit i8042_create_kbd_port(void) |
1da177e4 LT |
922 | { |
923 | struct serio *serio; | |
924 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
925 | ||
d39969de | 926 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
927 | if (!serio) |
928 | return -ENOMEM; | |
929 | ||
930 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
931 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
932 | serio->start = i8042_start; |
933 | serio->stop = i8042_stop; | |
934 | serio->port_data = port; | |
935 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 936 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d DT |
937 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
938 | ||
939 | port->serio = serio; | |
de9ce703 | 940 | port->irq = I8042_KBD_IRQ; |
0854e52d | 941 | |
de9ce703 | 942 | return 0; |
1da177e4 LT |
943 | } |
944 | ||
de9ce703 | 945 | static int __devinit i8042_create_aux_port(int idx) |
1da177e4 LT |
946 | { |
947 | struct serio *serio; | |
de9ce703 DT |
948 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
949 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 950 | |
d39969de | 951 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
952 | if (!serio) |
953 | return -ENOMEM; | |
954 | ||
955 | serio->id.type = SERIO_8042; | |
956 | serio->write = i8042_aux_write; | |
0854e52d DT |
957 | serio->start = i8042_start; |
958 | serio->stop = i8042_stop; | |
959 | serio->port_data = port; | |
960 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
961 | if (idx < 0) { |
962 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
963 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
964 | } else { | |
965 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
966 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
967 | } | |
0854e52d DT |
968 | |
969 | port->serio = serio; | |
de9ce703 DT |
970 | port->mux = idx; |
971 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 972 | |
de9ce703 | 973 | return 0; |
1da177e4 LT |
974 | } |
975 | ||
de9ce703 | 976 | static void __devinit i8042_free_kbd_port(void) |
1da177e4 | 977 | { |
de9ce703 DT |
978 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
979 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
980 | } | |
1da177e4 | 981 | |
de9ce703 DT |
982 | static void __devinit i8042_free_aux_ports(void) |
983 | { | |
984 | int i; | |
0854e52d | 985 | |
de9ce703 DT |
986 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
987 | kfree(i8042_ports[i].serio); | |
988 | i8042_ports[i].serio = NULL; | |
989 | } | |
990 | } | |
0854e52d | 991 | |
de9ce703 DT |
992 | static void __devinit i8042_register_ports(void) |
993 | { | |
994 | int i; | |
0854e52d | 995 | |
de9ce703 DT |
996 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
997 | if (i8042_ports[i].serio) { | |
998 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", | |
999 | i8042_ports[i].serio->name, | |
1000 | (unsigned long) I8042_DATA_REG, | |
1001 | (unsigned long) I8042_COMMAND_REG, | |
1002 | i8042_ports[i].irq); | |
1003 | serio_register_port(i8042_ports[i].serio); | |
1004 | } | |
1005 | } | |
1da177e4 LT |
1006 | } |
1007 | ||
de9ce703 | 1008 | static void __devinit i8042_unregister_ports(void) |
1da177e4 | 1009 | { |
de9ce703 | 1010 | int i; |
1da177e4 | 1011 | |
de9ce703 DT |
1012 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1013 | if (i8042_ports[i].serio) { | |
1014 | serio_unregister_port(i8042_ports[i].serio); | |
1015 | i8042_ports[i].serio = NULL; | |
1016 | } | |
1017 | } | |
1018 | } | |
1019 | ||
1020 | static void i8042_free_irqs(void) | |
1021 | { | |
1022 | if (i8042_aux_irq_registered) | |
1023 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1024 | if (i8042_kbd_irq_registered) | |
1025 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1026 | ||
1027 | i8042_aux_irq_registered = i8042_kbd_irq_registered = 0; | |
1028 | } | |
1029 | ||
1030 | static int __devinit i8042_setup_aux(void) | |
1031 | { | |
1032 | int (*aux_enable)(void); | |
1033 | int error; | |
1034 | int i; | |
1da177e4 | 1035 | |
de9ce703 | 1036 | if (i8042_check_aux()) |
87fd6318 | 1037 | return -ENODEV; |
1da177e4 | 1038 | |
de9ce703 DT |
1039 | if (i8042_nomux || i8042_check_mux()) { |
1040 | error = i8042_create_aux_port(-1); | |
1041 | if (error) | |
1042 | goto err_free_ports; | |
1043 | aux_enable = i8042_enable_aux_port; | |
1044 | } else { | |
1045 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1046 | error = i8042_create_aux_port(i); | |
1047 | if (error) | |
1048 | goto err_free_ports; | |
0854e52d | 1049 | } |
de9ce703 | 1050 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1051 | } |
1052 | ||
de9ce703 DT |
1053 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1054 | "i8042", i8042_platform_device); | |
1055 | if (error) | |
1056 | goto err_free_ports; | |
945ef0d4 | 1057 | |
de9ce703 DT |
1058 | if (aux_enable()) |
1059 | goto err_free_irq; | |
1da177e4 | 1060 | |
de9ce703 | 1061 | i8042_aux_irq_registered = 1; |
1da177e4 | 1062 | return 0; |
0854e52d | 1063 | |
de9ce703 DT |
1064 | err_free_irq: |
1065 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1066 | err_free_ports: | |
1067 | i8042_free_aux_ports(); | |
1068 | return error; | |
1069 | } | |
0854e52d | 1070 | |
de9ce703 DT |
1071 | static int __devinit i8042_setup_kbd(void) |
1072 | { | |
1073 | int error; | |
1074 | ||
1075 | error = i8042_create_kbd_port(); | |
1076 | if (error) | |
1077 | return error; | |
1078 | ||
1079 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1080 | "i8042", i8042_platform_device); | |
1081 | if (error) | |
1082 | goto err_free_port; | |
1083 | ||
1084 | error = i8042_enable_kbd_port(); | |
1085 | if (error) | |
1086 | goto err_free_irq; | |
1087 | ||
1088 | i8042_kbd_irq_registered = 1; | |
1089 | return 0; | |
1090 | ||
1091 | err_free_irq: | |
1092 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1093 | err_free_port: | |
1094 | i8042_free_kbd_port(); | |
1095 | return error; | |
1da177e4 LT |
1096 | } |
1097 | ||
de9ce703 | 1098 | static int __devinit i8042_probe(struct platform_device *dev) |
1da177e4 | 1099 | { |
de9ce703 | 1100 | int error; |
1da177e4 | 1101 | |
de9ce703 DT |
1102 | error = i8042_controller_selftest(); |
1103 | if (error) | |
1104 | return error; | |
1da177e4 | 1105 | |
de9ce703 DT |
1106 | error = i8042_controller_init(); |
1107 | if (error) | |
1108 | return error; | |
1109 | ||
1110 | if (!i8042_noaux) { | |
1111 | error = i8042_setup_aux(); | |
1112 | if (error && error != -ENODEV && error != -EBUSY) | |
1113 | goto out_fail; | |
1114 | } | |
1115 | ||
1116 | if (!i8042_nokbd) { | |
1117 | error = i8042_setup_kbd(); | |
1118 | if (error) | |
1119 | goto out_fail; | |
1120 | } | |
1da177e4 | 1121 | |
de9ce703 DT |
1122 | /* |
1123 | * Ok, everything is ready, let's register all serio ports | |
1124 | */ | |
1125 | i8042_register_ports(); | |
1126 | ||
1127 | return 0; | |
1128 | ||
1129 | out_fail: | |
1130 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1131 | i8042_free_irqs(); | |
1132 | i8042_controller_reset(); | |
1133 | ||
1134 | return error; | |
1135 | } | |
1136 | ||
1137 | static int __devexit i8042_remove(struct platform_device *dev) | |
1138 | { | |
1139 | i8042_unregister_ports(); | |
1140 | i8042_free_irqs(); | |
1141 | i8042_controller_reset(); | |
1da177e4 | 1142 | |
87fd6318 DT |
1143 | return 0; |
1144 | } | |
1145 | ||
1146 | static struct platform_driver i8042_driver = { | |
1147 | .driver = { | |
1148 | .name = "i8042", | |
1149 | .owner = THIS_MODULE, | |
1150 | }, | |
1151 | .probe = i8042_probe, | |
1152 | .remove = __devexit_p(i8042_remove), | |
1153 | .suspend = i8042_suspend, | |
1154 | .resume = i8042_resume, | |
1155 | .shutdown = i8042_shutdown, | |
1156 | }; | |
1157 | ||
1158 | static int __init i8042_init(void) | |
1159 | { | |
1160 | int err; | |
1161 | ||
1162 | dbg_init(); | |
1163 | ||
1164 | err = i8042_platform_init(); | |
1165 | if (err) | |
1166 | return err; | |
1167 | ||
de9ce703 DT |
1168 | err = i8042_controller_check(); |
1169 | if (err) | |
1170 | goto err_platform_exit; | |
87fd6318 DT |
1171 | |
1172 | err = platform_driver_register(&i8042_driver); | |
1173 | if (err) | |
1174 | goto err_platform_exit; | |
1175 | ||
1176 | i8042_platform_device = platform_device_alloc("i8042", -1); | |
1177 | if (!i8042_platform_device) { | |
1178 | err = -ENOMEM; | |
1179 | goto err_unregister_driver; | |
1180 | } | |
1181 | ||
1182 | err = platform_device_add(i8042_platform_device); | |
1183 | if (err) | |
1184 | goto err_free_device; | |
1185 | ||
de9ce703 DT |
1186 | panic_blink = i8042_panic_blink; |
1187 | ||
87fd6318 DT |
1188 | return 0; |
1189 | ||
1190 | err_free_device: | |
1191 | platform_device_put(i8042_platform_device); | |
1192 | err_unregister_driver: | |
1193 | platform_driver_unregister(&i8042_driver); | |
1194 | err_platform_exit: | |
1195 | i8042_platform_exit(); | |
1196 | ||
1197 | return err; | |
1198 | } | |
1199 | ||
1200 | static void __exit i8042_exit(void) | |
1201 | { | |
1da177e4 | 1202 | platform_device_unregister(i8042_platform_device); |
3ae5eaec | 1203 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1204 | i8042_platform_exit(); |
1205 | ||
1206 | panic_blink = NULL; | |
1207 | } | |
1208 | ||
1209 | module_init(i8042_init); | |
1210 | module_exit(i8042_exit); |